JP5718799B2 - OLT and frame transfer method - Google Patents

Description

  The present invention relates to an optical communication technique, and more particularly, to a frame transfer technique in an OLT (Optical Line Terminal) for connecting a PON system to a host device of a provider side network (service network).

  In 2009, standardization of 10G-EPON (10 Gigabit Ethernet Passive Optical Network: Ethernet is a registered trademark) was completed in IEEE 802.3av. The characteristic of 10G-EPON is that 10-times high-speed transmission is possible as compared with GE-PON (Gigabit Ethernet Passive Optical Network: see Non-Patent Document 1) that is already widely used. Furthermore, there is a feature that existing GE-PON and 10G-EPON can be used together.

  When using a mixture of GE-PON and 10G-EPON, use WDM technology that uses different wavelengths for 1G downstream signals and 10G downstream signals, and use TDM technology between 1G downstream signals and between 10G downstream signals. . In the upstream signal, the same wavelength is used for the 1G upstream signal and the 10G upstream signal, and the TDMA technique is used by combining the 1G upstream signal and the 10G upstream signal. That is, three different wavelengths are used for the 1G downstream signal, the 10G downstream signal, and the upstream signal.

  In the conventional GE-PON system, as shown in Non-Patent Document 2, in the OLT that is an in-station device for connecting to a provider's network (service network), an SNI port is provided on the SNI (Service Node Interface) side. When one OLT is connected to a plurality of networks (service networks), a switch (or a router or the like) is inserted between the OLT and the plurality of networks (service networks).

  FIG. 18 is a configuration example of a conventional GE-PON system. FIG. 19 shows another configuration example of the conventional GE-PON system. In the conventional GE-PON system, when it is necessary to change the network (service network) connected to each ONU, the system configuration is as shown in FIG. Of these, FIG. 19 shows a case where a switch (or router or the like) is inserted between the OLT and a plurality of networks (service networks). FIG. 20 is a block diagram showing a configuration of a conventional OLT (see Patent Document 1).

First, each processing unit of the conventional OLT will be described with reference to FIG.
The first transmission / reception circuit 52 is a circuit for transmitting / receiving a frame to / from the ONU via an ODN (Optical Distribution Network) connected to the PON port 51. A system that performs data transmission between the OLT and the ONU via the ODN is the PON.
The second transmission / reception circuit 58 is a circuit that serves as an interface with the operator network NW connected via the SNI port 59.

The frame separation unit 53 transmits a frame addressed to the OLT (a control frame used for PON control) among the frames input from the first transmission / reception circuit 52 to the control frame processing unit 54 and transmits other frames to the frame. It is a processing unit that transmits to the transfer processing unit 60.
The frame multiplexing unit 56 is a processing unit that multiplexes the downlink frame from the frame transfer processing unit 60 and the control frame from the control frame processing unit 54 in a time division manner and transmits the multiplexed frame to the first transmission / reception circuit 52.

The frame transfer processing unit 60 is a processing unit that performs frame transfer processing based on the destination MAC address of the frame received from both the frame separation unit 53 and the second transmission / reception circuit 58.
The control frame processing unit 54 is a processing unit that performs processing related to PON control, such as discovery processing (Discovery process) for assigning LLIDs to each ONU, and arbitration of upstream signals (signals sent from the ONU to the OLT).
The bandwidth allocation processing unit 55 is a processing unit that allocates bandwidth (transmission start time and transmission data amount) to the ONU in accordance with a request from the control frame processing unit 54.

  In both system configurations of FIGS. 18 and 19, a host device that performs transfer control and the like in the service network is inserted between the SNI and the network NW. At this time, the content of the service that can be realized by the PON system is limited by the host device connected to the OLT. For example, when the host device connected to the OLT is for 1G Ethernet, this PON system is limited to services by 1G Ethernet.

  In the case of FIG. 19, one switch and OLT are shared by a plurality of higher-level devices, that is, the bandwidth for one OLT is divided and used. For this reason, as compared with the case of FIG. 18, the bandwidth of the downstream frame that can be used in each host device is reduced.

In other words, when the network NW connected to each ONU is different, there have been two methods in the past.
Method 1 (FIG. 18): The maximum downlink bandwidth that can be used by each host device can be maximized, but the same number of OLTs as the network NW to be connected is required. Method 2 (FIG. 19): The downlink bandwidth that can be used by each host device is Method 1 ( FIG. 18) is smaller (the downstream bandwidth of the host device cannot be used to the maximum), but if only one OLT is required, both have advantages and disadvantages.

JP 2009-260668 A

“Technology Basic Course [GE-PON Technology] 1st PON”, NTT Technical Journal, Vol.17, No.8, pp.71-74, 2005 “Development of Gigabit Ethernet-PON (GE-PON) System”, NTT Technical Journal, Vol.17, No.3, pp.75-80, 2005

When connecting a plurality of networks (service networks) NW to one OLT, according to method 1 of the two conventional technologies described above, the same number of OLTs as the number of networks (service networks) to be connected is required. Method 2 is desirable when considering the number of OLTs in the entire PON system.
However, according to the method 2, it is necessary to insert a switch (or a router or the like) between the OLT and the host device of each network NW. For this reason, each upper apparatus shares the downstream band of the switch, and there is a problem that the downstream band that can be used by each upper apparatus is limited.

  In addition, in the OLT, when a configuration corresponding to a plurality of networks is provided with SNI ports for each higher-level device, only a specific combination of the user device and the provider network NW is connected via the OLT. There may also be an operational situation of doing. Therefore, when power is constantly supplied to the circuit units connected to the respective SNI ports, power is always supplied to the circuit units connected to the non-operating SNI ports. There was a problem of increasing.

  The present invention is to solve such a problem, and while suppressing an increase in circuit scale and power consumption and avoiding a restriction on a downstream band, an upstream frame received from an arbitrary ONU is referred to as the ONU. An object of the present invention is to provide a frame transfer technique that can be transferred to a corresponding host device.

In order to achieve such an object, the OLT according to the present invention is connected to a plurality of ONUs via PONs, and is connected to a plurality of higher-level devices via SNI provided for each higher-level device. And an OLT that mutually transfers frames exchanged between the host device and a higher-level device, and is provided for each reception circuit that receives an upstream frame from the ONU via the PON, and for each preset downstream transmission rate, A plurality of transmission circuits that transmit the downstream frame to the ONU at the downstream transmission speed via the PON and the SNI are provided for each SNI, and the upstream frame is transmitted to the host device via the SNI. a plurality of receiving circuits for receiving a downstream frame from the host device via the uplink frame received by the receiving circuit is transferred to the transmission and reception circuit, transmission and reception A frame transfer processing unit that transfers a downlink frame received on the path to a transmission circuit, and one or more always-powered blocks and one or more power-saving blocks as blocks for performing power control of each circuit unit constituting the OLT Among the circuit units, power is always supplied to the circuit units belonging to the constant power supply block, and power supply / stop is controlled for the circuit units belonging to the power saving block according to the operation of the power saving block. And an LLID of the upstream frame received by the receiving circuit, including a LLID table in which SNI selection information corresponding to the LLID is registered for each individual LLID in the ONU in the frame transfer processing unit. SNI selection information corresponding to the SNI selection information is acquired from the LLID table, and the upstream frame is sent to the transmission / reception circuit corresponding to the SNI selection information in the transmission / reception circuit. Transfer the over arm, the power control unit based on the setting from the outside indicating the operational state of the SNI, among power-saving block, transmission and reception circuit connected with SNI of Operational state to belong power saving block Power is supplied and power supply to the power saving block to which the transmission / reception circuit connected to the non-operating SNI belongs is stopped .

  In addition, in the above-described configuration example of the OLT according to the present invention, the frame transfer processing unit includes an output destination determination unit that obtains SLI selection information corresponding to the LLID of the uplink frame received by the reception circuit from the LLID table, and a transmission / reception circuit Among them, an uplink output destination control unit for transferring an uplink frame to a transmission / reception circuit corresponding to the SNI selection information acquired by the output destination determination unit, and an uplink frame provided for each transmission / reception circuit and output from the uplink output destination control unit And an upstream output timing adjustment unit that adjusts the timing to transfer the signal to the transmission / reception circuit, and the power supply control unit, based on an external setting indicating the operation state of each SNI, The power is supplied to the power saving block to which the upstream output timing adjustment unit corresponding to the SNI belongs, and the upstream output timing adjustment corresponding to the non-operating SNI is performed. Part is that so as to stop the power supply to belong power-saving block.

  In addition, in the configuration example of the OLT according to the present invention, the LLID and the downlink output destination selection information relating to the downlink frame are registered in the frame transfer processing unit for each VID for identifying the VLAN to which the downlink frame belongs. Further including a VID table, the LLID corresponding to the VID of the downlink frame received by the transmission / reception circuit and the downlink output destination selection information are obtained from the VID table, and the LLID is assigned to the downlink frame, and then the downlink of the transmission circuit The LLID and the downlink output destination selection information corresponding to the VID of the downlink frame that is transferred to the transmission circuit corresponding to the output destination selection information and is provided for each transmission / reception circuit in the frame transfer processing unit and received by the transmission / reception circuit. A plurality of downlink output destination determination units acquired from the table and each transmission / reception circuit are provided. The LLID acquired by the downlink output destination determination unit is provided for each of the transmission / reception circuits, and is provided by the downlink output destination determination unit of the transmission circuit, provided for each of the transmission / reception circuits. A plurality of downlink output destination control units that transfer the downlink frame from the LLID adding unit to the transmission circuit corresponding to the downlink output destination selection information, and the power supply control unit indicates the operation state of each downlink transmission rate Based on the setting from the outside, when there is an unused downlink transmission rate among the downlink transmission rates, to the downlink output destination determination unit, LLID adding unit, and downlink output destination control unit corresponding to the unused downlink transmission rate The power supply may be stopped.

  Further, in the above-described configuration example of the OLT according to the present invention, the LLID table is configured from a plurality of storage units, and the power supply control unit is configured to store the storage units based on the external setting indicating the use state of each storage unit. Among them, power is supplied to the storage unit in use, and power supply is stopped to the storage unit in unused state.

  Further, in the OLT according to the present invention, when the frame transfer processing unit determines that the upstream frame is a discard target frame by the circuit unit that performs processing related to the upstream frame before itself, the OLT is input to the frame. The upstream frame is discarded without performing the process of acquiring the SNI selection information of the upstream frame.

  Also, in the OLT according to the present invention, when the frame transfer processing unit determines that the downstream frame is a frame to be discarded by the circuit unit that performs processing related to the downstream frame before itself, the OLT is input to itself. In addition, the downlink frame is discarded without performing the process of acquiring the output destination selection information of the downlink frame and / or the process of assigning the output destination selection information to the downlink frame.

In addition, the frame transfer method according to the present invention connects to a plurality of ONUs via PON and connects to a plurality of host devices via SNI provided for each host device, and between these ONUs and host devices. A frame transfer method used in the OLT for mutually transferring a frame exchanged in each of the ONUs for each individual LLID, a storage step for storing SLI selection information corresponding to the LLID in an LLID table, and a PON The SNI selection information corresponding to the LLID of the upstream frame received from the ONU is acquired from the LLID table, and the transmission / reception circuit provided for each SNI and transmits / receives a frame to / from the host device via the SNI. a transfer step of transferring the uplink frame to the corresponding transmission and reception circuit and SNI selection information, those As a block for controlling the power supply of each circuit unit constituting the OLT, one or more constant power supply blocks and one or more power saving blocks are provided, and among the circuit units, a circuit unit belonging to the constant power supply block has a power supply. The circuit unit belonging to the power saving block includes a power control step for controlling power supply / stop according to the operation of the power saving block. In the power control step, the operation state of each SNI is determined. Based on the setting from the outside, a power transmission / reception circuit that supplies power to a power saving block to which a transmission / reception circuit connected to an SNI in operation belongs, among power saving blocks, and is connected to an SNI that is not in operation The power supply to the power-saving block to which is attached is stopped.

According to the present invention, when an OLT is connected to a plurality of higher-level devices via an SNI provided for each higher-level device, an upstream frame received from any ONU connected to the PON system is It can be transferred to the corresponding host device. In addition, it is possible to process downstream frames input via a plurality of SNI ports in parallel for each input SNI port and transfer them to the destination ONU.
Therefore, one OLT having a port for each SNI between each ONU of the PON system and each higher-level device, and further each carrier network, without a switch between the OLT and the plurality of SNIs. The frame can be transferred. For this reason, it is possible to avoid sharing the downstream band of the switch among the higher-level devices, and to avoid restrictions on the downstream bandwidth that can be used by the individual higher-level devices.

Also, in a system where 10G-ONU and 1G-ONU are mixed, when one SNI is for 10G-Ethernet and the other is for 1G-Ethernet, 10G-ONU is SNI for 10G-Ethernet and 1G-ONU is An SNI for 1G-Ethernet can be used. As a result, PON systems with different communication speeds can be constructed with one OLT.
Further, when there is an SNI in an unoperated state among SNIs connected to the OLT, power supply to a circuit related to frame transmission / reception between the non-operated SNI and the OLT can be stopped. Therefore, power consumption in the circuit unit connected to the non-operating SNI port can be omitted, and power consumption of the entire OLT can be reduced.

It is a block diagram which shows the structure of the PON system concerning this invention. It is a structural example of the frame transmitted in a PON section. It is a block diagram which shows the structure of OLT concerning 1st Embodiment. It is a block diagram which shows the structural example of the frame transfer process part concerning 1st Embodiment. It is an example of a structure of a LLID table. It is a flowchart which shows the output destination SNI determination procedure of an upstream frame. It is a structural example of a VID table. It is a flowchart which shows the output destination determination procedure of a downstream frame. It is a block diagram which shows the structure of OLT concerning 2nd Embodiment. It is a block diagram which shows the structural example of the frame transfer process part concerning 2nd Embodiment. It is a structural example of the LLID table concerning 2nd Embodiment. It is a structural example of the flame | frame and discard instruction | indication signal concerning 3rd Embodiment. It is a time chart which shows the relationship between an upstream frame and discard determination. It is a flowchart which shows the output destination SNI determination procedure of the upstream frame concerning 3rd Embodiment. It is a flowchart which shows the output destination determination procedure of the downstream flame | frame concerning 3rd Embodiment. It is a time chart which shows the relationship (delay priority) of an uplink frame, a discard instruction signal, and discard determination. It is a time chart which shows the relationship (power saving priority) of an uplink frame, a discard instruction signal, and discard determination. It is a structural example of the conventional GE-PON system. It is another example of composition of the conventional GE-PON system. It is a block diagram which shows the structure of the conventional OLT.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
[PON system]
First, a PON system 100 according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram showing a configuration of a PON system according to the present invention. FIG. 2 is a configuration example of a frame transmitted in the PON section.

As shown in FIG. 1, in this PON system 100, ONUn (n = 1 to 4) is connected to a user apparatus n via a UNI (User Network Interface).
Each ONU is commonly connected to one optical splitter via an optical communication path, and this optical splitter is further connected to one OLT 10 via one optical communication path. Since an upstream signal, a downstream signal addressed to ONU belonging to NW1, and a downstream signal addressed to ONU belonging to NW2 have different wavelengths, an optical demultiplexer (not shown in FIG. 1) is interposed between the optical communication path and the OLT 10. .

The OLT 10 is provided with two SNI ports on the SNI side, and the higher order apparatus 1 and the higher order apparatus 2 are individually connected to each SNI port via the SNI.
Further, a network (service network) NW1 on the operator side is connected to the host device 1, and a network (service network) NW2 on the operator side is connected to the host device 2.

In the PON section of the PON system 100, that is, the section between the ONUn and the OLT 10, data is exchanged in a frame configured as shown in FIG.
In FIG. 2, the preamble is an LLID embedded in the Ethernet preamble.

  The LLID (Logical Link ID) is an identifier that corresponds to each ONU in the case of unicast, and in a one-to-many relationship with each ONU in the case of multicast or broadcast. It is determined by the OLT at the time of ONU registration (ONU is under the control of the OLT), and the OLT manages the ONU under its control so that duplication of LLID does not occur.

The VLAN tag is a tag including VLAN information. There may be no tag or multiple tags. This VLAN tag includes TPID and TCI.
TPID (Tag Protocol ID) is an Ether Type value indicating that a VLAN tag continues. Normally, the TPID is 0x8100 indicating that it is a tagged frame according to IEEE 802.1Q.
TCI (Tag Control Information) is VLAN tag information. This TCI includes PCP, CFI, and VID.

PCP (Priority Code Point) is the priority of the frame.
CFI (Canonical Format Indicator) is a value indicating whether or not the MAC address in the MAC header conforms to the standard format.
The VID or VLAN ID (VLAN Identifier) is a value that specifies the VLAN to which the frame belongs.
Type is an Ether Type value indicating the type of the upper protocol.

[OLT]
Next, the configuration of the OLT 10 according to the present embodiment will be described with reference to FIG. FIG. 3 is a block diagram illustrating a configuration of the OLT according to the first embodiment. FIG. 4 is a block diagram of a configuration example of the frame transfer processing unit according to the first embodiment.
The difference in configuration of the OLT 10 according to the present embodiment from the conventional OLT is that an SNI port, a transmission / reception circuit, a frame multiplexing unit, and a transmission circuit are provided for each transmission system having different downlink transmission rates. .

With reference to FIG. 3 and FIG. 4, each processing unit of the OLT 10 according to the present embodiment will be described.
The PON port 11 is a circuit for exchanging frames with the ONU via the ODN.
The receiving circuit 12 is a circuit for receiving an upstream frame from the ONU via the ODN and the PON port 11.
A transmission circuit (system 0) 17A and a transmission circuit (system 1) 17B are provided for each preset downlink transmission rate, and are respectively ONU (system 0) and ONU (1) via the PON port 11 and ODN. This is a circuit for transmitting a downstream frame to the system) at the downstream transmission speed. In the present invention, for example, the 0 system indicates a transmission system with a downlink transmission rate of 1 Gbps, and the 1 system indicates a transmission system with a downlink transmission rate of 10 Gbps.

The SNI port (system 0) 19A and the SNI port 19B (system 1) are circuit units that are provided for each host device and exchange frames with the host device via the SNI.
The transmission / reception circuit (system 0) 18A and the transmission / reception circuit (system 1) 18B are provided for each higher-level device, that is, for each SNI, and are respectively connected to the operator via the SNI ports 19A and 19B and the corresponding higher-level devices 1 and 2. This is a circuit unit that transmits and receives frames between the network (0 system) NW1 and the carrier network (1 system) NW2.

The frame separation unit 13 transmits a frame addressed to the OLT 10 (control frame used for PON control) among the frames input from the reception circuit 12 to the control frame processing unit 14 and transmits other frames to the frame transfer processing unit. 20 is a processing unit that transmits data to 20.
The frame multiplexing unit (system 0) 16A multiplexes the downstream frame addressed to the ONU (system 0) from the frame transfer processing unit 20 and the control frame from the control frame processing unit 14 in a time division manner, and transmits the transmission circuit (system 0). ) A processing unit that transmits to 17A.
The frame multiplexing unit (system 1) 16B multiplexes the downlink frame addressed to the ONU (system 1) from the frame transfer processing unit 20 and the control frame from the control frame processing unit 14 in a time division manner, and transmits the transmission circuit (system 1). ) A processing unit that transmits to 17B.

  Based on the SNI selection information corresponding to the LLID of the upstream frame acquired from the LLID table 23, the frame transfer processing unit 20 receives the upstream frame received by the reception circuit 12 and input from the frame separation unit 13 from the transmission / reception circuit 18A. , 18B (0 system or 1 system), and the downstream frame received by the transmission / reception circuits 18A, 18B is converted into the downstream output destination selection information corresponding to the downstream frame VID acquired from the VID table 35. Based on this, it is a processing unit that performs a transfer process to one of the frame multiplexing units 16A and 16B (system 0 or system 1).

The control frame processing unit 14 is a processing unit that performs processing related to PON control such as discovery processing (Discovery process) for automatically assigning LLIDs to each ONU and arbitration of upstream signals (signals addressed to the OLT from the ONUs). .
The band allocation processing unit 15 is a processing unit that allocates a band (transmission start time and transmission data amount) to the ONU in accordance with a request from the control frame processing unit 14.

  In the present embodiment, one or more constant power supply blocks and one or more power saving blocks are provided in advance as blocks for performing power control of each circuit unit constituting the OLT 10. In the configuration example of FIG. 3, each circuit unit constituting the OLT 10 is divided into one constant power supply block B0 and two power saving blocks B1A and B1B.

  The constant power supply block B0 is always supplied with power when the OLT is used. The PON port 11, the receiving circuit 12, the frame separation unit 13, the control frame processing unit 14, the bandwidth allocation processing unit 15, the frame multiplexing unit ( 0A) 16A, frame multiplexing unit (1 system) 16B, transmission circuit (0 system) 17A, transmission circuit (1 system) 17B, SNI port (0 system) 19A, SNI port (1 system) 19B, and frame transfer A part of the processing unit 20 (see FIG. 4) belongs.

The power saving block (0 system SNI) is a block that can stop power supply when the 0 system SNI is not in operation, and is a part of the transmission / reception circuit (0 system) 18A and the frame transfer processing unit 20 (see FIG. 4) ) Belongs to.
The power saving block (system 1 SNI) is a block that can stop power supply when the system 1 SNI is not in operation, and is a part of the transmission / reception circuit (system 1) 18B and the frame transfer processing unit 20 (see FIG. 4). ).

  The power supply unit 49 has a function of supplying power to the power supply block B0 through the power supply line 49L, and a function of supplying power to the power saving block B1A through the power supply line 49L and the power switch (0 system SNI) 41A. And a function of supplying power to the power saving block B1B via the power supply line 49L and the power switch (1-system SNI).

  The power control unit 40 outputs a control signal (0 system SNI) S1A and a control signal (1 system SNI) S1B based on a user setting input from the outside of the OLT 10, and thereby the power switch 41A and the power switch It has a function of individually controlling the opening and closing of 41B.

  There are three user settings, which are selected and set from the outside of the OLT 10 according to the operating state of the SNI. Among these, the first mode is a mode in which power is supplied to the power saving block B1A and power supply to the power saving block B1B is stopped. The second mode is a mode in which power supply to the power saving block B1A is stopped and power is supplied to the power saving block B1B. In the third mode, power is supplied to both the power saving blocks B1A and B1B.

  Next, the frame transfer processing unit 20 used in the OLT according to the present embodiment will be described in detail with reference to FIGS. FIG. 5 is a configuration example of the LLID table. FIG. 6 is a flowchart showing an upstream frame output destination SNI determination procedure. FIG. 7 is a configuration example of the VID table. FIG. 8 is a flowchart showing a procedure for determining an output destination of a downstream frame.

First, the operation in which the frame transfer processing unit 20 determines the output destination of the upstream frame will be described.
If the upstream frame received at the PON port 11 is not a PON control frame, the frame transfer processing unit 20 determines to which provider network NW the received upstream frame is to be output as follows.

The frame transfer processing unit 20 includes an LLID table 23 as shown in FIG. In the LLID table 23, entry valid / invalid and SNI selection information are registered for each LLID of the ONU. The entry valid / invalid is information indicating validity / invalidity of the entry, that is, registered / unregistered of the LLID.
The output destination SNI determination unit 22 reads the SNI selection information from the LLID table 23 based on the LLID of the upstream frame, determines the output destination SNI by the procedure of FIG. 6, and determines the output destination SNI information as the upstream output destination control. Part 24 is given.

In the uplink frame output destination SNI determination procedure in FIG. 6, the output destination SNI determination unit 22 first determines whether the LLID in the LLID table 23 is based on the LLID entry validity / invalidity of the received uplink frame. (Step 100).
Here, when the “valid” state is set as the entry valid / invalid, that is, when the LLID is registered (step 100: YES), the output destination SNI determination unit 22 reads the LLID from the LLID table 23. SNI selection information corresponding to is acquired and specified as an output destination of a downstream frame (step 101), and a series of processing ends.

  On the other hand, when the “invalid” state is set as the entry valid / invalid, that is, when the LLID of the received upstream frame is not registered in the LLID table 23 (step 100: NO), the output destination SNI determining unit 22 Then, discard of the uplink frame is determined (step 102), and a series of processing is terminated.

In parallel with such an upstream frame output destination SNI determination procedure, the upstream latency absorption unit 21 adds a delay to the received upstream frame and absorbs the latency due to the output destination SNI determination process in the output destination SNI determination unit 22. To do.
The uplink output destination control unit 24 transfers the uplink frame from the uplink latency absorbing unit 21 to the corresponding uplink output timing adjustment units 25A and 25B according to the SNI selection information determined by the output destination SNI determination unit 22.

Upstream output timing adjustment units 25A and 25B are provided for each of the transmission / reception circuits 18A and 18B, and adjust the output order of each upstream frame based on the priority determined by the PCP included in each upstream frame. The upstream frame from the upstream output destination control unit 24 is transferred to the corresponding transmission / reception circuits 18A and 18B.
When frame discard is notified from the output destination SNI determination unit 22, the uplink output destination control unit 24 performs discard processing on the uplink frame.

  The values in the LLID table 23 are set by determining which network NW1 or NW2 is connected by external hardware or software (not shown in FIG. 3) when the ONU is registered in the control frame processing unit 14. For example, in a system in which 10G-ONU and 1G-ONU are mixed and one of the SNIs is for 10G-Ethernet, and the other is for 1G-Ethernet, the 10G-ONU SNI for 10G-Ethernet, 1G- For the ONU, an SNI for 1G-Ethernet can be specified.

Next, the operation in which the frame transfer processing unit 20 determines the output destination of the downstream frame will be described.
The frame transfer processing unit 20 determines from which transmission circuit 17A, 17B the received downlink frame is transmitted, that is, to which downlink system having a different speed, the data is output as follows.

  The frame transfer processing unit 20 includes a VID table 35 as shown in FIG. In the VID table 35, LLID, downlink output destination selection information, and entry valid / invalid are registered for each VID. VID (VLAN Identifier) is a value that specifies the VLAN to which the downlink frame belongs. The entry valid / invalid is information indicating the validity / invalidity of the entry, that is, the registered / unregistered of the VID.

  The downlink output destination determination unit (system 0) 34A and the downlink output destination determination unit (system 1) 34B are provided for each of the transmission / reception circuits 18A and 18B, and based on the received VID of the downstream frame, the LLID is obtained from the VID table 35. And the downlink output destination selection information are read out, and the assigned LLID and output destination of the downlink frame are determined by the procedure of FIG. The information of the determined LLID is given as the destination LLID to the LLID giving unit (0 system) 32A and the LLID giving unit (1 system) 32B of the corresponding system.

In the downlink output destination determination procedure of the downlink frame in FIG. 8, the downlink output destination determination units 34A and 34B first confirm whether or not the VLAN tag is included in the received downlink frame (step 110).
Here, when the VLAN tag is included (step 110: YES), the downlink output destination determination units 34A and 34B, based on the validity / invalidity of the VID entry of the received downlink frame in the VID table 35, It is confirmed whether or not the VID is registered in the VID table 35 (step 111).

  Here, when the “valid” state is set as the entry valid / invalid, that is, when the VID is registered (step 111: YES), the downlink output destination determination units 34A and 34B The LLID corresponding to the VID is acquired and specified as the destination LLID of the downlink frame (step 112), the downlink output destination selection information corresponding to the VID is acquired from the VID table 35, and the output system of the downlink frame is determined. Specify (step 113) and end the series of processing.

  On the other hand, if no VLAN tag is included in the received downlink frame in step 110 (step 110: NO), or if “invalid” state is set as entry valid / invalid in step 111, that is, receive If the downstream frame VID is not registered in the VID table 35 (step 111: NO), the downstream output destination determination units 34A and 34B decide to discard the downstream frame (step 114) and end the series of processes. To do.

In parallel with the downlink output destination determination procedure for the downlink frame, the downlink latency absorbing unit (system 0) 31A and the downlink latency absorbing unit (system 1) 31B provided for each of the transmission / reception circuits 18A and 18B receive A delay is added to the downstream frame to absorb the latency due to the downstream output destination determination processing in the downstream output destination determination units 34A and 34B.
The LLID assigning unit (0 system) 32A and the LLID providing unit (1 system) 32B are provided for each of the transmission / reception circuits 18A and 18B, and the downlink latency absorbing unit 31A according to the LLID determined by the downlink output destination determination units 34A and 34B. , 31B, the destination LLID is assigned to the downstream frame.

  The downlink output destination control unit (system 0) 33A and the downlink output destination control unit (system 1) 33B are provided for each of the transmission / reception circuits 18A and 18B, and follow the output destination information determined by the downlink output destination determination units 34A and 34B. Downstream from the LLID adding units 32A and 32B to the transmission circuits 17A and 17B corresponding to the downlink output destination selection information via the corresponding 0-system downlink output timing adjustment unit 36A or 1-system downlink output timing adjustment unit 36B. Forward the frame.

The downlink output timing adjustment unit (system 0) 36A and the downlink output timing adjustment unit (system 1) 36B are provided for each downlink transmission speed (downlink transmission system), and the priority of PCP and the like included in the downlink frame The downstream frame is transferred to the corresponding transmission circuits 17A and 17B via the corresponding frame multiplexing unit (0 system) 16A and the frame multiplexing unit (1 system) 16B by adjusting the output order of each downstream frame based on To do. For example, in a system in which 10G-ONU and 1G-ONU coexist, 10G (802.3av specification) output may be specified for 10G-ONU, and 1G (802.3ah specification) output may be specified for 1G-ONU.
When the downlink output destination determination units 34A and 34B determine that the packet is to be discarded, the downlink output destination control units 33A and 33B perform a process of discarding the downlink frame.

  When a downlink frame is transferred from the 0-system downlink output destination control unit 33A to the 1-system downlink output timing adjustment unit 36A, or from the 1-system downlink output destination control unit 33B to the 1-system downlink output timing adjustment unit 36B An example of a case where a downstream frame is transferred includes a system in which GE-PON and 10G-EPON coexist. In the present invention, the 0 system indicates a transmission system with a downlink transmission rate of 1 Gbps, and the 1 system indicates a transmission system with a downlink transmission rate of 10 Gbps.

In such a case, when the destination user apparatus of the downlink frame having a downlink transmission rate of 10 Gbps input from the SNI port (system 1) is under the GE-PON ONU, the OLT 10 transmits the downlink transmission rate of 1 Gbps from the PON port 11. It is necessary to output as a frame for GE-PON.
For this purpose, the frame transfer processing unit 20 needs to output the downlink frame received from the 1 system from the 0 system. Such a technique is necessary in the transition period from GE-PON to 10G-EPON.

  The values in the VID table 35 are determined and set by the external hardware or software (not shown in FIG. 4) when the ONU is registered in the control frame processing unit 14.

  In the downstream processing, it is necessary to process the frames input from the two transmission / reception circuits 18A and 18B in parallel. However, as shown in the configuration of FIG. The frame input throughput can be used up to the upper limit. At this time, since the upper limit of throughput when the 10G output is 802.3av specification is about 8.7 Gbps, the upper limit of the throughput of the SNI input for 10G output in that case is about 8.7 Gbps.

The frame transfer processing unit 20 includes a portion belonging to the constant power supply block B0, the power saving block (0 system) B1A, and the power saving block (1 system) B1B.
Among these, the constant power supply block B0 belongs to the uplink latency absorbing unit 21, the output destination SNI determining unit 22, the LLID table 23, the uplink output destination control unit 24, the VID table 35, and the downlink output timing adjustment unit (system 0) 36A. , A downlink output timing adjustment unit (system 1) 36B.

Further, the power saving block B1A belongs to the uplink output timing adjustment unit (system 0) 25A, the downlink latency absorption unit (system 0) 31A, the LLID provision unit (system 0) 32A, and the circuit output control unit (system 0). 33A, a downstream output destination determination unit (system 0) 34A.
The power saving block B1B belongs to the upstream output timing adjustment unit (system 1) 25B, the downstream latency absorption unit (system 1) 31B, the LLID provision unit (system 1) 32B, and the downstream output destination control unit (system 1). 33B, a downstream output destination determination unit (system 1) 34B.

Therefore, when the first mode is selected in the user setting, the power switch 41A is closed by the control signal S1A, power is supplied to the power saving block B1B, and the power switch 41B is opened by the control signal S1B. The power supply to the power saving block B1B is stopped.
When the second mode is selected, the power switch 41A is opened by the control signal S1A, the power supply to the power saving block B1A is stopped, and the power switch 41B is closed by the control signal S1B. Power is supplied to the power saving block B1B.
When the third mode is selected, the power switch 41A is closed by the control signal S1A, and the power switch 41B is closed by the control signal S1B, so that power is supplied to both the power saving blocks B1A and B1B. .

[Effect of the first embodiment]
As described above, in this embodiment, when the SNI selection information corresponding to the LLID is registered for each LLID of the ONU in the LLID table 23 and an upstream frame is received from the ONU, the frame transfer processing unit 20 The SNI selection information corresponding to the LLID of the uplink frame is obtained from the LLID table 23. Also, when the LLID corresponding to the VID and the downlink output destination selection information are registered for each VID in the VID table 35 and a downlink frame is received from the host device, the frame transfer processing unit 20 uses the input SNI port 19A. , 19B, the LLID corresponding to the VID of the uplink frame and the downlink output destination selection information are acquired from the VID table 35 in parallel.

  As a result, when the OLT is connected to a plurality of higher-level devices via the SNI provided for each higher-level device, an upstream frame received from any ONU connected to the PON system Can be transferred to the device. Further, it is possible to process downstream frames input via the plurality of SNI ports 19A and 19B in parallel for each of the input SNI ports 19A and 19B and transfer them to the destination ONU.

  Therefore, a port for each SNI is provided between each ONU of the PON system and each higher-level device and further each carrier network without a switch between the OLT 10 and the plurality of SNIs. One OLT 10 can transfer a frame. For this reason, it is possible to avoid sharing the downstream band of the switch among the higher-level devices, and to avoid restrictions on the downstream bandwidth that can be used by the individual higher-level devices.

  In this embodiment, in a system in which 10G-ONU and 1G-ONU are mixed, when one of the SNIs is for 10G-Ethernet and the other is for 1G-Ethernet, the 10G-ONU is the SNI for 10G-Ethernet. For 1G-ONU, an SNI for 1G-Ethernet can be used. As a result, PON systems with different communication speeds can be constructed with one OLT.

  In this case, all frames input from the 10G-Ethernet SNI are destined for the 10G-ONU, and all frames input from the 1G-Ethernet SNI are destined for the 1G-ONU. It is possible to use the downlink transfer capability (downlink transmission rate) of the section up to the upper limit. As a result, unlike the conventional configuration of FIG. 19, the downstream band is not shared by the two higher-level devices.

  When the downlink output addressed to 10G-ONU is 802.3av specification, the upper limit of the downlink throughput in the PON section is about 8.7 Gbps, so the upper limit of the throughput of the SNI input for 10G-ONU in that case is about 8.7 Gbps. Downstream bandwidth limitation is necessary in the host device for 10G-ONU. However, this band limitation is the same even when only one host device for 10G-ONU is connected, and the effectiveness of the present invention is not denied.

If an OLT having only one 10G-Ethernet SNI is configured in the prior art, the upper limit of the downlink throughput when the 802.3av specification and the 802.3ah specification are mixed is approximately the same as the present invention. Although 8.7 Gbps + 1 Gbps = about 9.7 Gbps, a switch or the like is required to connect to a plurality of host devices.
Also, in this embodiment, if the specification of the downlink output addressed to 10G-ONU is changed to a specification that enables throughput of 10 Gbps instead of 802.3av specification, 10G-ONU and 1G-ONU are mixed The maximum downstream downlink throughput is 10 Gbps + 1 Gbps = 11 Gbps, and no downstream bandwidth limitation is required in the host device.

  When the frame transfer processing unit 20 is configured as shown in FIG. 4, it is possible to use a 10G-Ethernet SNI as the 1G-ONU SNI. However, in this case, it is necessary for the host device to limit the downstream band to 1 Gbps or less. Conversely, a 1G-Ethernet SNI can be used as a 10G-ONU SNI. In this case, the downlink transfer capability in the PON section cannot be used up to the upper limit.

  Moreover, although this Embodiment demonstrated as an example the system in which 10G-ONU and 1G-ONU were mixed, it is not limited to this. For example, the ONU to be accommodated is only a 10G-ONU, but the present invention can also be applied when connecting to different networks for each ONU. The OLT in this case may be equipped with a plurality of 10G-Ethernet SNIs and a plurality of downstream PON outputs equivalent to the 802.3av specification. However, the downstream wavelength may be changed for each downstream output port, and may be changed for each higher-level network to which the WDM filter mounted on the ONU is connected as necessary.

  In the present embodiment, one or more constant power supply blocks B0 and one or more power saving blocks B1A and B1B are provided as power supply control blocks for each circuit unit, and the power supply control unit 40 uses the constant power supply block B0. The power supply is always supplied to the circuit units belonging to, and the power supply / stop of the circuit units belonging to the power saving blocks B1A and B1B is controlled according to the operation of the power saving block.

  Specifically, in the power control unit 40, based on the setting from the outside indicating the operation state of each SNI, the power saving block (0 system SNI) B1A and the power saving block (1 system SNI) B1B are operated. Power is supplied to the power saving block to which the transmission / reception circuit (18A or 18B) connected to the intermediate SNI belongs, and to the power saving block to which the transmission / reception circuit (18B or 18A) connected to the non-operating SNI belongs. The power supply is stopped.

  At this time, the power supply control unit 40, based on an external setting indicating the operation state of each SNI, of the power saving blocks B1A and B1B, the upstream output timing adjustment unit (25A or 25B) corresponding to the SNI in the operation state ) May be supplied to the power saving block to which the power saving block belongs, and the power supply to the power saving block to which the upstream output timing adjustment unit (25B or 25A) corresponding to the non-operating SNI belongs may be stopped.

  As a result, when there is an SNI in an unoperated state among SNIs connected to the OLT 10, it is possible to stop power supply to a circuit related to frame transmission / reception between the non-operated SNI and the OLT 10. Therefore, the power consumption in the circuit unit connected to the non-operating SNI port of the SNI ports 19A and 19B can be omitted, and the power consumption of the entire OLT 10 can be reduced.

  In general, depending on the operation status of the SNI, an SNI that has not been operated once may not be operated again, or may be temporarily operated during operation of the OLT 10. If an SNI that has become non-operating is not operated again, not only the power-saving block on the non-operating SNI side but also the power supply to the SNI port (19A or 19B) on the non-operating SNI side is stopped to save power. be able to. For example, in a system in which a host device for 1G-Ethernet (0 system) and a host device for 10G-Ethernet (1 system) are used together, when the host device for 1G-Ethernet (0 system) is abolished, the 0 system The SNI port can save power.

  Therefore, when any SNI is temporarily unnecessary during the operation of the OLT 10 by the power supply control unit 40, the power supply to the power saving block on the SNI side is stopped and the SNI is operated again. In this case, the power supply to the power saving block on the SNI side is resumed.

  Usually, in the Ethernet (registered trademark) standard specification for an interface of 100 Mbps or more, it is necessary to keep the line active even in an idle state. Therefore, it is necessary to operate the SNI ports 19A and 19B regardless of the presence or absence of data on the link. In FIG. 3, the SNI ports 19A and 19B are not included in the power saving block. However, when the host device is compatible with the power saving mode of the SNI ports 19A and 19B of the OLT 10, not only the power saving block but also the SNI ports 19A and 19B can be saved. For example, if both the host device and the OLT 10 are compatible with IEEE 802.3az, it is possible to save power in the SLT port of the OLT 10.

When the power supply to the power saving blocks B1A and B1B and the SNI ports 19A and 19B on the SNI side where the power supply is stopped is restarted, the activation control unit 48 generates an instruction signal for starting the circuit unit in a predetermined procedure. It has a function of outputting to the power supply control unit 40.
The activation control unit 48 monitors output signals such as frames output from each circuit unit, and by checking the presence / absence and normality of the output signal, its own circuit unit normally operates as the power is turned on. It has a function of confirming that it has started and starting each circuit part in turn. In the following procedure, x represents either A or B.

Procedure 1: Power-up procedure of upstream output timing adjustment unit 25x Procedure 2: Confirmation that upstream output timing adjustment unit 25x has started normally Procedure 3: Power-up procedure of upstream signal transmission circuit (not shown) in transmission / reception circuit 18x 4: Confirm that the upstream signal transmission circuit in the transmission / reception circuit 18x has started up normally. Procedure 5: Turn on the power of the SNI port 19x. Procedure 6: The SNI port 19x starts up normally and frame transmission / reception with the host device is possible. Confirmation procedure 7: Power-on procedure of downstream signal reception circuit (not shown) in the transmission / reception circuit 18x Procedure 8: Confirmation that the downstream signal reception circuit in the transmission / reception circuit 18x has started normally Procedure 9: Frame transfer Other circuits in the processing unit 20 (downlink latency absorbing unit 31x, LLID adding unit 32x, downlink output destination control unit 33x, downlink output destination determination unit 34x) Power-on Step 10: Check that the other circuits of the frame transfer processing unit 20 starts successfully

  As a result, the circuit unit can be activated in order from the frame transmission source side to the frame transmission destination side along the path through which the frame passes, and even when power is re-supplied to a specific power saving block, It is possible to start the operation of each circuit section stably.

  In the present embodiment, not only the power saving blocks B1A and B1B on the SNI side described above, but also a power saving block (0 system PON) and a power saving block (1 system PON) are provided on the PON side. Then, based on the setting from the outside indicating the operating state of each downlink transmission rate, the power supply to the power saving block to which the transmission circuit (17A or 17B) corresponding to the downlink transmission rate in the operating state belongs, among these power saving blocks. And the power supply to the power saving block to which the transmission circuit (17B or 17A) corresponding to the downlink transmission speed in the non-operating state belongs may be stopped.

  At this time, in the power supply control unit 40, if there is an unused downlink transmission rate among the downlink transmission rates based on the setting from the outside indicating the operation state of each downlink transmission rate, the frame transfer processing unit 20 The power supply to the downlink output destination determining unit (34A or 34B), the LLID adding unit (32A or 32B), and the downlink output destination control unit (33A or 33B) corresponding to the unused downlink transmission rate may be stopped. Good.

  As a result, among the downlink transmission rates (downlink transmission systems) used in the OLT 10, for example, the OLT 10 supports both 1G and 10G as the downlink transmission rate, but is not yet connected to the 1G-ONU. When there is a downstream transmission speed in the state, power supply to the circuit unit corresponding to the unoperated downstream transmission speed can be stopped. Therefore, it is possible to save power consumption in the circuit unit corresponding to the downlink transmission speed in an unoperated state, and it is possible to reduce power consumption of the entire OLT 10.

[Second Embodiment]
Next, the OLT 10 according to the second embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram illustrating a configuration of the OLT according to the second embodiment.
Compared with FIG. 3 described above, the OLT 10 according to the present embodiment separates the LLID table 23 from the power supply block B0 as the power saving block B3 and connects to the power supply unit 49 via the power switch 43. The difference is that the power supply is controlled more finely in the power saving block B3 by the control signal S3 from the power control unit 40.

FIG. 10 is a block diagram illustrating a configuration example of a frame transfer processing unit according to the second embodiment. FIG. 11 is a configuration example of an LLID table according to the second embodiment.
In the configuration example of FIG. 11, the LLID table 23 is a table in which a maximum of 32768 LLIDs (LLID = 0x0000 to 0x7FFF) can be registered, and four memories (storage units) # L1, # L2, # L3, # L4 It is divided and implemented. In this case, one memory (storage unit) is composed of one or a plurality of storage circuits (semiconductor memories). In particular, when one memory is constituted by a plurality of storage circuits, power supply control is collectively performed on these storage circuits. Note that the number of memories is not limited to four. Basically, if the LLID table 23 is divided into a plurality of memories, the present embodiment can be applied, and similar effects can be obtained. It is done.

In FIG. 11, LLID = 0x0000-0x1FFF is stored in memory # L1, LLID = 0x2000-0x3FFF is stored in memory # L2, LLID = 0x4000-0x5FFF is stored in memory # L3, and LLID = 0x6000-0x7FFF is stored in memory # L4. Is stored.
Each memory # L1 to # L4 is supplied with power from the power supply unit 49 via a power supply line 49L and a power switch 43 (43A, 43B, 43C, 43D) provided for each of the memories # L1 to # L4. Is done.

Opening and closing of the power switches 43A to 43D is controlled by # L1, # L2, # L3, # L4 of the control signal S3 from the power control unit 40. The power control unit 40 outputs control signals # L1 to # L4 addressed to the power switches 43A to 43D based on user settings from outside the OLT 10.
For example, when only LLID = 0x0000 to 0x3FFF is used, the power switches 43A and 43B are closed by the control signals # L1 and # L2, and the power is supplied to the memories # L1 and # L2, and the control signals # L3 and # L4 are used. The power switches 43C and 43D are opened to stop the power supply to the memories # L3 and # L4.

[Effect of the second embodiment]
As described above, in the present embodiment, the LLID table 23 is configured by a plurality of memories (storage units) # L1 to # L4, and the power supply control unit 40 is based on the setting from the outside indicating the use state of each memory. Among these memories, power is supplied to the memory in use, and power supply to the memory in unused is stopped.
Thereby, according to the number of LLID used among the memory which comprises the LLID table 23, the power supply to the memory which does not contain registration LLID can be stopped, and it is possible to reduce the power consumption of OLT10. Become.

[Third Embodiment]
Next, with reference to FIG. 12, an OLT 10 according to a third embodiment of the present invention will be described. FIG. 12 is a configuration example of a frame and a discard instruction signal according to the third embodiment.
In this embodiment, the configuration of the frame is the same as in FIG. 2 described above, but a discard instruction signal indicating the necessity of discard is transmitted between the circuit units in parallel with the end of the frame as a parallel signal of the frame. The difference is that the frame transfer processing unit 20 discards the discard target frames in a batch based on the discard instruction signal. Hereinafter, a frame having a discard instruction signal “1” is referred to as a discard instruction-added frame.

  In general, each circuit unit of the OLT confirms the normality of the frame in order to properly execute the processing for the input frame. If the normality cannot be confirmed, the frame is determined to be a discard target frame to be discarded. To do. In the conventional OLT, a frame determined to be a discard target frame is discarded by the circuit unit that performed the determination.

  However, the discard determination process for determining whether or not to discard the frame is completed after the frame data to be referenced is input to the circuit unit. For example, when it is determined whether or not the frame length is within a specified range, a determination result is output after the end of the frame is input to the circuit unit. Therefore, the frame needs to be buffered until the discard determination process is completed, and a delay occurs when the frame is transmitted to the subsequent circuit unit.

  FIG. 13 is a time chart showing the relationship between the upstream frame and the discard determination when the circuit unit determined to discard the frame discards the frame. The discard determination result “1” represents “discard”. In the case of FIG. 13, in all the circuit units (the receiving circuit 12 and the frame transfer processing unit 20) that perform the determination processing, delay due to frame buffering for discarding processing occurs. Note that TL in the figure is a latency generated in the frame separation unit 13.

  In this case, the uplink frame is applicable when the frame transfer processing unit 20 reads the LLID table 23 except when the reception circuit 12 can determine the frame length when it is out of the specified range or when an FCS error is detected. If the LLID is not registered, it is determined to be discarded. Therefore, if the receiving circuit 12 discards due to an FCS error or the like, and discards due to unregistration in the LLID table 23 in the frame transfer processing unit 20, it is necessary to perform buffering for discard determination twice. There will be a delay for two bufferings.

For this reason, a method may be considered in which frames determined to be discarded are not discarded by the determined circuit unit, but are sequentially transferred to the subsequent stage in the same manner as normal frames, and are collectively discarded by the subsequent circuit unit.
Specifically, in the upstream upstream circuit unit that performs upstream frame processing prior to the circuit unit that discards upstream discard target frames at once, if it is determined that upstream frame discard is necessary, or is input to the circuit unit When the upstream frame discard instruction signal is “1”, the upstream upstream circuit unit outputs the upstream frame without discarding, and at the same time, for example, the discard instruction signal “1” with a pulse of 1 clock width of the synchronization clock signal. In other cases, the discard instruction signal “0” may be output in parallel with the uplink frame.

Also for downstream frames, if it is determined that downstream frame discard is required in the downstream upstream circuit unit that performs processing related to downstream frames before the circuit unit that discards downstream discard target frames, or is input to the circuit unit When the downstream frame discard instruction signal is “1”, the downstream pre-stage circuit unit outputs the downstream frame without discarding, and at the same time, for example, a discard instruction signal “1 clock width pulse of the synchronization clock signal”. 1 ”is output in parallel. In other cases, the discard instruction signal“ 0 ”is output in parallel with the downstream frame.
Note that the discard instruction signal is output at the end of the output frame in consideration of the case where the discard determination extends to the end of the frame.

  As a result, for example, if the upstream output timing adjustment units 25A and 25B and the downstream output timing adjustment units 36A and 36B of the frame transfer processing unit 20 perform the discard processing of the frame with the discard instruction, Delays in disposal processing in each circuit unit can be absorbed.

  However, according to this method, since the discard target frame flows through each circuit unit in the same manner as the normal frame, the discard target frame is disposed between the circuit unit that has determined discard of the frame and the circuit unit that executes the discarding process. In each circuit unit, wasteful processing for the discard target frame is executed in the same manner as the normal frame. For this reason, this wasteful processing causes wasteful power consumption.

  On the other hand, in this embodiment, when the frame transfer processing unit 20 determines that the upstream frame is a discard target frame by the circuit unit that performs processing related to the upstream frame before itself, The process of acquiring the SNI selection information of the uplink frame is not performed, and the uplink frame is discarded.

  In addition, when the frame transfer processing unit 20 determines that the downstream frame is a frame to be discarded before the downstream frame is processed by the circuit unit that performs processing related to the downstream frame, the frame transfer processing unit 20 obtains the output destination selection information of the downstream frame input to itself And / or processing for assigning the output destination selection information to the downlink frame is not performed, and the downlink frame is discarded.

As a result, the frame transfer processing unit 20 can avoid the execution of the process for the frame with the discard instruction by confirming the discard instruction signal.
Therefore, it is possible to avoid performing useless processing on the discard target frame and to save power consumption generated by the useless processing. Therefore, the power consumption of the entire OLT 10 can be reduced.

Hereinafter, a specific processing operation including processing avoidance for a frame with a discard instruction in the frame transfer processing unit 20 will be described.
FIG. 14 is a flowchart illustrating an upstream frame output destination SNI determination procedure according to the third embodiment. This is different from FIG. 6 described above in that a discard instruction signal is confirmed before step 100.
First, the output destination SNI determination unit 22 confirms the received uplink frame discard instruction signal. If the uplink frame discard instruction signal indicates “0” and the received uplink frame is not a discard instruction-added frame (step 500: YES), the output destination SNI determination unit 22 executes the same processing as in FIG.

  On the other hand, when the upstream frame discard instruction signal indicates “1” and the received upstream frame is a frame with a discard instruction (step 500: NO), the output destination SNI determination unit 22 determines to discard the upstream frame. (Step 102), and a series of processing ends. As a result, the received upstream frame is transferred from the output destination SNI determination unit 22 to the subsequent stage as a frame with a discard instruction.

FIG. 15 is a flowchart of a downlink frame output destination determination procedure according to the third embodiment. This is different from FIG. 8 described above in that a discard instruction signal is confirmed before step 110.
First, when the received downlink frame discard instruction signal indicates “0” and the received downlink frame is not a discard instruction-added frame (step 510: YES), the downlink output destination determination units 34A and 34B indicate the downlink output destination. The determination units 34A and 34B execute the same process as in FIG.

  On the other hand, when the downlink frame discard instruction signal indicates “1” and the received downlink frame is a frame with a discard instruction (step 510: NO), the downlink output destination determination units 34A and 34B discard the downlink frame. Is determined (step 114), and the series of processing ends. Thereby, the received downlink frame is transferred from the downlink output destination determination units 34A and 34B to the subsequent stage as a frame with a discard instruction.

[Effect of the third embodiment]
As described above, in the present embodiment, when the frame transfer processing unit 20 determines that the uplink frame is a discard target frame by the circuit unit that performs processing related to the uplink frame before itself, the uplink input to the frame transfer processing unit 20 The process of acquiring the SNI selection information of the frame is not performed, and the uplink frame is discarded.

  In addition, when the frame transfer processing unit 20 determines that the downstream frame is a frame to be discarded before the downstream frame is processed by the circuit unit that performs processing related to the downstream frame, the frame transfer processing unit 20 obtains the output destination selection information of the downstream frame input to itself And / or processing for assigning the output destination selection information to the downlink frame is not performed, and the downlink frame is discarded.

As a result, frames determined to be discarded can be sequentially transferred to the subsequent stage in the same manner as normal frames without being discarded by the determined circuit unit, and can be discarded at once by the frame transfer processing unit 20 at the subsequent stage. Therefore, it is possible to absorb a delay associated with the discarding process in each circuit unit preceding the frame transfer processing unit 20.
Further, in the frame transfer processing unit 20, it is possible to avoid execution of useless processing on the discard target frame, and it is possible to omit power consumption generated in the useless processing. Therefore, the power consumption of the entire OLT 10 can be reduced.

  FIG. 16 is a time chart showing a relationship (delay priority) between an uplink frame, a discard instruction signal, and discard determination. In the case of FIG. 16, only the frame transfer processing unit 20 that performs batch discard processing lastly causes a delay due to frame buffering for discard processing. This is because, when discarding by the upstream output timing adjustment units 25A and 25B, the frame is buffered for determination processing by the output destination SNI determination unit 22 and confirmation of the presence or absence of a discard instruction at the end of the input frame. .

On the other hand, in the upstream upstream timing adjustment units 25A and 25B, for example, the receiving circuit 12 starts output of the frame being determined before the discard determination result is confirmed as shown in FIG. There is no delay due to frame buffering for discard processing.
Therefore, by discarding the frame at once with only one circuit in the frame transfer processing unit 20, for example, the upstream output timing adjustment unit (or the downstream output timing adjustment unit), buffering for discard determination is only required once. , Delay due to frame discard can be minimized. In addition, basically, since the frame output from the uplink output timing adjustment unit (or the downlink output timing adjustment unit) is not discarded, when the frame discard process is performed by only one circuit, the uplink output timing adjustment unit ( Alternatively, it can be performed by a downlink output timing adjustment unit).

  In the frame transfer processing unit 20, the output destination SNI determination unit 22 determines the output destination SNI of the input frame. When this output destination SNI determination process is performed, not all data up to the end of the frame is required. Therefore, if the output destination SNI determination process is started from the beginning of the frame, the determination result can be obtained before the end of the frame arrives, as shown in FIG. This determination result indicates any one SNI as an output destination. However, the output destination SNI may not be determined due to a frame error. In this case, a determination result that the frame is discarded is output.

Therefore, based on the logical sum of the determination result from the output destination SNI determination unit 22 generated by the upstream output destination control unit 24 and the discard instruction signal from the reception circuit 12, for example, the upstream output timing adjustment unit 25 Frame discard processing is performed.
For this reason, the frame transfer processing unit 20 can execute the frame output to the subsequent stage or the frame discarding process with little delay from the end of the input frame, and the delay in the frame transfer processing unit 20 can be minimized. However, since the output destination SNI determination process in the output destination SNI determination unit 22 is always executed even when the discard instruction signal from the receiving circuit 12 indicates discard, unnecessary power is consumed accordingly.

On the other hand, the output destination SNI determination processing in the output destination SNI determination unit 22 may be started after a discard instruction signal from the receiving circuit 12, for example. FIG. 17 is a time chart showing the relationship (upper power saving priority) between the uplink frame, the discard instruction signal, and the discard determination.
In the case of FIG. 17, since the start timing of the output destination SNI determination process is delayed, the delay in the frame transfer processing unit 20 is larger than that in FIG. For example, in a frame having a communication speed of 1 Gbps and a length of 2000 bytes, it takes about 16 microseconds from arrival at the beginning of the frame to arrival at the end of the frame.

However, when the discard instruction signal from the receiving circuit 12 indicates discard, the output destination SNI determination processing in the output destination SNI determination unit 22 can be omitted. As a result, it is possible to reduce power consumption required for the output destination SNI determination process.
As described above, the upstream frame output destination determination processing in the frame transfer processing unit 20 cannot simultaneously satisfy the delay reduction due to the frame discard and the power reduction when the frame with the discard instruction is input. Therefore, a configuration that prioritizes either delay or power consumption may be selected according to the actual operation using the OLT 10. The same applies to the output destination determination processing of the downstream frame.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  Further, in each of the above embodiments, the case where the power consumption is reduced by stopping the power supply to the power saving block has been described as an example. However, the present invention is not limited to this. For example, the power saving may be performed by stopping the supply of the clock signal for processing operation input for each power saving block, and the same effects as those of the above-described embodiments can be obtained.

  DESCRIPTION OF SYMBOLS 100 ... PON system, 10 ... OLT, 11 ... PON port, 12 ... Reception circuit, 13 ... Frame separation part, 14 ... Control frame processing part, 15 ... Band allocation processing part, 16A ... Frame multiplexing part (system 0), 16B ... Frame multiplexing unit (1 system), 17A ... Transmission circuit (0 system), 17B ... Transmission circuit (1 system), 18A ... Transmission / reception circuit (0 system), 18B ... Transmission / reception circuit (1 system), 19A ... SNI port ( 0 system), 19B ... SNI port (1 system), 20 ... frame transfer processing section, 21 ... uplink latency absorbing section, 22 ... output destination SNI determining section, 23 ... LLID table, 24 ... uplink output destination control section, 25A ... Upstream output timing adjustment unit (system 0), 25B ... Upstream output timing adjustment unit (system 1), 31A: Downstream latency absorption unit (system 0), 31B: Downstream latency absorption unit (system 1), 3 A ... LLID assigning unit (system 0), 32B ... LLID assigning unit (system 1), 33A ... downstream output destination control unit (system 0), 33B ... downstream output destination control unit (system 1), 34A ... downstream output destination determination Part (0 system), 34B ... downlink output destination determination part (1 system), 35 ... VID table, 36A ... downlink output timing adjustment part (0 system), 36B ... downlink output timing adjustment part (1 system), 40 ... power supply Control unit, 41A ... power switch (0 system SNI), 41B ... power switch (1 system SNI), 43, 43A, 43B, 43C, 43D ... power switch, 48 ... start control unit, 49 ... power supply unit, B0 ... always Power feeding block, B1A ... Power saving block (0 system SNI), B1B ... Power saving block (1 system SNI), B3 ... Power saving block (LLID table).

Claims (7)

In addition to connecting to a plurality of ONUs via a PON, connecting to a plurality of higher-level devices via SNI (Service Node Interface) provided for each higher-level device, and frames exchanged between these ONUs and the higher-level devices are mutually connected. OLT to transfer to
A receiving circuit for receiving an upstream frame from the ONU via the PON;
A plurality of transmission circuits that are provided for each predetermined downlink transmission rate and transmit a downstream frame to the ONU at the downlink transmission rate via the PON;
A plurality of transmission / reception circuits provided for each of the SNIs, for transmitting the uplink frame to the host device via the SNI and receiving the downlink frame from the host device via the SNI;
A frame transfer processing unit that transfers the uplink frame received by the reception circuit to the transmission / reception circuit and transfers the downlink frame received by the transmission / reception circuit to the transmission circuit;
As a block for performing power supply control of each circuit unit constituting the OLT, one or more constant power supply blocks and one or more power saving blocks are provided, and among the circuit units, circuit units belonging to the constant power supply block are provided. Always supplies power, and the circuit unit belonging to the power saving block includes a power control unit that controls supply / stop of power according to the operation of the power saving block,
The frame transfer processing unit
Each LLID (Logical Link ID) in the ONU includes an LLID table in which SNI selection information corresponding to the LLID is registered,
The SNI selection information corresponding to the LLID of the uplink frame received by the reception circuit is acquired from the LLID table, and the uplink frame is transferred to the transmission / reception circuit corresponding to the SNI selection information in the transmission / reception circuit ,
The power supply control unit supplies power to a power saving block to which a transmission / reception circuit connected to an operating SNI belongs, among the power saving blocks, based on an external setting indicating an operation state of each SNI. The power supply to the power-saving block to which the transmission / reception circuit connected to the non-operating SNI belongs is stopped . The OLT according to claim 1 ,
The frame transfer processing unit
An output destination determination unit that acquires, from the LLID table, SNI selection information corresponding to the LLID of the uplink frame received by the reception circuit;
An uplink output destination control unit that transfers the uplink frame to a transmission / reception circuit corresponding to the SNI selection information acquired by the output destination determination unit, of the transmission / reception circuit;
An uplink output timing adjustment unit that is provided for each of the transmission / reception circuits and adjusts the timing for transferring the uplink frame output from the uplink output destination control unit to the transmission / reception circuit;
The power control unit supplies power to a power saving block to which an upstream output timing adjustment unit corresponding to the SNI in operation belongs, among the power saving blocks, based on an external setting indicating an operation state of each SNI. The power supply to the power saving block to which the upstream output timing adjustment unit corresponding to the SNI in the non-operating state belongs is stopped. In the OLT according to claim 1 or 2 ,
The frame transfer processing unit
For each VID (VLAN Identifier) for identifying the VLAN to which the downlink frame belongs, the downlink frame received by the transceiver circuit further includes a VID table in which LLID and downlink output destination selection information related to the downlink frame are registered. LLID and downlink output destination selection information corresponding to the VID of the received information are acquired from the VID table, the LLID is assigned to the downlink frame, and then transferred to the transmission circuit corresponding to the downlink output destination selection information in the transmission circuit. And
The frame transfer processing unit
A plurality of downlink output destination determination units that are provided for each of the transmission / reception circuits and obtain LLID and downlink output destination selection information corresponding to the VID of the downlink frame received by the transceiver circuit from the VID table;
A plurality of LLID provision units provided for each of the transmission / reception circuits, and configured to append the LLID acquired by the downlink output destination determination unit to the downlink frame received by the transmission / reception circuit;
A plurality of the transmission / reception circuits that transfer the downlink frame from the LLID adding unit to the transmission circuit corresponding to the downlink output destination selection information acquired by the downlink output destination determination unit among the transmission circuits. And a downstream output destination control unit,
The power supply control unit, when there is an unused downlink transmission rate among the downlink transmission rates based on an external setting indicating an operation state of each downlink transmission rate, the downlink corresponding to the unused downlink transmission rate. An OLT characterized by stopping power supply to an output destination determination unit, an LLID assigning unit, and a downlink output destination control unit. In the OLT according to any one of claims 1 to 3 ,
The LLID table includes a plurality of storage units,
The power control unit supplies power to a storage unit in use and supplies power to a storage unit in an unused state based on an external setting indicating a use state of each storage unit. OLT characterized by stopping. In the OLT according to any one of claims 1 to 4 ,
The frame transfer processing unit acquires the SNI selection information of the uplink frame input to the frame transfer processing unit when the upstream frame is determined to be a discard target frame by a circuit unit that performs processing related to the uplink frame before the frame The OLT is characterized by discarding the uplink frame without performing the above. In the OLT according to any one of claims 1 to 5 ,
The frame transfer processing unit obtains output destination selection information of the downlink frame input to itself when the circuit unit that performs processing related to the downlink frame before it determines that the frame is a frame to be discarded An OLT characterized by discarding the downlink frame without performing the process and / or the process of assigning the output destination selection information to the downlink frame. In addition to connecting to a plurality of ONUs via a PON, connecting to a plurality of higher-level devices via SNI (Service Node Interface) provided for each higher-level device, and frames exchanged between these ONUs and the higher-level devices are mutually connected. A frame transfer method used in the OLT for transfer processing to
For each individual LLID (Logical Link ID) in the ONU, a storage step of storing SNI selection information corresponding to the LLID in an LLID table;
The SNI selection information corresponding to the LLID of the upstream frame received from the ONU via the PON is acquired from the LLID table, and the frame is provided for each SNI and transmitted / received to / from the host device via the SNI. A transfer step of transferring the uplink frame to a transmission / reception circuit corresponding to the SNI selection information,
As a block for performing power supply control of each circuit unit constituting the OLT, one or more constant power supply blocks and one or more power saving blocks are provided, and among the circuit units, circuit units belonging to the constant power supply block are provided. Includes a power control step for controlling the supply / stop of the power according to the operation of the power saving block in the circuit unit belonging to the power saving block .
In the power control step, power is supplied to a power saving block to which a transmission / reception circuit connected to the SNI in operation belongs, among the power saving blocks, based on an external setting indicating the operation status of each SNI. And stopping the power supply to the power-saving block to which the transmission / reception circuit connected to the non-operating SNI belongs .

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