JP5716521B2 - Signal processing device - Google Patents

Description

  The present invention relates to a signal processing apparatus that converts a digital signal into an analog signal.

In digital audio equipment, a signal processing device that converts an input digital signal into an analog signal is used. When this signal processing apparatus is constituted by one IC module, the IC module may include a digital circuit chip and an analog circuit chip.
An I2S format is known for data transmission between chips (see Patent Document 1). A digital signal transmitted in the I2S format includes a DATA signal in which L-channel audio data and R-channel audio data are alternately arranged for each word data, and a word clock signal for identifying the word data of the DATA signal. And a bit clock signal for identifying each bit data constituting the word data.

JP 2010-114640 A

By the way, signal wiring between chips may be connected via a lead frame or may be directly bonded, but in either case, if the number of wirings is large, the yield decreases and the cost also increases. The I2S format has a problem that there are many signal wirings.
It is also conceivable that a 1-bit ΔΣ signal is generated by a digital circuit, transmitted to an analog circuit, and the analog signal is taken out via a low-pass filter in the analog circuit. In this case, signal wiring can be reduced. However, the 1-bit ΔΣ signal has poor jitter tolerance and further has a problem that a sufficient S / N ratio cannot be obtained because the modulation rate is limited.

  The present invention has been made in view of the above-described points, and an object of the present invention is to suppress a decrease in the SN ratio while reducing the number of wirings connecting two chips.

In order to solve the above problems, a signal processing device according to the present invention includes a first chip, a second chip, a first signal wiring that connects the first chip and the second chip, and a second chip. The first chip includes a noise shaper that converts a first digital signal of a plurality of bits into a 1-bit pulse density modulation signal and outputs the pulse density modulation signal; and the first signal wiring. A transmission unit that transmits a 1-bit transmission signal including the pulse density modulation signal via the second signal wiring and transmits a clock signal synchronized with the transmission signal via the second signal wiring, and the second chip includes: Receiving the transmission signal through the first signal wiring to generate the pulse density modulation signal and receiving the clock signal through the second signal wiring; and a plurality of the pulse density modulation signals The number of bits The number of bit conversion unit for converting a digital signal, a DA converter for outputting a first analog signal the second digital signal by DA converter includes a calculation unit, wherein the noise shaper, using the dither signal The pulse density modulation signal is generated, the dither signal is output to the transmission unit, the transmission unit multiplexes the dither signal with the pulse density modulation signal to generate the transmission signal, and the reception unit is The pulse density modulation signal and the dither signal are separated from the received transmission signal, and the calculation unit subtracts the dither signal output from the reception unit from the first analog signal and outputs a second analog signal. It is characterized by.

  According to the present invention, the first digital signal having a plurality of bits is converted into a 1-bit pulse density modulation signal, and the pulse density modulation signal is transmitted from the first chip to the second chip via the first signal wiring. The number of wirings can be reduced. Further, by converting the number of bits of the pulse density modulation signal and supplying it to the DA converter, a DA converter that supports multi-bits can be used. As a result, the SN ratio and accuracy can be improved.

  In the signal processing apparatus described above, it is preferable that the noise shaper is an error feedback type or a ΔΣ modulation type, and the bit number conversion unit includes one of an FIR filter and a moving average filter. In particular, when a moving average filter is used, distortion caused by conversion to a 1-bit pulse density modulation signal by lowering the gain of the first digital signal at the input of the noise shaper and increasing the gain at the moving average filter. It becomes possible to suppress.

  In the signal processing apparatus described above, the DA converter is preferably a DEM (Dynamic Element Matching) method. In this case, the accuracy of DA conversion can be improved without performing laser trimming of resistors or the like.

In the signal processing device described above, the second chip includes a calculation unit, and the noise shaper generates the pulse density modulation signal using a dither signal, and outputs the dither signal to the transmission unit. The transmission unit multiplexes the dither signal with the pulse density modulation signal to generate the transmission signal, and the reception unit separates the pulse density modulation signal and the dither signal from the received transmission signal, Since the arithmetic unit subtracts the dither signal output from the receiving unit from the first analog signal and outputs the second analog signal, the dither signal is multiplexed with the transmission signal. Can be reduced.

  More specifically, the transmission unit multiplexes the pulse density modulation signal with the transmission signal in synchronization with one timing of rising or falling of the clock signal, and the other of rising or falling of the clock signal. The dither signal and the synchronization signal are multiplexed with the transmission signal in synchronization with the timing of the signal, and the receiving unit latches the received transmission signal in synchronization with one of the rising timing and falling timing of the clock signal. Preferably, the pulse density modulation signal is separated, and the received transmission signal is latched in synchronization with the other timing of rising or falling of the clock signal to separate the synchronization signal and the dither signal. In this case, the dither signal can be extracted by detecting the synchronization signal. Further, since the pulse density modulation signal can be separated using one of the rising edge and falling edge of the clock signal, the pulse density modulation signal can be easily reproduced.

It is a block diagram which shows the structure of the signal processing apparatus which concerns on embodiment. It is a block diagram which shows the structure of a noise shaper. It is a timing chart which shows operation | movement of a PDM transmission circuit and a PDM reception circuit. It is a block diagram which shows the structure of a moving average filter. It is a graph which shows the frequency characteristic of a moving average filter. It is a graph which shows the frequency characteristic of each part of a signal processor. It is explanatory drawing which shows the output signal of a quantizer. It is explanatory drawing which shows the relationship between the level of each part of a signal processing apparatus, and distortion. When the output of a noise shaper is supplied to a moving average filter, it is the graph which showed the relationship between the distortion of the output data of a moving average filter, and the input level of a noise shaper.

  Next, an embodiment suitable for the present application will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of the signal processing apparatus 100. The signal processing apparatus 100 according to the present embodiment is configured with one IC module. This IC module includes a first chip 10 and a second chip 20, and these chips are connected via a first signal wiring L1 and a second signal wiring L2. Although these wirings may be directly connected between chips, in this example, they are provided between lead frames. The first chip 10 and the second chip 20 are connected by a ground wiring (not shown) that connects the grounds in addition to the first signal wiring L1 and the second signal wiring L2.

  The first chip 10 performs digital processing, and the second chip 20 mainly performs analog processing. For example, the first chip 10 has a minimum wiring width of 0.18 [mu] m, and the second chip 20 has a minimum wiring width of 0.35 [mu] m because of the difference in use. Further, the second chip 20 may employ a process capable of forming a transistor having a higher breakdown voltage than that of the first chip 10.

  The first chip 10 includes an interface circuit 11 and a signal processing circuit 12. These configurations are supplied with an I2S format signal from the outside. Various control signals CTL are supplied to the interface circuit 11. The control signal CTL is a mute signal for instructing mute, for example. The signal processing circuit 12 is configured by a DSP (Digital Signal Processor) or the like. The signal processing circuit 12 is supplied with audio data Din in PCM format. The data rate of the audio data Din is the sampling frequency fs. The signal processing circuit 12 performs digital processing on the audio data Din to generate first data D1. The first data D1 is 24-bit data, and its data rate is 4fs.

  Further, the first chip 10 performs oversampling processing on the first data D1 to generate the second data D2, and generates third data D3 by shifting the quantization error noise to a high frequency. A noise shaper 14 and a PDM transmission circuit 15.

  The oversampling circuit 13 includes a fourfold oversampling filter and an IIR filter. The oversampling filter is used to increase the Nyquist frequency and reduce aliasing noise of the input first data D1. The data rate becomes 128 fs by performing this line interpolation 32 times or pre-hole. An IIR filter is connected to this data to remove aliasing and to correct the frequency characteristics of the moving average filter 22 described later, and become 32-bit second data D2.

Next, the noise shaper 14 operates in synchronization with the 128 fs clock signal CLK obtained by dividing the 256 fs clock signal YCLK by 1/2, and outputs the clock signals CLK and YCLK to the PDM transmission circuit 15. FIG. 2 shows the configuration of the noise shaper 14.
The noise shaper 14 includes seven adders 41-0 to 41-6, eight multipliers 42-0 to 42-7, and four delay circuits 45-0 to 45-3. Further, the noise shaper 14 adds the rectangular dither signal X1 to the output data of the adder 41-0, the adder 44 that adds the random dither signal X2 to the output data of the adder 43, and the output of the adder 44 A quantizer 46 that quantizes the data, an adder 47 that generates quantization error data De, and the output data of the adder 47 and the output data of the adder 41-4 are added and supplied to the delay circuit 45-0. An adder 48 is provided.

  The random dither signal X2 is generated by generating M-sequence data using a pseudo random signal generation circuit (not shown). By using all M-sequence data, it is possible to avoid the DC offset from being superimposed. The maximum output is masked. Further, in order to prevent an idling tone, the random dither signal X2 is attenuated by −18 dB before the quantizer 46 and added.

  The noise shaper 14 performs a fourth-order noise shaping process for reducing quantization error noise that is uniformly distributed in the entire Nyquist frequency band within the audible frequency band. Since the quantizer 46 compresses 52-bit data into 12-bit data, quantization error noise is generated. The quantization error data De represents the error. The quantization error noise is distributed to future samples with respect to the current sample. In order to distribute to future samples, four delay circuits 45-0 to 45-3 are used, and the distribution ratio is determined by coefficients a0 to a3 and b0 to b3.

  As described above, the output data of the quantizer 46 is 12 bits. On the other hand, the wiring that connects the first chip 10 and the second chip is limited to the first signal wiring L1 that transmits data and the second signal wiring L2 that transmits the clock signal YCLK. For this reason, the clipping circuit 50 is used to clip the 12-bit output data to generate the 1-bit third data D3. The third data D3 is a pulse density modulation signal in which the pulse density is modulated according to the level.

  Next, the PDM transmission circuit 15 will be described. In the above description, the interface circuit 11, the signal processing circuit 12, the oversampling circuit 13, and the noise shaper 14 have been described in one system. However, in the description of the PDM transmission circuit 15, two systems of L channel and R channel are assumed. The third data D3 is supplied from each system, and the L channel third data D3 is referred to as L channel data DL, and the R channel third data D3 is referred to as R channel data DR. In addition, it is assumed that the two systems of the L channel and the R channel operate in synchronization, and the clock signal YCLK is common to each system.

  FIG. 3 shows a timing chart of the PDM transmission circuit 15 and the PDM reception circuit 21. The PDM transmission circuit 15 generates audio data Da in which L channel data DL and R channel data DR are alternately arranged, and also generates control data Db. The control data Db has 16 bits as one frame, and the synchronization data Ds is assigned from the first bit to the fourth bit. The frame frequency is 16 fs. The bit pattern of the synchronization data Ds is “0111”. Also, "0" is assigned to the 8th, 11th and 14th bits, and the 5th to 7th bits, 9th bit, 10th bit, 12th bit, 13th bit, 15th bit, and Data d0 to d8 are assigned to the 16th bit. The reason why “0” is assigned to the 8th bit, 11th bit and 14th bit is that the synchronization data of “0111” is not generated regardless of the value of the data d0 to d8. This is because Ds can be discriminated.

In this example, the L channel rectangular dither signal X1 is assigned to the data d0 of the control data Db, and the R channel rectangular dither signal X1 is assigned to the data d1. Note that the data rate of the rectangular dither signal X1 is 4 fs, which is 1/4 of the frame rate (16 fs). Therefore, by assigning the rectangular dither signal X1 to the data d0 and d1, these can be transmitted. An L channel mute signal is assigned to the data d2 of the control data Db, and an R channel mute signal is assigned to the data d3.
The PDM transmission circuit 15 time-division-multiplexes the audio data Da and the control data Db to generate a transmission signal YPDM, outputs a clock signal YCLK synchronized with the transmission signal YPDM to the second signal line L2, and transmits the transmission signal YPDM. Output to the first signal line L1. That is, the PDM transmission circuit 15 multiplexes the audio data Da with the transmission signal YPDM in synchronization with the falling timing of the clock signal YCLK, and synchronizes with the rectangular dither signal X1 in synchronization with the rising timing of the clock signal YCLK. The data Ds is multiplexed with the transmission signal YPDM. The PDM transmission circuit 15 multiplexes the audio data Da with the transmission signal YPDM in synchronization with the rising timing of the clock signal YCLK, and outputs the rectangular dither signal X1 and the synchronization data Ds in synchronization with the falling timing of the clock signal YCLK. You may multiplex to the transmission signal YPDM.

Next, the second chip 20 will be described. As shown in FIG. 1, the second chip 20 includes a PDM receiving circuit 21, a moving average filter 22, a clip circuit 24, a DEM-DAC 25, an amplifier 26, and a buffer 27.
When receiving the transmission signal YPDM and the clock signal YCLK, the PDM receiving circuit 21 reproduces the audio data Da ′ and the control data Db ′ from the transmission signal YPDM as shown in FIG. Separated into data DL and R channel data DR, L channel and R channel rectangular dither signal X1 and L channel and R channel mute signal M are reproduced from control data Db ′.

  Specifically, the PDM receiving circuit 21 includes a first latch circuit that latches the received transmission signal YPDM at the rising edge of the clock signal YCLK, and a second latch circuit that latches the received transmission signal YPDM at the falling edge of the clock signal YCLK. And. The first latch circuit outputs the control data Db 'shown in FIG. 3, while the second latch circuit outputs the audio data Da' shown in FIG. Furthermore, the PDM receiving circuit 21 monitors the bit pattern of the control data Db ′, detects the synchronization data Ds (= 0111), and identifies the head of the frame. Then, the data d0 to d8 are specified from the control data Db ', and the L channel and R channel rectangular dither signal X1 and the L channel and R channel mute signal M are reproduced. Further, by specifying the head of the frame, the L channel data DL and the R channel data DR (third data D3) are identified from the audio data Da '.

In this way, the PDM receiving circuit 21 reproduces the 1-bit third data D3, but a DEM-DAC 25 described later is a DA converter corresponding to 5-bit input data. For this reason, it is necessary to convert the 1-bit third data D3 into 5-bit data. The moving average filter 22 has a function of expanding the number of bits of the 1-bit third data D3. FIG. 4 shows the configuration of the moving average filter 22. As shown in this figure, the moving average filter 22 includes 32 delay circuits 60-0 to 60-31 and 31 adders 61-0 to 61-30. The delay circuits 60-0 to 60-31 are configured by D flip-flops that operate with a clock signal having a frequency of 128 fs. The adder 61-30 outputs 6-bit fourth data D4.
FIG. 5 shows the frequency characteristics of the moving average filter 22. As shown in this figure, the frequency characteristic of the moving average filter 22 is a comb-shaped characteristic. The 32-stage moving average filter 22 has a gain of 20 KHz of −0.16 dB.

FIG. 6 shows the frequency characteristics of each part of the signal processing apparatus 100. In the figure, BIL is a frequency characteristic of linear interpolation with an oversampling filter included in the oversampling circuit 13, IIR2 is a frequency characteristic of an IIR filter included in the oversampling circuit 13, and MAF32 is a moving average filter. 22 shows the frequency characteristics from the input of the oversampling circuit 13 to the output of the moving average filter 22 as a whole.
As is apparent from FIG. 6, the IIR filter has a gain peak in the vicinity of 30 KHz, and corrects the decrease in gain of the oversampling filter, linear interpolation, and moving average filter 22 at 20 KHz.

Next, the clipping circuit 24 clips the 6-bit fourth data D4 to generate the 5-bit fifth data D5 and supplies it to the DEM-DAC 25. The clip circuit 24 has a function of matching the number of input bits of the DEM-DAC 25. The DEM-DAC 25 is a 5-bit multi-bit DAC and adopts a DEM (Dynamic Element Matching) method. In the DEM method, using a current divider enables high-precision DA conversion without adjusting the resistance value by laser trimming. The DEM-DAC 25 outputs the first analog signal S1 obtained by performing DA conversion on the fifth data D5 to the amplifier 26.

  The amplifier 26 subtracts the rectangular dither signal X1 from the first analog signal S1 to generate a second analog signal S2. The buffer 27 outputs the second analog signal S2 to the speaker 32 via a low-pass filter provided outside the signal processing apparatus 100. The low-pass filter in this example includes a coil 30 and a capacitor 31.

  In the present embodiment, in order to reduce the number of wirings connecting the first chip 10 and the second chip 20, 1-bit third data D 3 (pulse density) using the noise shaper 14 in the first chip 10. Modulation signal) is generated, and the transmission signal YPDM obtained by multiplexing the rectangular dither signal X1 and the mute signal M thereon is transmitted to the second chip 20. On the other hand, the second chip 20 performs DA conversion using a multi-bit DEM-DAC 25 in order to obtain a high S / N ratio. Therefore, the number of bits of the 1-bit third data D3 reproduced from the transmission signal YPDM is expanded by the moving average filter 22 and matched with the number of input bits of the DEM-DAC 25 using the clip circuit 24. As a result, the number of wires connecting the first chip 10 and the second chip 20 can be reduced.

  Incidentally, the noise shaper 14 uses the clip circuit 50 to limit the number of bits of the third data D3 as described with reference to FIG. When the sine wave audio signal Din is supplied, the output signal of the quantizer 46 is as shown in FIG. In this example, the amplitude corresponding to 1 bit is +0.5 to -0.5. When this is supplied to the clipping circuit 50, a portion of +0.5 or more and a portion of -0.5 or less are clipped and distorted.

  FIG. 8 shows the relationship between the level of each part of the signal processing apparatus 100 and distortion. As described above, since PDM transmission is performed with 1 bit, the maximum amplitude cannot be expressed, and distortion occurs. Therefore, at the input of the noise shaper 14, the gain is reduced by 6 dB from the full scale FS. This avoids distortion that occurs in PDM transmission.

  FIG. 9 shows the relationship between the distortion rate of the output data of the moving average filter 22 and the input level of the noise shaper 14 when the 1-bit third data D3 output from the noise shaper 14 is supplied to the 32-stage moving average filter 22. It shows the relationship. The input level is displayed with the full scale FS set to 0 dB. Here, when the ratio between the allowable distortion level and the full scale FS is defined as the modulation rate, it can be seen from this graph that the modulation rate is about 50%. This is the reason why the gain is reduced by 6 dB from the full scale FS at the input of the noise shaper 14.

  On the other hand, the moving average filter 22 is given a gain according to the number of stages. In the case of 32 stages as in the present embodiment, the gain of the moving average filter 22 is +6 dB. Thereby, the gain reduced by the input of the noise shaper 14 can be corrected by the moving average filter 22.

  As described above, in the present embodiment, the gain is lowered at the input of the noise shaper 14 (lowering the modulation rate), the 1-bit third data D3 is generated, and the gain is increased by the moving average filter 22, so the distortion is reduced. Can be reduced.

In the above-described embodiment, the error feedback type is adopted as the noise shaper 14, but the present invention is not limited to this, and the noise shaper 14 may be configured as a ΔΣ modulation type.
In the above-described embodiment, the moving average filter 22 is used to expand the number of bits of the 1-bit third data D3. However, the present invention is not limited to this, and is consistent with the number of input bits of the DEM-DAC 25. Any means may be adopted as long as the above can be taken. For example, the number of bits may be expanded using an FIR filter.

In the above-described embodiment, the 5-bit fifth data D5 is generated using the moving average filter 22 and the clip circuit 24 in order to convert the 1-bit third data D3 into 5 bits which is the number of input bits of the DEM-DAC 25. However, the present invention is not limited to this, and any means may be used as long as the third data D3 (pulse density modulation signal) can be converted into the number of input bits of the DEM-DAC 25. In short, any bit number conversion unit that converts the number of bits so that a 1-bit pulse density modulation signal can be matched with DA conversion of a multi-bit input may be used. For example, if the DEM-DAC 25 is a 6-bit input, the clipping circuit 24 is not necessary.
In the above-described embodiment, in the signal processing apparatus 100, the oversampling circuit 13 and the noise shaper 14 may be configured using a DSP.

  DESCRIPTION OF SYMBOLS 10 ... 1st chip | tip, 20 ... 2nd chip | tip, L1 ... 1st signal wiring, L2 ... 2nd signal wiring, 14 ... Noise shaper, 15 ... PDM transmission circuit (transmission part), 21 ...... PDM receiving circuit (receiving unit), 22 ... moving average filter (bit number converting unit), 24 ... clip circuit (bit number converting unit), 25 ... DEM-DAC (DA converting unit), 26 ... Amplifier (arithmetic unit), 100... Signal processing device, D2... Second data (first digital signal), D3... Third data (pulse density modulation signal), X1 ... rectangular dither signal (dither signal), YCLK: clock signal, YPDM: transmission signal, D5: fifth data (second digital signal), S1: first analog signal, S2: second analog signal, Ds: synchronization data (synchronization signal) .

Claims (4)

A first chip;
A second chip;
A first signal wiring and a second signal wiring connecting the first chip and the second chip;
The first chip is
A noise shaper that converts a first digital signal of a plurality of bits into a 1-bit pulse density modulation signal and outputs the pulse density modulation signal;
A transmission unit that transmits a 1-bit transmission signal including the pulse density modulation signal through the first signal wiring and transmits a clock signal synchronized with the transmission signal through the second signal wiring;
The second chip is
A receiving unit that receives the transmission signal through the first signal wiring to generate the pulse density modulation signal and receives the clock signal through the second signal wiring;
A bit number converter for converting the pulse density modulation signal into a second digital signal of a plurality of bits;
A DA converter that DA-converts the second digital signal and outputs a first analog signal ;
An arithmetic unit,
The noise shaper generates the pulse density modulation signal using a dither signal, and outputs the dither signal to the transmitter.
The transmission unit multiplexes the dither signal with the pulse density modulation signal to generate the transmission signal,
The receiving unit separates the pulse density modulation signal and the dither signal from the received transmission signal,
The calculation unit subtracts the dither signal output from the reception unit from the first analog signal and outputs a second analog signal.
A signal processing apparatus. The noise shaper is an error feedback type or a ΔΣ modulation type,
The bit number conversion unit includes one of an FIR filter and a moving average filter.
The signal processing apparatus according to claim 1.   The signal processing apparatus according to claim 1, wherein the DA conversion unit is a DEM system. The transmission unit multiplexes the pulse density modulation signal with the transmission signal in synchronization with one timing of rising or falling of the clock signal, and is synchronized with the other timing of rising or falling of the clock signal. Multiplexing the dither signal and the synchronization signal into the transmission signal;
The receiver is
The received transmission signal is latched in synchronization with one timing of the rising edge or falling edge of the clock signal to separate the pulse density modulation signal,
The received transmission signal is latched in synchronization with the other timing of the rising or falling edge of the clock signal to separate the synchronization signal and the dither signal,
The signal processing device according to claim 1 , wherein the signal processing device is a signal processing device.

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