JP5703324B2 - Time amplification circuit and program for executing characteristic test thereof - Google Patents

Description

  The present invention relates to a multistage time amplification circuit and a program for executing a characteristic test thereof.

  The principle of time amplifier (TA) was announced in 2003 (see Non-Patent Document 1). Since then, many research institutions have actively conducted research and development. In 2008, a group of Dr. AA Abidi confirmed circuit realization and operation on real silicon, and a high-resolution time digitizer circuit (Time-to-Digital Converter) : TDC) has been reported (see Non-Patent Document 2). Non-Patent Document 3 discloses a multistage connection type time amplification circuit for TDC in an ADPLL (all digital phase lock loop).

  In such a conventional technique, wiring is performed so that the wiring length is shortened when the time amplifiers are connected in multiple stages, and a wiring configuration considering time offset has not been studied. Therefore, there is a problem that the time offset becomes large.

  Therefore, a twist connection type configuration has been proposed as a technique for reducing the output time offset when the time amplification circuit is configured in a multistage configuration to obtain a high amplification factor (see Non-Patent Document 4).

  However, a specific configuration for realizing the twisted connection type in the multistage connection type time amplifier circuit has not been proposed.

A. M. Abas, et al., "Time difference amplifier", Electronics Letters, vol. 38, no. 23, pp. 1437-1438, Dec. 2002. M. Lee, et al., "A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue", IEEE JSSC, vol. 43, no. 4, pp. 769 -777, Apr. 2008. S. K. Lee, et al., "A 1 GHz ADPLL with a 1.25 ps minimum-resolution sub-exponent TDC in 0.18 μm CMOS", IEEE JSSC, vol. 44, no. 12, pp. 2874-2881, Dec. 2010. N. Harigai, et. Al., "A Twistedly-Cascaded Time Difference Amplifier for High Robustness Against Process Variation," in Proc. International Conference on Solid State Devices and Materials (SSDM 2011), Sep. 2011, pp. 184-185 .

  A multistage connection type time amplification circuit capable of reducing a time offset and a program for executing a characteristic test thereof are provided.

  The time amplification circuit according to the first aspect of the present invention is a time amplification circuit in which a plurality of time amplifiers are connected in multiple stages, and each of the plurality of time amplifiers amplifies a rising edge time difference between two input signals, Output as a rising edge time difference between two output signals, and the plurality of time amplifiers include first and second time amplifiers, wherein a first positive input terminal, a first negative input terminal, and a first positive output terminal And a first time amplifier having a first negative output terminal, a second positive input terminal, a second negative input terminal, a second positive output terminal, and a second negative output terminal, The second time amplifier to which the output signal of one time amplifier is input, the first wiring connecting the first positive output terminal and the second positive input terminal, and the first negative output A second wiring for connecting the terminal and the second negative input terminal. A third wiring that connects the first positive output terminal and the second negative input terminal, and a fourth wiring that connects the first negative output terminal and the second positive input terminal A first selection element and a second selection element, wherein the first selection element connects the first wiring or the fourth wiring to the second positive input terminal, and The second selection element connects the second wiring or the third wiring to the second negative input terminal, and connects the first positive input terminal and the first negative input terminal. A first switch element; a second switch element connecting the second positive input terminal and the second negative input terminal; and outputs of the first positive output terminal and the first negative output terminal. A first flip-flop circuit for detecting a first offset polarity of the first time amplifier based on a signal; A second flip-flop circuit that detects a second offset polarity of the second time amplifier based on output signals of two positive output terminals and the second negative output terminal; and When the second offset polarity is different, the selection circuit is controlled so that the first connection is made, and when the first offset polarity and the second offset polarity are the same, the second connection is made. And a control circuit for controlling the selection circuit, wherein the first connection is such that the first time amplifier and the second time amplifier are connected in series by the first wiring and the second wiring. In the second connection, the first time amplifier and the second time amplifier are twistedly connected by the third wiring and the fourth wiring.

  A program according to a second aspect of the present invention includes a first time amplifier, and a second time amplifier adjacent to the first time amplifier and to which an output signal of the first time amplifier is input. A program for executing a characteristic test of a multistage connection type time amplifier circuit, wherein the positive input and the negative input of the first time amplifier are short-circuited to the computer, and the positive input and the negative input of the second time amplifier are short-circuited. A test signal is input to the first and second time amplifiers, and the first and second time amplifiers are connected to each other based on output signals of the first and second time amplifiers. A step of detecting a second offset polarity, respectively, and when the first and second offset polarities are the same, the first and second time amplifiers are connected in series, and the first and second offset polarities are connected. If different to execute the steps of connecting twisting between the first and second time amplifier.

  ADVANTAGE OF THE INVENTION According to this invention, the program for performing the multistage connection type | mold time amplifier circuit which can reduce a time offset, and its characteristic test can be provided.

1 is a schematic diagram showing a time amplifier circuit according to an embodiment of the present invention. Schematic which shows the selection circuit in the time amplifier circuit which concerns on embodiment of this invention. The circuit diagram which shows the selection element which concerns on embodiment of this invention. The circuit diagram which shows the time amplifier which concerns on embodiment of this invention. The circuit diagram which shows the other time amplifier which concerns on embodiment of this invention. The figure which shows the outline | summary of the time amplifier circuit which concerns on embodiment of this invention. The figure which shows the outline | summary of the time amplifier circuit which concerns on embodiment of this invention. The figure which shows the effect of time offset reduction in the time amplifier circuit which concerns on embodiment of this invention. The figure which modeled the gain and time offset of the time amplifier circuit which concerns on embodiment of this invention. The figure which shows the total time offset of embodiment of this invention and the conventional time amplifier circuit. The figure which shows the total time offset with respect to the stage number of embodiment of this invention and the conventional time amplifier circuit. The figure which shows the decreasing rate of the total time offset with respect to the stage number and gain of the time amplifier circuit of embodiment of this invention. The figure which shows the simulation result of the time offset for every process condition of embodiment of this invention and the conventional time amplifier circuit. The figure which shows the simulation result of the offset of the time amplifier circuit by embodiment of this invention. The figure which shows the statistical analysis result using the Monte Carlo (Monte-Carlo) simulation of the offset of the time amplification circuit by embodiment of this invention. Schematic which shows the structure of the example of application of the time amplifier circuit by embodiment of this invention. The figure which shows the outline | summary of the application example of the time amplifier circuit by embodiment of this invention.

  Hereinafter, embodiments will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[1] Outline In an embodiment of the present invention, when time amplifiers are connected in multiple stages in order to obtain a high amplification factor, the connections between the time amplifiers are connected in series based on the detection result of the offset polarity in the time amplifier of each stage. By selecting either connection (non-twisted connection) or twisted connection, the output time offset is reduced.

  Here, the series connection (non-twisted connection) means that the positive output terminal of the preceding stage time amplifier and the positive input terminal of the succeeding stage time amplifier are connected, and the negative output terminal of the preceding stage time amplifier and the following stage amplifier are connected. This means that the negative input terminal of the time amplifier is connected. Twist connection means that the positive output terminal of the preceding time amplifier and the negative input terminal of the succeeding time amplifier are connected, and the negative output terminal of the preceding time amplifier and the positive input terminal of the succeeding time amplifier are connected. Means.

[2] Configuration of Time Amplifier Circuit A time amplifier circuit 100 according to an embodiment of the present invention will be described with reference to FIG. The time amplification circuit 100 according to the present embodiment can be used in general integrated circuits such as general-purpose microcomputers and communication integrated circuits.

  As shown in FIG. 1, the time amplification circuit 100 includes time amplifiers TA1, TA2, and TA3 connected in multiple stages, switch elements SW1, SW2, and SW3, flip-flop circuits FF1, FF2, and FF3, selection circuits 10a and 10b, and a control circuit. 50a and 50b, a storage unit 60, and a mode switching circuit 70.

  The time amplifiers TA1, TA2, and TA3 are connected in multiple stages. That is, the output signal of the first stage time amplifier TA1 is input to the next stage time amplifier TA2, and the output signal of the time amplifier TA2 is input to the last stage time amplifier TA3. Each of the time amplifiers TA1, TA2, and TA3 amplifies the rising edge time difference between the two input signals and outputs it as the rising edge time difference between the two output signals.

  The time amplifier TA1 amplifies the rising edge time difference between the input signals in1 and in2 input to the positive input terminal 1a and the negative input terminal 1b, and outputs them from the positive output terminal 1c and the negative output terminal 1d, respectively. The time amplifier TA2 amplifies the rising edge time difference between the input signals input to the positive input terminal 2a and the negative input terminal 2b, and outputs them from the positive output terminal 2c and the negative output terminal 2d, respectively. The time amplifier TA3 amplifies the rising edge time difference between the input signals input to the positive input terminal 3a and the negative input terminal 3b, and outputs the output signals out1 and out2 from the positive output terminal 3c and the negative output terminal 3d, respectively.

  The time amplifiers TA1 and TA2 are connected using wirings I1, I2, I3, and I4. The wiring I1 connects the positive output terminal 1c of the time amplifier TA1 and the positive input terminal 2a of the time amplifier TA2. The wiring I2 connects the negative output terminal 1d of the time amplifier TA1 and the negative input terminal 2b of the time amplifier TA2. The wiring I3 connects the positive output terminal 1c of the time amplifier TA1 and the negative input terminal 2b of the time amplifier TA2. The wiring I4 connects the negative output terminal 1d of the time amplifier TA1 and the positive input terminal 2a of the time amplifier TA2.

  Similarly, the time amplifiers TA2 and TA3 are connected using wirings I5, I6, I7 and I8. The wiring I5 connects the positive output terminal 2c of the time amplifier TA2 and the positive input terminal 3a of the time amplifier TA3. The wiring I6 connects the negative output terminal 2d of the time amplifier TA2 and the negative input terminal 3b of the time amplifier TA3. The wiring I7 connects the positive output terminal 2c of the time amplifier TA2 and the negative input terminal 3b of the time amplifier TA3. The wiring I8 connects the negative output terminal 2d of the time amplifier TA2 and the positive input terminal 3a of the time amplifier TA3.

  The selection circuits 10a and 10b are provided between the time amplifiers TA1 and TA2 and between the time amplifiers TA2 and TA3, respectively. The selection circuit 10a includes selection elements S1 and S2. The selection element S1 of the selection circuit 10a connects one of the wirings I1 and I4 to the positive input terminal 2a of the time amplifier TA2. The selection element S2 of the selection circuit 10a connects one of the wirings I2 and I3 to the negative input terminal 2b of the time amplifier TA2. Similarly, the selection circuit 10b also includes selection elements S1 and S2. The selection element S1 of the selection circuit 10b connects one of the wirings I5 and I8 to the positive input terminal 3a of the time amplifier TA3. The selection element S2 of the selection circuit 10b connects one of the wirings I6 and I7 to the negative input terminal 3b of the time amplifier TA3.

  The switch elements SW1, SW2, and SW3 short-circuit the input terminals of the time amplifiers TA1, TA2, and TA3, respectively. Specifically, the switch element SW1 connects or disconnects the positive input terminal 1a and the negative input terminal 1b of the time amplifier TA1. The switch element SW2 connects or disconnects the positive input terminal 2a and the negative input terminal 2b of the time amplifier TA2. The switch element SW3 connects or disconnects the positive input terminal 3a and the negative input terminal 3b of the time amplifier TA3.

  The flip-flop circuits FF1, FF2, and FF3 detect the offset polarities of the time amplifiers TA1, TA2, and TA3 based on the output signals of the time amplifiers TA1, TA2, and TA3, respectively. Specifically, the flip-flop circuit FF1 detects the offset polarity of the time amplifier TA1 using the output signals of the positive output terminal 1c and the negative output terminal 1d in the time amplifier TA1. The flip-flop circuit FF2 detects the offset polarity of the time amplifier TA2 using the output signals of the positive output terminal 2c and the negative output terminal 2d of the time amplifier TA2. The flip-flop circuit FF3 detects the offset polarity of the time amplifier TA3 using the output signals of the positive output terminal 3c and the negative output terminal 3d of the time amplifier TA3.

  The control circuit 50a controls switching of the selection elements S1 and S2 of the selection circuit 10a based on the output results of the flip-flop circuits FF1 and FF2. The control circuit 50b controls switching of the selection elements S1 and S2 of the selection circuit 10b based on the output results of the flip-flop circuits FF2 and FF3.

  Specifically, when the offset polarities of the adjacent time amplifiers TA1 and TA2 are different, the time amplifiers TA1 and TA2 are connected in series. In this case, the control circuit 50a connects the terminals 1c and 2a with the selection element S1 using the wiring I1, and connects the terminals 1d and 2b with the selection element S2 using the wiring I2.

  On the other hand, when the offset polarities of the adjacent time amplifiers TA1 and TA2 are the same, the time amplifiers TA1 and TA2 are twisted and connected. In this case, the control circuit 50a connects the terminals 1d and 2a with the selection element S1 using the wiring I4, and connects the terminals 1c and 2b with the selection element S2 using the wiring I3.

  When the offset polarities of the adjacent time amplifiers TA2 and TA3 are different, the time amplifiers TA2 and TA3 are connected in series. In this case, the control circuit 50b connects the terminals 2c and 3a with the selection element S1 using the wiring I5, and connects the terminals 2d and 3b with the selection element S2 using the wiring I6.

  On the other hand, when the offset polarities of the adjacent time amplifiers TA2 and TA3 are the same, the time amplifiers TA2 and TA3 are twisted and connected. In this case, the control circuit 50b connects the terminals 2d and 3a with the selection element S1 using the wiring I8, and connects the terminals 2c and 3b with the selection element S2 using the wiring I7.

  The control circuits 50a and 50b are configured by, for example, EXOR circuits EXOR1 and EXOR2.

  The storage unit 60 stores information (for example, offset polarities of the time amplifiers TA1, TA2, and TA3) related to the test results of the time offsets of the time amplifiers TA1, TA2, and TA3 at each stage. Based on this information, the storage unit 60 determines whether the connection configuration of each stage is connected in series or twisted so that the time offset in the entire time amplifier circuit 100 is minimized. And the memory | storage part 60 supplies the signal according to this judgment result to the control circuits 50a and 50b.

  The mode switching circuit 70 controls the switch elements SW1, SW2, and SW3 in order to switch between the operation mode and the test mode. In the operation mode, the mode switching circuit 70 controls to open the switch elements SW1, SW2, and SW3. In the test mode, the mode switching circuit 70 controls the switch elements SW1, SW2, and SW3 to close.

  The time amplification circuit 100 of the present embodiment is not limited to the configuration described above, and can be variously modified as follows, for example.

  (1) The number of time amplifiers TA1, TA2, and TA3 connected in multiple stages is not limited to three, and may be two or four or more.

  (2) In the example of FIG. 1, the selection circuits 10a and 10b are provided between the time amplifiers TA1 and TA2 and between the time amplifiers TA2 and TA3, respectively. That is, when the number of time amplifiers is n, the number of selection circuits is n−1, and the number of selection circuits: the number of time amplifiers = 1: 1. However, the present embodiment is not limited to a configuration in which selection circuits are provided for all the time amplifiers connected in multiple stages.

  For example, the selection circuit 10a of FIG. 1 may be eliminated, and one selection circuit 10b may be used for the two time amplifiers TA1 and TA2. That is, the relationship of the number of selection circuits: the number of time amplifiers = 1: 2 may be used, and a configuration with a selection circuit and a configuration without a selection circuit may alternate between the time amplifiers. However, the configuration with the selection circuit and the configuration without the selection circuit do not necessarily have to alternate between the time amplifiers.

  The number of selection circuits and the number between time amplifiers may be 1 to 3 or more. In this case, between the time amplifiers, the configuration with the selection circuit and the configuration without the selection circuit may be provided in a regular order or may be provided in an irregular order. In the latter case, more selection circuits may be arranged between time amplifiers near the first stage than between time amplifiers near the last stage. This is because the adjustment for minimizing the time offset of the entire time amplification circuit is easy to perform.

  One selection circuit may be provided for all the time amplifiers connected in multiple stages. In this case, one selection circuit may be provided, for example, between the last stage time amplifier and the last stage time amplifier, or on the output side of the last stage time amplifier.

  Further, in FIG. 1, the selection circuits 10a and 10b are illustrated as being disposed between the time amplifiers TA1 and TA2, and between the time amplifiers TA2 and TA3, respectively. It is not limited to being arranged. That is, the selection circuit can be physically arranged, for example, in the vicinity of the control circuit 50 by routing the wiring between the time amplifiers. In this case, it is also possible to employ a configuration in which one selection circuit can be shared and used by a plurality of time amplifiers connected in multiple stages.

  In addition, regarding the wiring configuration between the time amplifiers of the above-described modification (2), when the time amplifiers TA1 and TA2 in FIG. 1 are taken as an example, the wiring configuration where the selection circuit 10a is provided is the wirings I1, I2, Both the twisted connection and the series connection are possible using four of I3 and I4, and the wiring configuration at the place where the selection circuit 10a is not provided is only a serial connection using two of the wirings I1 and I2. Is configured to be possible.

  (3) The determination of the connection configuration of the time amplifiers TA1, TA2, and TA3 in each stage is not limited to being performed in the storage unit 60. For example, the determination may be made by an external circuit of the time amplification circuit 100, and the result may be stored in the storage unit 60 or the control circuits 50a and 50b. Such a determination may be made by the control circuits 50a and 50b. Furthermore, the storage unit 60 may not be provided in the time amplification circuit 100.

  (4) The mode switching circuit 70 may not be provided in the time amplification circuit 100.

[3] Selection Circuit Selection circuits 10a and 10b according to an embodiment of the present invention will be described with reference to FIGS. Note that the selection circuits 10a and 10b of the present embodiment are not limited to the configurations of FIGS. 2 and 3 and can be variously changed.

  As illustrated in FIG. 2, the selection circuits 10 a and 10 b may be configured by two selectors 11 and 12, for example.

  As shown in FIG. 3, the selector 11 includes NAND gates 13 and 14 and inverters 15 and 16. The selector 11 is controlled by a signal SEL supplied from the control circuit 50a shown in FIG.

  One input terminal of the NAND gate 13 is connected to the positive output terminal 1c in the previous stage through a wiring I1. A signal SEL supplied from the control circuit 50a of FIG. 1 is input to the other input terminal of the NAND gate 13.

  One input terminal of the NAND gate 14 is connected to the negative output terminal 1d of the previous stage through a wiring I4. A signal SEL supplied from the control circuit 50 a of FIG. 1 is input to the other input terminal of the NAND gate 14 via the inverter 15.

  The output terminals of the NAND gates 13 and 14 are connected to the input terminal of the inverter 16, and the output terminal of the inverter 16 is connected to the positive input terminal 2a of the next stage.

[4] Time Amplifier A circuit configuration of the time amplifier TA according to an embodiment of the present invention will be described with reference to FIGS. 4 and 5.

  As a circuit configuration of the time amplifier TA, there are a configuration using the metastability of the NAND-type SR latch (open loop TA) and a configuration in which variable delay cells are cross-coupled (closed loop TA). The former open loop TA has an advantage that it can be designed with a small area because it can be configured with only standard logic. On the other hand, the latter closed loop TA has an advantage that it is resistant to PVT (Process Voltage Temperature) variations because it uses feedback control. In this embodiment, the case where an open loop TA is used as the time amplifier TA is illustrated, but a closed loop TA can also be used.

As shown in FIG. 4, the time amplifier TA includes delay circuits 21 and 22 that generate a delay time T _off , NAND SR latch circuits 23 and 24, XOR gates 25 and 26, and capacitors 27, 28, 29, and 30. It is configured.

  The NAND type SR latch circuit 23 has a configuration in which NAND gates 31 and 32 are circularly connected. One input of the NAND gate 31 becomes the set input S, and one input of the NAND gate 32 becomes the reset input R. Here, the set input S is the output of the delay circuit 21, and the reset input R is the input in2 of the time amplifier TA.

  The NAND SR latch circuit 24 has a configuration in which NAND gates 33 and 34 are circularly connected. One input of the NAND gate 33 becomes the reset input R, and one input of the NAND gate 34 becomes the set input S. Here, the set input S is the output of the delay circuit 22, and the reset input R is the input in1 of the time amplifier TA.

  The XOR gate 25 compares the output signal of the NAND gate 31 with the output signal of the NAND gate 32 and outputs a signal out2. The XOR gate 26 compares the output signal of the NAND gate 33 with the output signal of the NAND gate 34, and outputs a signal out1.

  The capacitor 27 has one end connected to the ground and the other end connected to one input of the XOR gate 25. The capacitor 28 has one end connected to the ground and the other end connected to the other input of the XOR gate 25. The capacitor 29 has one end connected to the ground and the other end connected to one input of the XOR gate 26. The capacitor 30 has one end connected to the ground and the other end connected to the other input of the XOR gate 26.

  In the time amplifier TA having such a circuit configuration, when the rising edge times of the input signals in1 and in2 are substantially the same, the outputs of the NAND SR latch circuits 23 and 24 are in a metastable state, and the recovery time therefrom is the input signal. The characteristic is proportional to the rising edge time difference.

  Note that the time amplifier TA according to the present embodiment is not limited to the configuration of FIG. 4, and can be changed to the configuration of FIG. 5, for example.

In the time amplifier TA of FIG. 5, the delay time T _off of the delay circuits 21 and 22 on the input side is realized by an inverter chain. That is, the delay circuit 21 is composed of two inverters 35 and 36 connected in a chain, and the delay circuit 22 is composed of two inverters 37 and 38 connected in a chain.

  In the time amplifier TA of FIG. 5, the XOR gates 25 and 26 on the output side are configured so that the output does not become unstable when the NAND type SR latch circuits 23 and 24 fall into the forward stable state. Specifically, the XOR gate 25 includes inverters 39 and 40 and an OR gate 43. The XOR gate 26 includes inverters 41 and 42 and an OR gate 44.

In the time amplifier TA of FIG. 5, the inverter chain of the delay circuits 21 and 22 is composed of two inverters. However, the number of inverters is not limited to this, and may be three or more. The delay time _Toff increases as the number of inverters increases.

  4 can be changed to the delay circuits 21 and 22 shown in FIG. 5 or the XOR gates 25 and 26 shown in FIG.

[5] Test Method for Offset Polarity A test method for the offset polarity (offset positive / negative) of the multistage connection time amplifier circuit 100 according to this embodiment will be described with reference to FIGS. 1 and 6.

  First, the switch elements SW1, SW2, and SW3 are closed by the mode switching circuit 70 so as to enter the test mode, and the input terminals of the time amplifiers TA1, TA2, and TA3 in each stage are short-circuited. In the test mode, the switch elements SW1, SW2, and SW3 may be closed at the same timing or may be closed at different timings.

  Next, test signals are input to the time amplifiers TA1, TA2, and TA3 to obtain output signals of the flip-flop circuits FF1, FF2, and FF3, respectively. At this time, the flip-flop circuits FF1, FF2, and FF3 function as time comparators.

  For example, when testing the offset polarity of the time amplifier TA1, test signals are simultaneously input to the input terminals 1a and 1b (see FIG. 9B), and the output signals of the output terminals 1c and 1d are detected by the flip-flop circuit FF1. . At this time, the offset polarity is assigned according to the rising edge time between the output signal from the output terminal 1c and the output signal from the output terminal 1d. That is, when the rising edge time of the output signal of the output terminal 1c is earlier than the rising edge time of the output signal of the output terminal 1d, the offset polarity is set to “positive (+)” or “negative (−)”, and the output terminal 1c When the rising edge time of the output signal is later than the rising edge time of the output signal of the output terminal 1d, the offset polarity is set to “negative (−)” or “positive (+)”.

  As the test signal, a common signal may be used for the time amplifiers TA1, TA2, and TA3, or different signals may be used for the time amplifiers TA1, TA2, and TA3. In the former case, both the time amplifiers TA1 and TA2 and the time amplifiers TA2 and TA3 may be connected in series using the selection elements S1 and S2 of the selection circuits 10a and 10b. In the latter case, the test signals of the time amplifiers TA1, TA2, and TA3 may be input at different timings. However, in order to reduce the test time, the test signals of the time amplifiers TA1, TA2, and TA3 are input at the same timing. However, the characteristic test at each stage may be processed in parallel.

Next, based on the output results of the flip-flop circuits FF1, FF2, and FF3, the selection circuits 10a and 10b are controlled by the EXOR circuits EXOR1 and EXOR2 so as to have a twisted connection configuration or a non-twisted (series) connection configuration. Here, if the offset polarities of adjacent time amplifiers are the same, a twisted connection configuration is used, and if the offset polarities of adjacent time amplifiers are different, a non-twisted connection configuration is used.
Finally, the mode switching circuit 70 controls the switch elements SW1, SW2, and SW3 to open, and the test mode ends.

  The above-described test method according to the present embodiment can be provided as a program for causing a computer to execute each process of the test method, or for causing the computer to execute each process of the test method. It is also possible to provide a computer-readable recording medium that records the program. The test method according to the present embodiment includes, as programs that can be executed by a computer, for example, a magnetic disk (floppy (registered trademark) disk, hard disk, etc.), an optical disk (CD-ROM, DVD, Blu-ray (registered trademark) disk, etc.) It is also possible to write on a recording medium such as a semiconductor memory and apply it to various devices, or transmit it via a communication medium and apply it to various devices. A computer that implements the present apparatus reads a program recorded on a recording medium, and controls the operation by the program, thereby executing processing according to the test method described above.

[6] Effects The effects of the multistage connection time amplifier circuit 100 according to this embodiment will be described with reference to FIGS.

  In the multistage connection type time amplifier circuit 100 of the present embodiment, the wiring configuration between the time amplifiers TA is configured to be connected in series or twisted by the selection circuits 10a and 10b.

  In this embodiment, the characteristics (positive / negative of time offset) in the time amplifier TA at each stage are tested, and if the offset polarities of adjacent time amplifiers are the same based on the test results, a twisted connection configuration is adopted and adjacent. If the offset polarity of the time amplifier is different, a non-twisted connection configuration is used. In this way, the wiring configuration between the time amplifiers TA is reconfigured by the characteristic test so that the total time offset is minimized (see FIG. 7).

  In the conventional multistage connection type time amplifier circuit, as shown in FIG. 8A, the wiring is not formed by the twisted connection as in this embodiment. For this reason, the time offset is large, the variable delay for compensating it is large, and the cost is high. On the other hand, in the multistage connection type time amplifier circuit 100 of this embodiment, as shown in FIG. 8B, the characteristic test and the reconfiguration of the wiring are performed. For this reason, the time offset is small, the variable delay is small, and the cost can be reduced. The time offset reduction according to the present embodiment will be described in detail below.

As shown in FIG. 9A, the characteristics of the time amplifier TA are modeled. The gain of time the amplifier TA alpha, if the the β (β> 0) offset, the rising edge time difference [Delta] T _OUT of the rising edge time difference [Delta] T _IN of the input signal in1 and in2 output signals out1 and out2, the following equation ( There is a relationship 1).

ΔT _OUT = αΔT _IN + β (1)
The time offset of the time amplifier TA connected in multiple stages can be expressed mathematically as shown in FIGS. 10 (a) and 10 (b).

As shown in FIG. 10A, the total time offset β _TOTAL of the n-stage non-twisted connection time amplifier according to the prior art is expressed as the following equation (2).

β _TOTAL = (α ⁿ⁻¹ + α ⁿ⁻² +... + α ² + α + 1) β (2)
As can be seen from this equation (2), the offset β _{TOTAL of the} prior art increases as the number of stages of the time amplifier increases.

On the other hand, as shown in FIG. 10B, the total time offset β ′ _TOTAL of the n-stage twist-connected time amplifier 100 according to the present embodiment is expressed by the following equation (3).

β ′ _TOTAL = (α ⁿ⁻¹ −α ⁿ⁻² −... −α ² −α−1) β (3)
As can be seen from Equation (3), in this embodiment, the time offset can be significantly reduced even if the number of stages of the time amplifier TA is increased.

  Specifically, as shown in FIG. 11, the torsional connection type time amplification circuit 100 according to the present embodiment is more comprehensive as the number of stages of the time amplifier TA increases than the non-twisted connection type time amplification circuit of the prior art. The time offset can be reduced. Further, as shown in FIG. 12, it can be seen that the reduction rate of the total time offset of this embodiment increases as the number of stages of the time amplifier TA increases in any case of gains 2 to 4 per stage.

  FIGS. 13A and 13B show simulation results of three types of total time offsets in the conventional technology and the four-stage time amplification circuit of this embodiment. The three types are FF (gain / stage = 3.64), TT (gain / stage = 3.37), and SS (gain / stage = 2.93).

  Comparing the total time offset between the prior art and this embodiment, the FF type is 636.0 ps to 285.7 ps (55.1% reduction), and the TT type is 28.8 ps to 11.6 ps (58. It can be seen that the total time offset can be greatly reduced from −238.1 ps to −93.5 ps (61.0% reduction) in the case of the SS type. The calculation results by the above formulas (2) and (3) are 54.1% for the FF type, 58.2% for the TT type, and 66.4% for the SS type. .

  FIG. 14 shows the simulation result of the output (total) offset time by the connection structure of 8 patterns in the time amplification circuit of 4 stages connection. In this simulation, it is considered that the offset of the time amplifier TA at each stage is different (process variation).

  As shown in FIG. 14, the offsets of the time amplifiers TA at each stage are +1.11 ps, −1.34 ps, −0.44 ps, and +6.38 ps. The output offset time is 295 ps for pattern A, 297 ps for pattern B, 180 ps for pattern C, 191 ps for pattern D, 318 ps for pattern E, 327 ps for pattern F, 258 ps for pattern G, and 249 ps for pattern H. Therefore, among these eight patterns, the connection configuration in the worst situation (the longest output offset time) is the pattern F, and the connection configuration in the best situation (the shortest output offset time) is the pattern C. Therefore, by reconfiguring the pattern F into the pattern C, the output offset time can be reduced by 45% from 327 ps to 180 ps.

  FIG. 15 shows a statistical analysis result using the Monte Carlo simulation of the output time offset according to the present embodiment and the prior art. As in FIG. 14, FIG. 15 considers process variations of the time amplifier TA at each stage. Note that RIC (Reconfigurable Inter-Stage Connection) in FIG. 15 means reconfiguration of the connection between the time amplifiers TA.

  As shown in FIG. 15, the worst time offset between the present embodiment and the prior art is 745 ps, whereas the present embodiment is 353 ps, which can be reduced by 52.6%. Further, when the distribution center of the offset in the probability distribution function (PDF) is compared, the conventional technique is 290 ps, whereas this embodiment is 191 ps, which can be reduced by 34.0%. Thus, even if the process variation of the time amplifier TA at each stage is taken into consideration, it is possible to confirm a decrease in offset by simulation.

  As described above, in the present embodiment, when the multistage connection time amplifier circuit 100 is mounted on an integrated circuit or the like, the time offset polarity of the time amplifier TA at each stage is tested, and the multistage connection is made based on the test result. The wiring is rearranged in a twisted configuration so that the total time offset of the mold time amplifier circuit 100 is minimized. By using this configuration, it is possible to minimize the output time offset.

  In addition, when detecting the offset polarity of the time amplifier TA at each stage, a simple circuit such as a flip-flop circuit and an EXOR circuit is used between the stages to minimize the output time offset with a small area. It becomes possible.

  In addition, when the tendency of time offset is known in advance (for example, when the tendency of manufacturing variation is known and can be predicted from the arrangement relationship of the constituent elements), the wiring can be twisted before the test. The offset can be minimized.

[7] Application Example The configuration of an application example of the multistage connection time amplifier circuit 100 according to the embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 16, in the multi-stage connection time amplifier circuit 100 of the application example, a time digitizer circuit (TDC) 80 may be provided at the output of the final stage time amplifier TA3. The time digitizer circuit 80 measures the overall offset of the time amplifier circuit 100 and controls the control circuits 50a and 50b so as to select the optimum connection configuration.

  A method for testing the offset polarity of the multi-stage connection time amplifier circuit 100 according to the application example will be described with reference to FIGS.

  First, the time digitizer circuit 80 is used to measure the time offsets of all connection patterns in the time amplifiers TA1, TA2, and TA3. Here, the four-stage time amplification circuit in FIG. 16 has eight patterns of connection configurations NNN, NNT, NTN, NTT, TNN, TNT, TTN, and TTT (T: twist connection, N: non-twist connection). The measurement result obtained by the time digitizer circuit 80 is stored in the storage unit 60, for example.

  Next, the time offset of each connection pattern is compared. In the case of FIG. 16, the offset can be reduced most in the case of TNT (twisted-non-twisted-twisted) connection. This comparison is performed, for example, in the storage unit 60 or the like.

  Finally, based on the comparison result, reconfiguration is performed with a connection pattern that can reduce the time offset most.

  Also in the multistage time amplification circuit 100 of the application example as described above, the output time offset can be reduced.

  In addition, although embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  10a, 10b ... selection circuit, 11, 12 ... selector, 13, 14, 31, 32, 33, 34 ... NAND gate, 15, 16, 35, 36, 37, 38, 39, 40, 41, 42 ... inverter, 21, 22 ... Delay circuit, 23, 24 ... NAND SR latch circuit, 25, 26 ... XOR gate, 27, 28, 29, 30 ... Capacitor, 50a, 50b ... Control circuit, 60 ... Storage unit, 70 ... Mode switching Circuit, 80 ... Time digitizer circuit (TDC), 100 ... Time amplifier circuit, TA ... Time amplifier, I1-I8 ... Wiring, S1, S2 ... Selection element, SW1, SW2, SW3 ... Switch element, FF1, FF2, FF3 ... Flip-flop circuit.

Claims (11)

A time amplification circuit in which a plurality of time amplifiers are connected in multiple stages,
Each of the plurality of time amplifiers amplifies the rising edge time difference between two input signals and outputs the rising edge time difference between two output signals,
The plurality of time amplifiers include first and second time amplifiers;
The first time amplifier having a first positive input terminal, a first negative input terminal, a first positive output terminal and a first negative output terminal;
The second time amplifier having a second positive input terminal, a second negative input terminal, a second positive output terminal, and a second negative output terminal, to which an output signal of the first time amplifier is input When,
A first wiring connecting the first positive output terminal and the second positive input terminal;
A second wiring connecting the first negative output terminal and the second negative input terminal;
A third wiring connecting the first positive output terminal and the second negative input terminal;
A fourth wiring connecting the first negative output terminal and the second positive input terminal;
A first selection element and a second selection element, wherein the first selection element connects the first wiring or the fourth wiring to the second positive input terminal; A selection element that connects the second wiring or the third wiring to the second negative input terminal;
A first switch element connecting the first positive input terminal and the first negative input terminal;
A second switch element connecting the second positive input terminal and the second negative input terminal;
A first flip-flop circuit that detects a first offset polarity of the first time amplifier based on output signals of the first positive output terminal and the first negative output terminal;
A second flip-flop circuit that detects a second offset polarity of the second time amplifier based on output signals of the second positive output terminal and the second negative output terminal;
When the first offset polarity and the second offset polarity are different, the selection circuit is controlled so that the first connection is established, and when the first offset polarity and the second offset polarity are the same, A control circuit for controlling the selection circuit so as to be connected in two,
Comprising
In the first connection, the first time amplifier and the second time amplifier are connected in series by the first wiring and the second wiring,
The second connection is a time amplification circuit in which the first time amplifier and the second time amplifier are twistedly connected by the third wiring and the fourth wiring. The control circuit is an EXOR circuit,
The time amplification circuit according to claim 1, wherein the EXOR circuit receives the first offset polarity and the second offset polarity.   The time amplification circuit according to claim 1, wherein each of the first and second selection elements includes a selector. A plurality of selection circuits including the selection circuit;
The time amplification circuit according to claim 1, wherein the plurality of selection circuits are respectively provided between the plurality of time amplifiers. A plurality of selection circuits including the selection circuit;
A first configuration in which one selection circuit of the plurality of selection circuits is provided between the plurality of time amplifiers, and a second configuration in which one selection circuit of the plurality of selection circuits is not provided. The time amplification circuit according to claim 1, wherein:   The time amplification circuit according to claim 5, wherein the first and second configurations exist alternately between the plurality of time amplifiers. A storage circuit for storing information on each test result of time offsets of the plurality of time amplifiers, and supplying a signal based on the information to the control circuit;
The time amplification circuit according to claim 1, further comprising: A mode switching circuit that controls the first and second switch elements and switches between an operation mode and a test mode;
The time amplification circuit according to claim 1, further comprising: A time digitizer circuit connected to the second positive output terminal and the second negative output terminal and measuring an overall offset of the plurality of time amplifiers;
The time amplification circuit according to claim 1, further comprising: Performing a characteristic test of a multistage connection type time amplifier circuit comprising: a first time amplifier; and a second time amplifier adjacent to the first time amplifier and receiving an output signal of the first time amplifier. A program for
On the computer,
Shorting the positive and negative inputs of the first time amplifier and shorting the positive and negative inputs of the second time amplifier;
A test signal is input to the first and second time amplifiers, and first and second offset polarities of the first and second time amplifiers are determined based on output signals of the first and second time amplifiers. Each detecting step;
When the first and second offset polarities are the same, the first and second time amplifiers are connected in series, and when the first and second offset polarities are different, the first and second time amplifiers A step of twisting connection between,
A program for running   The program according to claim 10, wherein the test signal is simultaneously input to the first and second time amplifiers respectively, and the detection of the first and second offset polarities is processed in parallel.

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