JP5701336B2 - Photoelectric conversion device and imaging system using the same - Google Patents

Description

  The present invention relates to a photoelectric conversion device, and more particularly to a transfer structure of signal charges from a photoelectric conversion element.

2. Description of the Related Art Conventionally, a photoelectric conversion device is known in which charges of a photoelectric conversion element are transferred to a floating diffusion region by a transfer MOS transistor, converted into a voltage, and read.
Regarding such a photoelectric conversion device, Patent Document 1 discloses a configuration in which signal charges are read out at a low voltage and signal charges are not left behind. Specifically, a first gate electrode substantially adjacent to one end of the photodiode region, a second gate electrode adjacent to the first gate electrode, and a drain region substantially adjacent to one end of the second gate electrode; The photoelectric conversion device having

JP 2004-063498 A

However, in the configuration described in Patent Document 1, since the photodiode is formed deeply below the first gate electrode, when the pixel is miniaturized, the photodiode and the drain region are close to each other, There is a possibility of conduction by bulk punch-through.
An object of the present invention is to provide a photoelectric conversion device in which conduction between the photoelectric conversion element and the drain region is easily controlled and charge transfer efficiency from the photoelectric conversion element is improved.

The photoelectric conversion device of the present invention is a photoelectric conversion device having a pixel unit including a first pixel, a second pixel, a floating diffusion portion, and a readout circuit, wherein the first pixel is a first pixel A photoelectric conversion element; a first charge holding unit for holding charges of the first photoelectric conversion element; and a first charge transfer unit for transferring charges of the first charge holding unit, The second pixel transfers the charge of the second photoelectric conversion element, the second charge holding unit for holding the charge of the second photoelectric conversion element, and the charge of the second charge holding unit. A semiconductor region that forms the floating diffusion portion is disposed between the first charge transfer portion and the second charge transfer portion in a plan view. One pixel unit between the first photoelectric conversion element and the second photoelectric conversion element arranged along Between the semiconductor regions constituting the floating diffusion portion of the two pixel units arranged along the second direction intersecting the first direction. In addition, an amplification transistor and a reset transistor included in the readout circuit of the one pixel unit are disposed, and a first gate electrode is disposed adjacent to the first photoelectric conversion element in a plan view, and the first The electric charge of the first photoelectric conversion element is held in a region below the gate electrode, a second gate electrode is disposed adjacent to the second photoelectric conversion element in plan view, and the second gate electrode The electric charge of the second photoelectric conversion element is held in the lower region .

  According to the photoelectric conversion device of the present invention, it is easy to control the conduction between the photoelectric conversion element and the drain region, and the signal charge transfer efficiency can be improved.

Plane schematic diagram illustrating the first embodiment Cross-sectional schematic diagram for explaining the first embodiment Operation timing diagram for explaining the first embodiment Potential diagram for explaining the first embodiment Operation timing diagram for explaining the second embodiment Potential diagram for explaining the second embodiment Operation timing diagram for explaining the third embodiment Plane schematic diagram for explaining the fourth embodiment Cross-sectional schematic diagram for explaining the fourth embodiment Operation timing diagram for explaining the fourth embodiment Potential diagram for explaining the fourth embodiment Block diagram explaining the imaging system

  The photoelectric conversion device of the present invention is electrically connected to the photoelectric conversion element including the first semiconductor region of the first conductivity type and the second semiconductor region of the second conductivity type, and the second semiconductor region. A fourth semiconductor region of the second conductivity type is included. The fourth semiconductor region has an impurity concentration higher than that of the second semiconductor region, and is arranged closer to the main surface than the second semiconductor region. A first gate electrode covering the fourth semiconductor region and a second gate electrode for controlling conduction between the fourth semiconductor region and the third semiconductor region are provided. With such a configuration, the transfer efficiency of signal charges can be improved while facilitating separation of the photoelectric conversion element and the drain region.

  In addition, at least during a period in which signal charges are accumulated in the photoelectric conversion element, charges having a polarity opposite to that of the signal charges are accumulated below the first gate electrode. With such a configuration, it is possible to reduce the mixing of dark current due to defects at the interface of the semiconductor substrate.

  The outer edge of the semiconductor region can be determined as follows. For example, when the surrounding semiconductor region has a conductivity type opposite to its own conductivity type, the point where each net impurity concentration is substantially zero is defined as the outer edge. This outer edge can be confirmed by measuring with a scanning capacitive microscope (SCM) or the like. The net impurity concentration is a difference in concentration between N-type impurities and P-type impurities. Here, the depth of the semiconductor region is assumed to have the depth of the peak value of the impurity concentration. Further, a direction from the main surface of the semiconductor substrate including the light receiving surface toward the semiconductor substrate is defined as a downward direction or a deep direction.

  Hereinafter, embodiments will be described with reference to the drawings. The configurations of the embodiments can be appropriately combined. In the embodiment, the signal charge is an electron and the MOS transistor is an N type. However, the signal charge may be a hole and the conductivity type may be reversed.

(First embodiment)
First, a pixel to which the present invention can be applied will be described with reference to FIG. FIG. 1 is a schematic plan view showing elements as blocks. Reference numeral 100 denotes a pixel, 101 denotes a photoelectric conversion element, 102 denotes a charge holding unit, 103 denotes a floating diffusion unit, and 104 denotes a charge transfer unit. Other elements are collectively shown as 105 in a simple manner. The other elements are, for example, an amplification MOS transistor and a reset MOS transistor, and the detailed configuration is arbitrary. Further, the element isolation region is ignored. A pixel is a minimum repeating unit including at least one photoelectric conversion element. The pixel 100 is arranged in a one-dimensional or two-dimensional manner to form an imaging region. FIG. 1 shows an arrangement of three pixels 100. A cross-sectional view of such a pixel 100 taken along line AB is shown in FIG.

  FIG. 2 is a schematic cross-sectional view taken along line AB of FIG. 201 is a well, 202 is a first semiconductor region of a first conductivity type, 203 is a second semiconductor region of a second conductivity type, 204 is a first gate electrode, and 205 is a fourth semiconductor region of a first conductivity type. It is. Reference numeral 206 denotes a second gate electrode, 207 denotes a third semiconductor region of the first conductivity type, 208 denotes a conductor constituting a contact, and 209 denotes an insulating film covering the element. 210 is a gate insulating film, and 211 is an element isolation region such as STI. Reference numeral 200 denotes a semiconductor substrate on which the photoelectric conversion element is arranged, and reference numeral 212 denotes a main surface of the semiconductor substrate including the light receiving surface of the photoelectric conversion element 101. The dotted line indicates the position of the surface including the main surface 212. Here, the direction from the main surface 212 toward the semiconductor substrate 200 is defined as a downward direction or a deep direction. 201 may be the first conductivity type, the second conductivity type, or the semiconductor substrate 200.

  The first semiconductor region 202 and the second semiconductor region 203 are stacked, have a PN junction interface, and constitute a part of the photoelectric conversion element 101. The third semiconductor region 207 functions as a floating diffusion portion, and signal charges in the first semiconductor region 202 are transferred from the fourth semiconductor region 205 by the second gate electrode 206. Here, the fourth semiconductor region 205 has an impurity concentration higher than that of the first semiconductor region 202, is disposed closer to the main surface 212 than the first semiconductor region 202, and is electrically connected to the first semiconductor region 202. Connected to. It can be said that the fourth semiconductor region 205 and the first semiconductor region 202 are integrated or the semiconductor regions are continuously arranged. A first gate electrode 204 covers the upper portion. With such a configuration, the thickness of the fourth semiconductor region 205 in the depth direction can be reduced, and the proximity of the depletion layer at a depth that cannot be controlled by the gate can be prevented. That is, even when the distance between the fourth semiconductor region 205 and the third semiconductor region 207 is narrowed due to pixel miniaturization, it is possible to separate each other and control conduction. In addition, the signal charges in the first semiconductor region 202 can be efficiently transferred to the third semiconductor region 207. Furthermore, since the fourth semiconductor region having a high impurity concentration is disposed closer to the main surface 212 than the second semiconductor region, a large amount of charge can be stored in the n + region with a relatively low depletion voltage. An improvement in the number of saturated charges can be expected.

Next, driving of such a photoelectric conversion device will be described with reference to an operation timing chart of FIG.
φ 204 is a control signal for controlling the first gate electrode 204, and indicates a voltage supplied to the first gate electrode 204. φ206 is a control signal for controlling the second gate electrode 206, and indicates a voltage supplied to the second gate electrode 206. In this embodiment, the low level that can be taken by the control signal φ204 and the control signal φ207 is −1V, and the high level is 5V. The voltage (207) schematically shows a change in the voltage of the third semiconductor region 207. A state (207) indicates an operation performed in the third semiconductor region, and a state (101) indicates the state of the photoelectric conversion element 101, and here indicates an accumulation period. t1 to t9 indicate timings. Hereinafter, driving will be described.

At t1, the photoelectric conversion element 101 is performing signal charge accumulation operation. The third semiconductor region 207 is supplied with a desired voltage (reset voltage) and is 5V. Supplying a desired voltage to the third semiconductor region 207 is a reset operation, and the desired voltage is set to 5V. Next, at t2, the potential of the third semiconductor region 207 after reset is read. The signal from the third semiconductor region 207 after the reset can be used as a noise signal including a noise component at the time of reset. A noise signal is superimposed on the signal based on the signal charge. Therefore, the noise component can be removed by taking the difference between the signal based on the signal charge and the noise signal. The control signal φ204 and the control signal φ206 are at a low level from t1.
When the control signal φ204 is at a low level during the accumulation operation, charges (holes) having the opposite polarity to the signal charges are accumulated below the first gate electrode 204, and the main surface in the fourth semiconductor region 205, that is, the semiconductor The dark current from the substrate can be reduced. In the present embodiment, the control signal φ204 is always set to a low level, and the dark current can always be reduced. Further, since the control signal φ206 is at a low level, the fourth semiconductor region 205 and the third semiconductor region 207 are sufficiently separated, and darkness generated from the surface of the semiconductor substrate under the second gate electrode. The current is also suppressed.

  Next, from t3 to t4, the control signal φ206 becomes a high level, the fourth semiconductor region 205 and the third semiconductor region 207 are electrically connected, and the signal charge generated in the photoelectric conversion element 101 is changed to the third level. Transferred to the semiconductor region 207. Then, the transfer of the signal charge from the photoelectric conversion element 101 to the third semiconductor region 207 stops when the control signal φ206 returns to the low level. That is, the photoelectric conversion element 101 ends one accumulation period at t4 and enters the next accumulation period.

  While the control signal φ206 is at the high level, the voltage of the third semiconductor region 207 decreases by the voltage ΔVsig of the signal charge transferred from the photoelectric conversion element 101. A signal based on the voltage ΔVsig is output as an image signal between t4 and t5. Specifically, when the third semiconductor region 207 is connected to the gate electrode of the amplification MOS transistor, a signal based on the potential of the third semiconductor region 207 including the voltage ΔVsig is used as the source potential of the amplification MOS transistor. Is output. Then, the third semiconductor region 207 is reset at t5 and returns to the state of t1. The same drive is performed after t6.

  Next, the potential state of the semiconductor region in such driving will be described with reference to FIG. FIG. 4A to FIG. 4D schematically show the potential with respect to signal charges in each semiconductor region at a certain timing. 202 corresponds to the first semiconductor region 202, 204 corresponds to the fourth semiconductor region 205 below the first gate electrode 204, 206 corresponds to the well below the second gate electrode 206, and 207 corresponds to the third semiconductor region 207. It shows the potential to FIG. 4A shows an initial state in which no signal charge is generated in the photoelectric conversion element 101. 4B shows a state corresponding to t1 to t3 in FIG. 3, FIG. 4C shows a state between t3 and t4 in FIG. 3, and FIG. 4D shows t4 to t5 in FIG. Shows the state. Signal charges are indicated by hatching. L41 to L48 indicate the potential of each semiconductor region in each state.

  In FIG. 4A, the fourth semiconductor region 205 has an impurity concentration higher than that of the first semiconductor region 202, and thus has a potential L43 lower than the potential L42 of the first semiconductor region 202. Here, the potential under the second gate electrode is L41, but it may have a higher potential. In FIG. 4B, signal charges generated in the photoelectric conversion element 101 are accumulated. Since the fourth semiconductor region 205 has a higher impurity concentration than the first semiconductor region, the fourth semiconductor region 205 holds a larger amount of difference between the signal charge held at L42 and the signal charge held at L43 than the case where the impurity concentration is the same. It becomes possible to do. In FIG. 4C, a high level voltage is supplied to the second gate electrode 206, and the potential of the well below the second gate electrode 206 drops to L47. Here, a step-like potential is formed between the first semiconductor region 202 and the third semiconductor region 207, and the signal charge is smoothly transferred to the third semiconductor region 207. In FIG. 4D, since the low-level voltage is supplied to the second gate electrode 206, the potential of the well below the second gate electrode 206 becomes L41, and the transfer of the signal charge is completed. Then, signal charge accumulation in the photoelectric conversion element 101 starts again. Between this FIG. 4C and FIG. 4D, the potential of the fourth semiconductor region 205 is higher than the potential of the well below the second gate electrode 206. With such a potential relationship, it is possible to reduce signal charge remaining in the fourth semiconductor region 205.

  As described above, according to the configuration of this embodiment, the second semiconductor region and the third semiconductor region constituting the photoelectric conversion element are prevented from conducting in an undesired period, and the transfer efficiency is improved. Is possible. Since the fourth semiconductor region can be formed close to the main surface, that is, shallow, it can be easily connected to the charge path formed under the second gate electrode when the signal charge is transferred. In other words, since the transfer efficiency is high, it is possible to drive with a lower voltage compared to a configuration not using this configuration.

  Further, the dark current from the main surface is reduced by setting the first gate electrode 204 to a potential at which holes are accumulated in the fourth semiconductor region below the first gate electrode 204. It becomes possible.

  In this embodiment, the first gate electrode is always set to a constant potential, and the first gate electrode can perform common driving in all pixels. Therefore, the gate electrodes of all the pixels can be connected to the same control line, and the number of control lines and the control circuit can be reduced. In addition, the first gate electrode can be provided continuously over a plurality of pixels. With such a configuration, the pixel can be miniaturized.

(Second Embodiment)
This embodiment differs from the first embodiment in the control signal φ204. In the configuration of the first embodiment, the potential relationship between the first semiconductor region and the fourth semiconductor region is different.
FIG. 5 is an operation timing diagram, and FIG. 6 schematically shows the potential with respect to signal charges in each semiconductor region when the driving of FIG. 5 is performed. 5 corresponds to FIG. 3, and FIG. 6 corresponds to FIG. 4. In the case of similar functions, the same reference numerals are given, and the description thereof is omitted.

  First, in FIG. 5, the control signal φ204 is not always at a low level but at a high level at t3 (and t7). When the signal charge is transferred from the photoelectric conversion element 101, the control signal φ204 becomes a high level, so that the formation of a potential that becomes a barrier at the time of charge transfer can be suppressed and transfer efficiency can be improved. Description of other driving similar to that in FIG. 3 is omitted.

  Next, this transfer operation will be described in detail with reference to FIG. Description of the same state as in FIG. 4 is omitted. FIG. 6A shows an initial state in which no signal charge is generated in the photoelectric conversion element 101. 6B shows a state corresponding to t1 to t3 in FIG. 5, FIG. 6C shows a state between t3 and t11 in FIG. 5, and FIG. 6D shows t4 to t5 in FIG. Shows the state. Signal charges are indicated by hatching. L61 to L69 indicate the potential of each semiconductor region in each state.

  In FIG. 6A, the potential of the fourth semiconductor region 205 is L62, which is higher than the potential L63 of the first semiconductor region 202. Depending on the voltage of the first gate electrode 204 and the impurity concentration and depth of the fourth semiconductor region 205, such a potential relationship may occur. Of course, the potential relationship as in the first embodiment may be used. In FIG. 6B, signal charges are accumulated. In the case of the potential relationship of the present embodiment, the amount of signal charge that can be held is smaller than that of the first embodiment. In FIG. 6C, since the control signal φ206 is at the high level, the potential of the well below the second gate electrode 206 changes from L61 to L68. The control signal φ204 also goes high, and the potential of the fourth semiconductor region 205 becomes L66, which is lower than L62 to L63. By such an operation, the first semiconductor region 202 to the third semiconductor region 207 have a stepped potential, and signal charges can be transferred efficiently. In FIG. 6D, the control signal φ206 becomes low level, and the transfer of the signal charge is completed.

  Here, the operation between FIG. 6C and FIG. 6D, that is, t11 between t3 and t4 in FIG. 5 will be described. At t3 in FIG. 5, both the control signal φ204 and the control signal φ206 are at a high level. Then, at t11 in FIG. 5, the control signal φ204 becomes low level, and then the control signal φ206 becomes low level. That is, after the potential of the fourth semiconductor region 205 is returned from L66 to the potential L62, the potential of the well below the second gate electrode 206 is changed from L68 to L61. With such an operation, signal charges can be transferred to the third semiconductor region 207 without remaining in the fourth semiconductor region 205. Note that if the control signal φ206 is set to a low level before the control signal φ204, a potential L61 serving as a barrier may be formed between the potential L66 of the fourth semiconductor region 205 and the third semiconductor region 207. . In such a case, the signal charge tends to remain in the fourth semiconductor region, which is not desirable.

  As described above, by setting the control signal φ204 to the high level at the time of signal charge transfer, the transfer efficiency can be further improved as compared with the first embodiment. Of course, the driving method of this embodiment can also be applied to a configuration having a potential relationship between the first semiconductor region 202 and the fourth semiconductor region 205 as shown in FIG.

(Third embodiment)
This embodiment is different from the second embodiment in that the low level of the control signal φ204 and the control signal φ206 is different. In this embodiment, the low level of the control signal φ204 is set to −3V, and the low level of the control signal φ206 is set to −1V. That is, the low level of the voltage supplied to the second gate electrode is higher than the low level of the voltage supplied to the first gate electrode. With such a voltage relationship, the withstand voltage between the second gate electrode 206 and the third semiconductor region 207 can be improved. The reason is as follows. The third semiconductor region 207 is set to a high potential at reset. At this time, when a low-level voltage is supplied to the first gate electrode 204 and the second gate electrode 206, the electric field between the adjacent second gate electrode 206 and the third semiconductor region 207 may increase. is there. Therefore, the voltage between the adjacent second gate electrode 206 and the third semiconductor region 207 can be reduced by increasing the low-level voltage of the second gate electrode 206 higher than that of the first gate electrode 204. it can. Therefore, it is possible to reduce the mixing of dark current while maintaining the withstand voltage.

Next, the operation will be described in detail with reference to the operation timing chart of FIG. In the accumulation period of the photoelectric conversion element, the control signal φ204 and the control signal φ206 are at a low level. The value of the control signal φ204 at this time is a voltage (larger on the negative side) lower than the value of the control signal φ207.
In other words, the value of the low level control signal supplied to the second gate electrode is the value of the low level control signal supplied to the first gate electrode and the value of the high level supplied to the second gate electrode. Take between control signal values. By supplying such a voltage, mixing of dark current can be reduced and the breakdown voltage of the second gate electrode can be maintained. Of course, the driving method of this embodiment can also be applied to a configuration having a potential relationship between the first semiconductor region 202 and the fourth semiconductor region 205 as shown in FIG.

(Fourth embodiment)
In the present embodiment, the pixel configuration is different from that of the first embodiment. FIG. 8 is a schematic plan view showing elements as blocks. 801, 804, 813, and 816 are photoelectric conversion elements, 802, 805, 812, and 815 are charge holding units, 803, 806, 811 and 814 are charge transfer units, and 807 is a floating diffusion unit. The other elements are collectively shown as 808. The other elements are, for example, an amplification MOS transistor and a reset MOS transistor, and the detailed configuration is arbitrary. A pixel unit 800 includes four photoelectric conversion elements 801, 804, 813, and 816, and the reading circuit 808 is shared by the four photoelectric conversion elements. That is, it can be said that the pixel unit 800 includes four pixels. Each pixel includes a photoelectric conversion element, a charge holding unit, and a charge transfer unit. For example, the first pixel includes a photoelectric conversion element 801, a charge holding unit 802, and a charge transfer unit 803. The second pixel includes a photoelectric conversion element 804, a charge holding unit 805, and a charge transfer unit 806. The third pixel includes a photoelectric conversion element 813, a charge holding unit 812, and a charge transfer unit 811. The fourth pixel includes a photoelectric conversion element 816, a charge holding unit 815, and a charge transfer unit 814. The pixel unit 800 can be divided into a set of photoelectric conversion elements 801 and 804 and a set of photoelectric conversion elements 813 and 816. The charge transfer units 806 and 811 and the charge holding units 805 and 812 are shared by two photoelectric conversion elements. FIG. 9 shows a cross-sectional view of the pixel unit 800 taken along line AB, that is, one set of cross-sectional views.

  FIG. 9 is a schematic cross-sectional view taken along line AB of FIG. Reference numeral 901 denotes a well, 902 denotes a first conductivity type first semiconductor region, 903 denotes a second conductivity type second semiconductor region, 904 denotes a first gate electrode, and 905 denotes a first conductivity type fourth semiconductor region. , 906 are second gate electrodes, and 910 is a third semiconductor region. Further, 907 is a third gate electrode, 908 is a fifth semiconductor region of the first conductivity type, and 909 is a fourth gate electrode. Reference numeral 911 denotes a conductor constituting the contact, and 912 denotes an insulating film covering the element. Reference numeral 213 denotes a gate insulating film, and 214 denotes an element isolation region such as STI. Although not shown here, the first conductivity type semiconductor region of the photoelectric conversion element 804 is similar to the first semiconductor region 902. Reference numeral 900 denotes a semiconductor substrate on which a photoelectric conversion element is arranged, and reference numeral 915 denotes a main surface of the semiconductor substrate including a light receiving surface of the photoelectric conversion element 801. The dotted line indicates the position of the surface including the main surface 915. A direction from the main surface 915 toward the semiconductor substrate 900 is a downward direction or a deep direction.

The first semiconductor region 902 and the second semiconductor region 903 have a PN junction interface and constitute part of the photoelectric conversion element 101. The third semiconductor region 910 functions as a floating diffusion portion. A fifth semiconductor region 908 is disposed between the fourth semiconductor region 905 and the third semiconductor region 910. Then, the signal charge in the first semiconductor region 902 is transferred from the fourth semiconductor region 905 to the fifth semiconductor region 908 by the second gate electrode 906, and further to the third semiconductor region 910 by the fourth gate electrode 909. Forwarded to Here, the fourth semiconductor region 905 and the fifth semiconductor region 908 have a higher impurity concentration than the first semiconductor region 902 and are disposed closer to the main surface 212 than the first semiconductor region 902. The arrangement relation between the fourth semiconductor region 905 and the fifth semiconductor region 908 and the first conductivity type semiconductor region of the photoelectric conversion element 804 is also the same. The first semiconductor region 902 and the fourth semiconductor region 905 are electrically connected, and the fifth semiconductor region 908 and the first conductivity type semiconductor region of the photoelectric conversion element 804 are electrically connected. Yes. In other words, they are united or arranged continuously.
The upper portion of the fourth semiconductor region 905 is covered with the first gate electrode 904, and the upper portion of the fifth semiconductor region is covered with the third gate electrode 907. With such a configuration, the number of elements per photoelectric conversion element can be reduced as compared with the configuration of the first embodiment. Further, the fourth semiconductor region 905 and the fifth semiconductor region 908 having a high impurity concentration are arranged closer to the main surface 915 than the second semiconductor region 902. With such a configuration, signal charges can be efficiently transferred while facilitating control of conduction and non-conduction between the fifth semiconductor region 908 and the third semiconductor region 910. In addition, since a large number of signal charges can be stored in the n + region with a relatively low depletion voltage, an improvement in the number of saturated charges can be expected. Further, the total area of the same node portion as the floating diffusion portion can be made equal to that in the first embodiment. For example, when it becomes an input part of the MOS transistor for amplification, the voltage sensitivity per signal charge can be maintained as usual.

Next, an example of driving of such a photoelectric conversion device will be described with reference to an operation timing chart of FIG. φ 904 is a control signal for controlling the first gate electrode 904, and indicates a voltage supplied to the first gate electrode 904. φ906 is a control signal for controlling the second gate electrode 906, and indicates a voltage supplied to the second gate electrode 906. φ 907 is a control signal for controlling the third gate electrode 907 and indicates a voltage supplied to the third gate electrode 907.
φ 909 is a control signal for controlling the fourth gate electrode 909 and indicates a voltage supplied to the fourth gate electrode 909. In this embodiment, the low level of the control signal φ904 and the control signal φ907 is −3V, the high level is 5V, the low level of the control signal φ906 and the control signal φ909 is −1V, and the high level is 5V. The voltage (910) schematically shows a change in the voltage of the third semiconductor region 910. A state (910) indicates an operation performed in the third semiconductor region, and the state (shutter) indicates a state of a mechanical shutter of the imaging system, and indicates exposure and light shielding. t1 to t14 indicate timings. Hereinafter, driving will be described. Description of operations similar to those of the first embodiment is omitted.

  First, at t1, signal charges are accumulated in the photoelectric conversion element 801 and the photoelectric conversion element 804. The third semiconductor region 910 is supplied with a desired voltage (reset voltage) and is 5V. Next, at t2, the mechanical shutter is closed and shielded from light. At t3, the potential of the third semiconductor region 910 after reset is read. This read signal can be used as a noise signal in the signal from the photoelectric conversion element 804. Here, during the period from t1 to t3, the control signal φ904, the control signal φ906, the control signal φ907, and the control signal φ907 are at a low level. When the control signal φ904 is at a low level, charges (holes) having the opposite polarity to the signal charges are accumulated below the first gate electrode 904, and dark current from the main surface in the fourth semiconductor region 905 is reduced. It becomes possible to do. Further, since the control signal φ907 is at a low level, charges (holes) having a polarity opposite to that of the signal charges are accumulated below the third gate electrode 907, and darkness from the main surface in the fifth semiconductor region 908 occurs. The current can be reduced. In the present embodiment, the control signal φ904 is always set to a low level, and it is possible to always reduce the dark current. Further, by setting the control signal φ906 and the control signal φ909 to a low level, the fourth semiconductor region 905, the fifth semiconductor region 908, the fifth semiconductor region 908, and the third semiconductor region 910 are sufficiently provided. It is separated. At t4, the control signal φ907 and the control signal φ909 become high level. Here, signal charges from the photoelectric conversion element 804 are transferred to the third semiconductor region 910, and the voltage of the third semiconductor region 910 changes by the voltage ΔVsig. At t6, the transfer of the signal charge of the photoelectric conversion element 804 is completed, and a signal including the signal charge ΔVsig of the photoelectric conversion element 804 is read from the third semiconductor region 910. At t5 and t6, the control signal φ907 and the control signal φ909 are at the low level in this order, so that the remaining transfer of signal charge can be reduced.

  Next, at t7, the third semiconductor region 910 is reset, and the voltage of the third semiconductor region 910 becomes 5V. Then, reading of signal charges of the photoelectric conversion element 801 starts. At t8, the control signal φ906 becomes a high level, and signal charges are transferred from the first semiconductor region 902 and the fourth semiconductor region 905 to the fifth semiconductor region 908. During the period from t1 to t7, since the control signal φ904 is at a low level that reduces the dark current, the influence of the dark current on the signal charge is small. In addition, since the fourth semiconductor region 905 is provided, the transfer efficiency is improved and the voltage supplied as the high level of the control signal φ906 can be lowered. At t9, the potential of the third semiconductor region 910 after reset is read. This read signal can be used as a noise signal in the signal from the photoelectric conversion element 801. Further, the control signal φ907 becomes a high level, and the signal charge is transferred to the fifth semiconductor region 908 and held. Since there is no potential barrier between the photoelectric conversion element 804 and the charge holding portion 805, the photoelectric conversion element 804 can also be used for charge holding when holding signal charges. Even when the signal charge is large, the signal charge can be sufficiently retained. At t10, the control signal φ909 becomes a high level, and signal charges are transferred from the fifth semiconductor region 908 to the third semiconductor region 910. Here, since the control signal φ906, the control signal φ907, and the control signal φ909 are in the high level state, the second semiconductor region to the third semiconductor region are electrically connected to form a stepped potential relationship, so that the signal charge Can be efficiently transferred. From t11 to t13, the control signal φ906, the control signal φ907, and the control signal φ909 are sequentially set to a low level, so that the remaining transfer of signal charges can be reduced and the transfer efficiency to the third semiconductor region 910 can be improved. It becomes. Of course, the control signal φ906, the control signal φ907, and the control signal φ909 may be simultaneously at the low level. Here, the voltage of the third semiconductor region 910 changes by the voltage ΔVsig2 from the time t10 to the time t13 when the transfer of the signal charge to the third semiconductor region 910 starts. At t13, a signal based on the potential of the third semiconductor region 910 is output, and a signal including the voltage ΔVsig2 is read out. At t14, the third semiconductor region 910 is reset, returns to the state before exposure, and enters the state of t1 (exposure) by opening the mechanical shutter. Here, transfer is possible even when the control signal φ907 and the control signal φ909 simultaneously become high level at t10. Further, the control signal φ906, the control signal φ907, and the control signal φ909 after t8 may be simultaneously set to the high level if they do not overlap with the noise signal readout period.

  Next, the potential state of the semiconductor region in such driving will be described with reference to FIG. FIG. 11A to FIG. 11F schematically show the potential for the signal charge in each semiconductor region at a certain timing. Reference numeral 902 denotes that the first semiconductor regions 902 and 904 have a potential corresponding to the well below the second gate electrode 906, and the fourth semiconductor regions 905 and 906 below the first gate electrode 904. Reference numeral 907 denotes a fifth semiconductor region 908 below the third gate electrode 907, 909 denotes a well below the fourth gate electrode 909, and 910 denotes a potential corresponding to the third semiconductor region 910. FIG. 11A shows an initial state where no signal charges are generated in the photoelectric conversion element 801 and the photoelectric conversion element 804. 11B shows a state corresponding to t1 to t3 in FIG. 10, FIG. 11C shows a state at t6 in FIG. 10, and FIG. 11D shows a state at t9 in FIG. FIG.11 (e) shows the state of t12 of FIG. 10, FIG.11 (f) shows the state of t13. Signal charges are indicated by hatching. L101 to L112 indicate the potential of each semiconductor region in each state.

  In FIG. 11A, the fourth semiconductor region 905 and the fifth semiconductor region 908 have a higher impurity concentration than the first semiconductor region 902, and thus have a potential L103 lower than the potential L102 of the first semiconductor region 902. Have Here, although the potential below the second gate electrode 906 and the fourth gate electrode 907 is L101, it may have a higher potential. Here, a low level voltage is supplied to each gate electrode. In FIG. 11B, signal charges generated in the photoelectric conversion element 801 are accumulated in the second semiconductor region 902 and the fourth semiconductor region 905. At the same time, signal charges generated in the photoelectric conversion element 804 are accumulated in the fifth semiconductor region 908 and the first conductivity type semiconductor region (not shown) constituting the photoelectric conversion element 804. Here, for simplicity, it is assumed that the signal charge is the same amount L105 in the photoelectric conversion element 801 and the photoelectric conversion element 804. Thereafter, a signal charge reading operation from the photoelectric conversion element 804 is performed. Between FIG. 11B and FIG. 11C, a high-level voltage is supplied to the fourth gate electrode 909, the potential of the well below the fourth gate electrode 909 is lowered, and the fifth semiconductor region Signal charges are transferred from 908 to the third semiconductor region 910. FIG. 11C shows a state where a low level voltage is supplied to the fourth gate electrode 909. The signal charge of the photoelectric conversion element 804 held in the fifth semiconductor region 908 is held in the fourth semiconductor region. Here, the signal charge held in the fifth semiconductor region 908 can be completely transferred to the third semiconductor region 910. Thereafter, the operation of reading the signal charge of the photoelectric conversion element 801 starts.

  In FIG. 11D, a high level voltage is supplied to the second gate electrode 906 and the third gate electrode 907. The potential of the well below the second gate electrode 906 is changed from L101 to L107, and the potential of the fifth semiconductor region 908 is changed from L103 to L109. At this time, the potential from the fourth semiconductor region 905 to the fifth semiconductor region 908 is stepped, and the photoelectric conversion element 801 held in the second semiconductor region 902 and the fourth semiconductor region 905 has a staircase shape. Signal charges are efficiently transferred to the fifth semiconductor region 905. In FIG. 11E, a high-level voltage is supplied to the fourth gate electrode 909, and the potential of the well below the fourth gate electrode 909 decreases from L101 to L111. Here, since a stepped potential is formed from the fifth semiconductor region 908 to the third semiconductor region 910, signal charges are efficiently transferred from the fifth semiconductor region 908 to the third semiconductor region 910. . In FIG. 11F, a low-level voltage is supplied to the fourth gate electrode 909, the potential of the well below the fourth gate electrode 909 becomes L101, and the transfer of signal charges is completed.

  As described above, according to the configuration of the present embodiment, the number of elements can be reduced as compared with the configuration of the first embodiment. Further, the fourth semiconductor region 905 having a high impurity concentration is disposed closer to the main surface 915 than the second semiconductor region 902. With this configuration, signal charge can be efficiently transferred while facilitating control of conduction and non-conduction between the fourth semiconductor region 905 and the fifth semiconductor region 908. In addition, the fifth semiconductor region 908 having a high impurity concentration is disposed closer to the main surface 915 than the first conductivity type semiconductor region (not shown) included in the photoelectric conversion element 804. With this configuration, signal charges can be efficiently transferred while facilitating control of conduction and non-conduction between the fifth semiconductor region 908 and the third semiconductor region 910. Therefore, the transfer efficiency of signal charges from the first semiconductor region 902 to the third semiconductor region 910 can be improved. In addition, since a large number of signal charges can be stored in the n + region with a relatively low depletion voltage, an improvement in the number of saturated charges can be expected.

  In addition, since the first gate electrode 904 and the third gate electrode 907 are set to potentials such that holes are accumulated below the respective gate electrodes, the fourth semiconductor region 905 and the fifth gate electrode 907 are set. The dark current from the main surface in the semiconductor region 908 can be reduced. Here, since the first gate electrode 904 may be always set to a constant potential, a gate electrode commonly connected to all pixels can be used. Since all the pixels may be common, the number of control lines and control circuits can be reduced, and a gate electrode can be provided in common, so that the pixels can be miniaturized. Of course, the first gate electrode 904 may be driven as in the second embodiment.

  Here, in the present embodiment, the driving when the mechanical shutter is used has been described. The presence of the mechanical shutter can eliminate the influence of the signal charge generated in the photoelectric conversion element 804 when reading the signal charge of the photoelectric conversion element 801 in the driving of FIG. However, the use of a mechanical shutter is optional.

  In this embodiment, the configuration in which the pixel unit includes four photoelectric conversion elements has been described. However, the pixel unit includes two photoelectric conversion elements 801 and 804, and another circuit 808. May be. The number of photoelectric conversion elements included in the pixel unit is arbitrary.

(Application to imaging system)
In this embodiment, the case where the photoelectric conversion device described in the first to fourth embodiments is applied to an imaging system will be described with reference to FIG. The imaging system is a digital still camera, a digital video camera, or a digital camera for mobile phones.

  FIG. 12 is a block diagram of a digital still camera. The optical image of the subject is formed on the imaging surface of the photoelectric conversion device 1204 by an optical system including the lens 1202 and the like. On the outside of the lens 1202, a barrier 1201 that serves as a protection function of the lens 1202 and a main switch can be provided. The lens 1202 can be provided with a diaphragm 1203 for adjusting the amount of light emitted therefrom. The imaging signal output from the photoelectric conversion device 1204 through a plurality of channels is subjected to various corrections, clamping, and the like by the imaging signal processing circuit 1205. Imaging signals output from the imaging signal processing circuit 1205 through a plurality of channels are subjected to analog-digital conversion by an A / D converter 1206. The image data output from the A / D converter 1206 is subjected to various corrections, data compression, and the like by a signal processing unit (image processing unit) 1207. The photoelectric conversion device 1204, the imaging signal processing circuit 1205, the A / D converter 1206, and the signal processing unit 1207 operate according to the timing signal generated by the timing generation unit 1208. Each block is controlled by the overall control / arithmetic unit 1209. In addition, a memory unit 1210 for temporarily storing image data and a recording medium control interface unit 1211 for recording or reading an image on a recording medium are provided. The recording medium 1212 includes a semiconductor memory or the like and can be attached and detached. Furthermore, an external interface (I / F) unit 1213 for communicating with an external computer or the like may be provided. Here, 1205 to 1208 may be formed on the same chip as the photoelectric conversion device 1204.

Next, the operation of FIG. 9 will be described. When the barrier 1201 is opened, the main power source, the control system power source, and the power source of the imaging system circuit such as the A / D converter 1206 are sequentially turned on.
Thereafter, in order to control the exposure amount, the overall control / calculation unit 1209 opens the aperture 1203. A signal output from the photoelectric conversion device 1204 passes through the imaging signal processing circuit 1205 and is provided to the A / D converter 1206. The A / D converter 1206 performs A / D conversion on the signal and outputs the signal to the signal processing unit 1207. The signal processing unit 1207 processes the data and provides the processed data to the overall control / calculation unit 1209, and the overall control / calculation unit 1209 performs computation to determine the exposure amount. The overall control / calculation unit 1209 controls the aperture based on the determined exposure amount.

  Next, the overall control / calculation unit 1209 extracts a high frequency component from the signal output from the photoelectric conversion device 1204 and processed by the signal processing unit 1207, and calculates the distance to the subject based on the high frequency component. Thereafter, the lens 1202 is driven to determine whether or not it is in focus. If it is determined that the subject is not in focus, the lens 1202 is driven again to calculate the distance.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the imaging signal output from the photoelectric conversion device 1204 is corrected by the imaging signal processing circuit 1205, A / D converted by the A / D converter 1206, and processed by the signal processing unit 1207. The image data processed by the signal processing unit 1207 is accumulated in the memory unit 1210 by the overall control / calculation unit 1209. Thereafter, the image data stored in the memory unit 1210 is recorded on the recording medium 1212 via the recording medium control I / F unit under the control of the overall control / calculation unit 1209. The image data is provided to a computer or the like through the external I / F unit 1213 and processed.

  Thus, the photoelectric conversion device of the present invention is applied to an imaging system. By using the photoelectric conversion device of the present invention, driving with a low voltage is possible, so that power consumption in the imaging system can be reduced. In addition, since the signal charge transfer efficiency is improved, a good image signal can be obtained.

  According to the present invention, a high-concentration first-conductivity-type fourth semiconductor region 205 is formed on the main surface 212 more than the second semiconductor region 202 constituting the photoelectric conversion element 101 under most of the first gate electrode 204. It is possible to improve the transfer efficiency by arranging at a close depth. Further, dark current is suppressed by controlling the voltage value of the first gate electrode 204 instead of the second conductive type second semiconductor region 203 on the surface of the photoelectric conversion element 101. Further, since the transfer efficiency is high, the voltage for charge transfer applied to the second gate electrode at the time of charge transfer may be small. Therefore, even if the concentration of the fourth semiconductor region 205 is high, the drive voltage can be reduced. It can be controlled within the voltage range used in the CMOS process. As a result, it is possible to increase the number of saturated charges.

Hereinafter, the present invention has been described with specific embodiments, but the present invention is not limited to these embodiments. Modifications and combinations can be made as appropriate without departing from the gist of the invention. For example, in the embodiment, the signal charge has been described as an electron, but it may be a hole. In this case, the conductivity type of each semiconductor region becomes a reverse conductivity type, and the polarity of the supplied voltage is only reversed. Furthermore, although the low level of the first gate electrode and the voltage supplied to the second gate electrode as a negative voltage may be the same to a positive voltage.

Further, the low level of the control signal φ204 is not limited to −1V, and holes may be accumulated below the first gate electrode 204. The low level of the control signal φ204 and the control signal φ206 may be sufficient if the photoelectric conversion element 101 and the third semiconductor region 207 can be electrically separated (in a non-conducting state). Can be performed.
In addition, the first semiconductor region and the second semiconductor region may be disposed under the first gate electrode 204 (region 102).

200 Semiconductor substrate 201 Second conductivity type well 202 First conductivity type first semiconductor region 203 Second conductivity type second semiconductor region 204 First gate electrode 205 First conductivity type fourth semiconductor region 206 Second gate electrode 207 Third semiconductor region of first conductivity type 212 Main surface

Claims (17)

A photoelectric conversion device having a plurality of pixel units each including a first pixel, a second pixel, a floating diffusion portion, and a readout circuit,
The first pixel has a first photoelectric conversion element, a first charge holding unit for holding the charge of the first photoelectric conversion element, and a first charge holding unit for transferring the charge of the first charge holding unit. 1 charge transfer unit,
The second pixel transfers the second photoelectric conversion element, a second charge holding unit for holding the charge of the second photoelectric conversion element, and the charge of the second charge holding unit. A second charge transfer unit for
In plan view, a semiconductor region that constitutes the floating diffusion portion is disposed between the first charge transfer portion and the second charge transfer portion ,
An amplification transistor and a reset transistor included in the readout circuit of one pixel unit are arranged between the first photoelectric conversion element and the second photoelectric conversion element arranged in the first direction,
An amplification transistor included in the readout circuit of the one pixel unit between the semiconductor regions constituting the floating diffusion portion of the two pixel units arranged along a second direction intersecting the first direction; Reset transistor is arranged,
A first gate electrode is disposed adjacent to the first photoelectric conversion element in a plan view;
The electric charge of the first photoelectric conversion element is held in a region under the first gate electrode,
A second gate electrode is disposed adjacent to the second photoelectric conversion element in a plan view;
The photoelectric conversion device, wherein a charge of the second photoelectric conversion element is held in a region under the second gate electrode . In the first pixel, the charge of the first photoelectric conversion element is read as a signal through the first charge holding unit, the first charge transfer unit, and the floating diffusion unit in this order. Issued,
In the second pixel, the charge of the second photoelectric conversion element is read out as a signal through the second charge holding unit, the second charge transfer unit, and the floating diffusion unit in this order. The photoelectric conversion device according to claim 1, wherein: The floating diffusion section, in plan view, the photoelectric conversion device according possible to claim 1 or 2, characterized in that arranged between the first charge carrier holding portion and the second charge carrier holding portion. 4. The device according to claim 1, wherein a part of the readout circuit is arranged between the first charge transfer unit and the second charge transfer unit in a plan view. 5 . The photoelectric conversion device described. Before SL first photoelectric conversion element has a first semiconductor region of a first conductivity type disposed in the semiconductor substrate,
The first charge holding portion includes a second semiconductor region of the first conductivity type disposed on the semiconductor substrate,
Before the second photoelectric conversion element SL has a third semiconductor region of the first conductivity type disposed on said semiconductor substrate,
5. The photoelectric conversion device according to claim 1, wherein the second charge holding unit includes a fourth semiconductor region of the first conductivity type disposed on the semiconductor substrate. 6. . The second semiconductor region is provided at a depth closer to the main surface of the semiconductor substrate than the first semiconductor region;
The photoelectric conversion device according to claim 5, wherein the fourth semiconductor region is provided at a depth closer to the main surface than the third semiconductor region. The second semiconductor region has a higher impurity concentration of the first conductivity type than the first semiconductor region,
The photoelectric conversion device according to claim 5, wherein the fourth semiconductor region has an impurity concentration of the first conductivity type higher than that of the third semiconductor region. It said first gate electrode is not covered over the second semiconductor region,
The second gate electrode, a photoelectric conversion device according to any one of claims 5 to 7, characterized in the TURMERIC covering over said fourth semiconductor region. The first charge holding unit holds electrons;
A first voltage and a second voltage higher than the first voltage are supplied to the first gate electrode;
9. The first voltage is supplied to the first gate electrode during at least a part of a period in which the first charge holding portion holds charge. Item 1. The photoelectric conversion device according to item 1. 10. The photoelectric conversion device according to claim 9, wherein the first voltage is a voltage for storing a charge having a polarity opposite to that of the signal charge under the first gate electrode. 11. When the first voltage is supplied to the first gate electrode, the potential of the region under the first gate electrode is higher than the potential of the first photoelectric conversion element with respect to electrons. ,
When the second voltage is supplied to the first gate electrode, the potential of the region under the first gate electrode is lower than the potential of the first photoelectric conversion element with respect to electrons. The photoelectric conversion device according to claim 9 or 10, wherein: 12. The third voltage supplied to the first charge transfer unit to make the first charge transfer unit non-conductive is higher than the first voltage. The photoelectric conversion apparatus of any one of these. The first charge holding unit holds holes;
A first voltage and a second voltage lower than the first voltage are supplied to the first gate electrode;
9. The first voltage is supplied to the first gate electrode during at least a part of a period in which the first charge holding portion holds charge. Item 1. The photoelectric conversion device according to item 1. 14. The photoelectric conversion device according to claim 13, wherein the first voltage is a voltage for storing a charge having a polarity opposite to that of the signal charge under the first gate electrode. When the first voltage is supplied to the first gate electrode, the potential of the region below the first gate electrode is higher than the potential of the first photoelectric conversion element with respect to holes. high,
When the second voltage is supplied to the first gate electrode, the potential of the region below the first gate electrode is higher than the potential of the first photoelectric conversion element with respect to holes. The photoelectric conversion device according to claim 13 or 14, wherein the photoelectric conversion device is low. 16. The third voltage supplied to the first charge transfer unit to make the first charge transfer unit non-conductive is lower than the first voltage. The photoelectric conversion apparatus of any one of these. The photoelectric conversion device according to any one of claims 1 to 16 ,
And a processing circuit that processes a signal output from the photoelectric conversion device.

Images