JP5698714B2 - Nonvolatile memory device - Google Patents

Description

  Embodiments described herein relate generally to a nonvolatile memory device.

  As a nonvolatile memory device, there is a resistance change type memory (resistance change type nonvolatile memory device). In the resistance change type memory, for example, a memory having a higher density than a floating gate type NAND-Flash memory can be realized. In the variable resistance nonvolatile memory device, further higher memory density is desired.

U.S. Pat. No. 8,072,215

  Embodiments of the present invention provide a high storage density nonvolatile memory device.

According to the embodiment of the present invention, a nonvolatile memory device including a first conductive part, a second conductive part, and a storage layer is provided. The second conductive part may be at least one metal atom of lithium, chromium, iron, copper, indium, tellurium, calcium, sodium, silver, cobalt, gold, titanium, tungsten, erbium, platinum, aluminum, and nickel, or An alloy containing at least one metal atom is included. The storage layer includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first semiconductor layer is provided between the first conductive portion and the second conductive portion, and is in contact with the first conductive portion . The second semiconductor layer is provided between the first semiconductor layer and the second conductive part, and is in contact with the first semiconductor layer and in contact with the second conductive part . The memory layer has a resistance lower than that of the first state and the first state due to at least one of a voltage applied via the first conductive portion and the second conductive portion and a supplied current. Transition reversibly between high second states.

1 is a schematic cross-sectional view showing a nonvolatile memory device according to a first embodiment. It is a graph which shows the characteristic of the non-volatile memory device which concerns on 1st Embodiment. FIG. 3A to FIG. 3C are schematic cross-sectional views showing a part of the nonvolatile memory device according to the first embodiment. FIG. 4A to FIG. 4C are schematic band diagrams showing characteristics of the nonvolatile memory device according to the first embodiment. FIG. 4 is a schematic cross-sectional view showing another nonvolatile memory device according to the first embodiment. It is a graph which shows the characteristic of another nonvolatile memory device concerning a 1st embodiment. It is a graph which shows the characteristic of another nonvolatile memory device concerning a 1st embodiment. FIG. 8A to FIG. 8C are schematic cross-sectional views showing other nonvolatile memory devices according to the first embodiment. It is a typical perspective view which shows the non-volatile memory device which concerns on 2nd Embodiment. FIG. 6 is a schematic circuit diagram showing a nonvolatile memory device according to a second embodiment. FIG. 4 is a schematic cross-sectional view showing a part of a nonvolatile memory device according to a second embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic cross-sectional view illustrating the configuration of the nonvolatile memory device according to the first embodiment.
As illustrated in FIG. 1, the nonvolatile memory device 110 according to the present embodiment includes a first conductive unit 10, a second conductive unit 20, and a storage layer 15. The memory layer 15 is provided between the first conductive unit 10 and the second conductive unit 20.

  For example, a voltage applied via the first conductive unit 10 and the second conductive unit 20 is applied to the memory layer 15. For example, a current is supplied to the memory layer 15 via the first conductive unit 10 and the second conductive unit 20. The storage layer 15 has a first state (low resistance state) having a low resistance and a second state (high resistance state) having a higher resistance than the first state by at least one of an applied voltage and a supplied current. Can be reversibly transitioned between.

  The nonvolatile storage device 110 stores information by transition of the state of the storage layer 15. For example, the high resistance state is set to “0” of the digital signal, and the low resistance state is set to “1” of the digital signal. Thereby, 1-bit information of the digital signal can be stored.

  Here, the stacking direction of the first conductive portion 10 and the second conductive portion 20 is defined as the Z-axis direction. For example, the Z-axis direction is orthogonal to the surface of the first conductive unit 10, the surface of the second conductive unit 20, and the surface of the storage layer 15.

  The first conductive unit 10 includes, for example, at least one of tungsten, molybdenum, titanium, chromium, tantalum, and nickel. For example, TiN is used for the first conductive unit 10. The conductive material used for the first conductive portion 10 may be, for example, a semiconductor material into which impurities are introduced. For example, the first conductive part 10 may be silicon into which boron is introduced.

  The second conductive unit 20 includes, for example, at least one metal atom of lithium, chromium, iron, copper, indium, tellurium, calcium, sodium, silver, cobalt, gold, titanium, tungsten, erbium, platinum, aluminum, and nickel. Including. The second conductive portion 20 may include, for example, an alloy containing at least one of the metal atoms. For example, an alloy such as silicide may be used for the second conductive portion 20. In this example, the second conductive unit 20 includes silver. The second conductive portion 20 may further include a conductive matrix material. The at least one metal atom or alloy of the second conductive part 20 may be contained in, for example, a matrix material. For example, metal atoms or alloys are surrounded by the matrix material. Metal atoms or alloys are dispersed in the matrix material. In this case, the cohesive energy of the metal atoms or the cohesive energy of the alloy is made lower than the cohesive energy of the matrix material. “Agglomeration energy” is an attractive force that acts between atoms, and is the energy required to separate atoms or ions that make up a liquid or solid to infinity. Atoms with low cohesive energy are easier to ionize than atoms with high cohesive energy. That is, metal atoms or alloys are easier to ionize than matrix materials.

  As the matrix material, for example, at least one of tungsten, molybdenum, titanium, chromium, tantalum, and nickel is used. The matrix material may be, for example, a semiconductor material into which impurities are introduced. For example, the matrix material may be silicon doped with phosphorus.

The storage layer 15 includes a first conductivity type first semiconductor layer 31 and a second conductivity type second semiconductor layer 32. The first semiconductor layer 31 is provided between the first conductive unit 10 and the second conductive unit 20. The second semiconductor layer 32 is provided between the first semiconductor layer 31 and the second conductive unit 20. The first conductivity type is, for example, an n type. The second conductivity type is, for example, a p-type . In later than performs the described first conductivity type is n-type, the second conductivity type is p-type. That is, the first semiconductor layer 31 is an n-type semiconductor layer, and the second semiconductor layer 32 is a p-type semiconductor layer.

  In this example, the first semiconductor layer 31 is in contact with the second semiconductor layer 32. The first semiconductor layer 31 and the second semiconductor layer 32 are in pn junction with each other. The first semiconductor layer 31 is in contact with the first conductive unit 10. The second semiconductor layer 32 is in contact with the second conductive unit 20. The memory layer 15 has a first surface 15 a that faces the first conductive portion 10, and a second surface 15 b that faces the second conductive portion 20. The second surface 15b is a surface opposite to the first surface 15a. In this example, the first surface 15 a is in contact with the first conductive portion 10, and the second surface 15 b is in contact with the second conductive portion 20.

  For the first semiconductor layer 31 and the second semiconductor layer 32, for example, a semiconductor material such as polysilicon or amorphous silicon is used. The first semiconductor layer 31 is formed, for example, by introducing a donor such as arsenic or phosphorus into a semiconductor material. The second semiconductor layer 32 is formed, for example, by introducing an acceptor such as boron into a semiconductor material.

  The thickness (length along the Z-axis direction) of the first semiconductor layer 31 is, for example, 100 nm (50 nm or more and 200 nm or less). The thickness of the second semiconductor layer 32 is, for example, 400 nm (200 nm or more and 600 nm or less).

FIG. 2 is a graph illustrating characteristics of the nonvolatile memory device according to the first embodiment.
FIG. 2 shows a concentration profile of impurities contained in the memory layer 15.
The horizontal axis in FIG. 2 is the position z (nm) in the Z-axis direction, and the vertical axis is the impurity concentration IC (cm ⁻³ ). In FIG. 2, the solid line represents the acceptor concentration, and the broken line represents the donor concentration.
As illustrated in FIG. 2, the concentration of the donor included in the first semiconductor layer 31 is, for example, about 7 × 10 ¹⁸ cm ⁻³ (1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less). is there. The concentration of the acceptor included in the second semiconductor layer 32 is, for example, about 1 × 10 ²¹ cm ⁻³ (1 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less).

FIG. 3A to FIG. 3C are schematic cross-sectional views illustrating the configuration of a part of the nonvolatile memory device according to the first embodiment.
3A shows the memory layer 15 in the high resistance state, and FIGS. 3B and 3C show the memory layer 15 in the low resistance state.
As illustrated in FIG. 3A to FIG. 3C, the storage layer 15 includes a metal portion 16 that extends from the second surface 15 b toward the first surface 15 a. The metal part 16 includes metal atoms contained in the second conductive part 20. That is, in this example, the metal part 16 contains silver.

  The metal part 16 changes the length D1 along the Z-axis direction by at least one of a voltage applied via the first conductive part 10 and the second conductive part 20 and a supplied current. The length D1 of the metal part 16 varies depending on at least one of a voltage applied via the first conductive part 10 and the second conductive part 20 and a supplied current. The memory layer 15 transitions between a low resistance state and a high resistance state depending on the length D1 of the metal portion 16.

  As shown in FIGS. 3A to 3C, the memory layer 15 is in a high resistance state when the length D1 of the metal portion 16 is shortened, and is a state where the length D1 of the metal portion 16 is lengthened. In a low resistance state. The metal part 16 may be called a filament, a metal bridge, etc., for example.

  In order to increase the length D1 of the metal part 16, a forward voltage is applied between the first conductive part 10 and the second conductive part 20. The forward voltage is realized, for example, by grounding the first conductive unit 10 and applying a positive voltage to the second conductive unit 20. That is, in the forward voltage, the potential of the second conductive unit 20 is set higher than the potential of the first conductive unit 10.

  When a forward voltage is applied between the first conductive part 10 and the second conductive part 20, silver atoms contained in the second conductive part 20 are ionized to become positive silver ions. Silver ions diffuse into the storage layer 15 by the electric field between the first conductive unit 10 and the second conductive unit 20. Then, the silver ions are combined with electrons supplied from the first conductive unit 10 in the memory layer 15 and become silver atoms. As described above, when a forward voltage is applied between the first conductive unit 10 and the second conductive unit 20, silver atoms (metal atoms) included in the second conductive unit 20 are precipitated in the storage layer 15. That is, the metal part 16 is formed by silver atoms. Thereby, the length D1 of the metal part 16 becomes long by application of a forward voltage.

  When the length D1 of the metal part 16 is shortened, a reverse voltage is applied between the first conductive part 10 and the second conductive part 20. The reverse voltage is realized, for example, by applying a positive voltage to the first conductive unit 10 and grounding the second conductive unit 20. That is, in the reverse voltage, the potential of the second conductive unit 20 is made lower than the potential of the first conductive unit 10.

  When a reverse voltage is applied between the first conductive part 10 and the second conductive part 20, the silver atoms contained in the metal part 16 are ionized to become positive silver ions. Silver ions move from the storage layer 15 toward the second conductive unit 20 by the electric field between the first conductive unit 10 and the second conductive unit 20. Thereby, the length D1 of the metal part 16 becomes short by application of the voltage of a reverse direction.

（１）式には、
第１半導体層３１と金属部１６との間のＺ軸方向に沿う距離Δｄ（ｃｍ）、
第２半導体層３２の誘電率ε_ｓｅｍ（Ｆｃｍ^−１）、
金属部１６のフェルミ準位を基準にした第２半導体層３２の伝導バンドのショットキー・バリア高さφ_Ｂ（ｅＶ）（図４参照）、
単位素電荷ｑ（Ｃ）、及び、
第２半導体層３２の不純物濃度Ｎ_ｘ（ｃｍ^−３）、
が示される。
距離Δｄは、より詳しくは、金属部１６のＺ軸方向の端部１６ａと第１半導体層３１との間のＺ軸方向に沿う距離である。単位素電荷ｑは、例えば、約１．６×１０^−１９Ｃである。不純物濃度Ｎ_ｘは、アクセプタの濃度とドナーの濃度との差分で表される実効的な不純物濃度である。不純物濃度Ｎ_ｘは、いわゆるネット濃度である。 The memory layer 15 is in a low resistance state when the first condition represented by the expression (1) is satisfied, and is in a high resistance state when the first condition is not satisfied.

(1)
A distance Δd (cm) along the Z-axis direction between the first semiconductor layer 31 and the metal part 16,
Dielectric constant ε _sem (Fcm ⁻¹ ) of the second semiconductor layer 32,
Schottky barrier height φ _B (eV) of the conduction band of the second semiconductor layer 32 with reference to the Fermi level of the metal part 16 (see FIG. 4),
Unit elementary charge q (C), and
Impurity concentration N _x (cm ⁻³ ) of the second semiconductor layer 32,
Is shown.
More specifically, the distance Δd is a distance along the Z-axis direction between the end 16 a of the metal part 16 in the Z-axis direction and the first semiconductor layer 31. The unit elementary charge q is, for example, about 1.6 × 10 ⁻¹⁹ C. The impurity concentration N _x is an effective impurity concentration represented by the difference between the acceptor concentration and the donor concentration. The impurity concentration N _x is a so-called net concentration.

  3A to 3C show the length D2 of the shortest metal portion 16 that is in a low resistance state. The length D2 is a case where the right side and the left side are equal in the equation (1). In FIG. 3A, which is in a high resistance state, the length D1 is shorter than the length D2. In FIG. 3 (b) and FIG. 3 (c) in the low resistance state, the length D1 is longer than the length D2.

  As shown in FIG. 3C, the metal part 16 may penetrate the second semiconductor layer 32. The length D 1 of the metal part 16 may be longer than the thickness of the second semiconductor layer 32. In this case, the metal part 16 is in contact with the first semiconductor layer 31. That is, the metal part 16 and the first semiconductor layer 31 are Schottky joined to each other.

FIG. 4A to FIG. 4C are schematic band diagrams illustrating characteristics of the nonvolatile memory device according to the first embodiment.
4A to 4C, the vertical axis represents the potential energy En, and the horizontal axis represents the position z in the Z-axis direction.
In FIG. 4A, the length D1 is shorter than the length D2. In FIGS. 4B and 4C, the length D1 is longer than the length D2. 4B, the length D1 is shorter than the thickness of the second semiconductor layer 32. In FIG. 4C, the length D1 is longer than the thickness of the second semiconductor layer 32. 4 (a) corresponds to the state of FIG. 3 (a), FIG. 4 (b) corresponds to the state of FIG. 3 (b), and FIG. 4 (c) corresponds to FIG. 3 (c). Corresponds to the state of

As shown in FIG. 4A, when the length D1 is shorter than the length D2 (when the first condition is not satisfied), the memory layer 15 exhibits the characteristics of a pn junction diode.
On the other hand, as shown in FIG. 4C, when the metal portion 16 penetrates the second semiconductor layer 32 and reaches the first semiconductor layer 31, the memory layer 15 exhibits the characteristics of a Schottky barrier diode.
As shown in FIG. 4B, when the length D1 is longer than the length D2 (when the first condition is satisfied), the second semiconductor between the metal portion 16 and the first semiconductor layer 31 is used. The thickness of the layer 32 is reduced and exhibits substantially the same characteristics as the Schottky barrier diode.

  The resistance value when a forward voltage is applied to the Schottky barrier diode is lower than the resistance value when a forward voltage is applied to the pn junction diode. Thereby, by making the length D1 of the metal part 16 longer than the length D2, the memory layer 15 becomes in a low resistance state, and by making the length D1 of the metal part 16 shorter than the length D2, the memory layer 15 becomes High resistance state.

  In the memory layer 15 in the low resistance state, the first semiconductor layer 31 and the second semiconductor layer 32 are pn-junctioned at portions other than the metal portion 16 in the memory layer 15. When a reverse voltage is applied to the memory layer 15 in the low resistance state, a depletion layer extending from the pn junction portion also extends between the metal portion 16 and the first semiconductor layer 31. As a result, the reverse current flowing from the first conductive portion 10 toward the second conductive portion 20 is blocked by the depletion layer of the pn junction. Thus, in the nonvolatile memory device 110, when a forward voltage is applied, a low ON voltage of the Schottky junction can be obtained, and when a reverse voltage is applied, the pn A low junction leakage current can be obtained.

  In the nonvolatile memory device 110, the memory layer 15 has a function as a resistance change element that changes a resistance value by voltage or current and a function as a rectifier element that suppresses the generation of an unintended current path. For this reason, in the nonvolatile memory device 110, there is no need to separately provide a rectifying element or the like, which is advantageous for miniaturization. For example, the nonvolatile memory device 110 can be made thinner than the conventional configuration in which the resistance change element and the rectifying element are stacked in the Z-axis direction. Thereby, according to the nonvolatile memory device 110, the memory density can be improved.

  Further, in the configuration of the conventional nonvolatile memory device that connects the variable resistance element and the rectifying element, there are many parasitic resistances accompanying the connection between the variable resistance element and the rectifying element. On the other hand, in the nonvolatile memory device 110, since there is no need to connect the resistance change element and the rectifying element, parasitic resistance can be suppressed.

  In the nonvolatile memory device 110, the length D1 of the metal part 16 is defined by the first condition expressed by the equation (1). The first condition defines the length D1 of the metal part 16 by the depletion layer width of the Schottky barrier. Thereby, the relationship between the metal atom of the 2nd electroconductive part 20, the structure of the metal part 16, and an operating voltage and an operating current can be controlled appropriately.

  The metal atoms contained in the second conductive unit 20 can be classified into, for example, a group of metal atoms that are difficult to form an alloy and a group of metal atoms that are easy to form an alloy. Examples of the group of metal atoms that are difficult to form an alloy include lithium, chromium, indium, tellurium, calcium, and sodium. On the other hand, examples of the group of metal atoms that easily form an alloy include cobalt, iron, copper, titanium, tungsten, erbium, platinum, aluminum, nickel, silver, and gold.

  When metal atoms that easily form an alloy are used for the second conductive portion 20, for example, metal atoms included in the second conductive portion 20 are bonded to silicon included in the second semiconductor layer 32 and include silicide. The metal part 16 can be formed. For example, monosilicide has higher diffusibility in the second semiconductor layer 32 than disilicide. The conductivity of disilicide is higher than that of monosilicide containing the same metal atom.

  For example, when a metal atom that easily forms an alloy is used for the second conductive portion 20, when the memory layer 15 is changed from the high resistance state to the low resistance state, the first conductive portion 10 and the second conductive portion 20 A voltage is applied between them, and the temperature of at least one of the storage layer 15 and the second conductive portion 20 is set to a first temperature at which the metal atoms are easily monosilicided. Thereby, for example, the metal part 16 including monosilicide that easily diffuses into the second semiconductor layer 32 is formed, and the length D1 of the metal part 16 can be easily changed. That is, the controllability of the length D1 of the metal part 16 can be enhanced.

  In addition, after the storage layer 15 is brought into the low resistance state, the temperature of at least one of the storage layer 15 and the second conductive portion 20 is set to a second temperature at which the metal atoms are easily disilicided. Silicidize. Thereby, the length D1 of the metal part 16 becomes difficult to change compared with the case where monosilicide is included. That is, the storage retention time of the storage layer 15 can be appropriately maintained.

  In general, the second temperature is higher than the first temperature. The first temperature and the second temperature can be set, for example, by providing the nonvolatile memory device 110 with a temperature adjusting unit that adjusts the temperature of at least one of the storage layer 15 and the second conductive unit 20. A heater etc. can be used for a temperature control part, for example.

  As described above, by using metal atoms that easily form an alloy for the second conductive portion 20, for example, the metal portion 16 can be silicided, and the degree of freedom of design and operation of the nonvolatile memory device 110 is increased. be able to. Thus, in the second conductive portion 20, it is more preferable to use metal atoms that are easy to form an alloy.

FIG. 5 is a schematic cross-sectional view illustrating the configuration of another nonvolatile memory device according to the first embodiment.
As illustrated in FIG. 5, the nonvolatile storage device 111 includes a control unit 40. The control unit 40 is electrically connected to the first conductive unit 10 and the second conductive unit 20. The control unit 40 applies a voltage between the first conductive unit 10 and the second conductive unit 20 to switch between the low resistance state and the high resistance state of the storage layer 15 and to change the state of the storage layer 15. Read.

  The control unit 40 applies a forward write voltage between the first conductive unit 10 and the second conductive unit 20 when the storage layer 15 is transitioned from the high resistance state to the low resistance state. In the write voltage, the potential difference between the first conductive unit 10 and the second conductive unit 20 is set to 5 V, for example.

  The control unit 40 applies a reset voltage in the reverse direction between the first conductive unit 10 and the second conductive unit 20 when the storage layer 15 is transitioned from the low resistance state to the high resistance state. In the reset voltage, the potential difference between the first conductive unit 10 and the second conductive unit 20 is set to 5 V, for example.

（２）式には、
読み出し電圧Ｖ_ｒｅａｄ（Ｖ）、
ボルツマン定数ｋ_Ｂ（ＪＫ^−１）、
絶対温度Ｔ_Ａ（Ｋ）、
単位素電荷ｑ（Ｃ）、
第２半導体層３２に含まれる電子の濃度Ｎ_ｎ（ｃｍ^−３）、及び、
第２半導体層３２に含まれる正孔の濃度Ｎ_ｐ（ｃｍ^−３）、
が示される。
ボルツマン定数ｋ_Ｂは、例えば、約１．３８×１０^−２３（ＪＫ^−１）である。 When reading the state of the storage layer 15, the control unit 40 applies a read voltage that is a forward voltage smaller than the write voltage between the first conductive unit 10 and the second conductive unit 20.
The control unit 40 applies a read voltage that satisfies the second condition expressed by equation (2).

(2)
Read voltage V _read (V),
Boltzmann constant k _B (JK ⁻¹ ),
Absolute temperature T _A (K),
Unit elementary charge q (C),
The concentration N _n (cm ⁻³ ) of electrons contained in the second semiconductor layer 32, and
The concentration N _p (cm ⁻³ ) of holes contained in the second semiconductor layer 32,
Is shown.
The Boltzmann constant k _B is, for example, about 1.38 × 10 ⁻²³ (JK ⁻¹ ).

（３）式には、
第２半導体層３２に含まれるドナーの濃度Ｎ_Ｄ（ｃｍ^−３）、及び、
真性キャリア濃度ｎ_ｉ（ｃｍ^−３）、
が示される。 In the equation (2), the electron concentration N _n can be obtained by the equation (3).

(3)
The concentration N _D (cm ⁻³ ) of the donor contained in the second semiconductor layer 32, and
Intrinsic carrier concentration n _i (cm ⁻³ ),
Is shown.

（４）式には、
第２半導体層３２に含まれるアクセプタの濃度Ｎ_Ａ（ｃｍ^−３）が示される。 (2) In the equation, the concentration _{N p} of the hole can be obtained by (4).

(4)
The acceptor concentration N _A (cm ⁻³ ) contained in the second semiconductor layer 32 is shown.

（５）式には、
第２半導体層３２の伝導帯の有効状態密度Ｎ_Ｃ（ｃｍ^−３・ｅＶ）、
第２半導体層３２の価電子帯の有効状態密度Ｎ_Ｖ（ｃｍ^−３・ｅＶ）、及び、
第２半導体層３２のバンドギャップＥ_ｇａｐ（ｅＶ）、
が示される。 In (3) and (4), the intrinsic carrier concentration _{n i} can be determined by equation (5).

(5)
Effective state density N _C (cm ⁻³ · eV) of the conduction band of the second semiconductor layer 32,
Effective state density N _V (cm ⁻³ · eV) of the valence band of the second semiconductor layer 32, and
Band gap E _gap (eV) of the second semiconductor layer 32,
Is shown.

（６）式には、
電子の有効質量ｍ_ｅ（ｋｇ）、及び、
プランク定数ｈ（Ｊｓ）、
が示される。 In the equation (5), the effective state density N _C of the conduction band can be obtained by the equation (6).

(6)
Effective mass m _e (kg) of electrons, and
Planck's constant h (Js),
Is shown.

（７）式には、
正孔の有効質量ｍ_ｈ（ｋｇ）が示される。 In (5), the effective density of states N _V of the valence band, can be calculated by equation (7).

(7)
The effective mass m _h (kg) of holes is indicated.

FIG. 6 is a graph illustrating characteristics of another nonvolatile memory device according to the first embodiment.
The horizontal axis in FIG. 6 is the band gap E _gap of the second semiconductor layer 32, and the vertical axis is the read voltage V _read .
FIG. 6 shows an example of the relationship between the band gap E _gap and the read voltage V _read calculated using the equations (2) to (7).
In FIG. 6, the characteristic CT11 represents an example in which TiN is used for the first conductive portion 10 and the Schottky barrier height φ _B is 0.67 eV.
Characteristic CT12 represents using PtSi the first conductive section 10, the Schottky barrier height phi _B, was 0.9eV example.
Characteristic CT13 represents the used ErSi ₂ to the first conductive section 10, the Schottky barrier height phi _B, was 0.1eV example.

As shown in FIG. 6, for example, silicon (Si) having a band gap E _gap of about 1.1 eV is used for the second semiconductor layer 32. In this case, the read voltage V _read in the characteristic CT11 is calculated to be about 0.8 eV. For example, silicon carbide (SiC) having a band gap E _gap of about 3.25 eV is used for the second semiconductor layer 32. In this case, the read voltage V _read in the characteristic CT11 is calculated to be about 2.85 eV. For example, gallium nitride (GaN) having a band gap E _gap of about 3.4 eV is used for the second semiconductor layer 32. In this case, the read voltage V _read in the characteristic CT11 is calculated to be about 3 eV.

FIG. 7 is a graph illustrating characteristics of another nonvolatile memory device according to the first embodiment.
FIG. 7 shows an example of an experiment of the relationship between the voltage and current between the first conductive unit 10 and the second conductive unit 20.
The horizontal axis in FIG. 7 is the voltage (V) applied between the first conductive part 10 and the second conductive part 20, and the vertical axis is between the first conductive part 10 and the second conductive part 20. It is a flowing current (μA).
In the experiment, the voltage applied between the first conductive unit 10 and the second conductive unit 20 is changed to obtain the flowing current.
In the experiment, the same conditions as the characteristic CT11 of FIG. 6 are used. Silicon is used for the memory layer 15. The shape of the surface orthogonal to the Z-axis direction is a 20 nm × 20 nm rectangle. The thickness of the memory layer 15 is 500 nm. The thickness of the second semiconductor layer 32 is 100 nm. The width of the metal part 16 (the length in the direction orthogonal to the Z-axis direction) is 2 nm.

In the experiment, the length D1 of the metal part 16 is changed.
In FIG. 7, the characteristic CT21 is an example in which the length D1 of the metal part 16 is 70 nm, the characteristic CT22 is an example in which the length D1 is 80 nm, and the characteristic CT23 is an example in which the length D1 is 90 nm. The characteristic CT24 is an example in which the length D1 is 100 nm. That is, in the characteristic CT 24, the metal part 16 penetrates the second semiconductor layer 32. In this example, the length D2 is 70 nm or less. In the experiment, the length D1 is changed in the range of the length D2 or more.

As shown in FIG. 7, when the length D1 of the metal part 16 is changed, the resistance value changes and the flowing current also changes. When compared with 0.8 eV which is the read voltage V _read of the characteristic CT11 obtained in FIG. 6, the current of the characteristic CT21 is 1 × 10 ⁻⁹ μA, and the current of the characteristic CT24 is 1 × 10 ⁻⁶ μA. . That is, the characteristic CT21 current _{I reset} in the high resistance state, when the characteristic CT24 was current _{I The set} of low-resistance _state, the current ratio _I set _{/ I reset} the _{I The set} and _{I reset} is a 1 × 10 ³ or more .

As described above, by applying the read voltage V _read that satisfies the second condition represented by the expression (2), an appropriate current ratio I _set / I _reset can be obtained. For example, a current ratio I _set / I _reset of 1 × 10 ³ or more can be obtained. Thereby, for example, the high resistance state and the low resistance state can be appropriately identified by detecting the current.

FIG. 8A to FIG. 8C are schematic cross-sectional views illustrating the configuration of another nonvolatile memory device according to the first embodiment.
As shown in FIG. 8A, the control unit 40 applies the first write voltage V _set1 in the forward direction between the first conductive unit 10 and the second conductive unit 20, whereby the metal unit 16. Is set to the first length d11. The first length d11 is not less than the length D2 and shorter than the thickness of the second semiconductor layer 32.

As illustrated in FIG. 8B, the control unit 40 applies the second write voltage V _set2 in the forward direction between the first conductive unit 10 and the second conductive unit 20, so that the metal unit 16 Is set to a second length d12. The second length d12 is longer than the first length d11 and shorter than the thickness of the second semiconductor layer 32.

As shown in FIG. 8C, the control unit 40 applies the third write voltage V _set3 in the forward direction between the first conductive unit 10 and the second conductive unit 20, so that the metal unit 16 Is set to a third length d13. The third length d13 is longer than the second length d12.

  In addition, the control unit 40 applies a reset voltage in the reverse direction between the first conductive unit 10 and the second conductive unit 20 to make the length D1 of the metal unit 16 shorter than the length D2.

  As shown in FIG. 7, the voltage-current characteristic is changed by changing the length D1 in the range of the length D2 or more. In this example, the control unit 40 changes the length D1 of the metal unit 16 into four states shorter than the first length d11 to the third length d13 and the length D2 by applying a voltage. . Thereby, 2-bit information can be stored in the nonvolatile storage device 111. The information stored in the nonvolatile storage device 111 is not limited to 1 bit or 2 bits, and may be 3 bits or more. As described above, in the nonvolatile memory device 111, a multi-bit nonvolatile memory device can be realized by controlling the voltage applied between the first conductive unit 10 and the second conductive unit 20.

(Second Embodiment)
The nonvolatile memory device according to this embodiment has a cross-point configuration.
FIG. 9 is a schematic perspective view illustrating the configuration of the nonvolatile memory device according to the second embodiment.
FIG. 10 is a schematic circuit diagram illustrating the configuration of the nonvolatile memory device according to the second embodiment.
As shown in FIG. 9, the nonvolatile memory device 120 according to this embodiment includes a substrate 50. As the substrate 50, for example, a silicon substrate, a semiconductor substrate, a substrate containing an inorganic substance, a substrate containing a polymer, or the like is used. For example, a silicon-on-insulator (SOI) substrate or the like is used as the semiconductor substrate. For the substrate containing an inorganic substance, for example, glass or the like is used.

  Here, a plane parallel to the main surface 50a of the substrate 50 is defined as an XY plane. One direction in the XY plane is defined as an X-axis direction. A direction perpendicular to the X-axis direction in the XY plane is taken as a Y-axis direction. A direction perpendicular to the X-axis direction and the Y-axis direction is taken as a Z-axis direction.

As illustrated in FIG. 9, in the nonvolatile memory device 120 according to this embodiment, a plurality of first wirings (word lines WL _i−1 , WL) arranged in the first direction on the main surface 50 a of the substrate 50. _i , WL _{i + 1} ) and a plurality of second wirings (bit lines BL _j−1 , BL _j , BL _{j + 1} ) arranged in the second direction intersecting the first direction are provided. The plurality of first wirings (word lines WL _i−1 , WL _i , WL _{i + 1} ) have, for example, a line shape extending in a direction non-parallel to the first direction. The plurality of second wirings (bit lines BL _j−1 , BL _j , BL _{j + 1} ) have, for example, a line shape extending in a direction non-parallel to the second direction. In this example, the plurality of first wirings (word lines WL _i−1 , WL _i , WL _{i + 1} ) are arranged in the Y-axis direction and extend in the X-axis direction. A plurality of second wirings (bit lines BL _j−1 , BL _j , BL _{j + 1} ) are arranged in the X-axis direction and extend in the Y-axis direction. The second wiring (bit lines BL _j−1 , BL _j , BL _{j + 1} ) faces the first wiring (word lines WL _i−1 , WL _i , WL _{i + 1} ).

  In the above, the extending direction of the first wiring is orthogonal to the extending direction of the second wiring, but the extending direction of the first wiring only needs to intersect (non-parallel) with the extending direction of the second wiring.

In the above, the subscript i and the subscript j are arbitrary. That is, the number of first wirings and the number of second wirings are arbitrary.
In this specific example, the first wiring is a word line and the second wiring is a bit line. However, the first wiring may be a bit line and the second wiring may be a word line. In the following description, it is assumed that the first wiring is a word line and the second wiring is a bit line.

As shown in FIGS. 9 and 10, a plurality of memory cells 12 are provided between the first wiring and the second wiring. Each of the plurality of memory cells 12 is arranged at the intersection CP where the word lines WL _i−1 , WL _i , WL _{i + 1} and the bit lines BL _j−1 , BL _j , BL _{j + 1} are opposed to each other. .

As shown in FIG. 10, the control unit 40 includes a word line driver 41 and a bit line driver 42. The word line driver 41 has a decoder function. The bit line driver 42 has a decoder function and a read function. One end of each of the word lines WL _i−1 , WL _i , WL _{i + 1} is connected to the word line driver 41 via a MOS transistor RSW that is a selection switch. One end of each of the bit lines BL _j−1 , BL _j , BL _{j + 1} is connected to the bit line driver 42 via a MOS transistor CSW which is a selection switch.

Selection signals R _i−1 , R _i , and R _{i + 1} for selecting a word line (row) are input to the gate of the MOS transistor RSW, and a bit line (column) is selected to the gate of the MOS transistor CSW. Selection signals C _i−1 , C _i , and C _{i + 1} are input.

  As illustrated in FIG. 10, the memory cell 12 includes a resistance change element 12 a that changes a resistance value according to voltage or current, and a rectifier element 12 b that suppresses an unintended current path.

FIG. 11 is a schematic cross-sectional view illustrating the configuration of a part of the nonvolatile memory device according to the second embodiment.
As shown in FIG. 11, the memory cell 12 is provided between the word line WL _i and the bit line BL _j . The upper and lower arrangement relationship between the word line WL _i and the bit line BL _j is arbitrary.

As illustrated in FIG. 11, the memory cell 12 includes the first conductive unit 10, the second conductive unit 20, the storage layer 15 provided between the first conductive unit 10 and the second conductive unit 20, including. The configuration described in the first embodiment can be applied to the first conductive unit 10, the second conductive unit 20, and the memory layer 15. In this example, the first conductive portion 10 included in the memory cell 12 is provided on the substrate 50. In the memory cell 12 shown in FIG. 11, the first conductive unit 10 is provided on the word line WL _i , the storage layer 15 is provided on the first conductive unit 10, and the second conductive layer 10 is provided on the storage layer 15. A conductive part 20 is provided, and a bit line BL _i is provided on the second conductive part 20. On the other hand, the second conductive part 20 is provided on the word line WL _i , the storage layer 15 is provided on the second conductive part 20, the first conductive part 10 is provided on the storage layer 15, The bit line BL _i may be provided on the one conductive portion 10.

For example, at least one of the word line WL _i and the bit line BL _j adjacent to the memory cell 12 may be used as at least one of the first conductive unit 10 and the second conductive unit 20.

  Also in the configuration of the nonvolatile memory device 120, the first conductive unit 10, the second conductive unit 20 including metal atoms, and the storage layer 15 including the first semiconductor layer 31 and the second semiconductor layer 32 are used. As a result, higher storage density can be realized. The configuration of the nonvolatile memory device is not limited to the cross-point type, and may be a probe memory type, for example. The configurations of the first conductive unit 10, the second conductive unit 20, and the memory layer 15 provided on the substrate 50 are not limited to the above.

  According to the embodiment, a high storage density nonvolatile memory device is provided.

  In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. . In the specification of the application, the state of “provided on” includes not only the state of being provided in direct contact but also the state of being provided with another element inserted therebetween. The “stacked” state includes not only the state of being stacked in contact with each other but also the state of being stacked with another element inserted therebetween. The state of “facing” includes not only the state of facing directly but also the state of facing with another element inserted therebetween.

The embodiments of the present invention have been described above with reference to specific examples. However, embodiments of the present invention are not limited to these specific examples. For example, regarding a specific configuration of each element such as a first conductive unit, a second conductive unit, a storage layer, a first semiconductor layer, a second semiconductor layer, a metal unit, and a control unit included in the nonvolatile memory device, It is included in the scope of the present invention as long as a person skilled in the art can carry out the present invention by appropriately selecting from the known ranges and obtain the same effect.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all nonvolatile memory devices that can be implemented by those skilled in the art based on the nonvolatile memory device described above as an embodiment of the present invention are also included in the present invention as long as they include the gist of the present invention. Belongs to the range.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... 1st electroconductive part, 12 ... Memory cell, 12a ... Resistance change element, 12b ... Rectifier element, 15 ... Memory layer, 15a ... 1st surface, 15b ... 2nd surface, 16 ... Metal part, 16a ... End part DESCRIPTION OF SYMBOLS 20 ... 2nd electroconductive part, 31 ... 1st semiconductor layer, 32 ... 2nd semiconductor layer, 40 ... Control part, 41 ... Word line driver, 42 ... Bit line driver, 50 ... Substrate, 50a ... Main surface, 110, 111 120 ... nonvolatile memory device, CSW ... transistor, RSW ... transistor

Claims (11)

A first conductive part;
Lithium, chromium, iron, copper, indium, tellurium, calcium, sodium, silver, cobalt, gold, titanium, tungsten, erbium, platinum, aluminum and nickel, or at least one of the above metal atoms A second conductive part comprising an alloy comprising;
A first conductive type first semiconductor layer provided between the first conductive part and the second conductive part and in contact with the first conductive part ;
A second conductive type second semiconductor layer provided between the first semiconductor layer and the second conductive part, in contact with the first semiconductor layer and in contact with the second conductive part ;
A first state having a low resistance and a resistance having a higher resistance than the first state by at least one of a voltage applied through the first conductive part and the second conductive part and a supplied current. A storage layer capable of reversibly transitioning between two states;
A non-volatile storage device. A first conductive part;
Lithium, chromium, iron, copper, indium, tellurium, calcium, sodium, silver, cobalt, gold, titanium, tungsten, erbium, platinum, aluminum and nickel, or at least one of the above metal atoms A second conductive part comprising an alloy comprising;
A first semiconductor layer of a first conductivity type provided between the first conductive part and the second conductive part;
A second conductivity type second semiconductor layer provided between the first semiconductor layer and the second conductive portion;
A first state having a low resistance and a resistance having a higher resistance than the first state by at least one of a voltage applied through the first conductive part and the second conductive part and a supplied current. A storage layer capable of reversibly transitioning between two states;
With
The storage layer includes a first surface facing the first conductive portion, a second surface facing the second conductive portion, and at least the second surface including the metal atoms from the second surface toward the first surface . A metal portion extending in the semiconductor layer ,
The metal part has a stacking direction of the first conductive part and the second conductive part according to at least one of a voltage applied through the first conductive part and the second conductive part and a supplied current. Change the length along
The storage layer, nonvolatile memory device you transition between the second state and the first state by the length of the metal portion. A first conductive part;
Lithium, chromium, iron, copper, indium, tellurium, calcium, sodium, silver, cobalt, gold, titanium, tungsten, erbium, platinum, aluminum and nickel, or at least one of the above metal atoms A second conductive part comprising an alloy comprising;
A first semiconductor layer of a first conductivity type provided between the first conductive part and the second conductive part;
A second conductivity type second semiconductor layer provided between the first semiconductor layer and the second conductive portion;
A first state having a low resistance and a resistance having a higher resistance than the first state by at least one of a voltage applied through the first conductive part and the second conductive part and a supplied current. A storage layer capable of reversibly transitioning between two states;
With
The storage layer includes a first surface facing the first conductive portion, a second surface facing the second conductive portion, and a metal portion including the metal atoms and extending from the second surface toward the first surface. Have
The metal part has a stacking direction of the first conductive part and the second conductive part according to at least one of a voltage applied through the first conductive part and the second conductive part and a supplied current. Change the length along
The storage layer transitions between the first state and the second state according to the length of the metal part,
The distance between the first semiconductor layer and the metal part is Δd (cm),
The dielectric constant of the second semiconductor layer is ε _sem (Fcm ⁻¹ ),
The Schottky barrier height of the conduction band of the second semiconductor layer based on the Fermi level of the metal part is φ _B (eV),
Let unit elementary charge be q (C),
When the impurity concentration of the second semiconductor layer is N _x (cm ⁻³ ),
The storage layer is

In represented by first becomes the first state when conditions are satisfied, that Do and the second state when not satisfying the first condition non-volatile storage. A first conductive part;
Lithium, chromium, iron, copper, indium, tellurium, calcium, sodium, silver, cobalt, gold, titanium, tungsten, erbium, platinum, aluminum and nickel, or at least one of the above metal atoms A second conductive part comprising an alloy comprising;
A first semiconductor layer of a first conductivity type provided between the first conductive part and the second conductive part;
A second conductivity type second semiconductor layer provided between the first semiconductor layer and the second conductive portion;
A first state having a low resistance and a resistance having a higher resistance than the first state by at least one of a voltage applied through the first conductive part and the second conductive part and a supplied current. A storage layer capable of reversibly transitioning between two states;
A control unit that applies a read voltage for reading the state of the storage layer between the first conductive unit and the second conductive unit ;
With
The read voltage is V _read (V),
Let Boltzmann's constant be k _B (JK ^-1 )
Let absolute temperature be T _A (K),
Let unit elementary charge be q (C),
The concentration of electrons contained in the second semiconductor layer is N _n (cm ⁻³ ),
When the concentration of holes contained in the second semiconductor layer is N _p (cm ⁻³ ),
The read voltage V _read is

In non-volatile memory device that meets a second condition represented.   The nonvolatile memory device according to claim 1, wherein the first conductive portion includes at least one of tungsten, molybdenum, titanium, chromium, tantalum, and nickel. The second conductive part further includes a conductive matrix material,
The at least one metal atom or the alloy is included in the matrix material;
6. The nonvolatile memory device according to claim 1, wherein a cohesive energy of the metal atoms or a cohesive energy of the alloy is lower than a cohesive energy of the matrix material.   The nonvolatile memory device according to claim 6, wherein the matrix material includes at least one of tungsten, molybdenum, titanium, chromium, tantalum, and nickel.   The nonvolatile memory device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer include at least one of polysilicon and amorphous silicon. The concentration of impurities contained in the first semiconductor layer is 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less,
The non-volatile memory device according to claim 1, wherein a concentration of impurities contained in the second semiconductor layer is 1 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. A substrate including at least one of a silicon substrate, a semiconductor substrate, a substrate including an inorganic substance, or a substrate including a polymer;
The non-volatile memory device according to claim 1, wherein the first conductive portion is provided on the substrate. A plurality of first wires arranged in a first direction;
A plurality of second wirings arranged in a second direction intersecting the first direction;
A plurality of memory cells including the first conductive portion, the second conductive portion, and the memory layer, and provided at intersections of the plurality of first wirings and the plurality of second wirings;
The nonvolatile memory device according to claim 1, further comprising:

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