JP5696882B2 - Charged body, and field effect transistor and memory element using the same - Google Patents

Charged body, and field effect transistor and memory element using the same Download PDF

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JP5696882B2
JP5696882B2 JP2010280686A JP2010280686A JP5696882B2 JP 5696882 B2 JP5696882 B2 JP 5696882B2 JP 2010280686 A JP2010280686 A JP 2010280686A JP 2010280686 A JP2010280686 A JP 2010280686A JP 5696882 B2 JP5696882 B2 JP 5696882B2
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charge injection
charged body
withstand voltage
electric field
field strength
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JP2012129411A (en
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偉夫 中子
偉夫 中子
山本 和徳
和徳 山本
恭 神代
恭 神代
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Showa Denko Materials Co Ltd
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Hitachi Chemical Co Ltd
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本発明は、電荷を材料中に長時間に閉じ込められる材料(以降、帯電体)に関するものであり、さらに、その応用である閾値電圧が制御可能な電界効果型トランジスタ(以下「FET」)およびメモリ素子に関する。より詳細に述べると、本発明の帯電体は、絶縁特性に優劣のある2種の材料を積層した構造からなり、該帯電体の2種絶縁材料それぞれに接するように2枚の電極ではさみ高電界を印荷することにより、絶縁特性に劣る材料側から電荷を2種絶縁材料の界面に注入・蓄積し、電界除去後も該帯電体内に保持し周囲にクーロン力を及ぼすことができる。また、該帯電体をゲート絶縁膜に用いてFETを構成することにより、前記のようにして帯電体中に蓄積された電荷により閾値電圧を制御できる。さらに、該FETにおいて帯電体中に電荷が長時間保持される。すなわち制御された閾値電圧が保持されることを利用したメモリ素子に関する。   The present invention relates to a material (hereinafter referred to as a charged body) in which electric charges are confined in a material for a long time, and further, a field effect transistor (hereinafter referred to as “FET”) and a memory capable of controlling the threshold voltage as its application. It relates to an element. More specifically, the charged body of the present invention has a structure in which two kinds of materials having superior and inferior insulating properties are laminated, and the two electrodes are sandwiched between the two kinds of insulating materials so as to be in contact with the two kinds of insulating materials. By applying an electric field, charges can be injected and accumulated at the interface between the two insulating materials from the side of the material that is inferior in insulation characteristics, and can be retained in the charged body even after the electric field is removed to exert a Coulomb force on the periphery. Further, by configuring the FET using the charged body as a gate insulating film, the threshold voltage can be controlled by the charge accumulated in the charged body as described above. Furthermore, in the FET, the charge is held in the charged body for a long time. That is, the present invention relates to a memory element that utilizes the fact that a controlled threshold voltage is maintained.

従来、静電気は、集塵機、トナープリンタに用いられているが、これらの静電気では電荷が移動できるため電荷密度が低く、短時間で散逸してしまい応用分野は限られていた。
一方、フローティングゲートに代表される導体を極薄い絶縁体で被覆した構造では、絶縁体を通して導体に電荷が注入された後は、絶縁層により電荷の散逸が抑制され、電荷が長時間保持される。このように電荷をとじ込めた材料は帯電体と呼ばれ近年注目を集めている。
Conventionally, static electricity has been used in dust collectors and toner printers. However, since these static electricity can move charges, the charge density is low and dissipates in a short time, so the application field is limited.
On the other hand, in a structure in which a conductor typified by a floating gate is covered with an extremely thin insulator, after the charge is injected into the conductor through the insulator, the dissipation of the charge is suppressed by the insulating layer, and the charge is held for a long time. . Such a material containing a charge is called a charged body and has attracted attention in recent years.

このような、帯電体の用途としてはフローティングゲートメモリ(非特許文献)として実用化されている以外にも、クーロン引力、斥力を利用したモーターや発電機への可能性が考えられる。   In addition to being put into practical use as a floating gate memory (non-patent document), such a charged body can be used for a motor or a generator using Coulomb attractive force or repulsive force.

特許第3222404号公報Japanese Patent No. 3222404

S. M. SZE,“Floating−Gate Devices”. Physics of semiconductor devices. third edition, New Jersey,John Wiley,2007年,352〜357頁S. M.M. SZE, “Floating-Gate Devices”. Physics of semiconductor devices. third edition, New Jersey, John Wiley, 2007, 352-357. S. M. SZE,“Charge−Trapping Devices”. Physics of semiconductor devices. third edition, New Jersey,John Wiley,2007年,357〜360頁S. M.M. SZE, “Charge-Trapping Devices”. Physics of semiconductor devices. third edition, New Jersey, John Wiley, 2007, 357-360. S. M. SZE,“Appendix I, Properties of SiO2 and Si3N4 at 300K”. Physics of semiconductor devices. second edition, New Jersey,John Wiley,1981年,852頁S. M.M. SZE, "Appendix I, Properties of SiO2 and Si3N4 at 300K". Physics of semiconductor devices. second edition, New Jersey, John Wiley, 1981, page 852.

帯電体を帯電させるには、フローティングゲート構造では、極薄い絶縁膜を熱電子あるいはトンネル電流により内部導体に電荷を注入するが、極薄い絶縁膜を必要とするため、絶縁性が限られ蓄積できる電荷量や保持時間に制約が生じる。また極薄い絶縁膜の製造方法や材料へも制約が生じる。一方、絶縁体や内部金属へ加速器により加速した荷電粒子(イオン)を打ち込むという方法も提案されているが、大掛かりな荷電粒子加速装置が必要となり、さらに荷電粒子の打ち込み時にラジカル発生等が生じ絶縁劣化が懸念される。
本発明は、フローティングゲートメモリやMNOS(Metal-Nitride-Oxide-Semiconductor)メモリのような極薄膜の絶縁層を必要とせず、印刷、塗布でメモリ素子が製造可能となる簡便で、注入電荷量の制御が容易な帯電体、並びにこの帯電体をゲート絶縁膜に用いてFETを作製することにより、閾値電圧制御が可能で、長時間制御された閾値電圧状態を保持可能なFET及びメモリ素子を提供することを目的とする。
In order to charge the charged body, in the floating gate structure, a very thin insulating film is injected into the inner conductor by thermoelectrons or tunnel current. However, since an extremely thin insulating film is required, the insulating property is limited and can be accumulated. There are restrictions on the amount of charge and the retention time. In addition, there are restrictions on the manufacturing method and material of the extremely thin insulating film. On the other hand, a method of implanting charged particles (ions) accelerated by an accelerator into an insulator or internal metal has also been proposed. However, a large charged particle acceleration device is required, and further, generation of radicals occurs when charged particles are implanted, resulting in insulation. There is concern about deterioration.
The present invention does not require an ultra-thin insulating layer such as a floating gate memory or a MNOS (Metal-Nitride-Oxide-Semiconductor) memory, and allows a memory element to be manufactured by printing and coating. Provided an easily controllable charged body, and an FET and a memory element that can control a threshold voltage and maintain a threshold voltage state controlled for a long time by fabricating an FET using the charged body as a gate insulating film. The purpose is to do.

本発明は、以下に関する。
[1] 電荷注入が生じる電界強度(以降、電荷注入耐圧)および絶縁耐圧がそれぞれECI,HおよびEBHである絶縁体(以下、高電荷注入耐圧材料)と、その電荷注入耐圧ECI,LがECI,L < ECI,Hの関係にある絶縁体(以下、低電荷注入耐圧材料)の二種類の絶縁体を積層した絶縁物で、高電荷注入耐圧材料と低電荷注入耐圧材料のそれぞれに接し離れた2枚の電極にECI,L < |E| < EBH の電界強度で電圧を印加して低電荷注入耐圧材料側から電荷を絶縁体内に注入して帯電させることを特徴とする帯電体。
[2] 前記のECI,H とECI,Lの比(ECI,H/ECI,L)が、1.5〜1000であり、ECI,Lが0.01MV/cm以上である[1]に記載の帯電体。
[3] 前記高電荷注入耐圧材料の絶縁耐圧(EBH)が、0.1MV/cm以上で、高電荷注入耐圧材料および低電荷注入耐圧材料の0.5MV/cmにおける体積抵抗率がそれぞれ1011Ω・m以上である[1]または[2]に記載の帯電体。
[4] 前記高電荷注入耐圧材料と低電荷注入耐圧材料の少なくとも一方が有機高分子で構成される[1]〜[3]のいずれかに記載の帯電体。
[5] 前記低電荷注入耐圧材料および/または高電荷注入耐圧材料が、3次元架橋高分子材料である[1]〜[4]のいずれかに記載の帯電体。
[6] 前記3次元架橋高分子材料が、湿式工程によって形成されたものである上記[5]に記載の帯電体。
[7] 湿式工程が、ディップコーティング、スピンコーティング、スプレーコーティング、ロールコーティング、インクジェットコーティング、オフセットコーティング、インクジェット印刷、転写法、オフセット印刷、スクリーン印刷、凸版印刷、凹版印刷、ソフトリソグラフ、又はディスペンサ印刷から選ばれる上記[6]に記載の帯電体。
[8] ゲート絶縁膜を挟んでゲート電極と半導体層があり、その半導体層に接してソース−ドレイン電極を有する電界効果トランジスタにおいて、ゲート絶縁膜が[1]〜[7]のいずれかに記載の帯電体で、帯電体に注入される電荷量により電界効果トランジスタの閾値電圧を制御することを特徴とした電界効果トランジスタ。
[9] [8]に記載の電界効果トランジスタにおいて、帯電体内に保持された注入電荷量により情報を記録し、ECI,L > |E|のゲート電界強度下でのドレイン電流量の差として情報を呼び出すことを特徴としたメモリ素子、に関する。
The present invention relates to the following.
[1] the charge injection occurs field strength (hereinafter, charge injection tolerance) and dielectric breakdown voltage respectively E CI, insulators are H and E BH (hereinafter, high charge injection withstand material) and their charge injection withstand E CI, L is an insulator in which two types of insulators (hereinafter referred to as a low charge injection withstand voltage material) having a relationship of E CI, L <E CI, H are laminated, and a high charge injection withstand voltage material and a low charge injection withstand voltage material. A voltage is applied to the two electrodes that are in contact with and separated from each other at an electric field strength of E CI, L <| E | < EBH , and charges are injected into the insulator from the low charge injection withstand voltage material side to be charged. Characteristic charged body.
[2] said E CI, H and E CI, the ratio of L (E CI, H / E CI, L) is a from 1.5 to 1,000, E CI, L is at 0.01 MV / cm or more The charged body according to [1].
[3] The dielectric breakdown voltage (E BH ) of the high charge injection withstand voltage material is 0.1 MV / cm or more, and the volume resistivity at 10 MV / cm of the high charge injection withstand voltage material and the low charge injection withstand voltage material is 10 respectively. The charged body according to [1] or [2], which is 11 Ω · m or more.
[4] The charged body according to any one of [1] to [3], wherein at least one of the high charge injection withstand voltage material and the low charge injection withstand voltage material is formed of an organic polymer.
[5] The charged body according to any one of [1] to [4], wherein the low charge injection pressure-resistant material and / or the high charge injection pressure-resistant material is a three-dimensional crosslinked polymer material.
[6] The charged body according to [5], wherein the three-dimensional crosslinked polymer material is formed by a wet process.
[7] Wet process from dip coating, spin coating, spray coating, roll coating, ink jet coating, offset coating, ink jet printing, transfer method, offset printing, screen printing, letterpress printing, intaglio printing, soft lithography, or dispenser printing The charged body according to [6], which is selected.
[8] The field effect transistor according to any one of [1] to [7], wherein the gate insulating film has a gate electrode and a semiconductor layer sandwiching the gate insulating film and has a source-drain electrode in contact with the semiconductor layer. And a threshold voltage of the field effect transistor controlled by an amount of charge injected into the charged body.
[9] In the field effect transistor according to [8], information is recorded by the amount of injected charge held in the charged body, and the difference in drain current amount under the gate electric field strength of E CI, L > | E | The present invention relates to a memory element characterized by calling information.

本発明の帯電体は、簡便で、注入電荷量の制御が容易な帯電体が得られる。この帯電体をゲート絶縁膜に用いてFETを作製することにより、閾値電圧制御が可能で、長時間制御された閾値電圧状態を保持可能なFET、メモリ素子が得られる。また、フローティングゲートメモリやMNOSメモリのような極薄膜の絶縁層を必要とせず、印刷、塗布でメモリ素子が製造可能になる。   The charged body of the present invention is simple and provides a charged body with easy control of the injected charge amount. By manufacturing an FET using this charged body as a gate insulating film, a threshold voltage can be controlled, and an FET and a memory element capable of maintaining a threshold voltage state controlled for a long time can be obtained. In addition, an extremely thin insulating layer such as a floating gate memory or an MNOS memory is not required, and a memory element can be manufactured by printing and coating.

本発明の好適な一実施形態に係るFETおよびメモリ素子の断面を概略的に示す模式図である。1 is a schematic diagram schematically showing a cross section of an FET and a memory element according to a preferred embodiment of the present invention. 本発明の好適な一実施形態に係るFETおよびメモリ素子の断面を概略的に示す模式図である。1 is a schematic diagram schematically showing a cross section of an FET and a memory element according to a preferred embodiment of the present invention. 本発明の好適な一実施形態に係るFETおよびメモリ素子の断面を概略的に示す模式図である。1 is a schematic diagram schematically showing a cross section of an FET and a memory element according to a preferred embodiment of the present invention. 本発明の好適な一実施形態に係るFETおよびメモリ素子の断面を概略的に示す模式図である。1 is a schematic diagram schematically showing a cross section of an FET and a memory element according to a preferred embodiment of the present invention. 本発明の好適な一実施形態に係るFETおよびメモリ素子の断面を概略的に示す模式図である。1 is a schematic diagram schematically showing a cross section of an FET and a memory element according to a preferred embodiment of the present invention. 本発明の好適な一実施形態に係るFETおよびメモリ素子の断面を概略的に示す模式図である。1 is a schematic diagram schematically showing a cross section of an FET and a memory element according to a preferred embodiment of the present invention. 本発明の好適な一実施形態に係るFETおよびメモリ素子の断面を概略的に示す模式図である。1 is a schematic diagram schematically showing a cross section of an FET and a memory element according to a preferred embodiment of the present invention. 本発明の好適な一実施形態に係るFETおよびメモリ素子の断面を概略的に示す模式図である。1 is a schematic diagram schematically showing a cross section of an FET and a memory element according to a preferred embodiment of the present invention. 本発明の好適な一実施形態に係るFETおよびメモリ素子の断面を概略的に示す模式図である。1 is a schematic diagram schematically showing a cross section of an FET and a memory element according to a preferred embodiment of the present invention. (実施例1で使用したエポキシ樹脂の電界強度と電流の関係を示す図である。FIG. 3 is a diagram showing the relationship between electric field strength and current of the epoxy resin used in Example 1. (実施例1によって得られた素子に対し、正から負へゲート電界強度を掃引した際の電流伝達特性曲線である。(Current transfer characteristic curve when the gate electric field strength is swept from positive to negative with respect to the element obtained in Example 1. (実施例1によって得られた素子に対し、負から正へゲート電界強度を掃引した際の電流伝達特性曲線である。(Current transfer characteristic curve when the gate electric field strength is swept from negative to positive with respect to the element obtained in Example 1. (実施例1よって得られた同一素子に対し、3回ゲート電界強度を掃引した際の電流伝達特性曲線である。(Current transfer characteristic curve when the gate electric field strength is swept three times for the same element obtained in Example 1. (実施例1によって得られた素子に対し、−5MV/cmのゲート電界を印荷後の0、1、5、30分後の電流伝達特性曲線である。(Current transfer characteristic curves after 0, 1, 5, and 30 minutes after applying a gate electric field of −5 MV / cm to the device obtained in Example 1. FIG. (実施例2によって得られた素子の電流伝達特性曲線である。(Current transfer characteristic curve of the element obtained in Example 2. (実施例3によって得られた素子に対し、負から正へゲート電界強度を掃引した際の電流伝達特性曲線である。(Current transfer characteristic curve when the gate electric field strength is swept from negative to positive with respect to the element obtained in Example 3. (実施例3によって得られた素子に対し、正から負へゲート電界強度を掃引した際の電流伝達特性曲線である。(Current transfer characteristic curve when the gate electric field strength is swept from positive to negative with respect to the element obtained in Example 3. (実施例3によって得られた素子に対し、−5.9MV/cmのゲート電界を印荷後の0、1、30分後の電流伝達特性曲線である。(The current transfer characteristic curve after 0, 1, and 30 minutes after applying a gate electric field of −5.9 MV / cm to the device obtained in Example 3. (実施例4によって得られた素子の電流伝達特性曲線である。10 is a current transfer characteristic curve of an element obtained in Example 4. (実施例5で使用した低電荷注入耐圧樹脂の電界強度と電流の関係である。(Relationship between electric field strength and current of low charge injection withstand voltage resin used in Example 5. (実施例5によって得られた素子の電流伝達特性曲線である。10 is a current transfer characteristic curve of an element obtained in Example 5. (比較例1によって得られた素子の電流伝達特性曲線である。(A current transfer characteristic curve of an element obtained in Comparative Example 1.

以下、本発明をより詳細に説明する。   Hereinafter, the present invention will be described in more detail.

絶縁体内に、加速器を用いずに電荷注入し、帯電体を得ることができれば望ましい。絶縁体に電界を印加していくと(例として図10)、電界強度が低い場合(図10では3.5MV/cm以下)、ほとんど電流が流れないが、ある電界強度(以降、電荷注入耐圧)より高く(図10では3.5MV/cm)なると、電極から材料中に電荷が注入され微小な電流が流れるようになる。このように高電界をかけることにより材料中に電荷を注入できるが、注入された電荷は材料中を電場により移動し対電極側から抜けてしまい、十分な荷電量を有する帯電体とはならない。また、電荷注入の発生するような高電界強度は材料の絶縁耐圧(図10では6.3MV/cm)に近く、欠陥が存在すると、材料の絶縁耐圧以下の電界強度でも絶縁破壊に至るという不安定さを有する。なお、絶縁破壊を起こした絶縁材料は、材料の分解・炭化により絶縁性が大幅に低下し、使用できなくなる。   It is desirable if charge can be obtained by injecting charges into the insulator without using an accelerator. When an electric field is applied to the insulator (for example, FIG. 10), when the electric field strength is low (3.5 MV / cm or less in FIG. 10), almost no current flows, but a certain electric field strength (hereinafter referred to as charge injection withstand voltage). ) Higher (3.5 MV / cm in FIG. 10), charges are injected from the electrode into the material, and a minute current flows. In this way, charges can be injected into the material by applying a high electric field, but the injected charges move through the material by the electric field and escape from the counter electrode side, so that the charged body does not have a sufficient charge amount. In addition, the high electric field strength at which charge injection occurs is close to the dielectric strength of the material (6.3 MV / cm in FIG. 10), and if there is a defect, the electric field strength below the dielectric strength of the material does not cause dielectric breakdown. Has stability. Insulating materials that have undergone dielectric breakdown are greatly deteriorated in insulating properties due to decomposition and carbonization of the materials, and cannot be used.

本発明における、帯電体の原理を説明する。
本発明における帯電体は、高い電荷注入耐圧(ECI,H)の材料(以降、高電荷注入耐圧材料)と低い電荷注入耐圧(ECI,L)の材料(以降、低電荷注入耐圧材料)が積層された構造からなる。この帯電体の、高電荷注入耐圧の材料側と低電荷注入耐圧の材料側のそれぞれに電極を配して低電荷注入耐圧の材料にECI,L以上の電界をかけると、低電荷注入耐圧材料に電極から電荷が注入され、注入された電荷は対となる電極へ向かって移動する。しかし、高電荷注入耐圧の材料では、同じ電界強度でも電荷注入が起こらないか僅かであることから、低電荷注入耐圧材料内を移動した電荷は低電荷注入耐圧材料と高電荷注入耐圧材料の界面で止まり、この界面に電荷が蓄積される。
このようにして低電荷注入耐圧の材料と高電荷注入耐圧の材料の界面に蓄積された電荷は、高電界の除去後(|E| < |ECI,L|)は電界による移動力が働かないため界面に固定され、さらに絶縁体に囲まれているため散逸したり、他の対電荷と中和したりせず長期間安定に存在する。このため、この帯電体は電荷により帯電し、周囲にクーロン力を及ぼし帯電体としての使用が可能となる。
The principle of the charged body in the present invention will be described.
The charged body in the present invention includes a material having a high charge injection withstand voltage ( ECI, H ) (hereinafter referred to as a high charge injection withstand voltage material) and a material having a low charge injection withstand voltage ( ECI, L ) (hereinafter referred to as a low charge injection withstand voltage material). Has a laminated structure. When an electrode is placed on each of the charged material and the low charge injection withstand voltage material and an electric field of ECI, L or higher is applied to the low charge injection withstand voltage material, Charge is injected into the material from the electrode, and the injected charge moves toward the pair of electrodes. However, in a material having a high charge injection withstand voltage, charge injection does not occur or is slight even at the same electric field strength, so that the charge that has moved through the low charge injection withstand voltage material is the interface between the low charge injection withstand voltage material and the high charge injection withstand voltage material. The charge is accumulated at this interface.
The charges accumulated at the interface between the low charge injection withstand voltage material and the high charge injection withstand voltage material in this way are affected by the mobility due to the electric field after the removal of the high electric field (| E | <| E CI, L |). Since it is not fixed to the interface and is surrounded by an insulator, it does not dissipate or neutralize with other counter charges, and it exists stably for a long time. For this reason, this charged body is charged by electric charges, and exerts a Coulomb force around it, and can be used as a charged body.

また、高電荷注入耐圧材料は、一般に絶縁耐圧(EBH)も低電荷注入耐圧材料の絶縁耐圧(EBL)より高く、低電荷注入耐圧材料の絶縁耐圧付近の電界強度(|EBH| > |E|≒|EBL|)が印加された場合でも、高電荷注入耐圧材料の高い絶縁耐圧および低い電荷注入量により電荷の移動量が制限され、絶縁破壊を抑制できる。これにより、低電荷注入耐圧材料の絶縁耐圧付近での動作において、絶縁破壊や絶縁劣化を抑制し安定動作を可能とする。 In addition, a high charge injection withstand voltage material generally has a higher withstand voltage (E BH ) than an insulation withstand voltage (E BL ) of a low charge injection withstand voltage material, and an electric field strength (| E BH | Even when | E | ≈ | E BL |) is applied, the amount of charge movement is limited by the high withstand voltage and the low charge injection amount of the high charge injection withstand voltage material, and the dielectric breakdown can be suppressed. As a result, in the operation near the withstand voltage of the low charge injection withstand voltage material, it is possible to suppress the dielectric breakdown and the insulation deterioration and to enable the stable operation.

次に本発明における、電界効果トランジスタ(FET)およびメモリ素子の動作原理を説明する。
本発明における、FETおよびメモリ素子は、該帯電体をゲート絶縁膜として用いたFETの構造を有している。このFETに該帯電体の低電荷注入耐圧材料のECI,Lより低いゲート電界強度(E)で駆動させる場合には通常のFETと同じ動作をする。しかし、EBH > |E| > ECI,Lの条件では、前記の帯電体と同様に低電荷注入耐圧材料中に電荷が注入され、低電荷注入耐圧材料と高電荷注入耐圧材料の界面に電荷が蓄積・保存される。その後、帯電体に電荷が蓄積された状態で、|E| < ECI,L範囲のゲート電界強度で特性を測定すると、帯電体中に保持された電荷による電界により閾値電圧が大きくシフトする。
帯電体に正の電荷が蓄積している場合には閾値電圧は負に、逆に、負の電荷が蓄積している場合には閾値電圧は正にシフトし、シフト量は帯電体中の電荷量に依存する。
Next, the operation principle of the field effect transistor (FET) and the memory element in the present invention will be described.
The FET and the memory element in the present invention have a FET structure using the charged body as a gate insulating film. When this FET is driven with a gate electric field strength (E G ) lower than E CI, L of the low charge injection withstand voltage material of the charged body, the same operation as a normal FET is performed. However, under the condition of E BH > | E G |> E CI, L , charges are injected into the low charge injection withstand voltage material in the same manner as the charged body, and the interface between the low charge injection withstand voltage material and the high charge injection withstand voltage material. Charge is accumulated and stored in Thereafter, when the charge is accumulated in the charged body and the characteristics are measured with the gate electric field intensity in the range of | E G | <E CI, L, the threshold voltage is largely shifted by the electric field due to the charge held in the charged body. .
When positive charge is accumulated in the charged body, the threshold voltage is negative, and conversely, when negative charge is accumulated, the threshold voltage is shifted to positive, and the shift amount is the charge in the charged body. Depends on the amount.

このトランジスタの構造は、MNOS(metal-nitride-oxide-silicon)トランジスタ(非特許文献1)に似ているが、MNOSトランジスタでは、シリコン層から、20nm以下(非特許文献1)の極薄い酸化物膜をトンネル効果により超えて、窒化物層と酸化物膜の界面に電荷が注入され、保持される。   The structure of this transistor is similar to that of a MNOS (metal-nitride-oxide-silicon) transistor (Non-patent Document 1). However, in the MNOS transistor, an extremely thin oxide of 20 nm or less (Non-patent Document 1) from the silicon layer. Charges are injected and held at the interface between the nitride layer and the oxide film beyond the film due to the tunnel effect.

一方、本発明では、同様に絶縁特性の異なる2種の絶縁膜を積層してなるが、トンネル効果による2種の絶縁膜界面への電荷付与ではなく、低電荷注入耐圧の材料側からの電荷注入と移動によって界面に電荷を蓄積している。そのため、MNOSトランジスタのように片方の絶縁膜をトンネル効果が働くような20nm以下の薄層に成形する必要が無く((実施例2)、絶縁膜の成形方法、材料への制約が少ない。   On the other hand, in the present invention, two types of insulating films having different insulating characteristics are laminated in the same manner. However, charge from the material side having a low charge injection withstand voltage is not provided to the interface between the two types of insulating films by the tunnel effect. Charges are accumulated at the interface by injection and movement. Therefore, it is not necessary to form one insulating film into a thin layer of 20 nm or less so that the tunnel effect works like the MNOS transistor (Example 2), and there are few restrictions on the method and material for forming the insulating film.

帯電体の厚みは、低電荷注入耐圧の材料層と高電荷注入耐圧の材料層合わせて10,000nm以下が望ましい。これは、低電荷注入耐圧材料の電荷注入特性にも依存するが、電荷注入に、0.01MV/cm以上の電界強度をかける場合、100Vでこの電界強度をかけるとするとこの100,000nm以下である必要がある。より、現実的な電圧である10V以下で動作させるには10,000nm以下となる。また、最低の膜厚は、後述の制約から、20nmである。   The thickness of the charged body is preferably 10,000 nm or less in total for the low charge injection withstand voltage material layer and the high charge injection withstand voltage material layer. This depends on the charge injection characteristics of the low charge injection withstand voltage material. However, when an electric field strength of 0.01 MV / cm or more is applied to the charge injection, if this electric field strength is applied at 100 V, this is less than 100,000 nm. There must be. Therefore, it is 10,000 nm or less in order to operate at a realistic voltage of 10 V or less. The minimum film thickness is 20 nm due to the restrictions described later.

低電荷注入耐圧の材料層の厚みは、界面に蓄積された電荷が散逸せず保持できる厚みが必要であり、すなわち10nm以上必要であり、より好ましくは20nm以上、さらに好ましくは25nm以上である。この厚み以下であると、トンネル電流や絶縁体中の荷電の拡散により電荷が失われる。また、高電荷注入耐圧の材料でも同じ理由から同程度の膜厚が必要であり、すなわち10nm以上必要であり、より好ましくは20nm以上、さらに好ましくは25nm以上である。   The thickness of the low charge injection withstand voltage material layer needs to be a thickness that can hold the charges accumulated at the interface without being dissipated, that is, 10 nm or more, more preferably 20 nm or more, and further preferably 25 nm or more. If the thickness is less than this thickness, charges are lost due to tunneling current or diffusion of charges in the insulator. Further, even for a material having a high charge injection withstand voltage, the same film thickness is required for the same reason, that is, 10 nm or more is required, more preferably 20 nm or more, and further preferably 25 nm or more.

本発明の帯電体では、高電荷注入耐圧材料の絶縁耐圧ECI,H と低電荷注入耐圧材料の絶縁耐圧ECI,Lの比(ECI,H/ECI,L)が、1.5〜1000であり、ECI,L が0.1MV/cm以上である帯電体であることが好ましい。(ECI,H/ECI,L)が、1.5未満の場合、帯電体に電荷を注入する電界強度が高電荷注入耐圧材料の絶縁耐圧に近くなり,素子のばらつき等により絶縁破壊を起こす可能性が高くなる。また1000を超えて高い場合,低電荷注入耐圧材料の絶縁耐圧ECI,Lが低くなり過ぎ(0.01MV/cm未満)、帯電体中に保持できる電荷量が制限されることが予想される。
また、高電荷注入耐圧材料の絶縁耐圧(EBH)が、0.1MV/cm以上で、高電荷注入耐圧材料および低電荷注入耐圧材料の0.5MV/cmにおける体積抵抗率がそれぞれ1011Ω・m以上である帯電体であると好ましい。高電荷注入耐圧材料の絶縁耐圧(EBH)が、0.1MV/cm未満では、帯電体の絶縁破壊が生じる点で好ましくない傾向にある。高電荷注入耐圧材料および低電荷注入耐圧材料の0.5MV/cmにおける体積抵抗率がそれぞれ1011Ω・m未満である帯電体では、帯電体中に注入された電荷が徐々に帯電体外に流失し長時間保持できなくなる点で好ましくない傾向にある。
In the charged body of the present invention, the ratio of the withstand voltage E CI, H of the high charge injection withstand voltage material to the withstand voltage E CI, L of the low charge injection withstand voltage material (E CI, H / E CI, L ) is 1.5. It is preferably a charged body having an ECI , L of 0.1 MV / cm or more. When (E CI, H / E CI, L ) is less than 1.5, the electric field strength for injecting charges into the charged body is close to the insulation withstand voltage of the high charge injection withstand voltage material. The possibility of waking up is increased. On the other hand, if it exceeds 1000, the withstand voltage ECI , L of the low charge injection withstand voltage material becomes too low (less than 0.01 MV / cm), and the amount of charge that can be held in the charged body is expected to be limited. .
Further, the dielectric breakdown voltage (E BH ) of the high charge injection withstand voltage material is 0.1 MV / cm or more, and the volume resistivity at 0.5 MV / cm of the high charge injection withstand voltage material and the low charge injection withstand voltage material is 10 11 Ω, respectively. -It is preferable that it is a charged body which is m or more. If the dielectric breakdown voltage (E BH ) of the high charge injection withstand voltage material is less than 0.1 MV / cm, it tends to be undesirable in that dielectric breakdown of the charged body occurs. In a charged body in which the volume resistivity at 0.5 MV / cm of the high charge injection withstand voltage material and the low charge injection withstand voltage material is less than 10 11 Ω · m, the charge injected into the charged body gradually flows out of the charged body. However, it tends to be undesirable in that it cannot be held for a long time.

上記、帯電体の材料としては、低い電荷注入耐圧の材料とそれより電荷注入耐圧の高い材料を選んで用いればよく、材料に特に限定はないが、絶縁特性を示すほとんどの有機絶縁材料あるいは無機絶縁材料が適用できる。   As the material of the above-mentioned charged body, a material having a low charge injection withstand voltage and a material having a higher charge injection withstand voltage may be selected and used, and the material is not particularly limited. Insulating material can be applied.

その好適な有機絶縁材料の具体例として、熱硬化性樹脂、ポリエステル、ポリカーボネート、ポリビニルアルコール、ポリビニルフェノール、ポリビニルブチラール、ポリアセタール、ポリアリレート、ポリアミド、ポリアミドイミド、ポリフェニレンエーテル、ポリフェニレンスルファイド、ポリエーテルスルホン、ポリエーテルケトン、ポリフタルアミド、ポリエーテルニトリル、ポリベンズイミダゾール、ポリカルボジイミド、ポリシロキサン、ポリメチルメタクリレート、ポリメタクリルアミド、ニトリルゴム、アクリルゴム、ポリエチレンテトラフルオライド、ポリブテン、ポリペンテン、エチレン−プロピレン共重合体、ポリブタジエン、ポリスチレンおよびこれらの混合物を含むが、これらに制限されない。   Specific examples of suitable organic insulating materials include thermosetting resin, polyester, polycarbonate, polyvinyl alcohol, polyvinyl phenol, polyvinyl butyral, polyacetal, polyarylate, polyamide, polyamideimide, polyphenylene ether, polyphenylene sulfide, polyether sulfone, Polyether ketone, polyphthalamide, polyether nitrile, polybenzimidazole, polycarbodiimide, polysiloxane, polymethyl methacrylate, polymethacrylamide, nitrile rubber, acrylic rubber, polyethylene tetrafluoride, polybutene, polypentene, ethylene-propylene copolymer Including, but not limited to, coalesced, polybutadiene, polystyrene, and mixtures thereof.

上記熱硬化性樹脂としては、熱により硬化して接着作用を呈するものであれば良く、特に制限されないが、例えば、エポキシ樹脂、ビストリアジン樹脂、ポリイミド樹脂、フェノール樹脂、メラミン樹脂、シリコン樹脂、不飽和ポリエステル樹脂、シアン酸エステル樹脂、イソシアネート樹脂、ポリベンズオキサゾール樹脂、ポリベンゾシクロブテン樹脂またはこれらの種々の変性樹脂類が好適である。   The thermosetting resin is not particularly limited as long as it is cured by heat and exhibits an adhesive action. For example, epoxy resin, bistriazine resin, polyimide resin, phenol resin, melamine resin, silicon resin, Saturated polyester resins, cyanate ester resins, isocyanate resins, polybenzoxazole resins, polybenzocyclobutene resins or various modified resins thereof are suitable.

上記エポキシ樹脂としては、特に限定されないが、例えば、ビスフェノールA型エポキシ樹脂、ビスフェノールF型エポキシ樹脂、ビスフェノールS型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、サリチルアルデヒドノボラック型エポキシ樹脂、ビスフェノールFノボラック型エポキシ樹脂、脂環式エポキシ樹脂、グリシジルエステル型エポキシ樹脂、グリシジルアミン型エポキシ樹脂、ヒダントイン型エポキシ樹脂、イソシアヌレート型エポキシ樹脂、脂肪族環状エポキシ樹脂、およびそれらのハロゲン化物、水素添加物等を挙げることができ、これらは単独で用いても2種以上を併用しても構わない。   The epoxy resin is not particularly limited. For example, bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, phenol novolac type epoxy resin, salicylaldehyde novolac type epoxy resin, bisphenol F novolac type epoxy resin. Alicyclic epoxy resins, glycidyl ester type epoxy resins, glycidyl amine type epoxy resins, hydantoin type epoxy resins, isocyanurate type epoxy resins, aliphatic cyclic epoxy resins, and their halides, hydrogenated products, etc. These may be used alone or in combination of two or more.

本発明の帯電体には、必要に応じて、硬化剤を添加してもよい。硬化剤としては、用いる熱硬化性樹脂(絶縁性有機高分子)により適宜決定すればよく、特に限定されないが、例えば、絶縁性有機高分子がエポキシ樹脂である場合には、酸無水物化合物、一級または二級アミン、ポリアミン、ポリアミド、ジシアンジアミド、重縮合型アリーロキシシラン化合物、フェノール性水酸基を1分子中に2個以上有する化合物である、ビスフェノールA樹脂、ビスフェノールF樹脂、フェノールノボラック樹脂、ビスフェノールノボラック樹脂、クレゾールノボラック樹脂、サリチルアルデヒドノボラック樹脂及びこれらのフェノール樹脂のハロゲン化物、水素化物、トリアジン構造含有物等を使用できる。これらの硬化剤は1種または2種以上併用してもよい。   You may add a hardening | curing agent to the charged body of this invention as needed. The curing agent may be appropriately determined depending on the thermosetting resin (insulating organic polymer) to be used, and is not particularly limited. For example, when the insulating organic polymer is an epoxy resin, an acid anhydride compound, Primary or secondary amine, polyamine, polyamide, dicyandiamide, polycondensation type aryloxysilane compound, compound having two or more phenolic hydroxyl groups in one molecule, bisphenol A resin, bisphenol F resin, phenol novolac resin, bisphenol novolac Resins, cresol novolac resins, salicylaldehyde novolak resins, and halides, hydrides, triazine structure-containing materials, and the like of these phenol resins can be used. These curing agents may be used alone or in combination of two or more.

硬化剤の配合量は、特に限定されないが、例えば、絶縁性有機高分子としてエポキシ樹脂を用いる場合には、エポキシ当量に対して水酸基当量が、0.5〜2.0当量の範囲、好ましくは、0.8〜1.2当量の範囲、さらに好ましくは、0.9〜1.1当量の範囲となるように配合することが好ましい。   Although the compounding quantity of a hardening | curing agent is not specifically limited, For example, when using an epoxy resin as an insulating organic polymer, a hydroxyl group equivalent is the range of 0.5-2.0 equivalent with respect to an epoxy equivalent, Preferably , 0.8 to 1.2 equivalents, and more preferably 0.9 to 1.1 equivalents.

また、本発明の帯電体には、必要に応じて、硬化促進剤を添加してもよい。硬化促進剤としては、特に限定されないが、例えば、絶縁性有機高分子がエポキシ樹脂である場合には、イミダゾール化合物、有機リン化合物、第3級アミン、第4級アンモニウム塩、ルイス酸、トリアルキルオキソニウム塩、カルボニウム塩、ジアゾニウム塩、アルキル化剤、スルホニウム塩、ジアリルアイオドニウム塩を使用することができる。   Moreover, you may add a hardening accelerator to the charged body of this invention as needed. The curing accelerator is not particularly limited. For example, when the insulating organic polymer is an epoxy resin, an imidazole compound, an organic phosphorus compound, a tertiary amine, a quaternary ammonium salt, a Lewis acid, a trialkyl Oxonium salts, carbonium salts, diazonium salts, alkylating agents, sulfonium salts and diallyl iodonium salts can be used.

前記の無機絶縁材料として、SiO、SiON、SiN、SiOC、SiOF、Al、Ta、TiO、ZrO、BaTiO、Nb、セラミックス、ガラス、マイカが挙げられるがこれに限定されない。 Examples of the inorganic insulating material include SiO 2 , SiON, SiN, SiOC, SiOF, Al 2 O 3 , Ta 2 O 5 , TiO 3 , ZrO 2 , BaTiO 3 , Nb 2 O 5 , ceramics, glass, and mica. However, it is not limited to this.

前記のMNOSトランジスタように20nm以下の薄層に成形する必要が無いため、絶縁膜の成形には熱酸化膜や蒸着、CVD、スパッタのような高精度の製膜手法だけでなく、塗布や印刷による成膜手法も用いることができる。塗布、印刷方法としては、所望の塗布厚で各々の材料を塗布、印刷することが可能な方法を適用することができ、例えば、塗布方法としてディップコーティング、スピンコーティング、スプレーコーティング、インクジェットコーティング、オフセットコーティング、ロールコーティングが挙げられ、印刷方法としてはインクジェット印刷法、転写法、オフセット印刷法、スクリーン印刷法、凸版印刷、凹版印刷、ソフトリソグラフ、ディスペンサ法が挙げられる。   Since the MNOS transistor does not need to be formed into a thin layer of 20 nm or less, the insulating film can be formed not only by a highly accurate film formation method such as thermal oxide film, vapor deposition, CVD, and sputtering, but also by coating and printing. The film forming method by can also be used. As a coating and printing method, a method capable of applying and printing each material with a desired coating thickness can be applied. For example, as a coating method, dip coating, spin coating, spray coating, inkjet coating, offset Examples of the printing method include an inkjet printing method, a transfer method, an offset printing method, a screen printing method, a relief printing, an intaglio printing, a soft lithography, and a dispenser method.

本発明では、低電荷注入耐圧材料または高電荷注入耐圧材料のいずれか一方が、又は両方が、有機高分子で構成されると好ましい。また、3次元架橋高分子材料であると好ましい。上記のような、塗布や印刷による成膜手法を用いることができ容易に帯電体を形成できる。3次元架橋高分子材料は、前記の熱硬化性樹脂を硬化剤、硬化促進剤などにより架橋させたものである。また、熱可塑性樹脂、ゴムの側鎖や主鎖に架橋性の官能基である、−OH、−COOH、−NHなどを導入し、架橋させる方法、有機過酸化物、光重合開始剤などを配合し、熱や光によりラジカルを発生させ架橋させる方法などを用いることができる。3次元架橋高分子材料が、湿式工程によって形成されたものであると、簡便に帯電体を形成できるので好ましい。 In the present invention, it is preferable that either one or both of the low charge injection withstand voltage material and the high charge injection withstand voltage material are composed of an organic polymer. A three-dimensional cross-linked polymer material is preferable. As described above, a film forming technique by coating or printing can be used, and a charged body can be easily formed. The three-dimensional crosslinked polymer material is obtained by crosslinking the thermosetting resin with a curing agent, a curing accelerator or the like. Also, a method of introducing a crosslinkable functional group such as —OH, —COOH, —NH 2 into a thermoplastic resin, a side chain or a main chain of rubber, and crosslinking, an organic peroxide, a photopolymerization initiator, etc. And a method of generating a radical by heat or light to cause crosslinking. It is preferable that the three-dimensional crosslinked polymer material is formed by a wet process because a charged body can be easily formed.

(FETおよびメモリ素子)
本発明のFETおよびメモリ素子は、基板上にゲート電極と、ソース−ドレイン電極と、チャネル層を構成する半導体層と、ゲート電極とチャネル層に挟まれた前記の帯電体(ゲート絶縁膜)とを備えたFETにおいて、帯電体が高絶縁耐圧の材料と低絶縁耐圧の材料が積層された構造からなることを特徴とする。基本的な素子構造を図1から図9に示したが、本発明はこれらの図で示される素子構成に限定されるものではない。
(FET and memory device)
The FET and the memory element of the present invention comprise a gate electrode, a source-drain electrode, a semiconductor layer constituting a channel layer on the substrate, and the charged body (gate insulating film) sandwiched between the gate electrode and the channel layer. In the FET having the above structure, the charged body has a structure in which a material with a high withstand voltage and a material with a low withstand voltage are stacked. Although the basic element structure is shown in FIGS. 1 to 9, the present invention is not limited to the element structure shown in these drawings.

本発明に係るFETおよびメモリ素子において、半導体層として用いられる半導体は、有機半導体や無機半導体として用いられる公知の全ての材料を用いて製造できる。好ましい半導体層は、シリコン、窒化珪素、ペンタセン、テトラセン、TIPS−ペンタセン(6,13−ビス(トリイソプロピルシリルエチニル)ペンタセン)、ポリチオフェン、チエニルチオフェン誘導体、銅フタロシアニン、ポリアニリン、ポリピロール、ポリフェニレンビニレン、ポルフルオレン、カーボンナノチューブ、SnO粒子、ZnO粒子、シリコン、SnO前駆体溶液、ZnO前駆体溶液またはこれらの誘導体から製造できるが、これに制限されない。   In the FET and the memory element according to the present invention, a semiconductor used as a semiconductor layer can be manufactured using all known materials used as an organic semiconductor or an inorganic semiconductor. Preferred semiconductor layers are silicon, silicon nitride, pentacene, tetracene, TIPS-pentacene (6,13-bis (triisopropylsilylethynyl) pentacene), polythiophene, thienylthiophene derivatives, copper phthalocyanine, polyaniline, polypyrrole, polyphenylene vinylene, porfluorene. , Carbon nanotubes, SnO particles, ZnO particles, silicon, SnO precursor solution, ZnO precursor solution, or derivatives thereof, but is not limited thereto.

本発明に係るFETおよびメモリ素子の基板、ゲート電極、およびソース−ドレイン電極の材質は、FETの分野で公知の全ての材料を含む。より好ましくは、基板はプラスチック基板、樹脂シート、金属シート、ガラス基板、石英基板またはシリコン基板であり、ゲートおよびソース−ドレイン電極は導電性の材料からなり、好ましくはAu、Ag、Cu、Al、アルミニウム合金、ニッケル、Cr、カルシウム、タンタル、白金、パラジウム、チタン,ドープしたSiの他、ITO、SnOの透明電極または有機伝導体材料としてPEDOT−PSS(Poly(3,4−ethylenedioxythiophene)poly(styrenesulfonate))、カーボンナノチューブ、グラフェンシート、TTF−TCNQ(テトラチアフルバレン−テトラシアノキノジメタン)が挙げられるが、これに制限されない。   The materials of the substrate, gate electrode, and source-drain electrode of the FET and memory device according to the present invention include all materials known in the field of FET. More preferably, the substrate is a plastic substrate, a resin sheet, a metal sheet, a glass substrate, a quartz substrate, or a silicon substrate, and the gate and source-drain electrodes are made of a conductive material, preferably Au, Ag, Cu, Al, Aluminum alloy, nickel, Cr, calcium, tantalum, platinum, palladium, titanium, doped Si, ITO, SnO transparent electrode or organic conductive material PEDOT-PSS (Poly (3,4-ethylenedioxythiophene) poly (styreneenesulfonate) )), Carbon nanotubes, graphene sheets, and TTF-TCNQ (tetrathiafulvalene-tetracyanoquinodimethane), but are not limited thereto.

本発明のFETは、ゲート絶縁膜を挟んでゲート電極と半導体層があり、その半導体層に接してソース−ドレイン電極を有する電界効果トランジスタにおいて、ゲート絶縁膜が上記の帯電体で、帯電体に注入される電荷量により電界効果トランジスタの閾値電圧を制御することを特徴とするものである。そして、それを用いた本発明のメモリ素子は、前記の電界効果トランジスタに、帯電体内に保持された注入電荷量により情報を記録し、ECI,L > |E|のゲート電界強度下でのドレイン電流量の差として情報を呼び出すことを特徴とするものである。 The FET of the present invention has a gate electrode and a semiconductor layer sandwiching a gate insulating film, and in a field effect transistor having a source-drain electrode in contact with the semiconductor layer, the gate insulating film is the above charged body, The threshold voltage of the field effect transistor is controlled by the amount of charge injected. The memory element of the present invention using the same records information on the above-mentioned field effect transistor by the amount of injected charge held in the charged body, under the gate electric field strength of E CI, L > | E | The information is called as a difference in drain current amount.

以下、本発明を実施例に基づき説明するが、本発明は以下実施例に制限されるものではない。   EXAMPLES Hereinafter, although this invention is demonstrated based on an Example, this invention is not restrict | limited to an Example below.

(実施例1)
(ビスフェノールFのジフェニルシリル化体の製造)
セパラブルフラスコに、ビスフェノールF(本州化学工業株式会社製) 160g(0.80mol)、ジメトキシジフェニルシラン(AZ−6183:東レ・ダウコーニング株式会社製) 95.3g(0.8mol)、リン触媒 (PPQ:北興化学工業株式会社製) 0.80g(0.5質量%)を仕込み、130℃で溶解させ15時間攪拌した。この時発生するメタノールは系外に除去した。その後、加熱減圧下、さらに20時間反応を行うことで、ビスフェノールFのジフェニルシリル化体を270g得た。
(Example 1)
(Production of diphenylsilylated bisphenol F)
In a separable flask, bisphenol F (manufactured by Honshu Chemical Industry Co., Ltd.) 160 g (0.80 mol), dimethoxydiphenylsilane (AZ-6183: manufactured by Toray Dow Corning Co., Ltd.) 95.3 g (0.8 mol), phosphorus catalyst ( PPQ: manufactured by Hokuko Chemical Co., Ltd.) 0.80 g (0.5% by mass) was charged, dissolved at 130 ° C., and stirred for 15 hours. Methanol generated at this time was removed out of the system. Then, 270 g of diphenylsilylated bisphenol F was obtained by further reaction for 20 hours under heating and reduced pressure.

(低電荷注入耐圧樹脂の溶液調製)
ついで、ビスフェノールAノボラック型エポキシ樹脂(N−865:大日本インキ化学工業株式会社製)0.50g、(ビスフェノールFのジフェニルシリル化体の製造)に従い合成したビスフェノールFのジフェニルシリル化体0.34g、1−シアノエチル−2−フェニルイミダゾール(2PZ−CN:四国化成工業株式会社製) 1質量%のアニソール溶液0.01gを、アニソール41.16gに溶解させて(樹脂濃度2質量%)、低電荷注入耐圧樹脂の溶液を調整した。
(Preparation of low charge injection pressure resistant resin solution)
Next, 0.50 g of bisphenol A novolac epoxy resin (N-865: manufactured by Dainippon Ink and Chemicals, Inc.), 0.34 g of diphenylsilylated bisphenol F synthesized according to (production of diphenylsilylated bisphenol F) 1-cyanoethyl-2-phenylimidazole (2PZ-CN: manufactured by Shikoku Kasei Kogyo Co., Ltd.) A 1% by weight anisole solution 0.01 g was dissolved in 41.16 g of anisole (resin concentration 2% by weight) to reduce the charge. An injection pressure resistant resin solution was prepared.

(絶縁特性測定)
プラズマアッシャーで250W、5分処理したCrを50nm蒸着したシリコンウエハ(直径50mm、厚み 280μm、タイプN、抵抗率 1〜10 Ω・cm、片面鏡面研磨、株式会社KNプラッツ製)上に、前記と同様の方法で作製した樹脂濃度15質量%に調製した低電荷注入耐圧樹脂の溶液をメンブランフィルタ(Anotop 10、ワットマン社製)を透過した後滴下し、スピンコータにより、500rpm、5秒、2000rpm、60秒の条件でスピンコートした。その後、100℃のホットプレート上で10分間乾燥し、さらに、200℃のホットプレート上で15分間硬化した。カッターナイフで樹脂の一部に傷をつけ、傷の深さを触針式表面形状測定装置(DEKTAK、株式会社アルバック製)にて測定した結果、樹脂の膜厚は310nmであった。この樹脂膜の上に、メタルマスクを用いて直径100μmの円形のAu電極を蒸着装置(Thermal deposition system、Kurt J. Lesker社製)にて0.4Å/秒で30nmの厚さで蒸着した。ソースメジャーユニット(SOURCE MEASURE UNIT(SOUCE MEASURE UNIT 237、 KEITHLEY Instruments社製)を接続したニードルプローブを用いてCrとAu電極の間に、0から300Vの電圧を1Vステップで昇圧しながらかけて、電流を測定した(図10)。5点の平均をとった結果、電荷注入の始まる電界強度は3.4MV/cm、絶縁耐圧は6.3MV/cmであった。
なお、シリコンウエハの熱酸化膜の絶縁耐圧は10MV/cmである(非特許文献3)。
(Insulation characteristics measurement)
On a silicon wafer (diameter 50 mm, thickness 280 μm, type N, resistivity 1 to 10 Ω · cm, single-sided mirror polished, manufactured by KN Platz Co., Ltd.), on which Cr treated by O 2 plasma asher at 250 W for 5 minutes was deposited by 50 nm. A solution of a low charge injection pressure resistant resin prepared to have a resin concentration of 15% by mass prepared in the same manner as described above was dropped after passing through a membrane filter (Anotop 10, manufactured by Whatman), and was spin-coated at 500 rpm, 5 seconds, 2000 rpm. And spin-coated under the conditions of 60 seconds. Then, it dried for 10 minutes on a 100 degreeC hotplate, and also hardened | cured for 15 minutes on a 200 degreeC hotplate. A portion of the resin was scratched with a cutter knife, and the depth of the scratch was measured with a stylus type surface shape measuring device (DEKTAK, manufactured by ULVAC, Inc.). As a result, the resin film thickness was 310 nm. On this resin film, a circular Au electrode having a diameter of 100 μm was vapor-deposited at a thickness of 30 nm at a rate of 0.4 mm / second by a vapor deposition apparatus (Thermal deposition system, manufactured by Kurt J. Lesker) using a metal mask. Using a needle probe to which a source measure unit (SOURCE MEASURE UNIT (SOURCE MEASURE UNIT 237, manufactured by KEITHLEY Instruments)) is connected, a voltage of 0 to 300 V is stepped up in 1 V step between Cr and Au electrodes. (Fig. 10) As a result of taking the average of 5 points, the electric field strength at which charge injection started was 3.4 MV / cm, and the withstand voltage was 6.3 MV / cm.
Note that the withstand voltage of the thermal oxide film of the silicon wafer is 10 MV / cm (Non-Patent Document 3).

(メモリ素子形成)
厚さ100nmの熱酸化膜を有する高ドープシリコンウエハ(直径50mm、厚み 280μm、タイプN、抵抗率 0.002〜0.004Ω・cm、片面鏡面研磨、株式会社KNプラッツ製)をOプラズマアッシャーで250W、5分処理後、メンブランフィルタ(Anotop 10、ワットマン社製)を透過した低電荷注入耐圧樹脂の溶液をスピンコータにより、500rpm、5秒、2000rpm、60秒の条件でスピンコートした。その後、100℃のホットプレート上で10分間乾燥し、さらに、200℃のホットプレート上で15分間硬化した。低電荷注入耐圧樹脂の膜厚は、硬化樹脂をカッターナイフで傷つけて、その傷の深さを原子間力顕微鏡(Scanning Prove Microscope Dimension 3100、 Digital Instruments社製)にて測定した。その結果、低電荷注入耐圧樹脂の膜厚は、21nmであった。この場合、熱酸化膜が高電荷注入耐圧の絶縁体、エポキシ樹脂が低電荷注入耐圧の絶縁体に相当する。
(Memory element formation)
A highly doped silicon wafer (diameter 50 mm, thickness 280 μm, type N, resistivity 0.002 to 0.004 Ω · cm, single-side mirror polished, manufactured by KN Platz Co., Ltd.) having a thermal oxide film of 100 nm thickness is O 2 plasma asher After 250 minutes of treatment at 250 W, a solution of a low charge injection pressure resistant resin that passed through a membrane filter (Anotop 10, manufactured by Whatman) was spin-coated with a spin coater under conditions of 500 rpm, 5 seconds, 2000 rpm, and 60 seconds. Then, it dried for 10 minutes on a 100 degreeC hotplate, and also hardened | cured for 15 minutes on a 200 degreeC hotplate. The film thickness of the low charge injection pressure-resistant resin was measured by damaging the cured resin with a cutter knife and measuring the depth of the damage with an atomic force microscope (Scanning Probe Microscope Dimension 3100, manufactured by Digital Instruments). As a result, the film thickness of the low charge injection withstand voltage resin was 21 nm. In this case, the thermal oxide film corresponds to an insulator with a high charge injection breakdown voltage, and the epoxy resin corresponds to an insulator with a low charge injection breakdown voltage.

以降、素子特性の測定までは、窒素グローブボックス中で行った。エポキシ樹脂上にメタルマスクを用いてペンタセンを蒸着装置(Thermal deposition system、Kurt J. Lesker社製)で0.4Å/秒で60nmの厚さで蒸着し半導体層を形成し、続けてAuをメタルマスクを用いて0.4Å/秒で60nmの厚さで蒸着してソース・ドレイン電極を形成した。
この素子のゲート電極は、高ドープシリコン、ソースおよびドレイン電極は、Auであり、ゲート長1mm、ゲート幅5mmである。
Thereafter, the device characteristics were measured in a nitrogen glove box. Using a metal mask on the epoxy resin, pentacene is deposited at a thickness of 60 nm at a rate of 0.4 nm / second with a vapor deposition apparatus (Thermal deposition system, manufactured by Kurt J. Resker) to form a semiconductor layer, and then Au is metalized. A source / drain electrode was formed by vapor deposition at a thickness of 60 nm at 0.4 Å / sec using a mask.
The gate electrode of this element is highly doped silicon, the source and drain electrodes are Au, the gate length is 1 mm, and the gate width is 5 mm.

(素子特性測定)
メモリ素子特性は上面の帯電体(ゲート絶縁膜)を削った後、銀ペーストを塗布してゲート電極への端子とし、窒素グローブボックス中でニードルプローブを用いて導通をとり、Parameter Analyzer(4156A or 4156C Precision Semiconductor Parameter Analyzer、Agilent Technologies社製) を用いて計測した。
素子にゲート電界強度範囲と、掃引方向を変えてかけ、ドレイン電圧V=−10V 一定の条件でドレイン電流Iを測定した。
(I1/2とゲート電圧Vを変数とした電流伝達特性のグラフを得、その傾きと切片を下記式(1)に代入して電界効果移動度μと、閾値電圧Vthを求めた。
(Element characteristic measurement)
The memory element characteristic is that after removing the charged body (gate insulating film) on the upper surface, a silver paste is applied to make a terminal to the gate electrode, and conduction is made using a needle probe in a nitrogen glove box, and Parameter Analyzer (4156A or 4156C Precision Semiconductor Parameter Analyzer, manufactured by Agilent Technologies).
The gate current intensity range and the sweep direction were applied to the device, and the drain current I D was measured under a constant condition of the drain voltage V D = −10 V.
A graph of current transfer characteristics with (I D ) 1/2 and the gate voltage V G as variables is obtained, and the slope and intercept are substituted into the following equation (1) to determine the field effect mobility μ and the threshold voltage V th . Asked.

Figure 0005696882
式(1)中、Cはゲート絶縁膜の静電容量、Wはチャネル幅、Lはチャネル長、Vはゲート電圧である。
Figure 0005696882
In formula (1), C i is the capacitance of the gate insulating film, W is the channel width, L is the channel length, and V G is the gate voltage.

(素子特性)
素子特性の測定結果を表1にまとめて示した。電界強度の絶対値が2.7MV/cm以下では閾値電圧は掃引方向によらずほぼ一定の−3V前後になった。それに対し、電界強度の絶対値が3.6MV/cm以上のとき、負から正へ掃引した場合には閾値電圧は−3Vより負にシフトし、より強い電界強度から開始するほど大きく負にシフトした(図12)。逆に、正から負へ掃引した場合には閾値電圧が正にシフトし、より強い電界強度から開始するほど大きく正にシフトした(図11)。閾値電圧のシフトが始まる電界強度3.6MV/cm以上は、エポキシ樹脂に電荷注入による微小電流が流れる電界強度3.4MV/cmと対応しており、エポキシ樹脂内に電荷が注入され、熱酸化膜とエポキシ樹脂の界面に電荷が蓄積し、蓄積した電荷による電界により閾値電圧がシフトした。
(Element characteristics)
The measurement results of device characteristics are summarized in Table 1. When the absolute value of the electric field strength was 2.7 MV / cm or less, the threshold voltage was approximately constant -3 V regardless of the sweep direction. On the other hand, when the absolute value of the electric field strength is 3.6 MV / cm or more, the threshold voltage shifts from −3V to negative when sweeping from negative to positive, and shifts more negative as starting from a stronger electric field strength. (FIG. 12). On the contrary, when sweeping from positive to negative, the threshold voltage shifted to positive, and shifted more positively as it started from stronger electric field strength (FIG. 11). The electric field strength of 3.6 MV / cm or more at which the threshold voltage starts to shift corresponds to the electric field strength of 3.4 MV / cm in which a minute current flows through the epoxy resin due to the charge injection. Charges accumulated at the interface between the film and the epoxy resin, and the threshold voltage shifted due to the electric field generated by the accumulated charges.

Figure 0005696882
Figure 0005696882

(複数回動作)
ゲート電界強度を+5MV/cmから−5MV/cmの間で昇圧、降圧を3回繰り返し測定した(図13)。電流伝達特性曲線(図13)は、前述の理由で、ゲート電界強度として正の高電界(+5MV/cm)がかかった後は、帯電体中の界面に負電荷が蓄積して正に閾値電圧がシフトし、逆にゲート電界強度として負の高電界(−5MV/cm)がかかった後は、帯電体中の界面に正電荷が蓄積して負に閾値電圧がシフトして強いヒステリシスを持ったトランスファーカーブを描いた。このヒステリシスを有した電流伝達特性曲線は同一デバイスを3回測定しても、図13のようにほぼ同一の曲線を描き、この挙動が絶縁破壊のような不可逆な変化ではなく、可逆な特性であることを示す。
このことから、本発明の帯電体を用いたメモリ素子は書き換え可能なメモリとして働く。
(Operation multiple times)
The gate electric field strength was repeatedly measured by increasing and decreasing the pressure three times between +5 MV / cm and -5 MV / cm (FIG. 13). In the current transfer characteristic curve (FIG. 13), for the reason described above, after a positive high electric field (+5 MV / cm) is applied as the gate electric field strength, negative charges accumulate at the interface in the charged body, and the threshold voltage is positive. In contrast, after a negative high electric field (-5 MV / cm) is applied as the gate electric field strength, positive charges accumulate at the interface in the charged body, and the threshold voltage shifts negatively, resulting in strong hysteresis. Draw a transfer curve. Even if the same device is measured three times, the current transfer characteristic curve with hysteresis draws almost the same curve as shown in FIG. 13, and this behavior is not an irreversible change such as dielectric breakdown but a reversible characteristic. It shows that there is.
For this reason, the memory element using the charged body of the present invention functions as a rewritable memory.

(メモリ動作)
ゲート電界強度を−5MV/cmかけ、その後ゲート電圧を除去し一定時間後にゲート電界強度を0から−5MV/cm、ドレイン電圧−10Vでデバイス特性を測定し閾値電圧を求めた。結果を図14と図2にまとめた。
前記のように、電荷注入の始まる電界強度である−3.4MV/cm以下のゲート電界強度でデバイス特性を測定した場合の閾値電圧は−4.1Vであった。それに対し、ゲート電界強度を−5MV/cmかけた直後の閾値電圧は−23.5Vであり、熱酸化膜とエポキシ樹脂の界面に電荷が蓄積した。
−5MV/cmかけた後、1分、5分、30分経過後の閾値電圧はそれぞれ−20.6、−19.8、−17.8Vと、熱酸化膜とエポキシ樹脂の界面に電荷が蓄積していない場合の−4.1Vと比較して大きく負にシフトした閾値電圧が保持され、熱酸化膜とエポキシ樹脂の界面に電荷が蓄積した電荷が30分後でも保持されていた。
これにより、例えば図14において−1.5MV/cmのゲート電界強度と−10Vのドレイン電圧でドレイン電流を読み出せば、熱酸化膜とエポキシ樹脂の界面に電荷が蓄積されていない場合とされている場合で、それぞれ、1.7×10−6Aと2.3×10−10Aと4桁の電流差として記憶状態を読み出せる。このとき、−1.5MV/cmのゲート電界強度は電荷注入の始まる電界強度を大幅に下回っており、この読み出し操作により熱酸化膜とエポキシ樹脂の界面に蓄積された電荷量への影響はない。
(Memory operation)
A gate electric field strength of −5 MV / cm was applied, and then the gate voltage was removed. After a predetermined time, device characteristics were measured at a gate electric field strength of 0 to −5 MV / cm and a drain voltage of −10 V to obtain a threshold voltage. The results are summarized in FIG. 14 and FIG.
As described above, the threshold voltage when the device characteristics were measured at a gate field strength of −3.4 MV / cm or less, which is the field strength at which charge injection starts, was −4.1V. On the other hand, the threshold voltage immediately after applying the gate electric field strength of −5 MV / cm was −23.5 V, and charges accumulated at the interface between the thermal oxide film and the epoxy resin.
After applying −5 MV / cm, the threshold voltages after 1 minute, 5 minutes, and 30 minutes passed are −20.6, −19.8, and −17.8 V, respectively, and there is a charge at the interface between the thermal oxide film and the epoxy resin. The threshold voltage, which was largely negatively shifted compared to −4.1 V in the case where the charge was not accumulated, was retained, and the charge accumulated at the interface between the thermal oxide film and the epoxy resin was retained even after 30 minutes.
Thus, for example, in FIG. 14, if the drain current is read with a gate electric field strength of −1.5 MV / cm and a drain voltage of −10 V, no charge is accumulated at the interface between the thermal oxide film and the epoxy resin. In this case, the storage state can be read as a current difference of 1.7 × 10 −6 A and 2.3 × 10 −10 A and 4 digits, respectively. At this time, the gate electric field strength of −1.5 MV / cm is significantly lower than the electric field strength at which charge injection starts, and this read operation does not affect the amount of charge accumulated at the interface between the thermal oxide film and the epoxy resin. .

Figure 0005696882
Figure 0005696882

(実施例2)
低電荷注入耐圧樹脂溶液の濃度が15質量%であり、結果として製膜された低電荷注入耐圧樹脂の膜厚が327nmである以外は、実施例1と同様に(素子特性)まで実施した。図15に示したように、初期に高ゲート電界強度をかける前の閾値電圧−8Vと、−6.1MV/cmかけた後では、閾値電圧−30Vと、閾値電圧に大きな差を生じた。このデバイスは、厚み100nmの熱酸化膜と厚み327nmのエポキシ樹脂が積層した帯電体をゲート絶縁膜に用いており、いずれもトンネル効果を無視できる厚みであることから、−3.4MV/cm以上の電界強度がかかることによりエポキシ樹脂側から電荷注入が生じて帯電体内の界面に電荷が蓄積し、閾値電圧がシフトした。
(Example 2)
The process was performed up to (element characteristics) in the same manner as in Example 1 except that the concentration of the low charge injection pressure resistant resin solution was 15% by mass and the film thickness of the resulting low charge injection pressure resistant resin was 327 nm. As shown in FIG. 15, there was a large difference between the threshold voltage and the threshold voltage of −30 V after applying −6.1 MV / cm before applying the high gate electric field strength in the initial stage. In this device, a charged body in which a thermal oxide film having a thickness of 100 nm and an epoxy resin having a thickness of 327 nm are stacked is used as a gate insulating film, and the thickness is such that the tunnel effect can be ignored. Therefore, −3.4 MV / cm or more As a result of this electric field strength being applied, charge injection occurred from the epoxy resin side, charges accumulated at the interface inside the charged body, and the threshold voltage shifted.

(実施例3)
低電荷注入耐圧樹脂溶液として、ジビニルテトラメチルシロキサン−ビス(ベンゾシクロブテン)(以下BCB)のメシチレン溶液(30質量%、メルク社製)をメシチレンで2質量%に希釈して用い、結果として製膜された低電荷注入耐圧樹脂の膜厚が15nmである以外は、実施例1と同様に(素子特性)まで実施した。
(Example 3)
As a low-charge injection pressure-resistant resin solution, a mesitylene solution of divinyltetramethylsiloxane-bis (benzocyclobutene) (hereinafter BCB) (30% by mass, manufactured by Merck & Co., Inc.) was diluted to 2% by mass with mesitylene and used as a result. The process was performed up to (element characteristics) in the same manner as in Example 1 except that the film thickness of the formed low charge injection withstand voltage resin was 15 nm.

(素子特性)
素子特性の測定結果を表3にまとめて示した。電界強度の絶対値が2.3MV/cm以下では閾値電圧は掃引方向によらずほぼ一定の−5V前後になった。それに対し、電界強度の絶対値が3.2MV/cm以上のとき、負から正へ掃引した場合には閾値電圧は−5Vより負にシフトし、より強い電界強度から開始するほど大きく負にシフトした(図16)。逆に、電界強度の絶対値が3.2MV/cm以上の正のゲート電界強度から負へ掃引した場合には閾値電圧が正にシフトし、より強い電界強度から開始するほど大きく正にシフトした(図17)。熱酸化膜より電荷注入の開始する電界強度の低いBCB側から電荷がBCB内に注入され、熱酸化膜とBCBの界面に電荷が蓄積し、蓄積した電荷による電界により閾値電圧がシフトした。
(Element characteristics)
The measurement results of the device characteristics are summarized in Table 3. When the absolute value of the electric field strength was 2.3 MV / cm or less, the threshold voltage was approximately constant -5 V regardless of the sweep direction. On the other hand, when the absolute value of the electric field strength is 3.2 MV / cm or more, the threshold voltage shifts from -5 V to negative when sweeping from negative to positive, and shifts more negative as starting from a stronger electric field strength. (FIG. 16). On the contrary, when the absolute value of the electric field strength is swept from a positive gate electric field strength of 3.2 MV / cm to negative, the threshold voltage is shifted to positive, and the threshold voltage is shifted more positive as starting from a stronger electric field strength. (FIG. 17). Charges were injected into the BCB from the BCB side where the electric field strength started from the thermal oxide film was low, and charges were accumulated at the interface between the thermal oxide film and the BCB, and the threshold voltage was shifted by the electric field due to the accumulated charges.

Figure 0005696882
Figure 0005696882

(メモリ動作)
ゲート電界強度を−5.9MV/cmかけ、その後ゲート電圧を除去し一定時間後に、ドレイン電圧−10V(一定)、ゲート電界強度を−0.5から−5.9MV/cmまで掃引しデバイス特性を測定して、閾値電圧を求めた。結果を図18と表4にまとめて示した。
−5.9MV/cmかけた後、0分、1分、30分経過後の閾値電圧はそれぞれ−30.2、−27.1、−19.2Vと−5.5Vと比較して大きく負にシフトしていた。熱酸化膜とBCBの界面に蓄積した電荷が30分後でも保持されていた。
BCBでは実施例1のエポキシ樹脂と比較して、30分間の閾値電圧の変化は11Vと大きかったが、これはBCB膜厚が15nmとエポキシ樹脂の21nmより薄いため、蓄積された電荷を保持する能力が低くなったためである。
(Memory operation)
The gate electric field strength is -5.9 MV / cm, then the gate voltage is removed, and after a certain period of time, the drain voltage is -10 V (constant), and the gate electric field strength is swept from -0.5 to -5.9 MV / cm. Was measured to determine the threshold voltage. The results are summarized in FIG. 18 and Table 4.
After applying −5.9 MV / cm, the threshold voltages after 0 minutes, 1 minute, and 30 minutes passed are significantly negative compared to −30.2, −27.1, −19.2 V, and −5.5 V, respectively. Had shifted to. The charge accumulated at the interface between the thermal oxide film and BCB was retained even after 30 minutes.
In BCB, compared with the epoxy resin of Example 1, the change in the threshold voltage for 30 minutes was as large as 11 V. This is because the BCB film thickness is 15 nm, which is thinner than 21 nm of the epoxy resin, so that the accumulated charge is retained. This is because the ability has decreased.

Figure 0005696882
Figure 0005696882

(実施例4)
実施例1の(低電荷注入耐圧樹脂の溶液調製において、ビスフェノールFのジフェニルシリル化体の代わりにビスフェノールAノボラック(VH−4170:大日本インキ化学工業株式会社製)を0.27g用いた以外は同様に低電荷注入耐圧樹脂の溶液を調整した。以降、実施例1と同様に(素子特性)まで行った。
その結果、電荷注入の始まる電界強度は2.8MV/cm、絶縁耐圧は5.9MV/cmであった。また、帯電体の低電荷注入耐圧樹脂の厚みは20nmであった。
Example 4
Except that 0.27 g of bisphenol A novolak (VH-4170: manufactured by Dainippon Ink & Chemicals, Inc.) was used in place of the diphenylsilylated product of bisphenol F in the preparation of the low charge injection pressure resistant resin solution of Example 1 Similarly, a solution of a low charge injection pressure-resistant resin was prepared, and the process up to (element characteristics) was performed in the same manner as in Example 1.
As a result, the electric field strength at which charge injection started was 2.8 MV / cm, and the withstand voltage was 5.9 MV / cm. The thickness of the low charge injection pressure resistant resin of the charged body was 20 nm.

(素子特性)
ドレイン電圧−10V(一定)で、ゲート電界強度を+0.9から−2.6MV/cmの間で掃引してドレイン電流を測定したところ、電流伝達特性曲線は、+0.9から−2.6MV/cmへ掃引した場合も、−2.6から+0.9MV/cmへ掃引した場合もほぼ一致した。それに対し、ゲート電界強度を+1.7から−5.0MV/cmの間で測定した場合、+1.7から−5.0MV/cmへ掃引した場合は、+0.9から−2.6MV/cmの間で掃引した電流伝達特性曲線とほぼ一致したが、−5.0から+1.7MV/cmへ掃引した場合には電流伝達特性曲線は大きく負にシフトした(図19)。すなわち、電荷注入の始まる2.8MV/cm以上の電界がかかったことでゲート絶縁膜(帯電体)に正の電荷が注入、保持され、閾値電圧が負の方向へシフトしたためである。
(Element characteristics)
When the drain current was measured by sweeping the gate electric field strength between +0.9 and −2.6 MV / cm at a drain voltage of −10 V (constant), the current transfer characteristic curve was +0.9 to −2.6 MV. In the case of sweeping to / cm, the case of sweeping from -2.6 to +0.9 MV / cm was almost the same. On the other hand, when the gate electric field strength is measured between +1.7 and −5.0 MV / cm, when swept from +1.7 to −5.0 MV / cm, +0.9 to −2.6 MV / cm However, when the current transfer characteristic curve was swept from -5.0 to +1.7 MV / cm, the current transfer characteristic curve was greatly shifted to a negative value (FIG. 19). That is, when an electric field of 2.8 MV / cm or more at which charge injection starts is applied, positive charges are injected and held in the gate insulating film (charged body), and the threshold voltage is shifted in the negative direction.

(実施例5)
(高電荷注入耐圧樹脂の溶液調整)
高電荷注入耐圧樹脂の溶液として実施例1の低電荷注入耐圧樹脂の溶液を、溶液濃度12質量%で調製して用いた。
(低電荷注入耐圧樹脂の溶液調製)
エポキシ変性シリコーン(信越シリコーン株式会社製)2.4g、ビスフェノールA型ノボラック(CZ256A:大日本インキ化学工業株式会社製)1.0gを、2−エチル−4−メチルイミダゾール(2E4MZ:四国化成工業株式会社製)1質量%のアニソール溶液0.34gを、アニソール16.3gに溶解させて(樹脂濃度17質量%)、低電荷注入耐圧樹脂の溶液を調整した。実施例1と同様に絶縁特性測定を実施した(図20)。結果、電荷注入の始まる電界強度は0.1MV/cm、絶縁耐圧は1.5MV/cmであった。
(Example 5)
(Solution adjustment of high charge injection pressure resistant resin)
The solution of the low charge injection pressure resistant resin of Example 1 prepared at a solution concentration of 12% by mass was used as the solution of the high charge injection pressure resistant resin.
(Preparation of low charge injection pressure resistant resin solution)
2.4 g of epoxy-modified silicone (manufactured by Shin-Etsu Silicone Co., Ltd.) and 1.0 g of bisphenol A type novolak (CZ256A: Dainippon Ink and Chemicals Co., Ltd.) were added to 2-ethyl-4-methylimidazole (2E4MZ: Shikoku Kasei Kogyo Co., Ltd.) (Company) 0.34 g of 1% by mass anisole solution was dissolved in 16.3 g of anisole (resin concentration: 17% by mass) to prepare a low charge injection pressure-resistant resin solution. Insulation characteristics were measured in the same manner as in Example 1 (FIG. 20). As a result, the electric field strength at which charge injection started was 0.1 MV / cm, and the withstand voltage was 1.5 MV / cm.

(メモリ素子形成)
Crを50nm蒸着したシリコンウエハ上に高電荷注入耐圧樹脂の溶液をメンブランフィルタを透過した後滴下し、スピンコータにより、500rpm、5秒、2000rpm、60秒の条件でスピンコートした。その後、100℃のホットプレート上で10分間乾燥し、さらに、200℃のホットプレート上で15分間硬化した。触針式表面形状測定装置にて測定した樹脂膜厚は226nmであった。次に、高電荷注入耐圧樹脂をコートしたCr蒸着シリコンウエハに低電荷注入耐圧樹脂の溶液をメンブランフィルタを透過した後滴下し、スピンコータにより、500rpm、5秒、2000rpm、60秒の条件でスピンコートした。触針式表面形状測定装置にて測定した樹脂膜厚から、高電荷注入耐圧樹脂の厚みを差分して求めた低電荷注入耐圧樹脂の膜厚は252nmであった。
以降、実施例1と同様に半導体層と電極を形成してデバイスを得た。
(Memory element formation)
A high charge injection pressure-resistant resin solution was dropped on a silicon wafer on which Cr was deposited to 50 nm after passing through a membrane filter, and spin-coated with a spin coater under conditions of 500 rpm, 5 seconds, 2000 rpm, and 60 seconds. Then, it dried for 10 minutes on a 100 degreeC hotplate, and also hardened | cured for 15 minutes on a 200 degreeC hotplate. The resin film thickness measured with a stylus type surface shape measuring apparatus was 226 nm. Next, the solution of the low charge injection pressure resistant resin is dropped on the Cr-deposited silicon wafer coated with the high charge injection pressure resistant resin after passing through the membrane filter, and spin coated with a spin coater under the conditions of 500 rpm, 5 seconds, 2000 rpm, and 60 seconds. did. The film thickness of the low charge injection pressure resistant resin obtained by subtracting the thickness of the high charge injection pressure resistant resin from the resin film thickness measured by the stylus type surface shape measuring apparatus was 252 nm.
Thereafter, a semiconductor layer and an electrode were formed in the same manner as in Example 1 to obtain a device.

(素子特性)
実施例1と同様にデバイス特性を測定した。
ドレイン電圧−10V(一定)にてゲート電界強度を0から−1MV/cmの範囲で掃引してデバイス特性を測定したところ、図21のようにゲート電界強度を0から−1.0 MV/cmへ掃引した場合より、−1.0から0MV/cmへ掃引した場合の伝達特性曲線は大きく負にシフトした。すなわち、電荷注入の始まる0.1MV/cm以上の電界強度で、帯電体に電荷が蓄積した。
(Element characteristics)
Device characteristics were measured in the same manner as in Example 1.
When the gate electric field strength was swept in the range of 0 to -1 MV / cm at a drain voltage of -10 V (constant), and the device characteristics were measured, the gate electric field strength was changed from 0 to -1.0 MV / cm as shown in FIG. The transfer characteristic curve in the case of sweeping from -1.0 to 0 MV / cm was greatly shifted to a negative value compared with the case of sweeping to. That is, electric charges accumulated in the charged body with an electric field strength of 0.1 MV / cm or more at which charge injection started.

(比較例1)
厚さ100nmの熱酸化膜を有する高ドープシリコンウエハ(直径50mm、厚み280μm、タイプN、抵抗率0.002〜0.004Ω・cm、片面鏡面研磨、株式会社KNプラッツ製)をOプラズマアッシャーで250W、5分処理後、ヘキサメチルジシラザン(シグマアルドリッチ社製)を加熱ガス化した気流中で15分間保持し、表面をメチル化した。その後、ペンタセンの蒸着以降は実施例1と同様に(素子特性)まで実施した。
(Comparative Example 1)
A highly doped silicon wafer (diameter 50 mm, thickness 280 μm, type N, resistivity 0.002 to 0.004 Ω · cm, single-side mirror polishing, manufactured by KN Platz Co., Ltd.) having a thermal oxide film of 100 nm thickness is O 2 plasma asher After treatment at 250 W for 5 minutes, hexamethyldisilazane (manufactured by Sigma-Aldrich) was held for 15 minutes in a gas stream heated and gasified to methylate the surface. Then, after vapor deposition of pentacene, it implemented to (element characteristic) like Example 1. FIG.

(素子特性)
ゲート電界強度を+2から−6MV/cm、ドレイン電圧−10V(一定)でデバイス特性を測定し、閾値電圧を求めた。電流伝達特性曲線を図22に示した。−6MV/cm印荷前後の閾値電圧は+3.3Vおよび+3.5Vでほとんど変化無く、電荷の注入による帯電体としての動作は見られなかった。
(Element characteristics)
The device characteristics were measured at a gate electric field strength of +2 to −6 MV / cm and a drain voltage of −10 V (constant), and a threshold voltage was obtained. The current transfer characteristic curve is shown in FIG. The threshold voltages before and after −6 MV / cm imprinting were almost unchanged at +3.3 V and +3.5 V, and no operation as a charged body due to charge injection was observed.

1‥高電界により電荷注入が生じ,微小電流が流れる領域
2‥絶縁破壊
11、21、31、41、51、61、71、81、91‥基板
12、22、32、42、52、62、72、82、82’、92、92’‥ゲート電極
13、23、33、43、53、63、73、83、83’、93、93’‥低電荷注入耐圧材料又は高電荷注入耐圧材料
14、24、34、44、54、64、74、84、84’、94、94’‥高電荷注入耐圧材料又は低電荷注入耐圧材料
15、25、35、45、55、65、75、85、95‥半導体層
16、17、26、27、36、37、46、47、56、57、66、67、76、77、86、87、96、97‥ソース-ドレイン電極
DESCRIPTION OF SYMBOLS 1 ... Area | region where electric charge injection arises by a high electric field, and a minute electric current flows 2 ... Dielectric breakdown 11, 21, 31, 41, 51, 61, 71, 81, 91 ... Substrate 12, 22, 32, 42, 52, 62, 72, 82, 82 ′, 92, 92 ′... Gate electrodes 13, 23, 33, 43, 53, 63, 73, 83, 83 ′, 93, 93 ′... Low charge injection withstand voltage material or high charge injection withstand voltage material 14 24, 34, 44, 54, 64, 74, 84, 84 ′, 94, 94 ′... High charge injection withstand voltage material or low charge injection withstand voltage material 15, 25, 35, 45, 55, 65, 75, 85, 95. Semiconductor layer 16, 17, 26, 27, 36, 37, 46, 47, 56, 57, 66, 67, 76, 77, 86, 87, 96, 97 Source-drain electrode

Claims (8)

電荷注入が生じる電界強度(以降、電荷注入耐圧)および絶縁耐圧がそれぞれECIおよびEBHである絶縁体(以下,高電荷注入耐圧材料)と、その電荷注入耐圧ECI,LがECI < EClの関係にある絶縁体(以下、低電荷注入耐圧材料)の二種類の絶縁体を積層した絶縁物で、高電荷注入耐圧材料と低電荷注入耐圧材料のそれぞれに接し離れた2枚の電極にECI < |E| < EBH の電界強度で電圧を印加して低電荷注入耐圧材料側から電荷を絶縁体内に注入して帯電させる帯電体であって、前記高電荷注入耐圧材料と低電荷注入耐圧材料の少なくとも一方が有機高分子で構成されることを特徴とする帯電体。 Charge injection occurs field strength (hereinafter, charge injection tolerance) and dielectric breakdown voltage respectively E CI, insulators are H and E BH (hereinafter, high charge injection withstand material) and their charge injection withstand E CI, L is E An insulator in which two types of insulators of CI , L < ECl , H (hereinafter referred to as a low charge injection withstand voltage material) are laminated, and each of the high charge injection withstand voltage material and the low charge injection withstand voltage material is provided. A charged body in which a voltage is applied to two electrodes in contact with each other at an electric field strength of E CI , L <| E | < EBH , and charges are injected into the insulator from the low charge injection withstand voltage material side and charged. A charged body , wherein at least one of the high charge injection withstand voltage material and the low charge injection withstand voltage material is composed of an organic polymer . 前記のECIとECIの比(ECI/ECI)が、1.5〜1000であり、ECIが0.01MV/cm以上である請求項1に記載の帯電体。 Said E CI, H and E CI, the ratio of L (E CI, H / E CI, L) is a 1.5 to 1,000, according to claim 1 E CI, L is 0.01 MV / cm or more The charged body described in 1. 前記、高電荷注入耐圧材料の絶縁耐圧(EBH)が、0.1MV/cm以上で、高電荷注入耐圧材料および低電荷注入耐圧材料の0.5MV/cmにおける体積抵抗率がそれぞれ1011Ω・m以上である請求項1または請求項2に記載の帯電体。 The dielectric breakdown voltage (E BH ) of the high charge injection breakdown voltage material is 0.1 MV / cm or more, and the volume resistivity at 0.5 MV / cm of the high charge injection breakdown voltage material and the low charge injection breakdown voltage material is 10 11 Ω, respectively. The charged body according to claim 1, wherein the charged body is m or more. 前記低電荷注入耐圧材料および/または高電荷注入耐圧材料が、3次元架橋高分子材料である請求項1〜請求項のいずれかに記載の帯電体。 Charged body according to any one of said low charge injection withstand voltage materials and / or high charge injection withstand voltage materials, claims 1 to 3 is a three-dimensional crosslinked polymeric material. 前記3次元架橋高分子材料が、湿式工程によって形成されたものである請求項に記載の帯電体。 The charged body according to claim 4 , wherein the three-dimensional crosslinked polymer material is formed by a wet process. 湿式工程が、ディップコーティング、スピンコーティング、スプレーコーティング、ロールコーティング、インクジェットコーティング、オフセットコーティング、インクジェット印刷、転写法、オフセット印刷、スクリーン印刷、凸版印刷、凹版印刷、ソフトリソグラフ、又はディスペンサ印刷から選ばれる請求項に記載の帯電体。 Claims wherein the wet process is selected from dip coating, spin coating, spray coating, roll coating, inkjet coating, offset coating, inkjet printing, transfer method, offset printing, screen printing, letterpress printing, intaglio printing, soft lithography, or dispenser printing Item 6. A charged body according to Item 5 . ゲート絶縁膜を挟んでゲート電極と半導体層があり、その半導体層に接してソース−ドレイン電極を有する電界効果トランジスタにおいて、ゲート絶縁膜が請求項1〜のいずれかに記載の帯電体で、帯電体に注入される電荷量により電界効果トランジスタの閾値電圧を制御することを特徴とした電界効果トランジスタ。 In the field effect transistor which has a gate electrode and a semiconductor layer on both sides of a gate insulating film and has a source-drain electrode in contact with the semiconductor layer, the gate insulating film is the charged body according to any one of claims 1 to 6 , A field effect transistor characterized in that a threshold voltage of a field effect transistor is controlled by an amount of charge injected into a charged body. 請求項に記載の電界効果トランジスタにおいて、帯電体内に保持された注入電荷量により情報を記録し、ECI>|E|のゲート電界強度下でのドレイン電流量の差として情報を呼び出すことを特徴としたメモリ素子。 8. The field effect transistor according to claim 7 , wherein information is recorded by an injected charge amount held in the charged body, and the information is called as a difference in drain current amount under a gate field intensity of E CI , L > | E |. A memory element characterized by that.
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