JP5692439B1 - Optical phase locked loop circuit and optical phase locked method - Google Patents

Abstract

Frequency discrimination is performed stably without using a digital filter. A demodulating unit that generates an I-axis signal and a Q-axis signal by demodulating an optical phase-modulated signal that is a binary phase-modulated signal using local oscillation light, and sin2θk from the I-axis signal and the Q-axis signal. A phase error signal including the information of, a digital processing unit that generates a phase modulation component signal including the information of sin (ω0tk + 2θk), a phase error θ included in the phase error signal, and a phase error θ included in the phase modulation component signal And a local oscillation light generation unit that generates the local oscillation light based on the local oscillation control signal. [Selection] Figure 1

Description

  The present invention relates to an optical phase locked loop circuit and an optical phase locked method suitable for use in coherent optical communication.

  Along with the recent increase in capacity of optical communication, coherent communication using phase modulation and the like, which can easily improve bandwidth utilization efficiency by multi-leveling as compared to conventional intensity modulation, has attracted attention. In communication using phase modulation, information is superimposed on the phase and transmitted.

  As a reception method in coherent communication, there are a reception method using homodyne detection and a reception method using heterodyne detection. In homodyne detection, local oscillation light having the same frequency and phase as the carrier wave of the phase-modulated reception signal is generated at the receiving end, and demodulation is performed by causing interference between the carrier wave of the reception signal and the local oscillation light. In heterodyne detection, a carrier wave of a phase-modulated received signal and a local oscillation light slightly different in frequency are generated at the receiving end, and the carrier wave of the reception signal and the local oscillation light are interfered to perform down-conversion and demodulation. . Both homodyne detection and heterodyne detection can be realized by using a phase synchronization circuit of the received signal and the local oscillation light.

  In order to demodulate a phase shift keying (PSK) signal using such a phase synchronization technique, the PSK signal does not include the spectrum component of the carrier wave. Therefore, the carrier wave of the received signal that is a PSK signal and the local oscillation light A means for extracting the phase error is required. As a means for extracting this phase error, a multiplication method and a Costas loop are known.

  For example, in a binary phase shift keying (BPSK) signal, phase modulation is performed with a binary value whose phase is shifted by π with respect to the carrier wave. When a multiplication method that simply multiplies the carrier wave is used, for example, in the case of double multiplication, the phase 0 or π of the carrier wave is doubled to appear as 0 or 2π. Due to the periodicity of the trigonometric function, the waveform in each time slot has the same shape, and as a result, it is possible to extract a signal having a frequency twice the carrier wave. However, since a method for directly multiplying an optical signal has not been established, it is difficult to apply the multiplying method to an optical signal.

  In the case of the Costas loop disclosed in Non-Patent Document 1, it is possible to extract twice the phase error between the carrier wave and the local oscillation light. In this Costas loop, the I-axis signal is sin (θ + d) and the Q-axis signal is −cos (θ + d). Here, θ represents a phase error between the carrier wave of the received signal and the local oscillation light. Further, d represents a data string and takes π / 2 or −π / 2 for each time slot. When these are multiplied, the change in the data string d is canceled and sin2θ is output. Therefore, this multiplication signal can be used as a control signal for the phase locked loop. In this case, feedback control is performed so that θ is zero.

  Non-Patent Document 2 or 3 discloses a Costas loop using an optical VCO (Voltage Controlled Oscillator) for generating local oscillation light. In the Costas loop, it is known that demodulation is difficult when the frequency difference between the carrier wave and the local oscillation light fluctuates with time. For example, when a semiconductor laser is used as a light source for signal light or local oscillation light, the fluctuation of both is generally several hundred Hz to several tens MHz (see, for example, Patent Document 1). In order to realize the frequency pull-in range required for stable operation of the optical phase-locked loop circuit, the operating band of each element constituting the circuit is required up to about several tens GHz. However, it is not easy to configure a circuit with each element satisfying these operating band requirements.

JP-A-11-133472

Y. Chiou and L. Wang, “Effect of Optical Amplifier Noise on Laser Linewidth Requirements in Long Haul Optical Fiber Communication Systems Witth of the World. 14, no. 10, pp. 2126-2134 (1996) Takahide Sakamoto et al. , “Real-Time Homedyne Reception of 40-Gb / s BPSK Signal by Digital Optical-Locked Loop” ECOC 2010, 19-23 September, 2010, Tori Tori Takahide Sakamoto et al. , “Digital Optical Phase Locked Loop for Real-Time Coherent Demolition of Multilevel PSK / QAM”, OSA / OFC / NFOEC 2010 OMS5. pdf

  Non-Patent Document 2 is a report in an experimental system, in which light waves output from the same light source are used for both in order to cancel out frequency fluctuations existing between a carrier wave and local oscillation light.

  However, in a real environment, a transmitter that generates signal light and a receiver that generates local oscillation light exist at different points. Therefore, it is difficult to apply the technique of Non-Patent Document 2 to an actual network.

  In Non-Patent Document 3, a frequency discriminator is used for the phase error extracted by digital arithmetic processing.

  However, in this case, the phase error signal becomes 0 V except for a slight offset when the phase synchronization is established. Generally, a frequency discriminator is used for a sine wave having a certain amplitude. With the method disclosed in Non-Patent Document 3, the average power of the phase error signal is small for frequency errors within a certain value, making it difficult to perform frequency discrimination stably.

  There is also a cross-product type frequency discriminator used for digital demodulation of a binary phase modulation (BPSK) signal or a quaternary phase modulation (QPSK: Quadrature Phase Shift Keying) signal.

  However, when this cross-product type frequency discriminator is used, it is necessary to insert a smoothing filter such as a digital filter before the frequency discriminator in order to reduce noise. For example, when a finite impulse response (FIR) filter is used as a digital filter, multiplication processing and addition processing proportional to the number of taps are required, so that processing time due to digital computation becomes obvious, and loop propagation delay time Will increase. In a phase locked loop circuit, it is known that demodulation performance deteriorates when the loop propagation delay time increases. For this reason, it is not desirable to use a digital filter in the phase-locked loop circuit.

  The present invention has been made in view of the above-described problems. An object of the present invention is to provide an optical phase-locked loop circuit and an optical phase-locking method capable of stably performing frequency discrimination without using a digital filter.

In order to achieve the above-described object, the optical phase-locked loop circuit according to the present invention demodulates an optical phase modulation signal, which is a binary phase modulation signal, using local oscillation light to generate an I-axis signal and a Q-axis signal. a demodulator for, from the I-axis signal and the Q-axis signal, and a digital processor for generating a phase-modulated component signal comprising a phase error signal containing information Sin2shita _k, the information of _{sin (ω 0 t k + 2θ} k), Based on the phase error θ _k included in the phase error signal and the time differential of the phase error θ _k included in the phase modulation component signal, a filter unit that generates a local oscillation control signal, and the local oscillation light based on the local oscillation control signal And a local oscillation light generation unit for generating

Further, the optical phase synchronization method of the present invention includes a process of demodulating an optical phase modulation signal, which is a binary phase modulation signal, using local oscillation light to generate an I-axis signal and a Q-axis signal, from the Q-axis signal, a phase error signal containing information Sin2shita _k, and generating a phase-modulated component signal containing information _{sin (ω 0 t k + 2θ} k), the phase error theta _k included in the phase error signal , A process of generating a local oscillation control signal from the time differentiation of the phase error θ _k included in the phase modulation component signal, and a process of generating local oscillation light based on the local oscillation control signal.

Incidentally, when the optical phase modulation signal is quaternary phase modulation signal, the digital processing unit, the I-axis signal and the Q-axis signal, a phase error signal containing information _{sin4θ k, sin (ω 0 t} k + 4θ k ) Is generated.

According to the optical phase-locked loop circuit and the optical phase-locked method of the present invention, when the optical phase-modulated signal is a binary phase-modulated signal, the phase-modulated component signal including the information of sin (ω ₀ t _k + 2θ _k ) is generated. When the optical phase modulation signal is a quaternary phase modulation signal, a phase modulation component signal including information of sin (ω ₀ t _k + 4θ _k ) is generated separately from the phase error signal. By inputting this phase modulation component signal to the frequency discriminator, the time differential of the phase error θ _k corresponding to the time variation of the frequency can be obtained. If the frequency synchronization using the time derivative of the phase error theta _k, without using a digital filter, it is possible to perform stable frequency discriminator.

It is a schematic diagram for demonstrating schematically an optical phase locked loop circuit. It is a schematic diagram for demonstrating the sample hold circuit with which an optical phase locked loop circuit is provided. It is a schematic diagram for demonstrating a digital calculating part when an optical phase modulation signal is a BPSK signal. It is a schematic diagram for demonstrating a digital calculating part when an optical phase modulation signal is a QPSK signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the drawings are merely schematically shown to the extent that the present invention can be understood. In the following, a preferred configuration example of the present invention will be described, but it is merely a preferred example. Therefore, the present invention is not limited to the following embodiments, and many changes or modifications that can achieve the effects of the present invention can be made without departing from the scope of the configuration of the present invention. In each figure, the optical signal is indicated by a thick line, and the electric signal is indicated by a thin line.

(Outline of optical phase-locked loop circuit)
The outline of the optical phase-locked loop circuit according to the present invention will be described with reference to FIG. FIG. 1 is a schematic diagram for schematically explaining an optical phase-locked loop circuit.

  The optical phase-locked loop circuit 10 includes a demodulation unit 100, a digital processing unit 200, a filter unit 300, a local oscillation light generation unit 400, a clock signal generation unit 500, and first and second delay units 550-1 and 550-2. It is configured with.

  For example, a binary phase modulation (BPSK) signal or a quaternary phase modulation (QPSK) signal is input to the optical phase locked loop circuit 10 as an optical phase modulation signal (indicated by an arrow S10 in the figure).

  The optical phase modulation signal S10 input to the optical phase locked loop circuit 10 is sent to the demodulator 100. Further, local oscillation light (indicated by an arrow S400 in the figure) generated by the local oscillation light generation unit 400 is input to the demodulation unit 100. The demodulator 100 generates an I-axis signal and a Q-axis signal from the input optical phase modulation signal S10 and the local oscillation light S400. The demodulator 100 outputs the generated I-axis signal and Q-axis signal as demodulated signals and sends them to the digital processing unit 200.

  The digital processing unit 200 generates a phase error signal and a phase modulation component signal from the I-axis signal and the Q-axis signal.

When the optical phase modulation signal S10 is a BPSK signal, in this optical phase-locked loop circuit 10, the I-axis signal is sin (θ _k + d _k ) and the Q-axis signal is −cos (θ _k + d _k ). Here, θ _k represents a phase error between the carrier wave of the received signal and the local oscillation light. D _k represents a data string and takes π / 2 or −π / 2 for each time slot. When these are multiplied, the change in the data string d _k is canceled and sin 2θ _k is output. By using the phase error signal S260-1 as a feedback control signal, a phase locked loop for BPSK can be configured. The phase error signal S260-1 generated by the digital processing unit 200 is sent to the filter unit 300. The phase modulation component signal S260-2 is given by sin (ω ₀ t _k + 2θ _k ) and sent to the filter unit 300.

When the optical phase modulation signal S10 is a QPSK signal, the data string d _k is d _k = kπ / 2 (k = 0, 1, 2, 3). Accordingly, the phase error signal S260-1 is the sin4θ _k. By using this phase error signal as a feedback control signal, a phase locked loop for QPSK can be configured. The phase error signal S260-1 generated by the digital processing unit 200 is sent to the filter unit 300. Further, the phase modulation component signal S260-2 is given by sin (ω ₀ t _k + 4θ _k ) and sent to the filter unit 300.

Filter unit 300, the phase error theta _k included in the phase error signal S260-1, the time derivative of the phase error theta _k included in the phase modulated component signal S260-2 obtained by using a frequency discriminator, a local oscillator A control signal (indicated by an arrow S300 in the figure) is generated. The filter unit 300 forms a phase locked loop using the phase error signal and a frequency locked loop using the phase modulation component signal.

  The local oscillation light generator 400 is a means for generating the local oscillation light S400 based on the local oscillation control signal S300, and functions as an optical voltage controlled oscillator (optical VCO). In this local oscillation light generation unit 400, the phase or frequency of the local oscillation light S400 is set based on the local oscillation control signal S300.

(Optical phase-locked loop circuit)
A configuration example of the optical phase locked loop circuit of the present invention will be described with reference to FIGS. FIG. 2 is a schematic diagram for explaining a sample hold circuit included in the optical phase locked loop circuit.

  The demodulator 100 includes a 90 ° hybrid coupler 120 and first and second balance detectors 122-1 and 122-2.

  The 90 ° hybrid coupler 120 that is an interference signal generation unit can be configured in the same manner as in Non-Patent Document 2, and includes first and second beam combiners and a 90 ° phase shifter. The first and second beam combiners and the 90 ° phase shifter are not shown.

  The optical phase modulation signal S10 input as the reception signal is branched into two, one is sent to the 90 ° hybrid coupler 120 (indicated by an arrow S12 in the figure), and the other is sent to the clock signal generator 500 (in the figure). , Indicated by arrow S14). The optical phase modulation signal S12 and the local oscillation light S400 generated by the local oscillation light generation unit 400 are input to the 90 ° hybrid coupler 120 in a state where the polarization planes coincide. The 90 ° hybrid coupler 120 causes the optical phase modulation signal S12 and the local oscillation light S400 to interfere with each other to generate the first interference signal S120-1 and the second interference signal S120-2 that reflect the phase error between the two signals. To do. In order to make the polarization planes of the optical phase modulation signal S12 and the local oscillation light S400 input to the 90 ° hybrid coupler 120 coincide with each other, a conventionally known polarization plane controller can be used. Omitted.

  The first beam combiner combines the optical phase modulation signal S12 and the local oscillation light S400 to obtain these sum and difference components as the first interference signal S120-1. The second beam combiner combines the optical phase modulation signal S12 and the optical signal obtained by phase shifting the local oscillation light S400 by π / 2 (90 °) to thereby generate the second interference signal S120-2. To obtain these sum and difference components.

  The first interference signal S120-1 and the second interference signal S120-2 generated by the 90 ° hybrid coupler 120 are sent to the first and second balance detectors 122-1 and 122-2, respectively.

  The first balance detector 122-1 includes two photodetectors inside. The first balance detector 122-1 photoelectrically converts the sum component and the difference component included in the first interference signal S120-1, respectively, and then subtracts the difference component photoelectric conversion signal from the sum component photoelectric conversion signal. The signal is generated as a first modulated electrical signal S122-1.

  The second balance detector 122-2 includes two photodetectors inside. The second balance detector 122-2 photoelectrically converts the sum component and difference component included in the second interference signal S120-2, and then subtracts the difference component photoelectric conversion signal from the sum component photoelectric conversion signal. The signal is generated as a second modulated electrical signal S122-2.

  In the following description, the first modulated electrical signal S122-1 may be referred to as an I-axis signal, and the second modulated electrical signal S122-2 may be referred to as a Q-axis signal.

  The I-axis signal S122-1 is branched into two, one of which is output as the demodulated signal S124-1 from the optical phase-locked loop circuit 10, and the other is sent to the digital processing unit 200 (in the figure, indicated by an arrow S126-1). Show). The Q-axis signal S122-2 is branched into two, one of which is output from the optical phase-locked loop circuit 10 as the demodulated signal S124-2, and the other is sent to the digital processing unit 200 (in the figure, the arrow S126). -2). If the optical phase modulation signal S10 is a BPSK signal, the Q-axis signal may not be output from the optical phase locked loop circuit 10.

  The digital processing unit 200 includes first and second sample and hold circuits 230-1 and 230-2, first and second analog-digital converters (A / D) 240-1 and 240-2, and a digital arithmetic unit. 250, and first and second digital-analog converters (D / A) 260-1 and 260-2.

  The first sample hold circuit 230-1 holds the intensity of the I-axis signal S126-1 for a predetermined period. The period held by the first sample-and-hold circuit 230-1 is determined corresponding to the cycle T of the clock signal S500 generated by the clock signal generation unit 500.

  Here, the first sample hold circuit 230-1 will be described with reference to FIG. The sample hold circuit 230-1 in this configuration example includes a first buffer 232, a second buffer 236, a capacitor 238, and a switch 234. The switch 234 opens and closes in accordance with the period T of the clock signal, whereby the voltage corresponding to the signal strength is held in the capacitor 238 for a period determined by the period T. Note that the sample hold circuit 230-1 only needs to have a function of holding the intensity for a predetermined period, and is not limited to this configuration example. The second sample and hold circuit 230-2 as the second intensity holding means can be configured in the same manner as the first sample and hold circuit 230-1, and thus the description thereof is omitted.

  The first and second sample and hold circuits 230-1 and 230-2 respectively hold the intensities of the I-axis signal and the Q-axis signal for a predetermined period, that is, the first intensity hold signal S230-1 that has been sampled and held. And a second intensity holding signal S230-2. The first and second intensity holding signals S230-1 and S230-2 are sent to the first and second A / D 240-1 and 240-2 and subjected to AD conversion. The first and second intensity holding signals S <b> 230-1 and S <b> 230-2 that have been subjected to AD conversion are sent to the digital calculation unit 250. The digital calculation unit 250 generates a phase error signal S260-1 and a phase modulation component signal S260-2 from the first and second intensity holding signals S230-1 and S230-2. The phase error signal S260-1 is sent to the filter unit 300 after being DA-converted by the first D / A 260-1. The phase modulation component signal S260-2 is sent to the filter unit 300 after being DA-converted by the second D / A 260-2. The configuration of the digital arithmetic unit 250 will be described later.

Next, the filter unit 300 will be described. Filter unit 300, as described above, from the phase error theta _k included in the phase error signal S260-1, the time derivative of the phase error theta _k included in the phase modulated component signals S260-2, the local oscillation control signal S300 Is generated.

  The filter unit 300 includes first and second loop filters 320 and 330, a smoothing filter 322, a frequency discriminator 324, and an adder 340. The phase error signal S260-1 DA-converted by the first D / A 260-1 is sent to the adder 340 through the first loop filter 320. The first loop filter 320 functions as a loop filter of a phase locked loop.

In addition, the phase modulation component signal S260-2 DA-converted by the second D / A 260-2 is sent to the adder 340 via the smoothing filter 322, the frequency discriminator 324, and the second loop filter 330. When the phase modulation component signal S260-2 is input to the frequency discriminator 324 having the center frequency ω ₀ , an output corresponding to the time differentiation of θ _k is obtained. The smoothing filter 322, the frequency discriminator 324, and the second loop filter 330 are components of a frequency locked loop that suppresses frequency fluctuations.

  The adder 340 adds the outputs of the first and second loop filters 320 and 330 to generate a local oscillation control signal S300. Adding the output of the first loop filter 320 and the output of the second loop filter 330 corresponds to adding a frequency locked loop to the phase locked loop. The local oscillation control signal S300 generated by the adder 340 is sent to the local oscillation light generation unit 400.

  Next, the local oscillation light generation unit 400 will be described. The local oscillation light generation unit 400 includes a voltage controlled oscillator (VCO) 410, a light source 420, and a modulator 430. The VCO 410 changes its own oscillation frequency fVCO according to the local oscillation control signal S300 and generates the oscillation signal S410. The light source 420 is a so-called continuous light source (CW light source) that generates continuous light S420 having a carrier frequency f0 of the optical phase modulation signal S10. The modulator 430 modulates the continuous light S420 according to the oscillation signal S410 generated by the VCO 410 to obtain a local oscillation light S400. The local oscillation light S400 generated by the local oscillation light generation unit 400 is sent to the 90 ° hybrid coupler 120.

  Here, as the modulator 430, for example, a single side band (SSB) modulator can be used. The SSB modulator is a modulator that outputs only a single sideband. For this reason, the use of the SSB modulator eliminates the need for a bandpass filter that removes excess sidebands. Note that a Mach-Zehnder type intensity modulator may be used as the modulator 430, and an optical bandpass filter may be provided.

  The clock signal generation unit 500 includes a 1-bit delay interferometer 510, a photoelectric converter 520, a clock extractor 530, and a frequency divider 540.

  The 1-bit delay interferometer 510 divides the optical phase modulation signal S14 into two, delays one of them and then causes interference to generate a 1-bit delayed interference signal S510. At the time of interference, if the phase error between the two is 0, they are strengthened, and if π, they are weakened. As a result, the 1-bit delayed interference signal S510 is generated as a signal similar to the light intensity modulation signal.

  The photoelectric converter 520 photoelectrically converts the 1-bit delayed interference signal S510 to generate a delayed interference electrical signal S520.

  The clock extractor 530 extracts a clock S530 having a period Ts from the delayed interference electric signal S520.

  The frequency divider 540 divides the clock S530 having the period Ts extracted by the clock extractor 530 to generate the clock signal S500 having the period T. The period T of the clock signal S500 defines the holding period in the sample and hold circuit 230. Therefore, by dividing the frequency, a frequency that can be processed by the digital calculation unit 250 is obtained. Since the fluctuation component of the phase error may be about several MHz, the frequency of the clock signal S500 is preferably sufficiently higher than this.

  It should be noted that each component of the clock signal generation unit 500 can be any suitably known one.

  The clock signal S500 is branched into two, and one (indicated by an arrow S500-1 in the figure) is sent to the first delay device 550-1, and the other (indicated by an arrow S500-2 in the figure) is the first. 2 to the second delay unit 550-2. The clock signals S550-1 and S550-2, the timings of which are adjusted by the first and second delay units 550-1 and 550-2, respectively, are the first and second sample and hold circuits 230-1 and 230-2. Sent to.

  Note that the configurations of the demodulation unit 100, the local oscillation light generation unit 400, and the clock signal generation unit 500 are not limited to the above-described configurations, and may be configured as any suitable conventional one.

(Digital operation part of 1st Embodiment)
With reference to FIG. 3, the digital arithmetic unit when the optical phase modulation signal is a BPSK signal will be described. FIG. 3 is a schematic diagram for explaining a digital operation unit when the optical phase modulation signal is a BPSK signal among the digital processing units included in the optical phase locked loop circuit.

  The digital calculation unit 600 includes first and second square calculators 602 and 604, first to third adders 612, 614 and 616, first to third multipliers 622, 624 and 626, first and first. 2 dividers 642 and 644, and a double calculator 630.

  The first intensity holding signal having the I-axis component is branched into two, and one is sent to the first square calculator 602 and the other is sent to the first multiplier 622. The second intensity holding signal having the Q-axis component is branched into two, one is sent to the second square calculator 604 and the other is sent to the first multiplier 622.

The first square calculator 602 performs a square calculation on the first intensity holding signal having the I-axis component. Since the first intensity holding signal is represented by Kd _k sin θ _k , the output of the first square calculator 602 is K ² sin ² θ _k . The output of the first square calculator 602 is sent to the first and second adders 612 and 614. Here, K represents the gain of the optical phase-locked loop circuit, for example. Here, it is assumed that d _k ² = 1.

The second square calculator 604 performs a square operation on the second intensity holding signal having the Q-axis component. Since the second intensity holding signal is represented by Kd _k cos θ _k , the output of the second square calculator 604 is K ² cos ² θ _k . The output of the second square calculator 604 is sent to the first and second adders 612 and 614.

The first adder 612 inverts the sign of the output of the first square calculator 602 and adds it with the output of the second square calculator 604. Since the output of the first square calculator 602 is K ² sin ² θ _k and the output of the second square calculator 604 is K ² cos ² θ _k , the output of the first adder 612 is , K ² cos ² θ _k −K ² sin ² θ _k = K ² cos 2θ _k . The output of the first adder 612 is sent to the first divider 642.

The second adder 614 adds the output of the first square calculator 602 and the output of the second square calculator 604. Since the output of the first square calculator 602 is K ² sin ² θ _k and the output of the second square calculator 604 is K ² cos ² θ _k , the output of the second adder 614 is , K ² cos ² θ _k + K ² sin ² θ _k = K ² . The output of the second adder 614 is sent to the first divider 642 and the second divider 644.

The first multiplier 622 calculates the product of the first intensity holding signal having the I-axis component and the second intensity holding signal having the Q-axis component. The output of the first multiplier 622 is Kd _k sin θ _k * Kd _k cos θ _k = K ² sin 2θ _k / 2. The output of the first multiplier 622 is sent to the double calculator 630.

The double calculator 630 doubles the output of the first multiplier 622. Since the output of the first multiplier 622 is K ² sin2θ _k / 2, the output of the doubling calculator 630 is K ² sin2θ _k . The output of the double calculator 630 is sent to the second divider 644.

The first divider 642 divides the output of the first adder 612 by the output of the second adder 614. That is, the output of the first divider 642 is K ² cos 2θ _k / K ² = cos 2θ _k . The output of the first divider 642 is sent to the second multiplier 624.

The second divider 644 divides the output of the double calculator 630 by the output of the second adder 614. That is, the output of the second divider 644 is K ² sin2θ _k / K ² = sin2θ _k . The output of the second divider 644 is branched into two, one being sent to the third multiplier 626 and the other being outputted as a phase error signal. This phase error signal is sent to the first D / A 260-1.

The second multiplier 624 multiplies the output of the first divider 642 and sin ω ₀ t _k . The third multiplier 626 multiplies the output of the second divider 644 and cosω ₀ t _k . Here, ω ₀ is the frequency of the sine wave or cosine wave to be multiplied, and is sufficiently smaller than the sampling rate. Also, sin ω ₀ t _k and cos ω ₀ t _k are orthogonal to each other. These sin ω ₀ t _k and cos ω ₀ t _k may be generated using any suitable oscillator.

The output of the second multiplier 624 is cos 2θ _k * sin ω ₀ t _k . Further, the output of the third multiplier 626 is sin 2θ _k * cos ω ₀ t _k . The output of the second multiplier 624 and the output of the third multiplier 626 are added by the third adder 616. That is, the output of the third adder 616, a _{cos2θ k * sinω 0 t k +} sin2θ k * cosω 0 t k = sin (ω 0 t k + 2θ k). The output of the third adder 616 is output as a phase modulation component signal. This phase modulation component signal is sent to the second D / A 260-2.

The configuration of the digital calculation unit is not limited to the above example. Any suitable configuration can be employed in which sin 2θ _k is generated as the phase error signal and sin (ω ₀ t _k + 2θ _k ) is generated as the phase modulation component signal.

  In this configuration example, the phase error signal and the phase modulation component signal are standardized by the first divider 642 and the second divider 644. For this reason, even when the intensity of the I-axis signal or the Q-axis signal fluctuates, such as when the gain of the optical phase-locked loop circuit fluctuates, the amplitude of the phase error signal or the phase modulation component signal is kept constant. For this reason, more stable phase loop synchronization and frequency loop synchronization can be realized.

  On the other hand, when the intensity fluctuation of the I-axis signal or the Q-axis signal does not become a problem, a configuration that does not standardize may be used. If not normalized, the second adder 614 and the first and second dividers 642 and 644 are not necessary.

(Digital operation part of 2nd Embodiment)
With reference to FIG. 4, a digital arithmetic unit when the optical phase modulation signal is a QPSK signal will be described. FIG. 4 is a schematic diagram for explaining a digital operation unit when the optical phase modulation signal is a QPSK signal among the digital processing units provided in the optical phase locked loop circuit.

  The digital arithmetic unit 700 includes first to fifth square calculators 702, 704, 706, 708 and 710, first to fourth adders 712, 714, 716 and 718, first to fourth multipliers 722, 724, 726 and 728, first and second dividers 742 and 744, and first and second ½ multipliers 732 and 734.

  The first intensity holding signal having the I-axis component is branched into two, and one is sent to the first square calculator 702 and the other is sent to the first multiplier 722. The second intensity holding signal having the Q-axis component is branched into two, one being sent to the second square calculator 704 and the other being sent to the first multiplier 722.

The first square calculator 702 performs a square calculation on the first intensity holding signal having the I-axis component. Since the first intensity holding signal is represented by K (d _1k cos θ _k −d _2k sin θ _k ), the output of the first square calculator 702 is K ² (1−d _1k d _2k sin 2θ _k ). Become. The output of the first square calculator 702 is sent to the first and second adders 712 and 714. Here, it is considered that d _1k ² = 1 and d _2k ² = 1.

The second square calculator 704 performs a square calculation on the second intensity holding signal having the Q-axis component. Since the second intensity holding signal is represented by K (d _1k sin θ _k + d _2k cos θ _k ), the output of the second squaring unit is K ² (1 + d _1k d _2k sin 2θ _k ). The output of the second square calculator 704 is sent to the first and second adders 712 and 714.

The first adder 712 inverts the sign of the output of the first square calculator 702 and adds it with the output of the second square calculator 704. Since the output of the first square calculator 702 is K ² (1-d _1k d _2k sin2θ _k ) and the output of the second square calculator 704 is K ² (1 + d _1k d _2k sin2θ _k ). The output of the first adder 712 is −K ² (1−d _1k d _2k sin 2θ _k ) + K ² (1 + d _1k d _2k sin 2θ _k ) = 2K ² d _1k d _2k sin 2θ _k . The output of the first adder 712 is sent to the second ½ multiplication unit 734 and the second multiplier 724.

The second adder 714 adds the output of the first square calculator 702 and the output of the second square calculator 704. Since the output of the first square calculator 702 is K ² (1-d _1k d _2k sin2θ _k ) and the output of the second square calculator 704 is K ² (1 + d _1k d _2k sin2θ _k ). The output of the second adder 714 is K ² (1−d _1k d _2k sin 2θ _k ) + K ² (1 + d _1k d _2k sin 2θ _k ) = 2K ² . The output of the second adder 714 is sent to the first ½ calculator 732. The output of the first 1/2 calculator 732 becomes K ² and is sent to the fifth square calculator 710. The output of the fifth square calculator 710 becomes K ⁴ and is sent to the first and second dividers 742 and 744.

The second 1/2 multiplication unit 734 multiplies the output of the first adder 712 by 1/2. Since the output of the first adder 712 is 2K ² d _1k d _2k sin 2θ _k , the output of the second ½ calculator 734 is K ² d _1k d _2k sin 2θ _k and the third 2 The result is sent to the multiplier 706.

The third square calculator 706 performs a square calculation on the output of the ½ multiplier 734. The output of the 1/2 calculator ^734, because it is _{K 2 d 1k d 2k sin2θ k} , the output of the third square operator ^706, K 4 ^sin 2 2 [Theta] _k becomes, the third adder 716 Sent.

The first multiplier 722 calculates a product of a first intensity holding signal having an I-axis component and a second intensity holding signal having a Q-axis component. The output of the first multiplier 722 is K (d _1k cos θ _k −d _2k sin θ _k ) * K (d _1k sin θ _k + d _2k cos θ _k ) = K ² d _1k d _2k cos 2θ _k . The output of the first multiplier 722 is sent to the second multiplier 724 and the fourth square calculator 708.

The second multiplier 724 multiplies the output of the first adder 712 and the output of the first multiplier 722. The output of the second multiplier 724 is 2K ² d _1k d _2k sin 2θ _k
* K ² d _1k d _2k cos 2θ _k = K ⁴ sin 4θ _k , which is sent to the first divider 742 and the fourth multiplier 728.

The first divider 742 divides the output of the second multiplier 724 by the output of the fifth square calculator 710. That is, the output of the first divider 742 is K ⁴ sin4θ / K ⁴ = sin4θ. The output of the first divider 742 is output as a phase error signal. This phase error signal is sent to the first D / A 260-1.

The fourth square calculator 708 performs a square calculation on the output of the first multiplier 722. Since the output of the first multiplier 722 is ^{_{K 2 d 1k d 2k cos2θ k}} , the output of the fourth square operator 708 ^is sent K 4 ^cos 2 2 [Theta] _k becomes, the third adder 716 .

The third adder 716 inverts the sign of the output of the third square calculator 706 and adds it with the output of the fourth square calculator 708. The output of the third adder 716 is −K ⁴ sin ² 2θ _k + K ⁴ cos ² 2θ _k = K ⁴ cos 4θ _k and is sent to the third multiplier 726.

The third multiplier 726 multiplies the output of the third adder 716 and sin ω ₀ t _k . The fourth multiplier 728 multiplies the output of the second multiplier 724 and cos ω ₀ t _k . Here, ω ₀ is the frequency of the sine wave or cosine wave to be multiplied, and is sufficiently smaller than the sampling rate. Also, sin ω ₀ t _k and cos ω ₀ t _k are orthogonal to each other. These sin ω ₀ t _k and cos ω ₀ t _k may be generated using any suitable oscillator.

The output of the third multiplier 726 is K ⁴ cos4θ * sinω ₀ t _k . The output of the fourth multiplier 728 is K ⁴ sin 4θ _k * cos ω ₀ t _k . The output of the third multiplier 726 and the output of the fourth multiplier 728 are added by the fourth adder 718. That is, the output of the fourth adder ^718, the _{K 4 cos4θ k * sinω 0 t} k + K 4 sin4θ k * cosω 0 t k = K 4 sin (ω 0 t k + 4θ k). The output of the fourth adder 718 is sent to the second divider 744.

The second divider 744 divides the output of the fourth adder 718 by the output of the fifth square calculator 710. That is, the output of the second divider 744 is K ⁴ sin (ω ₀ t _k + 4θ _k ) / K ⁴ = sin (ω ₀ t _k + 4θ _k ). The output of the second divider 744 is sent to the second D / A 260-2 as a phase modulation component signal.

The configuration of the digital calculation unit is not limited to the above example. Any suitable configuration may be employed in which sin 4θ _k is generated as the phase error signal and sin (ω ₀ t _k + 4θ _k ) is generated as the phase modulation component signal.

  Moreover, in this structural example, it is standardized by the 1st divider and the 2nd divider. For this reason, even when the intensity of the I-axis signal or the Q-axis signal fluctuates, such as when the gain of the optical phase-locked loop circuit fluctuates, the amplitude of the phase error signal or the phase modulation component signal is kept constant. For this reason, more stable phase loop synchronization and frequency loop synchronization can be realized.

  On the other hand, when the intensity fluctuation of the I-axis signal or the Q-axis signal does not become a problem, a configuration that does not standardize may be used.

As described above, according to the optical phase-locked loop circuit and the optical phase-locking method of the present invention, when the optical phase-modulated signal is a BPSK signal, the phase-modulated component including information of sin (ω ₀ t _k + 2θ _k ) When the optical phase modulation signal is a QPSK signal, a phase modulation component signal including information on sin (ω ₀ t _k + 4θ _k ) is generated separately from the phase error signal. By inputting this phase modulation component signal to the frequency discriminator, the time differential of the phase error θ _k corresponding to the time variation of the frequency can be obtained. If the frequency synchronization using the time derivative of the phase error theta _k, without using a digital filter, it is possible to perform stable frequency discriminator.

DESCRIPTION OF SYMBOLS 10 Optical phase-locked loop circuit 100 Demodulation part 120 90 degree hybrid coupler 122 Balance detector 200 Digital processing part 230 Sample hold circuit 232, 236 Buffer 234 Switch 238 Capacitor 240 Analog-digital converter (A / D)
250, 600, 700 Digital operation part 260 Digital-analog converter (D / A)
300 Filter unit 320, 330 Loop filter 322 Smoothing filter 324 Frequency discriminator 340 Adder 400 Local oscillation light generation unit
410 Voltage controlled oscillator (VCO)
420 light source 430 modulator 500 clock signal generator
510 1-bit delay interferometer 520 Photoelectric converter 530 Clock extractor 540 Frequency divider 550 Delay device 602, 604, 702, 704, 706, 708, 710 Square calculator 612, 614, 616, 712, 714, 716 718 Adder 622, 624, 626, 722, 724, 726, 728 Multiplier 630 Double calculator 642, 644, 742, 744 Divider 732, 734 1/2 multiplier

Claims (9)

A demodulator that demodulates an optical phase modulation signal that is a binary phase modulation signal using local oscillation light to generate an I-axis signal and a Q-axis signal;
From the I-axis signal and the Q-axis signal, a digital to generate the phase error signal including the information of Sin2shita _k the phase error theta _k, a phase-modulated component signal containing information _{sin (ω 0 t k + 2θ} k) A processing unit;
From the phase error theta _k included in the phase error signal, the time derivative of the phase error theta _k and included in the phase modulated component signals, and a filter unit for generating a local oscillation control signal,
An optical phase-locked loop circuit comprising: a local oscillation light generation unit that generates the local oscillation light based on the local oscillation control signal. The optical phase-locked loop circuit according to claim 1, wherein amplitudes of the phase error signal and the phase modulation component signal are standardized. The digital processing unit
A first square calculator that squares the I-axis signal converted into a digital signal;
A second square calculator that squares the Q-axis signal converted into a digital signal;
A first adder that inverts the sign of the output of the first square calculator and adds it to the output of the second square calculator;
A second adder for adding the output of the first square calculator and the output of the second square calculator;
A first multiplier for multiplying the I-axis signal converted into a digital signal by the Q-axis signal converted into a digital signal;
A doubling calculator for doubling the output of the first multiplier;
A first divider for dividing the output of the first adder by the output of the second adder;
A second divider for dividing the output of the doubling calculator by the output of the second adder;
A second multiplier for multiplying the output of the first divider by sin ω ₀ t _k ;
A third multiplier for multiplying the output of the second divider by cos ω ₀ t _k ;
A third adder for adding the output of the second multiplier and the output of the third multiplier to generate a phase modulation component signal;
The output of the second divider is branched into two, one is sent to the third multiplier, and the other is output from the digital processing unit as a phase error signal. Optical phase-locked loop circuit. A demodulator that demodulates an optical phase modulation signal that is a quaternary phase modulation signal using local oscillation light to generate an I-axis signal and a Q-axis signal;
From the I-axis signal and the Q-axis signal, and a digital processor for generating a phase-modulated component signal comprising a phase error signal containing information Sin4shita _k, the information of _{sin (ω 0 t k + 4θ} k),
From the phase error theta _k included in the phase error signal, the time derivative of the phase error theta _k and included in the phase modulated component signals, and a filter unit for generating a local oscillation control signal,
An optical phase-locked loop circuit comprising: a local oscillation light generation unit that generates the local oscillation light based on the local oscillation control signal. The optical phase-locked loop circuit according to claim 4, wherein amplitudes of the phase error signal and the phase modulation component signal are standardized. The digital processing unit
A first square calculator that squares the I-axis signal converted into a digital signal;
A second square calculator that squares the Q-axis signal converted into a digital signal;
A first adder that inverts the sign of the output of the first square calculator and adds it to the output of the second square calculator;
A second adder for adding the output of the first square calculator and the output of the second square calculator;
A second ½ times calculator for halving the output of the first adder;
A third squaring unit that performs a squaring operation on the output of the second halving unit;
A first multiplier that calculates a product of the I-axis signal converted into a digital signal and the Q-axis signal converted into a digital signal;
A second multiplier that multiplies the output of the first adder with the output of the first multiplier;
A first ½ times calculator for halving the output of the second adder;
A fifth squaring unit that performs a squaring operation on the output of the first ½ multiplier unit;
A first divider that divides the output of the second multiplier by the output of the fifth squaring operator to generate a phase error signal;
A fourth squaring operator that performs a squaring operation on the output of the first multiplier;
A third adder that inverts the sign of the output of the third square calculator and adds it to the output of the fourth square calculator;
A third multiplier for multiplying the output of the third adder by sin ω ₀ t _k ;
A fourth multiplier for multiplying the output of the second multiplier by cosω ₀ t _k ;
A fourth adder for adding the output of the third multiplier and the output of the fourth multiplier;
The second divider for generating a phase modulation component signal by dividing the output of the fourth adder by the output of the fifth square computing unit. Optical phase-locked loop circuit. A process of generating an I-axis signal and a Q-axis signal by demodulating an optical phase modulation signal, which is a binary phase modulation signal, using local oscillation light;
From the I-axis signal and the Q-axis signal, and generating a phase-modulated component signal comprising a phase error signal containing information Sin2shita _k, the information of _{sin (ω 0 t k + 2θ} k),
A phase error theta _k included in the phase error signal, and a time derivative of the phase error theta _k contained in the phase modulated component signal, and generating a local oscillation control signal,
And a step of generating the local oscillation light based on the local oscillation control signal. A process of demodulating an optical phase modulation signal that is a quaternary phase modulation signal using local oscillation light to generate an I-axis signal and a Q-axis signal;
From the I-axis signal and the Q-axis signal, and generating a phase-modulated component signal comprising a phase error signal containing information Sin4shita _k, the information of _{sin (ω 0 t k + 4θ} k),
A phase error theta _k included in the phase error signal, and a time derivative of the phase error theta _k contained in the phase modulated component signal, and generating a local oscillation control signal,
And a step of generating the local oscillation light based on the local oscillation control signal. 9. The optical phase synchronization according to claim 7, wherein amplitudes of the phase error signal and the phase modulation component signal are standardized in the process of generating the phase error signal and the phase modulation component signal. Method.

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