JP5688286B2 - Digital clock recovery circuit and semiconductor chip - Google Patents

Description

  The present invention relates to a clock recovery circuit and a semiconductor chip that recover a clock from a digital data reception signal on which a clock signal is superimposed.

  In recent years, an interface for performing high-speed serial transfer has been adopted in order to satisfy the demand for large-capacity and high-speed data transmission in a board, a chip, and the like. A clock for performing synchronization is superimposed on the serial signal. On the receiving side, the edge (signal transition) of the data signal is detected, and the clock (timing information) is restored by adjusting the phase of the internal DLL clock signal.

  A circuit that performs this clock restoration process is called a clock data recovery (CDR) circuit (hereinafter referred to as “CDR”). In a conventional CDR circuit, a PLL (Phase Locked Loop) circuit is generally used. Using a VCO (Voltage Controlled Oscillator) included in the PLL, the VCO transmission clock is controlled so as to be synchronized with the phase of the clock signal of the received signal, and used as a clock for reproducing the received signal.

N. Miura, K. Kasuga, M. Saito, and T. Kuroda, "An 8Tb / s 1pJ / b 0.8mm2 / Tb / s QDR Inductive-Coupling Interface Between 65nm CMOS GPU and 0.1 um DRAM," ISSCC Dig. Of Tech. Papers, pp.436-437, Feb. 2010 M. Loh, et al., "All-Digital CDR for High-Density, High-Speed I / O," VLSI Circuits, 2010 Symposium on, pp. 147-148, Jun. 2010

  In recent years, there has been an increasing need for serial transfer in a three-dimensional chip using an inductive coupling interface (see Non-Patent Document 1) and narrowband communication. Inductive coupling means that two circuits are coupled to each other by mutual induction (electromagnetic coupling). In such an application, the interface speed may be about several Gb / s, and the communication range may be about several centimeters or less. In order to omit the dedicated clock channel and reduce the area occupied by the interface, it is necessary to superimpose the clock on the data, perform serial transfer, and restore the clock on the receiving side. As described above, various clock recovery circuits have been proposed for conventional wired high-speed serial transfer. However, these presuppose an environment with a high signal-to-noise ratio (SNR). Also, non-return-to-zero signal (1 and 0 are represented by mutually opposite voltages of high or low voltage, and between encoded bits returns to zero (reference) voltage. Most of them have been developed on the premise that they will be used for binary coding systems that do not have any. On the other hand, for example, in the case of serial transfer via an inductive coupling link, a pulse-based signal is adopted and a simplified transceiver is used. In this case, since the pulse width is much shorter than 1 UI (UI: Unit Interval is the reciprocal of the clock frequency), it may be difficult to use a conventionally used CDR.

  For this reason, in recent years, there has been a movement to develop a new CDR that restores the clock signal by oversampling the received signal (see Non-Patent Document 2). However, the proposed technique requires a delay element that is accurately calibrated, increases the circuit configuration, and consumes a large amount of power.

  Moreover, in pulse-based serial transfer using an inductive coupling link, when the transmission path exceeds several millimeters, the voltage of the received signal becomes several tens of mV or less, and the SNR rapidly deteriorates. In addition, pulse-based signals have an ultra-wide band and it is difficult to use a band-pass filter.

  Therefore, it would be desirable to provide a CDR for pulse-based signals that has the ability to denoise. In particular, transceivers used for inductive coupling links must be very small and operate at low power. It is also important to prevent large overhead. For this reason, it is required to realize a small and power-saving CDR that can be adapted to applications such as inductive coupling links.

  The present invention aims to solve the above-mentioned problems. That is, an object of the present invention is to realize a CDR that is small, power-saving, and can be used for pulse-based ultrahigh-speed serial transfer. The present invention is not limited to the use of inductive coupling link signal transmission, and can naturally be used for other purposes. The object of the present invention is not limited to the above-mentioned object.

In order to achieve the above object, the present invention is a clock data recovery circuit for recovering a clock signal included in an input data signal as a recovered clock signal,
A delay circuit that delays a reference signal and outputs the recovered clock signal; and
A first converter that samples the data signal at a predetermined first time interval and generates a data sampling sequence including change edge position information of the data signal in a predetermined voltage direction;
A second converter that samples the recovered clock signal at the first time interval and generates a recovered clock sampling sequence including change edge position information in the predetermined voltage direction;
A comparator that performs a plurality of comparisons for each of the predetermined number of bits and outputs the comparison result as the data sampling sequence and the restored clock sampling sequence;
A delay control unit for instructing the delay circuit to change or fix a delay amount based on the comparison result;
A clock data recovery circuit.

  According to the present invention, a small and power-saving CDR that can be applied to a high-speed pulse-based signal can be realized.

FIG. 6 is a block diagram illustrating signal transmission using inductive coupling with CDRs according to the present invention. It is a block diagram which shows the Example of CDR which concerns on this invention. It is a block diagram which shows the Example of TDC used for this invention. It is a block diagram of the edge detector used for this invention. It is a figure which shows the specific example of the edge detection process of an edge detector. It is a block diagram showing an example of a latch circuit. It is a block diagram which shows an example of a digital comparator. FIG. 3 is a block diagram of a lock validity determination circuit and a truth table of a lock validity determination logic. It is a figure which shows the operation | movement of a lock validity determination logic.

  FIG. 1 shows a signal transmission circuit 100 using an inductive coupling 120 having a CDR 150 according to the present invention. The signal transmission circuit 100 is mounted on a chip, for example, and has a function of receiving input data 101 from a preceding circuit (not shown) and supplying it as a data output 171 to a succeeding circuit (not shown).

  In FIG. 1, input data 101 is input to a transmitter Tx (110), and driving power is supplied to an inductive coupling 120. Via the inductive coupling 120, the signal is further transmitted to Rx1 (130) for amplification. The waveform of the amplified signal 131 is shown in FIG. In the signal 131, data to be transmitted indicated by a solid line and noise indicated by a broken line are superimposed. The signals 131 and 132 from the receiver Rx1 (130) are further input to the receiver Rx2 (140), and are subjected to waveform shaping to become a data signal 141 in the form of a pulse train. FIG. 1 shows a signal waveform of the data signal 141. In the data signal 141, a pulse of noise indicated by a broken line is superimposed on a pulse of data indicated by a solid line.

  The data signal 141 and the reference signal 142 generated inside the reception side are input to the CDR 150. In the CDR 150, the delay amount of the reference signal 142 is adjusted based on the data pulse train, and the DLL clock signal 151 is output.

  Further, the signal 131 and the signal 132 are waveform-shaped through the asynchronous hysteresis comparator 160 to become a signal 161. Further, the signal 161 is input to the latch circuit 170, the value is latched at the timing of the DLL clock signal 151, and data is extracted as the data output 171.

  FIG. 2 shows an embodiment of a CDR 150 according to the present invention. The data signal 141 from Rx2 (140) is oversampled at a sampling interval δ by a time digital converter TDC1 (210) (TDC: Time to Digital Converter). From the TDC1 (210), 32 pieces of sampled data are transmitted to the edge detector 1 (220). The edge detector 1 (220) filters noise and extracts edge timing from oversampled 32 sampling data. The number of oversampling is not limited to 32. Therefore, this example is not intended to limit the present invention.

  Further, the reference signal 142 is input to a digital lock loop DLL (250) in which delay elements are connected in series. The DLL (250) has a function of changing the delay amount based on a signal from the delay control unit 240. The DLL clock signal 151 delayed by the DLL (250) is input to the time digital converter TDC2 (260). The TDC2 (260) may have the same configuration as the TDC1 (210). The 32 sampling data oversampled by the TDC2 (260) are input to the edge detector 2 (270). It is estimated that no noise is mixed in the reference signal 142. For this reason, unlike the edge detector 1, the edge detector 2 may not have a filtering function for noise. The edge detector 2 extracts edge timing from 32 pieces of sampling data of the DLL clock signal 151.

  Then, the edge timing output of the edge detector 1 and the edge timing output of the edge detector 2 are input to the digital comparator 230. This digital comparator checks whether the positions of the edges from the two edge detectors 1 and 2 match. If the edge positions match, the data signal 141 and the DLL clock signal 151 are synchronized. In this case, the DLL clock signal 151 can be used as a synchronization signal. In addition, the digital comparator 230 sends a lock signal indicating synchronization to the delay control unit 240. The delay control unit 240 receives the lock signal to fix the delay amount of the DLL 250 (lock state).

  On the other hand, when the digital comparator 230 determines that the edge positions do not match, it can be seen that the data signal 141 and the DLL clock signal 151 are not synchronized. For this reason, the digital comparator sends an update signal to the delay control unit 240. When the delay control unit 240 receives the update signal, the delay control unit 240 sends a control signal to the DLL 250 instructing to increase the delay amount of the DLL 250. Upon receiving this control signal, the DLL 250 increases the delay amount of the reference signal 142 by a certain amount. Thus, the digital comparator 230 receives the sampling data of the DLL clock signal 151 whose delay amount has changed, and checks again whether the edge positions match. This operation is repeated until the positions of the edges coincide. If the edge positions match, the lock state is established as described above, and the DLL clock signal 151 can be used as a synchronization signal.

  Although the DLL 250 has a function of changing the delay amount of the signal as described above, it is assumed that the control signal from the delay control unit continuously arrives and the DLL 250 reaches the maximum delay amount. Is done. In this case, the DLL delay amount may be returned to the minimum value by resetting the DLL delay amount. Note that the delay control unit may include a shift register that sequentially shifts the control signal (H “high” level). Control may be made so that a plurality of DLL delay elements are used by the number of (H “high” level) levels stored in the shift register, so that the overall delay amount of the DLL can be adjusted.

  By performing the above operation, the CDR 150 can output the locked DLL clock signal 151 from the output side of the DLL 250 and provide it as a synchronization signal.

FIG. 3 shows an embodiment of TDC1 (210). The TDC 1 (210) in this embodiment includes 32 stages of D-type flip-flops 310 (F ₁ to F ₃₂ ) and 32 delay elements 320 (D ₁ to D ₃₂ ) having a delay amount δ. Note that the number of stages is not limited to 32, and may be other stages. Accordingly, FIG. 3 is not intended to limit the present invention.

The clock signal iCLK 340 is input to the first stage D ₁ of the delay element 320. The period of iCLK 340 may be equal to the total delay amount 32 δ of the delay element 320. A signal 341 obtained by delaying iCLK 340 by δ is input to the clock terminal C of the flip-flop F ₁ . Then, to the clock terminal C of the flip-flop _{F 2,} the signal 342 obtained by delaying the iCLK340 only 2δ is input. The timing chart of these signals is shown in FIG. Flip-flop _{F 1} latches the value of the data signal 141 at the rising edge of e1 signal 341, and outputs the tdc <1>. Flip-flop _{F 2} latches the value of the data signal 141 at the rising edge of e2 of the signal 342, and outputs the tdc <2>. Therefore, from tdc <1> to tdc <32>, signals obtained by oversampling the data signal 141 at intervals of δ are sequentially output. As for the delay amount δ, the data signal 141 can be oversampled by setting at least a value shorter than the data pulse width of the data signal 141. Note that the value of the delay amount δ may be adjusted to a predetermined value by controlling the bias voltage of the delay element 320, for example. For example, δ may be adjusted to an appropriate value that allows oversampling in accordance with the data pulse width of the data signal 141. Note that the cycle of iCLK (32δ in this embodiment) is not necessarily the same as the cycle of the reference signal 142.

  FIG. 4 shows a block diagram of the edge detector 1 (220).

  FIG. 5 shows a specific example of the edge detection process of the edge detector 1 (220).

  As shown in FIG. 4, the sampling outputs tdc <1> to tdc <32> from the TDC1 (210) are input to the latch circuit 410 of the edge detector 1 (220). The values of these sampling outputs are latched and input to the “011” detector 420 and the “111” detector 430 as 32 parallel signals 411. As shown in FIG. 5, the “011” detector 420 outputs “1” to the output 421 when the bit pattern of the parallel signal 411 is “011”. Further, as shown in FIG. 5, the “111” detector 420 outputs “1” to the output 431 when the bit pattern of the parallel signal 411 is “111”. The above process is called a first stage.

  Then, the output 421 and the output 431 are input to the OR circuit 440 in FIG.

  The output of the OR circuit 440 is further input to the “011” detector 450, and the output of the “011” detector 450 is transmitted to the digital comparator 230 as the edge detection signal 451. The above process is called the second stage.

  FIG. 5 shows a specific example of the first stage, the addition process, and the bit process of the second stage. By executing these processes, the value of the noise pulse existing in the values of tdc <1> to tdc <32> is removed, and the head of the portion where “111” continues is the edge position in the edge detection signal 451. 1 "is output. Note that the above-described bit processing related to noise removal is an example. Therefore, these examples do not limit the present invention.

  The edge detector 2 (270) that performs edge processing on the DLL clock signal 151 may have the same configuration as the edge detector 1 described above. In most cases, noise is not superimposed on the DLL clock signal 151. Therefore, the edge detector 2 (270) may be configured by only a latch circuit among the components of the edge detector 1 (220). Good.

  FIG. 6 shows an embodiment of the latch circuit 410. The latch circuit 410 may include two latches, a first latch 615 and a second latch 617 that perform a latch operation at different timings. In this embodiment, the first latch 615 latches tdc <1> to tdc <16> at the timing of iCLK + 16δ (616). Then, the second latch 617 latches the output of the first latch and tdc <17> to tdc <32> at the timing of iCLK + 32δ (618) and outputs it as a parallel signal 411. Thus, two latches are provided. According to this configuration, during the time interval of 16δ from the rising timing of iCLK until the first latch latches the signal, the first stage and the latch data one cycle before already stored in the second latch Second stage processing can be performed. Therefore, by using the latch circuit 410 shown in the embodiment of FIG. 6, the edge detector 1 (220) can be operated in a pipeline manner in each cycle of iCLK. Note that the present invention is not limited to this processing.

  FIG. 7 shows an embodiment of the digital comparator 230. In the case of the present embodiment, the 32-bit data from the edge detection circuit 1 and the edge detection circuit 2 is divided into 8 bits in time series, and the divided 8 bits are compared with the comparators 711 to 711. 714 is input to four 8-bit comparators. Each of the comparators 711 to 714 transmits a logical value “1” to the majority circuit 720 as a comparison result when the two 8 bits input have the same pattern. If they do not match, the logic value “0” is transmitted.

  The majority circuit 720 outputs a logical value “1” to the majority signal output 721 when three or more coincidence signals (logical value “1”) from four comparators are input. When the number of mismatches is two or less, a logical value “0” is output. The majority signal output 721 is input to the AND circuit 740 and the NAND circuit 750.

  In the embodiment of FIG. 7, a 32-bit signal is divided every 8 bits for comparison. However, in the present invention, 32 bits may be compared for each bit, or may be divided into 4 bits and compared. In the present embodiment, the reason why the comparison is performed every 8 bits is to simplify the majority circuit. Therefore, this example is not intended to limit the present invention.

  If the majority signal output 721 outputs a logical value “1”, it means that there is a very high possibility that the edge positions of the data signal 141 and the DLL clock signal 151 match. However, for example, a case where the data signal 141 is all “0” or a case where the edge of the DLL clock signal 151 is located at the noise pulse timing of the data signal 141 is assumed. In such a case, even if the majority output signal outputs a logical value “1”, it may be in a mislocked state.

  In order to detect the above-described mislock state, a lock validity determination circuit 730 may be provided. A data signal 141 and a DLL clock signal 151 are input to the lock validity determination circuit 730. The lock validity determination circuit 730 determines whether the lock state is valid, and outputs a logical value “1” to the lock validity signal 731 if the lock is valid. When the lock is not valid, a logical value “0” is output.

  FIG. 8A shows an embodiment of the lock validity determination circuit 730. Data signal 141 is connected to the data terminals of D flip-flops 820 and 830. In addition, the data signal 141 is connected to the data terminal of the D flip-flop 810 via a delay element 840 having a delay amount γ. DLL clock signal 151 is connected to the clock terminals of D flip-flops 810 and 820. In addition, the DLL clock signal 151 is connected to the clock terminal of the D flip-flop 830 via a delay element 850 having a delay amount γ.

  The flip-flop 820 latches the value of the data signal 141 at the rising timing of the DLL clock signal 151 and transmits the output MID to the lock validity determination logic 860. The flip-flop 810 latches the value of the data signal 141 temporally before the rising timing of the DLL clock signal 151 and transmits the output PRE to the lock validity determination logic 860. The flip-flop 830 latches the value of the data signal 141 that is later by γ than the rising timing of the DLL clock signal 151, and transmits the output POST to the lock validity determination logic 860.

  FIG. 8B shows a truth table of the lock validity determination logic 860. Here, when “PRE, MID, POST” is “111”, “110”, or “011”, the lock valid signal OUT outputs “1”. Otherwise, “0” is output.

  FIG. 9 is a diagram for understanding the operation of the lock validity determination logic 860. FIG. 9 shows a data signal 141 and a DLL clock signal 151. The data signal 141 is a signal in which a data pulse 1 having a pulse width of td and a noise pulse 1 are mixed. The state in which the DLL clock signal 151 is effectively locked with respect to the data signal 141 is a case where the rising timing of the DLL clock signal 151 exists during the pulse width td of the data pulse 1 of the data signal 141. . That is, this is a case where the rising timing of the DLL clock signal 151 is located at t1, t2, and t3. On the other hand, in the case of mislock, the rising timing of the DLL clock signal 151 does not exist at td between the pulses of the data pulse 1, but exists at other times, for example, at the position of t4 or t5. is there. That is, when “PRE, MID, POST” is “111”, “110”, or “011”, the rising timing of the DLL clock signal 151 is within the range of the data pulse 1. On the other hand, when “PRE, MID, POST” are other patterns, the rising timing of the DLL clock signal 151 does not exist within the range of the data pulse 1. At t4, the rising timing of the DLL clock signal 151 exists at the time of “0” level of the data signal 141, and at t5, it exists at the time within the pulse of the noise pulse 1. These are all determined to be in a mislock state.

  As described above, the lock validity determination circuit 730 can check the lock validity state.

  Returning to FIG. When the output of the majority circuit 720 is logic “1” and the lock valid signal is logic “1”, the output of the AND circuit 740 becomes logic “1”, and the delay control unit 240 is used as the DLL lock signal 741. And the DLL delay amount is fixed. This is called a locked state. In the locked state, the power consumption of the circuits of the present invention may be suppressed to keep the power saving state. A similar signal is also input to the NAND circuit 750. Therefore, when the output of the NAND circuit is logic “1”, the DLL update signal 751 is transmitted to the delay control unit 240 because it is not in the locked state. The delay control unit receives this signal and increases the delay amount of the DLL by a certain amount.

  If a state in which the DLL clock signal 151 is synchronized with the data signal 141 is obtained by repeating the above processing, the locked state is maintained. Note that when the lock state is released due to some disturbance, the above process is repeated again, and the process of returning to the lock state is performed.

  As mentioned above, although the Example of this invention was described, each Example can be selected and combined as long as there is no contradiction. In addition, it should be noted that the above description and drawings are merely examples of the present invention and are not intended to limit the present invention according to the claims.

120 Inductive coupling 150 Clock recovery circuit (CDR)
210 TDC1
220 Edge detection circuit 1
230 Digital Comparator 240 Delay Control Unit 250 DLL
260 TDC2
270 Edge detection circuit 2

Claims (6)

A clock data recovery circuit that restores a clock signal included in an input data signal as a restored clock signal,
A delay circuit that delays a reference signal by a delay amount and outputs the restored clock signal; and
A first converter that samples the data signal at a predetermined first time interval and generates a data sampling sequence including change edge position information of the data signal in a predetermined voltage direction;
A second converter that samples the recovered clock signal at the first time interval and generates a recovered clock sampling sequence including change edge position information in the predetermined voltage direction;
A comparator that performs a plurality of comparisons for each of the predetermined number of bits and outputs the comparison result as the data sampling sequence and the restored clock sampling sequence;
A delay control unit that instructs the delay circuit whether to change or fix the delay amount based on the comparison result;
A clock data recovery circuit.   Of the first converter and the second converter, at least the first converter deletes changed edge position information having a pulse smaller than a predetermined number of first bit strings. The clock data recovery circuit according to claim 1.   The clock data recovery circuit according to claim 1, wherein the comparator makes a majority decision based on the plurality of comparisons, and outputs a result of the majority decision as a comparison result. The comparator has a start position and an end position before and after a predetermined second time interval γ from the bit position of the data sampling sequence at the time corresponding to the bit position of the changing edge in the restored clock sampling sequence. Further outputting a determination result as to whether or not the number of bits of the pulse width of the data sampling sequence in a time interval of 2γ is larger than a predetermined number of second bit sequences,
The delay control unit instructs the delay circuit to change or fix a delay amount based on the comparison result and the determination result.
The clock data recovery circuit according to claim 1.   The clock data recovery circuit according to claim 1, wherein a delay element is used to obtain the first time interval.   6. A semiconductor chip comprising the clock data recovery circuit according to claim 1.

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