JP5684518B2 - Software component execution control device - Google Patents

Description

  The present invention relates to an execution control apparatus that controls execution of software components (hereinafter simply referred to as “software components”) used in real-time control processing for controlling, for example, sensors, switches, 7-segment displays, and buzzers.

  Conventionally, real-time control system software uses PLC (Programmable Logic Controller) to improve software production efficiency, and PLC control processing is described in SFC (Sequential Function Chart) or LD (Ladder Diagram). In many cases, the program is completed.

  Another thing that promotes the reusability of software components is to reduce the time spent customizing the system by arranging and connecting software components without knowledge of object-oriented technology or PLC programming language. (For example, refer to Patent Document 1).

JP 2001-14155 A

  However, since the PLC starts the sequential program at a cycle called cycle time, there is a problem that the processing response speed decreases as the program size increases.

  On the other hand, the software component execution control device disclosed in Patent Document 1 is activated by a change in data input from a sensor, but there is no change in data input from an input pin between software components. However, since a software component may be activated, a software component that does not need to be activated may be activated, which may cause a load on a processor such as a CPU (Central Processing Unit) that executes the software component. There was a problem.

  The present invention has been made to solve the conventional problems as described above. Software component execution capable of reducing the processing load on a processor such as a CPU while improving the processing response speed compared to the conventional one. An object is to provide a control device.

A software component execution control device according to the present invention includes a plurality of software components each having at least one input pin and at least one output pin, which are functionally arranged in a matrix using a software tool, and an input external device An input data buffer that temporarily stores data input from the output, an output data buffer that temporarily stores data to be output to the output external device, and an activation unit that activates the plurality of software components in row order and column order In the software component execution control device, further comprising a data buffer between software components that temporarily stores data delivered between the plurality of software components, and the activation unit includes the plurality of software components as the plurality of software components. Each input pin provided in a software component is an array of the input data buffer or the data buffer between the software components Is determined based on input pin connection information indicating which array element has a structure and a change flag included in each array element having the array structure of the input data buffer or the inter-software component data buffer. It is configured to be activated only when the data input to any of the input pins changes .

  With this configuration, the software component execution control device of the present invention starts only the software component whose data input to any of the input pins has changed, so that the processing response speed is improved compared to the conventional one and the CPU It is possible to reduce the processing load on the processor.

  By the way, as described above, the PLC needs to describe detailed functions in SFC or LD, etc., the function of the software component is as simple as a bit logical operation, and these software components need to be combined.

  Accordingly, even if there is a program having a reusable part for creating a program for a new system constituted by the PLC, if the program cannot be used as it is in the new system, the new system Since it is necessary to create the program again, the efficiency of creating the program may be reduced.

Therefore, in the software component execution control apparatus of the present invention, data of the same bit length may be input / output between the input pins and the output pins of the plurality of software components.

  With this configuration, the software component execution control device according to the present invention facilitates the connection between the software components and enhances the function of each software component to promote the reuse of the software component. Creation efficiency can be improved.

  The present invention can provide a software component execution control device capable of reducing the processing load on a processor such as a CPU while improving the processing response speed compared to the conventional one.

It is a hardware block diagram of the software component execution control apparatus as one embodiment of this invention. It is a block diagram which shows an example of the software structure of the software component execution control apparatus as one embodiment of this invention. It is a conceptual diagram which shows the structure of each data buffer of the input data buffer, the output data buffer, and the software buffer between software components which comprise the software component execution control apparatus as one embodiment of this invention. It is a conceptual diagram which shows the input data buffer definition information referred by the software component execution control apparatus as one embodiment of this invention. It is a conceptual diagram which shows the output data buffer definition information referred by the software component execution control apparatus as one embodiment of this invention. It is a conceptual diagram which shows the software component starting information referred by the software component execution control apparatus as one embodiment of this invention. It is a conceptual diagram which shows the data input / output by the software component of the software component execution control apparatus as one embodiment of this invention. It is a conceptual diagram which shows the input pin connection information referred by the software component execution control apparatus as one embodiment of this invention. It is a conceptual diagram which shows the output pin connection information referred by the software component execution control apparatus as one embodiment of this invention. It is a flowchart which shows operation | movement of the processor which comprises the software component execution control apparatus as one embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. A software component execution control apparatus according to an embodiment of the present invention is shown in FIG.

  As shown in FIG. 1, a software component execution control apparatus 1 according to an embodiment of the present invention includes a processor 10 such as a CPU, a random access memory (RAM) 11, a read only memory (ROM) 12, and a hard disk. The computer 13 includes a device 13, an input device 14 including a keyboard device and a pointing device, a display device 15 including a liquid crystal display device, an input port 16, an output port 17, and a network module 18. ing.

  The ROM 12 and the hard disk device 13 store a program for causing the computer device to function as the software component execution control device 1. That is, when the processor 10 executes a program stored in the ROM 12 and the hard disk device 13 using the RAM 11 as a work area, the computer device functions as the software component execution control device 1, and the RAM 11 or the hard disk device 13 is a software component. It functions as the storage unit 19 of the execution control device 1.

  The input port 16 is connected to input external devices such as various sensors according to the application of the software component execution control device 1. An output external device such as a 7-segment display or a digital / analog (hereinafter simply referred to as “D / A”) converter is connected to the output port 17 in accordance with the application of the software component execution control device 1. .

  FIG. 2 shows an example of the structure of a program executed by the processor 10. By executing this program, the processor 10 temporarily stores the input data buffer 31 for temporarily storing data input from the input external device and the data output to the external device. Output data buffer 32, a plurality of software components 34a to 34h arranged in a matrix (hereinafter also collectively referred to as “software component 34”), and data delivered between the software components 34a to 34h are temporarily stored. It functions as an inter-software-component data buffer 33 for storing data.

  The soft component 34 has at least one input pin 35 and at least one output pin 36. Note that the number of input pins 35 and the number of output pins 36 included in the software component 34 may be different for each software component 34.

  As shown in FIG. 3, each of the input data buffer 31, the output data buffer 32, and the inter-software component data buffer 33 has an array structure, and an array element number is assigned to each element of the array.

  Each array element of each data buffer of the input data buffer 31, the output data buffer 32, and the inter-software component data buffer 33 includes data and a change flag indicating whether or not the data has changed. In the present embodiment, the bit length of data stored in each array element of each data buffer is 32 bits.

  As shown in FIG. 4, the storage unit 19 stores in advance input data buffer definition information 50 indicating which input external device receives data output from each array element of the input data buffer 31. Yes.

  For example, in the example shown in FIG. 4, the data output from the sensor A is input to the array element of the array number 1, and the data output from the sensor B is input to the array element of the array number 2. The N array elements indicate that the data output from the sensor N is input.

  Further, as shown in FIG. 5, output data buffer definition information 51 indicating in which output external device data is output from each array element of the output data buffer 32 is stored in the storage unit 19 in advance. .

  For example, in the example shown in FIG. 5, data is output from the array element of array number 1 to the 7-segment display 1, data is output from the array element of array number 2 to the D / A converter 1, and array element of array number N It represents that data is output from the array element to the 7-segment display N.

  In addition, as shown in FIG. 6, software component activation information 52 representing the activation order of the software components 34 is stored in the storage unit 19 in advance. In the software component activation information 52, the software components 34 are activated in the column order, and when there are a plurality of software components 34 in the same column, they are activated in the row order.

  For example, the example shown in FIG. 6 represents that the software component a, the software component b, the software component c, the software component d, the software component e, the software component f, the software component g, and the software component h are activated in this order. Yes.

  Here, each software component 34 is activated only when the data input to any of the input pins 35 changes. For this reason, if the connection source of the input pin 35 of a certain software component 34 (for example, software component 34d) is the output pin 36 of another software component 34 (for example, software component 34a), The software component 34d is arranged in a row behind the software component 34a.

  As shown in FIG. 7, in this embodiment, the bit length of data input / output via the input pin 35 and the output pin 36 of the software component 34 is set between the input data buffer 31, the output data buffer 32 and the software component. The bit length of the data stored in the data buffer 33 is 32 bits.

  Thus, by making the bit length of the data stored in the input data buffer 31, the output data buffer 32, and the inter-software component data buffer 33 the same as the bit length of the data input / output by the software component 34, It is possible to appropriately connect between the external device and the software component 34 or between the software components 34.

  Therefore, since the software component 34 has a plurality of input pins 35 and output pins 36, it can handle a large amount of data, and not only a simple process such as a bit logic operation but also an arithmetic operation, Advanced numerical operations such as least squares and FFT (Fast Fourier Transform), and advanced processing such as sequence control using information of 32 bits or more can be executed, facilitating the reuse of software components 34 can do.

  Further, in the storage unit 19, as shown in FIG. 8, each input pin 35 provided in each software component 34 is connected to the array element of which array number in the input data buffer 31 or the inter-software component data buffer 33. The input pin connection information 53 indicating whether or not is stored. Input pin connection information 53 exists for each software component 34.

  Further, in the storage unit 19, as shown in FIG. 9, each output pin 36 provided in each software component 34 is connected to the array element of which array number in the output data buffer 32 or the inter-software component data buffer 33. The output pin connection information 54 indicating whether or not is stored. The output pin connection information 53 exists for each software component 34.

  Here, the arrangement of the software components 34 and the connection between the input pins 35 and the output pins 36 between the software components 34 are generally performed using a software tool executed by a general-purpose personal computer.

  Specifically, by this software tool, the input data buffer definition information 50 shown in FIG. 4, the output data buffer definition information 51 shown in FIG. 5, the software component activation information 52 shown in FIG. 6, and the information shown in FIG. The input pin connection information 53 of each software component 34 and the output pin connection information 54 of each software component 34 shown in FIG. 9 are created.

  That is, the software component execution control device 1 updates each array element of the input data buffer 31, the output data buffer 32, and the inter-software component data buffer 33 while referring to the information 50 to 54 created by the software tool. As a result, each software component 34 is executed.

  The operation of the processor 10 constituting the software component execution control device 1 configured as described above will be described with reference to FIG.

  Note that the operation of the processor 10 described below will be described by taking as an example the case where the software components 34 are arranged in a matrix with three rows and three columns as shown in FIG. The operation of the processor 10 described below is executed at regular time intervals or timing when an interrupt signal is input from the input external device.

  First, the processor 10 updates the input data buffer 31 based on the input data buffer definition information 50 (step S1).

  For example, in the input data buffer definition information 50, the processor 10 first inputs data from the sensor A and stores the data in the array element of array number 1. At this time, if there is a difference from the previous data content, the processor 10 sets the change flag of the array element of the array element number 1 to ON.

  Similarly, the processor 10 inputs data from the sensor B and stores the data in the array element of array element number 2. At this time, if there is a difference from the previous data content, the processor 10 sets the change flag of the array element of the array element number 2 to ON. Thereafter, similarly, the processor 10 inputs data up to the array element number N based on the input data buffer definition information 50.

  Next, the processor 10 executes software component activation pre-processing (step S2). Specifically, the processor 10 sets the change flags of all the array elements of the output data buffer 32 and the change flags of all the array elements of the inter-software-component data buffer 33 to OFF.

  Next, the processor 10 initializes i as a column count variable for identifying each software component 34 to 1 (step S3), and initializes j as a row count variable to 1 (step S4). Thereafter, the processor 10 determines whether or not the data of the input pin 35 of the software component 34 arranged in the j row and i column has changed, and activates the software component 34 whose data of the input pin 35 has changed.

  First, the processor 10 determines whether or not the software component 34 is arranged in the j-th row and the i-th column based on the software component activation information 52 (step S5). Here, when it is determined that the software component 34 is not arranged in the j-th row and the i-th column, the processor 10 executes Step S9 described later.

  On the other hand, if it is determined that the software component 34 is arranged in the j row and the i column, the processor 10 receives the data input to any one of the input pins 35 of the software component 34 arranged in the j row and the i column. Whether or not there is a change is determined based on the input pin connection information 53 and the change flag of the array element of the input data buffer 31 or the inter-software component data buffer 33 (step S6).

  For example, when the input pin connection information 53 of the software component 34 is FIG. 8, the processor 10 inputs data from the array element of the array number 100 of the input data buffer to the input pin 35 corresponding to the input pin number 1. At this time, it is determined whether or not the change flag of the array element with the array element number 100 is ON.

  Similarly, the processor 10 inputs data from the array element of array number 1 of the inter-software-component data buffer 33 to the input pin 35 corresponding to the input pin number 2, and changes the array element of array number 1 at that time. Determine if the flag is on. In this way, the processor 10 performs the same processing for each input pin 35.

  Here, if it is determined that the data input to all the input pins 35 of the software component 34 arranged in the j-th row and the i-th column has not changed, the processor 10 executes Step S9.

  On the other hand, if it is determined that the data input to any of the input pins 35 of the software component 34 arranged in the j row and the i column has changed, the processor 10 determines the software arranged in the j row and the i column. The component 34 is activated (step S7).

  Next, the processor 10 refers to the output pin connection information 54 and updates the data of the array elements of the inter-software-component data buffer 33 or the output data buffer 32 (step S8).

  For example, when the output pin connection information 54 of the software component 34 is FIG. 9, the processor 10 executes the software component 34 arranged in j rows and i columns and is output from the output pin 36 corresponding to the output pin number 1. Data is stored in the array element of array number 200 in the output data buffer 32, and if the data is different from the previous data, the change flag is set to ON.

  Similarly, the processor 10 stores the data output from the output pin 36 corresponding to the output pin number 2 in the array element of the array number 100 of the inter-software component data buffer 33, and if the data is different from the previous, the change flag Set to on. In this way, the processor 10 performs the same processing for each output pin 36.

  Next, the processor 10 increments j (step S9), and determines whether j exceeds the number of rows (step S10). Here, when it is determined that j does not exceed the number of rows, the processor 10 executes Step S5.

  On the other hand, if it is determined that j exceeds the number of rows, the processor 10 increments i (step S11), and determines whether i exceeds the number of columns (step S12). If it is determined that i does not exceed the number of columns, the processor 10 executes step S4.

  On the other hand, if it is determined that i exceeds the number of columns, the processor 10 executes post-software component activation processing (step S13). Specifically, the processor 10 outputs only the data of the array element whose change flag of the output data buffer 32 is turned on to the output external device based on the output data buffer definition information 51.

  As described above, the software component execution control apparatus 1 according to the embodiment of the present invention activates only the software component 34 whose data input to any of the input pins 35 has changed. The processing load on the processor 10 such as a CPU can be reduced while the speed is improved from the conventional one.

  In addition, the software component execution control apparatus 1 according to the embodiment of the present invention connects the software components 34 by inputting and outputting data having the same bit length to the input pins 35 and the output pins 36 of the software components 34. Since the functions of each software component 34 can be enhanced and the reuse of the software component 34 can be promoted, the efficiency of creating a program can be improved.

1 software component execution control device 10 processor 11 RAM
12 ROM
13 hard disk device 14 input device 15 display device 16 input port 17 output port 18 network module 19 storage unit 31 input data buffer 32 output data buffer 33 software component data buffer 34, 34a to 34h software component 35 input pin 36 output pin 50 input Data buffer definition information 51 Output data buffer definition information 52 Software component activation information 53 Input pin connection information 54 Output pin connection information

Claims (2)

A plurality of software components each having at least one input pin and at least one output pin, which are functionally arranged in a matrix using a software tool, and data input from an input external device are temporarily stored. A software component execution control device comprising: an input data buffer to be output; an output data buffer for temporarily storing data to be output to an output external device; and an activation unit that activates the plurality of software components in row order and column order.
A data buffer between software components for temporarily storing data delivered between the plurality of software components;
The activation means determines which array element having the array structure of the input data buffer or the inter-software-part data buffer is connected to the plurality of software parts, and each input pin provided in the plurality of software parts. Data input to any of the input pins, determined based on the input pin connection information that represents and the change flag included in each array element having the array structure of the input data buffer or the inter-software data buffer A software component execution control device that is activated only when the value of the software changes . 2. The software component execution control device according to claim 1, wherein the input pins and the output pins of the plurality of software components respectively input and output data having the same bit length.

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