JP5684451B2 - Signal processing apparatus and signal processing method - Google Patents

Description

  The present invention relates to a signal processing apparatus and a signal processing method.

  Conventionally, in order to improve the SN ratio and the BER (bit error rate) in a magnetic disk device, researches on a head, a medium, a signal processing technique, and the like have been performed. For example, improvement of MR (Magneto Resistive) sensitivity for obtaining a larger signal amplitude, refinement of the particle size of the medium and reduction of medium noise, LDPC (Low Density Parity) for ensuring a predetermined error rate even at a low S / N ratio Signal processing techniques such as Check code and iterative decoding have been studied.

  Recently, a dual stripe head for adding and decoding signals read from the same track by two MR elements has been proposed. The dual stripe head is described in Patent Document 1, for example.

JP 2001-14603 A

  However, in the conventional dual stripe head, since the two MR elements are provided apart from each other, the signal read from one MR element is delayed with respect to the signal read from the other MR element. For this reason, when the recording density of the medium is increased, there is a problem that it becomes difficult for the two MR elements to normally read signals from the same recording bit. That is, in the conventional dual stripe head, there is a concern that the recording density of the medium is limited depending on the distance between the two MR elements.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is a new and improved technique capable of synchronizing and adding signals read by a plurality of MR elements. Another object is to provide a signal processing apparatus and a signal processing method.

  In order to solve the above problems, according to one aspect of the present invention, a plurality of MR elements having the same polarity for reading signals from the same track formed on a recording medium, and signals read by the plurality of MR elements A plurality of discretization units for discretizing each of the plurality of sample value sequences, a plurality of synchronization detection units for detecting a synchronization signal from each of the plurality of sample value sequences, and synchronization detection by the plurality of synchronization detection units And a summing unit for synchronizing and adding the plurality of sample value sequences.

  In such a configuration, the signal component is N times (N = the number of MR elements) as compared with the case where only one MR element is used, while the electric noise mixed in the signal processing is √N times. Therefore, it is possible to improve the SN gain. Furthermore, since the adding unit adds a plurality of sample value sequences in synchronization, it is possible to obtain a normal result even if the recording density of the recording medium is increased.

  The signal processing apparatus further includes a decoding unit that performs iterative decoding after the addition in the adding unit. Here, the SN gain improved by iterative decoding becomes more prominent as the ratio of the medium noise with the recording medium as the noise source to the total noise increases. Further, according to the configuration in which the plurality of sample value sequences are added in synchronization, the ratio of the medium noise to the total noise can be increased. Therefore, it is possible to synergistically improve the SN gain obtained by iterative decoding by combining the configuration in which the plurality of sample value sequences are added in synchronization with iterative decoding.

  In order to solve the above problem, according to another aspect of the present invention, a plurality of MR elements having the same polarity from the same track formed on a recording medium read signals, and the plurality of MR A step of discretizing each of the signals read by the element to obtain a plurality of sample value sequences; a step of detecting a synchronization signal from each of the plurality of sample value sequences; and the plurality of sample value sequences based on synchronization detection And synchronizing and adding the signal.

  As described above, according to the signal processing apparatus and signal processing method of the present invention, signals read by a plurality of MR elements can be added in synchronization.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

Further, the “best mode for carrying out the invention” will be described according to the following item order.
[1] Outline of HDD according to this embodiment [1-1] Appearance of HDD [1-2] Configuration of disk [1-3] Background to this embodiment [2] Details of HDD according to this embodiment Description [2-1] HDD configuration [2-2] HDD operation [3] Summary

[1] Outline of HDD According to this Embodiment First, an HDD 10 according to this embodiment will be schematically described with reference to FIG.

[1-1] External View of HDD FIG. 1 is an external view of the HDD 10 according to the present embodiment. As shown in FIG. 1, the HDD 10 according to this embodiment includes a spindle motor 30 installed on a base member 11, a disk group 20 as a recording medium mounted on the spindle motor 30, data reproduction and And an actuator 40 for moving a read / write head for recording to a predetermined position on the disk group 20. The disk group 20 includes a plurality of disks. In general, there is a cover member corresponding to the base member 11 in FIG. 1, and the base member 11 is covered with the cover member to form one housing (housing). However, the cover member is illustrated and described. Omitted.

  The actuator 40 has a swing arm 44 rotatably coupled to a pivot 42 installed on the base member 11 and a head 48 installed on one end of the swing arm 44 urged toward the surface of the disk group 20. And a voice coil motor (hereinafter referred to as VCM) 50 for rotating the swing arm 44. The swing arm 44, the suspension 46, and the head 48 are also provided between the disks included in the disk group 20.

  The VCM 50 is controlled by a servo control system, for example, as a head drive unit that rotates the swing arm 44 in the direction according to Fleming's left-hand rule by the interaction between the current input to the VCM coil and the magnetic field formed by the magnet. Function. That is, when the power of the HDD 10 is turned on and the disk group 20 starts to rotate, the VCM 50 rotates the swing arm 44 to move the read / write head 48 onto the recording surface of the disk group 20. On the other hand, when the power of the HDD 10 is turned off and the rotation of the disk group 20 is stopped, the VCM 50 rotates the swing arm 44 so that the head 48 is detached from the recording surface of the disk group 20.

  Further, the head 48 records data on one surface of a disk constituting the disk group 20 or reads data from one surface of the disk by the functions of the preamplifier IC 100 and the read channel IC 120 shown in FIG.

  The HDD 10 having such a function as a signal processing device includes, for example, a PC (Personal Computer), a home video processing device (DVD recorder, VCR, etc.), a mobile phone, a PHS (Personal Handyphone System), and portable music. You may provide in information processing apparatuses, such as a reproducing | regenerating apparatus, a portable video processing apparatus, PDA (Personal Digital Assistants), a home game device, a portable game device, a household appliance.

[1-2] Configuration of Disk Next, the configuration of a certain disk 21 constituting the disk group 20 will be described with reference to FIGS.

(Patterned media)
FIG. 2 is an explanatory diagram showing a configuration example of the disks 21 included in the disk group 20. More specifically, FIG. 2 shows a case where the disk 21 is a patterned medium. As shown in FIG. 2, recording bits 22 and non-recording bits 23 are regularly formed on one surface of the disk 21. The recording bit 22 is a minute magnetic material and functions as a recording area in which 1-bit information is recorded for each dot.

  Each of the recording bits 22 is formed at a predetermined interval in the track direction and separated by non-recording bits 23. Each track is also separated by a non-record bit 23. The head 48 moves on, for example, a certain track, records information while being positioned on the recording bit 22 included in the track, and reverses the magnetic field while being positioned on the non-recording bit 23. Therefore, recording on the disk 21 which is such a patterned medium requires a recording method synchronized with the rotation of the disk 21, but the patterned medium exceeds the limit of the recording density of the continuous medium, High density recording is possible.

  In FIG. 2, the track is shown linearly, but strictly, it may be arcuate. The shape of the track may be a sine wave that intersects the concentric circle of the disk 21 a plurality of times, or may be a polygon.

(Discrete media)
FIG. 3 is an explanatory diagram showing another configuration example of the disks 21 included in the disk group 20. More specifically, FIG. 3 shows a case where the disk 21 is a discrete medium. As shown in FIG. 3, the disk 21 is a medium in which magnetic thin films 24 are continuously arranged in the track direction. Then, a minute region magnetized in the plane or perpendicular to the surface is formed on the thin film 24 by the head 48, and 0 and 1 information bits are written. Further, a groove 25 is provided between the thin films 24 of each magnetic material.

  2 and 3, the example in which the disk 21 is a patterned medium or a discrete medium has been described. However, the disk 21 is not limited to such an example. The disk 21 may be a medium having an arbitrary configuration such as a continuous medium.

(Format structure)
FIG. 4 is an explanatory diagram showing an example of the format of the disk 21. The format of the disk 21 is, for example, as shown in FIG. 4A, servo areas 320-1 (Servo1), 320-2 (Servo2), data areas 310-1 (Data1), 310-2 (Data2),. .., 310-N (DataN) and a gap (Gap) between the servo area and the data area.

  In the example shown in FIG. 4A, there are N data areas, and each data area holds, for example, 512 bytes of data. The servo area and data area are repeatedly arranged in the track direction with the format shown in FIG. 4A as a unit.

  4B is an explanatory diagram showing details of each data area (Data 1, 2,..., N) in FIG. 4A. For example, as shown in FIG. 4B, the format of the data area (Data 1, 2,..., N) includes a preamble portion (Preamble) 311 for synchronizing data reading and data indicating the head of the data. It includes a Sync Mark (synchronization signal) 312 which is the head part, a data part (Data) 313 having, for example, 512 bytes, and an ECC / CRC 314 having an ECC for error correction and a CRC for error detection.

  FIG. 4C is an explanatory diagram showing details of the servo areas (Servo 1 and 2) of FIG. 4A. For example, as shown in FIG. 4C, the format of the servo area (Servo 1 and 2) includes a preamble part (Preamble) 321 for synchronizing at the time of servo reading and a servo head part (Sync Mark) indicating the head of the servo. 322, a gray code 323 including head information and sector information, and a burst 324 including information for positioning.

[1-3] Background to the Present Embodiment Conventionally, in order to improve the SN ratio and the BER in a magnetic disk device, researches on a head, a medium, a signal processing technique, and the like have been made. For example, improvement of MR sensitivity for obtaining a larger signal amplitude, refinement of the grain size of the medium and reduction of medium noise, signal processing such as LDPC code and iterative decoding for ensuring a predetermined error rate even at a low S / N ratio Technology is being studied.

  Note that sudden noise other than medium noise is mostly thermal noise that follows a Gaussian distribution. If an error occurs, the probability of normal data demodulation can be increased by rereading.

  Here, the capacity and recording density of the magnetic disk device are improved by about 40% per year. However, there is a concern that the SN ratio is reduced and the BER is deteriorated due to the miniaturization of recording bits. In addition, when the parity bits are increased in the LDPC code and iterative decoding, the correction capability is improved, but the frequency in the medium becomes higher, so that noise is emphasized and the original effect cannot be obtained. In addition, when the frequency of re-reading increases, the performance of the magnetic disk device decreases.

  Therefore, the HDD 10 according to the present embodiment has been created with the above circumstances taken into consideration. According to the HDD 10 according to the present embodiment, it is possible to improve the SN gain by synchronizing and adding signals read by a plurality of MR elements. Hereinafter, the HDD 10 will be described in detail.

[2] Detailed Description of HDD According to the Present Embodiment [2-1] Configuration of HDD FIG. 5 is a functional block diagram showing a configuration of the HDD 10 according to the present embodiment. As shown in FIG. 5, the HDD 10 according to the present embodiment includes a head 48, a preamplifier IC 100, and a read channel IC 120.

  In the present embodiment, as shown in FIG. 5, the head 48 includes a plurality of MR elements 70A and 70B. Hereinafter, the detailed structure of the head 48 will be described with reference to FIG.

  FIG. 6 is an explanatory diagram showing the configuration of the head 48. More specifically, FIG. 6 schematically shows the configuration of the head 48 when the disk surface is the viewpoint. As shown in FIG. 6, the head 48 includes MR elements 70A and 70B, a magnetic shield and electrode 72A of the MR element 70A, a magnetic shield and electrode 72B of the MR element 70B, and an insulating layer 74.

  MR elements 70A and 70B are arranged on the same width and on the same track in order to read signals from the same track. The MR elements 70A and 70B are arranged at an interval L such that signals read by the MR elements 70A and 70B do not interfere with each other. Note that a mechanism for writing to the disk 21 is also stacked on the head 48, but the description is omitted in FIG.

  Further, in this specification, an explanation will be given focusing on an example in which there are two MR elements that read signals from the same track, but the present invention is not limited to such an example. For example, the present invention can be similarly applied to the case where an arbitrary number of three or more MR elements that read signals from the same track are provided.

  Returning to the description of the configuration of the HDD 10 with reference to FIG. 5, each of the MR elements 70A and 70B is independently provided with a terminal for reading a signal (magnetic reproduction signal) from the disk 21 as an electrical signal. ing. The signals read by each of the MR elements 70A and 70B are individually processed in the preamplifier IC 100 and the read channel IC 120, as will be described below.

  The preamplifier IC 100 includes an amplifier 108A that amplifies the signal read by the MR element 70A and an amplifier 108B that amplifies the signal read by the MR element 70A.

  The read channel IC 120 includes VGAs 124A and 124B, CTFs 128A and 128B, ADCs 132A and 132B, FIR filters 136A and 136B, AGCs 140A and 140B, TRCs 144A and 144B, SMDs 148A and 148B, an addition unit 152, and a data detection unit. 156 and a decoding unit 160.

  A VGA (Variable Gain Amplifiers) 124A amplifies the signal amplified by the amplifier 108A so as to have a desired output amplitude based on control by the AGC 140A. Similarly, the VGA 124B amplifies the signal amplified by the amplifier 108B so as to have a desired output amplitude based on control by the AGC 140B. Therefore, the VGAs 124A and 124B can output signals with the same amplitude even when the sensitivity of the MR elements 70A and 70B and the amplification factors of the amplifiers 108A and 108B are different.

  The CTF (Continuous Time Filter) 128A is an analog filter that performs high-frequency noise suppression of the signal output from the VGA 124A and coarse adjustment of signal characteristics such as boosting of a predetermined band. Similarly, the CTF 128B is an analog filter that performs high-frequency noise suppression of a signal output from the VGA 124B and coarse adjustment of signal characteristics such as boosting of a predetermined band.

  The ADC (Analog to Digital Converter) 132A functions as a discretization unit that converts a signal output from the CTF 128A from an analog format to a digital format, that is, discretizes the signal. Similarly, the ADC 132B functions as a discretization unit that discretizes the signal output from the CTF 128B. Hereinafter, the sample value sequence obtained by discretization in the ADC 132A is referred to as a sample value sequence A, and the sample value sequence obtained by discretization in the ADC 132B is referred to as a sample value sequence B.

  The FIR (Finite Impulse Response) filter 136A is a digital filter that performs fine adjustment (such as waveform equalization) of the signal characteristics of the sample value sequence A. Similarly, the FIR filter 136B is a digital filter that finely adjusts the signal characteristics of the sample value sequence B.

  An AGC (Automatic Gain Control) 140A controls the amplification factor in the VGA 124A based on the amplitude of the sample value sequence A output from the FIR filter 136A. Similarly, the AGC 140B controls the amplification factor in the VGA 124B based on the amplitude of the sample value sequence B output from the FIR filter 136B.

  A TRC (Timing Rccovery Circuit) 144A performs phase control based on the value of the sample value sequence A in the preamble section 311 so that sampling is performed at a desired signal position in the ADC 132A. Similarly, the TRC 144B performs phase control so that sampling is performed at a desired signal position in the ADC 132B based on the value of the sample value string B in the preamble section 311. Hereinafter, the function of the TRC 144 will be described in detail with reference to FIG.

  FIG. 7 is an explanatory diagram showing analog signals read by a plurality of MR elements 70A and 70B and sample value strings. As shown in FIG. 7, the TRC 144 performs sampling of the ADC 132 so that the preamble unit 311 can obtain sample values according to the rules 1, 1, 0, 0, 1, 1, 0, 0,. Control timing.

  Here, an analog signal read by MR element 70B (hereinafter referred to as analog signal B) is L (element spacing) / V (relative velocity between head 48 and disk 21) with respect to analog signal A read by MR element 70A. ).

  Further, the delay time d is not necessarily an integral multiple of the sampling period T, and can be rewritten as, for example, delay time d = nT + φ (n is the number of delay bits (integer) in the sample value sequence). However, since TRCs 144A and 144B perform sampling phase control in ADC 132A and ADC 132B as described above, φ is absorbed by TRCs 144A and 144B. Therefore, the ADC 132A and the ADC 132B can perform sampling at the same position on the analog signal as shown in FIG.

  The SMD (Synchronous Mark Detector) 148A illustrated in FIG. 5 functions as a synchronization detection unit that detects the Sync Mark 312 indicating the start of the data part 313 from the sample value sequence A. Similarly, the SMD 148B functions as a synchronization detection unit that detects the Sync Mark 312 indicating the start of the data unit 313 from the sample value sequence B. Then, the adder 152 adds the sample value sequence A and the sample value sequence B in synchronization based on the detection of the Sync Mark 312 by the SMDs 148A and 148B. Hereinafter, the functions of the SMD 148 and the addition unit 152 will be described in detail with reference to FIG.

  FIG. 8 is an explanatory diagram showing an analog signal and a sample value string near the data line head 312. As shown in FIG. 8, the adder 152 detects the Sync Mark 312 by the SMD 148A, and the Sync Mark 312 ends with the x-th sample value of the sample value sequence A, and the data unit 313 starts from the x + 1-th sample value. Grasp that. Similarly, the addition unit 152 recognizes that the Sync Mark 312 ends with the y-th sample value of the sample value sequence B and the data unit 313 starts from the y + 1-th sample value by detection of the Sync Mark 312 by the SMD 148B.

  Therefore, since the x + 1-th sample value of the sample value sequence A and the y + 1-th sample value of the sample value sequence B can be determined to be sample values corresponding to the same signal position, the adder 152 determines both samples. Add the values. Similarly, the addition unit 152 adds the x + 2th sample value of the sample value sequence A and the y + 2th sample value of the sample value sequence B, and the x + 3th sample value of the sample value sequence A and the sample value sequence B The y + 3rd sample value of is added. When generalized, the adding unit 152 adds the x + z-th sample value of the sample value sequence A and the y + z-th sample value of the sample value sequence B.

  In the above example, the addition unit 152 adds from the data start unit (z> 0) of the sample value sequences A and B. However, the data detection unit 156 may also consider Sync Mark intersymbol interference. In this case, it may be necessary to go back in time and add from the Sync Mark start position. Therefore, when the x + z-th sample value and the y + z-th sample value of the sample value sequence B are added, z <0 may be set using a buffer or the like. In the above description, the example in which the sample value sequences A and B are added in synchronization with each other based on the detection of the Sync Mark 312 has been described. However, the present embodiment is not limited to such an example. For example, the adding unit 152 identifies the number of delay bits of the sample value sequence B with respect to the sample value sequence A from the element interval d of the MR elements 70A and 70B, the sampling period, and the disk rotation speed, and based on the number of delay bits The sample value sequences A and B may be synchronized and added.

  Hereinafter, with reference to FIG. 9 and FIG. 10, the effect obtained by the addition in the adding unit 152 will be described.

  FIG. 9 is an explanatory diagram in which the functional block diagram shown in FIG. 5 is rewritten focusing on signal components and noise components. In FIG. 9, s indicates the signal source from the disk 21, nm indicates the medium noise from the disk 21, MRG1 indicates the sensitivity (gain) of the MR element 70A, and MRG2 indicates the sensitivity (gain) of the MR element 70B. N1e and n2e indicate electrical noise mixed in the head 48, the preamplifier IC 100, and the like. In this case, an input i1 via the MR element 70A to the adding unit 152 is expressed by the following expression 1, and an input i2 via the MR element 70B is expressed by the following expression 2.

  Here, for convenience of explanation, assuming that MRG1 = MRG2 = 1, the output a from the adder 152 is expressed as in Equation 3 below.

  Further, assuming that the standard deviation of the electrical noise n1e is σ1e, the standard deviation of the electrical noise n2e is σ1e, and the electrical noises n1e and n2e are uncorrelated, the standard deviation σae of the output from the adder 152 is , Expressed as Equation 4 below.

  When each of the above parameters is used, the SN gain (SNG) according to the present embodiment is expressed as Equation 5 below.

  Furthermore, when the total noise σt including the medium noise and the electrical noise is defined as the following Expression 6, and the medium noise ratio r with respect to the total noise is defined as the following Expression 7, Expression 8 is obtained.

  FIG. 10 is an explanatory diagram showing the relationship between the medium noise ratio r and the SN gain obtained by this embodiment. As shown in FIG. 10, the SN gain obtained by this embodiment increases as the medium noise ratio decreases. Here, the effect of doubling the sensitivity of the MR elements 70A and 70B is greater than that of the present embodiment. However, as shown by the triangular plot in FIG. 10, a further SN gain can be obtained by combining both. Is possible.

  The medium noise ratio depends on the recording density and data transfer speed of the HDD 10, and is, for example, 0.8 to 0.9 when the frequency band is narrow 1.8 ", and 0.5 to 3.5 when the frequency band is 3.5". It is about 0.7. Therefore, this embodiment is expected to have a remarkable effect in the HDD 10 having a large diameter and high-speed rotation. Further, when the density increases and the signal and noise from the disk 21 become weak, the medium-to-noise ratio becomes small, so that the effect according to the present embodiment is expected to increase.

  Here, returning to the description of the configuration of the HDD 10 with reference to FIG. 5, the data detection unit 156 determines 0 or 1 of the sample value obtained by the addition in the addition unit 152. As described above, since the sample value obtained by the addition in the addition unit 152 has a higher SN gain than usual, the data detection unit 156 can perform binarization (0, 1 determination) with higher accuracy. Become.

  The decoding unit 160 decodes the bit value sequence binarized by the data detection unit 156. More specifically, in the present embodiment, it is assumed that the signal is recorded on the disc 21 by the LDPC code, and the decoding unit 160 decodes the LDPC code by iterative decoding. In this way, when the decoding unit 160 performs iterative decoding, a synergistic effect with the addition in the adding unit 152 is obtained. Hereinafter, this synergistic effect will be described with reference to FIGS.

  FIG. 11 is an explanatory diagram showing an SN gain predicted by employing an LDPC code and iterative decoding. The SN gain here corresponds to the difference between the SN ratio for obtaining a predetermined bit error rate and the conventional PRML system. The SN gain depends not only on the medium noise ratio but also on the normalized line density (the value obtained by normalizing the signal rise time by the bit period, also called User Bit Density: UBD), but UBD = 1. Calculated by setting to 2.

  As shown in FIG. 11, the SN gain predicted by employing the LDPC code and iterative decoding improves as the medium noise ratio increases. This is presumably due to the characteristics of medium noise in current magnetic recording and the processing method of iterative decoding.

  Specifically, in current magnetic recording, it is considered that the medium noise is caused by a variation in magnetization transition jitter or transition width. Accordingly, when the medium noise ratio is small even with the same S / N ratio, the electrical noise is dominant, and therefore the noise is superimposed on the reproduced signal equally (probably with the same amount of dispersion at any position). However, when the medium noise ratio is large, the noise is concentrated in a dense portion of magnetization transition, and there is almost no noise in a rough place.

  On the other hand, iterative decoding uses a probability propagation algorithm such as Sum-Product Algorithm, and saves information with low reliability by using highly reliable information (reproduced signal). Therefore, iterative decoding is considered more suitable when there is a dense and coarse area of noise and information on the coarse area with high reliability can be used than when noise is superimposed on average. . In addition, as described above, when the medium noise ratio is large, it is estimated that the medium noise is concentrated in a dense portion of the magnetization transition. Therefore, it is considered that iterative decoding is more advantageous as the medium noise ratio is larger. .

  Here, according to the present embodiment, as shown in FIG. 12, the medium noise ratio can be increased.

  FIG. 12 is an explanatory diagram showing how the medium noise ratio changes due to the application of this embodiment. In the present embodiment, since electrical noise and total noise can be reduced, the media noise ratio can be increased as a result, as shown in FIG. For example, the medium noise ratio that was 0.7 is improved to 0.8 or more by the present embodiment.

  Further, as described above, it is considered that iterative decoding is more advantageous as the medium noise ratio is larger. Therefore, the addition in the adder 152 of the sample value sequences A and B according to this embodiment is performed by iterative decoding as shown in FIG. The effect becomes even more pronounced. Note that the effect of doubling the sensitivity of the MR elements 70A and 70B is greater than that of the present embodiment. However, as shown by the triangular plot in FIG. It becomes possible to plan.

  FIG. 13 is an explanatory diagram showing the SN gain when iterative decoding is applied in the present embodiment. When the SN gain obtained when iterative decoding and addition of the sample value sequences A and B are applied separately, that is, when the circle plot of FIG. 10 and the plot of FIG. 11 are added, the square plot of FIG. 13 is obtained. It is done. On the other hand, in this embodiment, it is possible to obtain a higher SN gain as shown in the triangular plot of FIG. 13 by simultaneously applying iterative decoding and the addition of the sample value sequences A and B. .

[2-2] Operation of HDD The configuration of the HDD 10 according to the present embodiment has been described above with reference to FIGS. Subsequently, a signal processing method executed in the HDD 10 according to the present embodiment will be described with reference to FIG.

  FIG. 14 is a flowchart showing a flow of a signal processing method executed in the HDD 10 according to the present embodiment. As shown in FIG. 14, the HDD 10 first reads a signal from the same track of the disk 21 by the MR elements 70A and 70B (S204). Then, the HDD 10 individually performs discretization and signal processing on both signals (S208).

  Thereafter, the SMD 148A detects the Sync Mark 312 from the sample value sequence A of the signal read by the MR element 70A, and the SMD 148B detects the Sync Mark 312 from the sample value sequence B of the signal read by the MR element 70B (S212). Then, the adding unit 152 adds the sample value sequences A and B in synchronization (S216). Further, the data detection unit 156 binarizes the sample value sequence obtained by the addition in the addition unit 152, and the decoding unit 160 repeatedly decodes the bit sequence obtained by the binarization (S220).

[3] Summary As described above, the HDD 10 according to the present embodiment individually processes the signals read by the plurality of MR elements 70A and 70B, and synchronizes the bit value sequences A and B obtained by discretization. By adding them, the SN gain can be improved. Note that this embodiment in which synchronization is performed in the digital stage based on the detection of the Sync Mark 312 is advantageous in that it is necessary to appropriately control the delay amount of one signal in order to achieve synchronization in the analog stage.

  Further, according to the present embodiment, the medium noise ratio is increased as shown in FIG. For this reason, a synergistic improvement in SN gain can be realized by applying iterative decoding, which is more advantageous as the medium noise ratio is higher in this embodiment.

  In addition, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

It is an external view of HDD concerning this embodiment. It is explanatory drawing which showed the structural example of the disk contained in a disk group. It is explanatory drawing which showed the other structural example of the disk contained in a disk group. It is the 1st explanatory view showing an example of a format of a disk. It is the 2nd explanatory view showing an example of the format of a disk. It is a 3rd explanatory drawing which shows an example of the format of a disk. It is a functional block diagram showing the configuration of the HDD according to the present embodiment. It is explanatory drawing which showed the structure of the head. It is explanatory drawing which showed the signal of the analog format read by several MR element, and the sample value row | line | column. It is explanatory drawing which showed the analog signal near a data line head, and a sample value row | line | column. It is explanatory drawing which rewritten the functional block diagram shown in FIG. 5 paying attention to a signal component and a noise component. It is explanatory drawing which showed the relationship between medium noise ratio and SN gain obtained by this embodiment. It is explanatory drawing which showed SN gain estimated by adoption of an LDPC code and iterative decoding. It is explanatory drawing which showed a mode that medium noise ratio changed by application of this embodiment. It is explanatory drawing which showed SN gain at the time of applying iterative decoding in this embodiment. It is the flowchart which showed the flow of the signal processing method performed in HDD concerning this embodiment.

Explanation of symbols

10 HDD
70, 70A, 70B MR element 132A, 132B ADC
148A, 148B SMD
152 Adder 160 Decoder

Claims (3)

A plurality of MR elements of the same polarity for reading signals from the same track formed on the recording medium;
A plurality of discretization units for discretizing each of the signals read at different timings by the plurality of MR elements to obtain a plurality of sample value sequences;
A plurality of synchronization detectors for detecting a synchronization signal from each of the plurality of sample value sequences;
An adder that synchronizes and adds the plurality of sample value sequences based on synchronization detection by the plurality of synchronization detectors;
Bei to give a,
The adding unit is detected by a first synchronization detection unit of the plurality of synchronization detection units out of a first sample value sequence obtained by a first discretization unit of the plurality of discretization units. The second sample value of the plurality of synchronization detection units among the next sample value of the synchronized signal and the second sample value sequence obtained by the second discretization unit of the plurality of discretization units. Are added to the next sample value of the synchronization signal detected by the synchronization detection unit, and thereafter, the order of the sample values of the first sample value sequence and the order of the sample values of the second sample value sequence are determined. A signal processing apparatus that adds the first sample value sequence and the second sample value sequence in association with each other .   The signal processing device according to claim 1, further comprising: a decoding unit that performs iterative decoding after addition in the addition unit. Reading a signal by a plurality of MR elements having the same polarity from the same track formed on the recording medium;
Discretizing each of the signals read at different timings by the plurality of MR elements to obtain a plurality of sample value sequences;
Detecting a synchronization signal from each of the plurality of sample value sequences;
Synchronizing and adding the plurality of sample value sequences based on synchronization detection;
Only including,
In the adding step, out of the first sample value sequence obtained in the step of obtaining the plurality of sample value sequences, the next sample value of the synchronization signal detected by the step of detecting the synchronization signal; Among the second sample value sequences obtained in the step of obtaining the sample value sequence, the next sample value of the synchronization signal detected by the step of detecting the synchronization signal is added, and thereafter, the first sample value sequence is added. A signal processing method for associating the order of sample values in a sample value string with the order of sample values in the second sample value string and adding the first sample value string and the second sample value string .

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