JP5679514B2 - Inverter drive circuit - Google Patents

Description

  The present invention relates to an inverter drive circuit in which an active element such as a MOS (metal oxide semiconductor) transistor is configured as a push-pull in an output stage, and more specifically, a short-circuit breakdown is prevented by eliminating a through current of an output stage transistor. The present invention relates to an inverter drive circuit.

  In general, as an inverter drive circuit, a circuit configuration having an output stage in which a drain of a P-channel MOS transistor and a drain of an N-channel MOS transistor are connected is known. For example, the inverter driving circuit 101 shown in FIG. In the conventional inverter drive circuit 101 having this configuration, the P-channel MOS transistor TP101 of the upper arm circuit 110 or the N-channel MOS transistor of the lower arm circuit 120 is selected according to the level of the input signal Vs applied from the input terminal 130. Only one of the TN 101 is turned on, and the output signal VM obtained by inverting the input signal is output to the output terminal 140.

  Here, it is well known that a parasitic capacitance exists between the gate and the drain of the MOS transistor. That is, a parasitic capacitance CPp exists between the gate and drain of the P-channel MOS transistor TP101, and a parasitic capacitance CNp exists between the gate and drain of the N-channel MOS transistor TN101 (see FIG. 7). Since these parasitic capacitances CPp and CNp are connected to the output terminal 140, the parasitic capacitances CPp and CNp are affected by the voltage change of the output voltage VM, causing the following problems.

Along with the voltage change that occurs when the output voltage VM rises from the low level to the high level, a phenomenon occurs in which a current flows from the output voltage VM to the parasitic capacitance CNp in order to accumulate charges. By this current flow, the gate voltage of the N-channel MOS transistor TN101 is increased by the voltage drop based on the resistance value of the buffer 122 connected to the gate of the N-channel MOS transistor TN101. Therefore, the more current flows in, the greater the gate voltage rises, and there is a risk that the N-channel MOS transistor TN101 will erroneously turn on (hereinafter referred to as an erroneous on operation).
In addition, with the voltage change that occurs when the output voltage VM drops from the high level to the low level, a phenomenon occurs in which current flows from the parasitic capacitance CPp to the output voltage VM in order to release charges. By this current flow, the gate voltage of the P-channel MOS transistor TP101 is lowered by the voltage drop based on the resistance value of the buffer 112 connected to the gate of the P-channel MOS transistor TP101. Therefore, the more current flows in, the more the gate voltage drops, and the P-channel MOS transistor TP101 may be erroneously turned on.

  As described above, in the conventional inverter drive circuit 101, when a MOS transistor that should originally be turned off erroneously turns on, a through current flows through the P-channel MOS transistor TP101 and the N-channel MOS transistor TN101. Eventually there is a risk of short circuit failure. Therefore, as a technique for preventing this short-circuit breakdown, there is a technique for controlling the ON operation of the P-channel MOS transistor TP101 and the N-channel MOS transistor TN101. See, for example, US Pat.

The conventional inverter drive circuit 102 described in Patent Document 1 has the configuration shown in FIG. 8 and realizes the following control.
When the output MOS transistor TP101 of the upper arm circuit 110 is turned on and the output MOS transistor TN101 of the lower arm circuit 120 is turned off, the output MOS transistor TN101 is inserted in parallel when erroneously turned on. The sense MOS transistor TN102 also erroneously turns on at the same time. Due to the erroneous ON operation of the sense MOS transistor TN102, the output MOS transistor TP101 shifts to the OFF operation. After a while, when the output MOS transistor TN101 returns to the normal off operation, the sense MOS transistor TN102 inserted in parallel also turns off, so that the output MOS transistor TP101 returns to the normal on operation. By this control, the conventional inverter drive circuit 102 prevents short-circuit breakdown.

JP 2002-353802 A

  As described above, the conventional inverter drive circuit 102 performs control to normally return the erroneous ON operation generated in the output MOS transistor TP101 or TN101 to the OFF operation before the short-circuit breakdown of the MOS transistor occurs. .

  However, in the conventional inverter drive circuit 102, the output MOS transistor TP101 and the sense MOS transistor TP102 of the upper arm circuit 110 or the output MOS transistor TN101 and the sense MOS transistor TN102 of the lower arm circuit 120 are simultaneously turned on erroneously. I do. For this reason, there is a period in which the output MOS transistor TP101 and the output MOS transistor TN101 are simultaneously turned on, and a through current inevitably flows during that period.

  Therefore, an object of the present invention is to consider that the output transistor of the upper arm circuit and the output transistor of the lower arm circuit are simultaneously turned on by a malfunction and the through current flows while considering the influence of the parasitic capacitance existing in the transistor. It is to provide an inverter drive circuit that is prevented.

The present invention, outputs the upper arm circuits and outputs the input signal thus an upper limit voltage as a high voltage of the output signal to the output terminal, and a lower limit voltage to a low voltage thus the output signal to the input signal to the output terminal It is directed to an inverter drive circuit composed of a lower arm circuit. In order to achieve the above object, the inverter drive circuit of the present invention is configured such that each of the upper arm circuit and the lower arm circuit uses the power supply voltage applied to the source at the time of the on operation based on the input signal as the upper limit voltage or As a lower limit voltage, an output MOS transistor that outputs to the output terminal via the drain, a detection MOS transistor that turns off the output MOS transistor included in the other arm circuit at the time of on operation, and a change in voltage that appears at the output terminal are detected, and a gate voltage control unit for controlling the gate voltage of the detection MOS transistor, the gate voltage control unit is larger than the amount of change is output MOS transistors per unit time of the gate voltage with a change of the voltage appearing at the output terminal A gate voltage is input to the gate of the detection MOS transistor.
With this configuration, when the output MOS transistor tries to turn on due to a malfunction, the detection MOS transistor can be turned on first, and the output MOS transistor can be kept off.

In this inverter drive circuit, it is preferable that the switching threshold, which is a voltage level at which the detection MOS transistor is turned on , is equal to that of the output MOS transistor.
With this configuration, it becomes easy to control the base voltages of the detection MOS transistor and the output MOS transistor in the gate voltage control unit.

A typical gate voltage control unit includes a resistor R inserted between the gate of the detection MOS transistor and the gate of the output MOS transistor, and a capacitor inserted between the gate of the detection MOS transistor and the drain of the output MOS transistor. C.
With such a configuration, the gate of the output MOS transistor and the gate of the detection MOS transistor can be controlled to different voltages.

More specifically, assuming that a resistor equivalently added to the gate of the output MOS transistor is a resistor Zn, and a parasitic capacitance inserted between the gate and drain of the output MOS transistor is a capacitor Cp, the resistor R and the capacitor C may be set to a value satisfying C × (Zn + R)> Cp × Zn.
If designed in this way, the change amount per unit time of the gate voltage accompanying the change in the voltage appearing at the output terminal is necessarily larger in the detection MOS transistor than in the output MOS transistor.

The detection MOS transistor of the upper arm circuit may output the cathode voltage of a Zener diode connected to the drain via a resistor as a voltage for turning off the output MOS transistor included in the lower arm circuit. .
With this configuration, even when the power supply voltage of the upper arm circuit is high, the output from the detection MOS transistor of the upper arm circuit can be input to the lower arm circuit.

  As described above, according to the inverter drive circuit of the present invention, the output MOS transistor of the upper arm circuit and the output MOS transistor of the lower arm circuit are not simultaneously turned on by malfunction. Thereby, it is possible to prevent a through current from flowing through the output MOS transistor and the output MOS transistor.

The figure which shows the structure of the inverter drive circuit 1 which concerns on the 1st Embodiment of this invention. The figure which showed the change of each voltage in the time chart when the transistor of the upper arm circuit 10 of the inverter drive circuit 1 performs ON operation | movement The figure which showed the change of each voltage in the time chart when the transistor of the lower arm circuit 20 of the inverter drive circuit 1 performs ON operation | movement The figure which shows the equivalent circuit of the lower arm circuit 20 when considering the lower arm buffer 22 as the resistance Zn connected to the same electric potential as the source | sauce of lower arm output transistor TN1. The figure which shows the equivalent circuit which further simplified the equivalent circuit of Fig.4 (a) The figure which shows the structure of the inverter drive circuit 2 which concerns on the 2nd Embodiment of this invention. The figure which shows the structure of the conventional inverter drive circuit 101 The figure which shows the structure of the other conventional inverter drive circuit 102

Hereinafter, each embodiment of the present invention will be described with reference to the drawings.
<First Embodiment>
FIG. 1 is a diagram showing a configuration of an inverter drive circuit 1 according to the first embodiment of the present invention. In FIG. 1, the inverter drive circuit 1 according to the first embodiment includes an upper arm circuit 10 that generates an upper limit voltage (high voltage) of the output signal VM, and a lower limit voltage (low voltage) of the output signal VM. The arm circuit 20 is configured. The upper arm circuit 10 includes an upper arm driving unit 11, an upper arm buffer 12, an upper arm gate voltage control unit 13, an upper arm output transistor TP1, an upper arm detection transistor TP2, and a resistor RP3. The lower arm circuit 20 includes a lower arm driving unit 21, a lower arm buffer 22, a lower arm gate voltage control unit 23, a lower arm output transistor TN1, a lower arm detection transistor TN2, and a resistor RN3. The upper arm gate voltage control unit 13 includes a resistor RP2 and a capacitor CP, and the lower arm gate voltage control unit 23 includes a resistor RN2 and a capacitor CN.

First, the outline | summary of each structure of the inverter drive circuit 1 is demonstrated.
In the upper arm circuit 10, the upper arm drive unit 11 receives the input signal Vs given from the input terminal 30 and the detection voltage Ven output from the lower arm detection transistor TN2 of the lower arm circuit 20, and receives the input signal Vs and the detection voltage. A drive signal Vsp corresponding to Ven is output. The drive signal Vsp is a signal for switching the on operation or the off operation of the upper arm output transistor TP1 and the upper arm detection transistor TP2. The drive signal Vsp is input to the gate of the upper arm output transistor TP1 as the gate voltage Vgp after passing through the upper arm buffer 12. The drive signal Vsp is input to the gate of the upper arm detection transistor TP2 as the gate voltage Vgp ′ after passing through the upper arm buffer 12 and the resistor RP2.

  The upper arm output transistor TP1 is typically a P-channel type MOS transistor. The upper arm output transistor TP1 has a gate voltage Vgp input to the gate, a power supply voltage VH applied to the source, and a drain connected to the output terminal 40. In the upper arm output transistor TP1, a parasitic capacitance CPp (drawn with a dotted line) exists between the gate and the drain. When the gate voltage Vgp input to the gate is at a voltage level for turning on the transistor, the upper arm output transistor TP1 conducts between the source and the drain to raise the output voltage VM appearing at the output terminal 40 to the power supply voltage VH.

  The upper arm detection transistor TP2 is typically a P-channel MOS transistor and has switching characteristics equivalent to those of the upper arm output transistor TP1. In the upper arm detection transistor TP2, the gate voltage Vgp 'is input to the gate, the power supply voltage VH is applied to the source, and the drain is grounded through the resistor RP3. Although the upper arm detection transistor TP2 also has a parasitic capacitance between the gate and the drain, it does not directly affect the operation of the present invention, and therefore description and explanation regarding the parasitic capacitance are omitted. When the gate voltage Vgp ′ input to the gate is at a voltage level for turning on the transistor, the upper arm detection transistor TP2 conducts between the source and the drain to generate a detection voltage Vep corresponding to the resistor RP3 at the drain. This detection voltage Vep is applied to the lower arm circuit 20.

  In the lower arm circuit 20, the lower arm drive unit 21 receives the input signal Vs given from the input terminal 30 and the detection voltage Vep outputted from the upper arm detection transistor TP2 of the upper arm circuit 10, and receives the input signal Vs. A drive signal Vsn corresponding to the detection voltage Vep is output. This drive signal Vsn is a signal for switching on / off operation of the lower arm output transistor TN1 and the lower arm detection transistor TN2. The drive signal Vsn is inputted to the gate of the lower arm output transistor TN1 as the gate voltage Vgn after passing through the lower arm buffer 22. The drive signal Vsn is input to the gate of the lower arm detection transistor TN2 as the gate voltage Vgn ′ after passing through the lower arm buffer 22 and the resistor RN2.

  The lower arm output transistor TN1 is typically an N-channel MOS transistor. In the lower arm output transistor TN1, the gate voltage Vgn is input to the gate, the power supply voltage VG (VG <VH) is applied to the source, and the drain is connected to the output terminal 40. The lower arm output transistor TN1 has a parasitic capacitance CNp (drawn with a dotted line) between the gate and the drain. When the gate voltage Vgn input to the gate is at a voltage level for turning on the transistor, the lower arm output transistor TN1 conducts between the source and the drain to lower the output voltage VM appearing at the output terminal 40 to the power supply voltage VG.

  The lower arm detection transistor TN2 is typically an N-channel MOS transistor and has switching characteristics equivalent to those of the lower arm output transistor TN1. In the lower arm detection transistor TN2, the gate voltage Vgn 'is input to the gate, the power supply voltage VG is applied to the source, and the drain is connected to the power supply voltage VL (VG <VL <VH) via the resistor RN3. Although the lower arm detection transistor TN2 also has a parasitic capacitance between the gate and the drain, it does not directly affect the operation of the present invention, and therefore description and explanation regarding the parasitic capacitance are omitted. When the gate voltage Vgn ′ input to the gate is at a voltage level for turning on the transistor, the lower arm detection transistor TN2 conducts between the source and the drain and generates a detection voltage Ven corresponding to the resistor RN3 at the drain. This detection voltage Ven is given to the upper arm circuit 10.

  Next, the process performed by the inverter drive circuit 1 will be described in detail with further reference to FIGS. FIG. 2 is a time chart showing changes in each voltage when the transistor of the upper arm circuit 10 of the inverter drive circuit 1 is turned on. FIG. 3 is a time chart showing changes in each voltage when the transistor of the lower arm circuit 20 of the inverter drive circuit 1 performs the on operation.

  First, with reference to FIG. 2, a process when the transistor of the upper arm circuit 10 performs the on operation will be described. In the following description, it is assumed that the transistor of the lower arm circuit 20 is on according to the high level input signal Vs.

  When the input signal Vs changes from the high level to the low level ((1) in FIG. 2), the lower arm drive unit 21 changes the output drive signal Vsn from the high level to the low level ((2) in FIG. 2). . In accordance with the change of the drive signal Vsn, the gate voltage Vgn output from the lower arm buffer 22 also gradually changes from the high level to the low level, and at the same time, the gate voltage Vgn ′ via the resistor RN2 gradually increases from the high level to the low level. ((3) in FIG. 2). Note that the gate voltage Vgn ′ changes more slowly than the gate voltage Vgn due to the influence of the time constant generated by the resistor RN2.

  When the gate voltage Vgn changes from the high level to the low level and reaches the threshold value of the lower arm output transistor TN1, the lower arm output transistor TN1 switches from the on operation to the off operation. Due to this switching of operation, the source and drain of the lower arm output transistor TN1 become non-conductive. When the gate voltage Vgn ′ changes from the high level to the low level and reaches the threshold value of the lower arm detection transistor TN2, the lower arm detection transistor TN2 also switches from the on operation to the off operation. Due to this switching of operation, the source and drain of the lower arm detection transistor TN2 become non-conductive, and the power supply voltage VL appears at the drain of the lower arm detection transistor TN2 via the resistor RN3. Therefore, the detection voltage Ven which has been at the low level (power supply voltage VG) is changed to the high level (power supply voltage VL) ((4) in FIG. 2) and is supplied to the upper arm drive unit 11 of the upper arm circuit 10. .

  The upper arm drive unit 11 receives the input signal Vs changed to the low level and the detection voltage Ven changed to the high level, and changes the output drive signal Vsp from the high level to the low level ((5) in FIG. 2). ). In accordance with the change of the drive signal Vsp, the gate voltage Vgp output from the upper arm buffer 12 also gradually changes from the high level to the low level, and at the same time, the gate voltage Vgp ′ via the resistor RP2 gradually increases from the high level to the low level. ((6) in FIG. 2). Note that the difference between the gate voltage Vgp and the gate voltage Vgp 'is due to the influence of the time constant generated by the resistor RP2.

  When the gate voltage Vgp changes from the high level to the low level and reaches the threshold value of the upper arm output transistor TP1, the upper arm output transistor TP1 switches from the off operation to the on operation. Due to the switching of the operation, the source-drain of the upper arm output transistor TP1 becomes conductive, the drive current corresponding to the power supply voltage VH flows to the output terminal 40, and the output voltage VM rises ((7) in FIG. 2). . This increase in the output voltage VM causes the lower arm circuit 20 to increase the gate voltage Vgn via the parasitic capacitance CNp and raise the gate voltage Vgn ′ via the capacitance CN ((8) in FIG. 2).

  Here, the amount of change (increase amount) per unit time of the gate voltage Vgn ′ is the amount of change (increase amount) per unit time of the gate voltage Vgn ′ in accordance with the mathematical formula described later. ) To be larger than As a result, since the gate voltage Vgn ′ of the lower arm detection transistor TN2 first exceeds the switching threshold ((8) in FIG. 2), both of them having the same switching characteristics are detected by the lower arm before the lower arm output transistor TN1. The transistor TN2 is turned on.

  By this ON operation, the source and the drain of the lower arm detection transistor TN2 become conductive, and the detection voltage Ven that has been at a high level changes to a low level ((9) in FIG. 2). The upper arm drive unit 11 changes the output drive signal Vsp from the low level to the high level in response to the change of the detection voltage Ven to the low level ((10) in FIG. 2). In accordance with the change of the drive signal Vsp, the gate voltage Vgp output from the upper arm buffer 12 also changes from the low level to the high level. When the gate voltage Vgp changes from the low level to the high level and reaches the threshold value of the upper arm output transistor TP1, the upper arm output transistor TP1 is switched from the on operation to the off operation. By this switching of operation, the source and drain of the upper arm output transistor TP1 become non-conductive, the drive current corresponding to the power supply voltage VH does not flow to the output terminal 40, and the increase of the output voltage VM is stopped ((( 11)). When the increase of the output voltage VM stops, the lower arm circuit 20 does not increase the gate voltage Vgn via the parasitic capacitance CNp and the gate voltage Vgn ′ via the capacitance CN ((12) in FIG. 2).

  By eliminating the increase in the gate voltage Vgn ′, the lower arm detection transistor TN2 switches from the on operation to the off operation in accordance with the original gate voltage Vgn ′ output from the lower arm buffer 22 and via the resistor RN2, and again becomes high. The level detection voltage Ven is output to the upper arm drive unit 11 ((13) in FIG. 2). On the other hand, the lower arm output transistor TN1 maintains the off operation state according to the original gate voltage Vgn output from the lower arm buffer 22 ((14) in FIG. 2).

  Thereafter, until the output voltage VM reaches the power supply voltage VH, “(i) Upper arm output transistor TP1: ON operation → (ii) Lower arm detection transistor TN2: ON operation → (iii) Upper arm output transistor TP1: OFF operation → The process of (iv) Lower arm detection transistor TN2: OFF operation → (i) ”is repeated ((15) in FIG. 2). When the output voltage VM reaches the power supply voltage VH and the voltage is stabilized ((16) in FIG. 2), the upper arm output transistor TP1 is stabilized in the on operation and the lower arm output transistor TN1 is deactivated (in FIG. 2). (17)).

  As described above, in the process in which the transistor of the upper arm circuit 10 is turned on, the output voltage VM is in the process of rising, and if the lower arm output transistor TN1 is likely to be erroneously turned on via the parasitic capacitor CNp, the capacitor CN First, the lower arm detection transistor TN2 is forcibly erroneously turned on via Accordingly, the lower arm output transistor TN1 can be returned to a normal switching operation according to the gate voltage Vgn output from the lower arm buffer 22 without erroneously turning on the parasitic capacitor CNp.

  Next, with reference to FIG. 3, a process when the transistor of the lower arm circuit 20 performs the on operation will be described. In the following description, it is assumed that the transistor of the upper arm circuit 10 has been turned on according to the low-level input signal Vs.

  When the input signal Vs changes from the low level to the high level ((1) in FIG. 3), the upper arm driver 11 changes the output drive signal Vsp from the low level to the high level ((2) in FIG. 3). . In accordance with the change of the drive signal Vsp, the gate voltage Vgp output from the upper arm buffer 12 also gradually changes from the low level to the high level, and at the same time, the gate voltage Vgp ′ via the resistor RP2 gradually increases from the low level to the high level. ((3) in FIG. 3). Note that the gate voltage Vgp ′ changes more slowly than the gate voltage Vgp due to the influence of the time constant generated by the resistor RP2.

  When the gate voltage Vgp changes from the low level to the high level and reaches the threshold value of the upper arm output transistor TP1, the upper arm output transistor TP1 is switched from the on operation to the off operation. Due to this switching of operation, the source and drain of the upper arm output transistor TP1 become non-conductive. When the gate voltage Vgp ′ changes from the low level to the high level and reaches the threshold value of the upper arm detection transistor TP2, the upper arm detection transistor TP2 is also switched from the on operation to the off operation. Due to the switching of the operation, the source and the drain of the upper arm detection transistor TP2 become non-conductive, and the drain of the upper arm detection transistor TP2 becomes the ground level. Therefore, the detection voltage Vep, which has been at the high level (power supply voltage VH), changes to the low level (GND) ((4) in FIG. 3) and is supplied to the lower arm drive unit 21 of the lower arm circuit 20.

  The lower arm drive unit 21 receives the input signal Vs changed to high level and the detection voltage Vep changed to low level, and changes the output drive signal Vsn from low level to high level ((5) in FIG. 3). ). In accordance with the change of the drive signal Vsn, the gate voltage Vgn output from the lower arm buffer 22 also gradually changes from the low level to the high level, and at the same time, the gate voltage Vgn ′ via the resistor RN2 gradually increases from the low level to the high level. ((6) in FIG. 3). Note that the difference between the gate voltage Vgn and the gate voltage Vgn 'is due to the influence of the time constant generated by the resistor RN2.

  When the gate voltage Vgn changes from the low level to the high level and reaches the threshold value of the lower arm output transistor TN1, the lower arm output transistor TN1 is switched from the off operation to the on operation. As a result of this switching, the source and drain of the lower arm output transistor TN1 become conductive, a drive current corresponding to the power supply voltage VG flows from the output terminal 40, and the output voltage VM decreases ((7) in FIG. 3). . This drop in the output voltage VM causes the upper arm circuit 10 to lower the gate voltage Vgp via the parasitic capacitance CPp and lower the gate voltage Vgp ′ via the capacitance CP ((8) in FIG. 3).

  Here, the resistance value of the resistor RP2 and the capacitance value of the capacitor CP are changed in accordance with a mathematical expression described later. ) To be larger than Thus, since the gate voltage Vgp ′ of the upper arm detection transistor TP2 first exceeds the switching threshold ((8) in FIG. 3), both of the switching characteristics are the same before the upper arm output transistor TP1. The transistor TP2 is turned on.

  By this ON operation, the source-drain of the upper arm detection transistor TP2 becomes conductive, and the detection voltage Vep that has been at a low level changes to a high level ((9) in FIG. 3). The lower arm drive unit 21 changes the drive signal Vsn to be output from the high level to the low level in response to the change of the detection voltage Vep to the high level ((10) in FIG. 3). In accordance with the change of the drive signal Vsn, the gate voltage Vgn output from the lower arm buffer 22 also changes from the high level to the low level. When the gate voltage Vgn changes from the high level to the low level and reaches the threshold value of the lower arm output transistor TN1, the lower arm output transistor TN1 is switched from the on operation to the off operation. Due to this switching of operation, the source and drain of the lower arm output transistor TN1 become non-conductive, the drive current corresponding to the power supply voltage VG does not flow from the output terminal 40, and the decrease in the output voltage VM is stopped ((( 11)). When the fall of the output voltage VM stops, the upper arm circuit 10 does not drop the gate voltage Vgp via the parasitic capacitance CPp and the gate voltage Vgp ′ via the capacitance CP ((12) in FIG. 3).

  By eliminating the decrease in the gate voltage Vgp ′, the upper arm detection transistor TP2 is switched from the on operation to the off operation in accordance with the original gate voltage Vgp ′ output from the upper arm buffer 12 and through the resistor RP2, and is again low. The level detection voltage Vep is output to the lower arm drive unit 21 ((13) in FIG. 3). On the other hand, the upper arm output transistor TP1 maintains the OFF operation state according to the original gate voltage Vgp output from the upper arm buffer 12 ((14) in FIG. 3).

  Thereafter, until the output voltage VM reaches the power supply voltage VG, “(i) Lower arm output transistor TN1: ON operation → (ii) Upper arm detection transistor TP2: ON operation → (iii) Lower arm output transistor TN1: OFF operation → The process of (iv) Upper arm detection transistor TP2: OFF operation → (i) ”is repeated ((15) in FIG. 3). When the output voltage VM reaches the power supply voltage VG and the voltage is stabilized ((16) in FIG. 3), the lower arm output transistor TN1 is stabilized in the on operation and the upper arm output transistor TP1 is deactivated (in FIG. 3). (17)).

  As described above, in the process in which the transistor of the lower arm circuit 20 is turned on, the output voltage VM is in a decreasing process, and when the upper arm output transistor TP1 is likely to be erroneously turned on via the parasitic capacitance CPp, the capacitance CP First, the upper arm detection transistor TP2 is forcibly erroneously turned on via As a result, the upper arm output transistor TP1 can be returned to a normal switching operation according to the gate voltage Vgp output from the upper arm buffer 12 without erroneously turning on the parasitic capacitance CPp.

Next, the principle that the gate voltages of the output transistor and the detection transistor change as the output voltage VM changes will be described with further reference to FIGS.
In this embodiment, the principle of the lower arm output transistor TN1 and the lower arm detection transistor TN2 of the lower arm circuit 20 will be described, but the same applies to the upper arm output transistor TP1 and the upper arm detection transistor TP2 of the upper arm circuit 10. .

  FIG. 4 is a diagram showing an equivalent circuit of the lower arm circuit 20 when the lower arm buffer 22 is regarded as a resistor Zn connected to the same potential as the source of the lower arm output transistor TN1. FIG. 4A is an equivalent circuit for the lower arm output transistor TN1, and FIG. 4B is an equivalent circuit for the lower arm detection transistor TN2. The resistor ZTN1 is a resistance value of the lower arm output transistor TN1. However, when determining the influence of the parasitic capacitance CNp when the lower arm output transistor TN1 is in the OFF operation, the resistor ZTN1 can be regarded as infinite, and therefore the equivalent circuit of FIG. 4A is the same as that of FIG. It can be simplified to an equivalent circuit.

First, the operation of the equivalent circuit shown in FIG. 5A is confirmed by qualitative consideration.
When the output voltage VM rises, a current I1 flows from the output voltage VM toward the ground, and charges are accumulated in the parasitic capacitance CNp. The voltage obtained by the product of the current I1 flowing at this time and the resistance Zn is the gate voltage Vgn (Vgn = I1 × Zn). Therefore, the gate voltage Vgn increases as the resistance Zn increases. That is, the gate voltage Vgn depends on the value of the resistor Zn. Further, the gate voltage Vgn increases as the current I1 increases. This current I1 is determined according to the magnitude of the parasitic capacitance CNp. If the parasitic capacitance CNp is large, the amount of charge to be accumulated increases. Therefore, the current defined by the amount of moving charge per unit time increases. That is, the gate voltage Vgn depends on the magnitude of the parasitic capacitance CNp. Further, when the rate of change of the output voltage VM is large, the voltage changes greatly in a short time, so that the change of the current I1 also increases. That is, the gate voltage Vgn depends on the rate of change of the output voltage VM.

Next, the operation of the equivalent circuit shown in FIG.
Given that the output voltage VM at a certain time t is VM (t), the voltage applied to the parasitic capacitor CNp is VCNp, and the voltage applied to the resistor Zn is VZn, the following equation [1] is used to obtain the output voltage VM by the Kirchhoff voltage side. Is obtained.

When this equation [1] is differentiated with respect to time t, the voltage change rate is obtained, and the following equation [2] is obtained.

Here, if the parasitic capacitance CNp and the resistance Zn are constants that do not depend on time, voltage, current, and charge, the equation [2] can be expressed as the following equation [3].

Now, the output voltage VM starts to gradually increase (the upper arm output transistor TP1 is turned on) from the state where the power supply voltage VG = 0 V (the upper arm output transistor TP1 is turned off and the lower arm output transistor TN1 is turned on). And the case where the lower arm output transistor TN1 shifts to the off operation). When the output voltage VM changes linearly with respect to time t with the proportionality constant VP, it is expressed by the following equation [4].

Substituting equation [4] into equation [3] and rearranging results in differential equation [5].

This equation [5] is transformed into the following equation [6].

When QCNp (t) is solved for the equation [6] using the integration constants D1 and D2 with the time t as a variable, the following equation [7] is obtained.

Since the current I1 is I1 = dQCNp / dt, the equation [7] is differentiated by the time t to obtain the current. D3 is an integral constant.

Here, at time t = 0, since the output voltage VM does not change, the current I1 is also zero. Therefore, by substituting t = 0 into the equation [8], the integral constant D3 is obtained from the equation [9] from I1 (t) = 0.

Therefore, when this equation [9] is substituted into equation [8] and I1 (t) is rearranged, equation [10] is obtained.

Therefore, the gate voltage Vgn is obtained by the equation [11].

  Thus, in the obtained equation [11], the gate voltage Vgn is proportional to the value of the resistor Zn, is proportional to the magnitude of the parasitic capacitance CNp, and is further proportional to the rate of change of the output voltage VM. This result is consistent with the content of the qualitative consideration described above.

This arithmetic expression is the same for the gate voltage Vgn ′ of the lower arm detection transistor TN2, and when the lower arm output transistor TN1 is in the off operation, the resistor ZTN1 can be regarded as infinite, so the equivalent circuit is shown in FIG. To FIG. 5 (b). Therefore, by replacing the resistor Zn in the above equation [11] with the resistor Zn + ZRN2 and the parasitic capacitor CNp with the capacitor CN, an equation for calculating the gate voltage Vgn ′ is obtained as shown in the following equation [12].

この式［１３］を満足させる値で抵抗ＲＮ２及び容量ＣＮを設定すれば、常に下アーム出力トランジスタＴＮ１よりも先に下アーム検出トランジスタＴＮ２がオン動作することになる。 From the equations [11] and [12] thus obtained, the amount of change (increase amount) per unit time of the gate voltage Vgn ′ is larger than the amount of change (increase amount) of the gate voltage Vgn per unit time. As a condition for achieving this, the following equation [13] is obtained.

If the resistor RN2 and the capacitor CN are set with values satisfying the equation [13], the lower arm detection transistor TN2 is always turned on before the lower arm output transistor TN1.

  As described above, according to the inverter drive circuit 1 according to the first embodiment of the present invention, the base voltage is applied to the base of each detection transistor via the resistor and is connected to the output voltage VM via the capacitor. To do. With this configuration, even when the gate voltage rises or falls as the output voltage VM changes, the detection transistor is turned on earlier than the output transistor so that the change in the gate voltage is reversed. . Therefore, in the inverter drive circuit 1, since the upper arm output transistor and the lower arm output transistor are not simultaneously turned on, it is possible to prevent a through current from flowing.

<Second Embodiment>
In the first embodiment, when the upper arm detection transistor TP2 is turned on, the detection voltage Vep appearing at the drain of the upper arm detection transistor TP2 is at a high level substantially equivalent to the power supply voltage VH. For this reason, when the power supply voltage used in the lower arm drive unit 21 is equal to or lower than the power supply voltage VH, if the high level detection voltage Vep is applied to the lower arm drive unit 21 as it is, there is a possibility that the operation is not performed normally. .
Therefore, in the second embodiment, a configuration of an inverter drive circuit that applies the detection voltage Vep to a level used in the lower arm drive unit 21 will be described.

  FIG. 6 is a diagram showing a configuration of the inverter drive circuit 2 according to the second embodiment of the present invention. In FIG. 6, the inverter drive circuit 2 according to the second embodiment includes an upper arm circuit 50 that generates an upper limit voltage of the output signal VM and a lower arm circuit 20 that generates a lower limit voltage of the output signal VM. The upper arm circuit 50 includes an upper arm driving unit 11, an upper arm buffer 12, an upper arm gate voltage control unit 13, an upper arm output transistor TP1, an upper arm detection transistor TP2, a resistor RP4, and a Zener diode DP. The lower arm circuit 20 includes a lower arm driving unit 21, a lower arm buffer 22, a lower arm gate voltage control unit 23, a lower arm output transistor TN1, a lower arm detection transistor TN2, and a resistor RN3.

  The inverter drive circuit 2 according to the second embodiment differs from the inverter drive circuit 1 according to the first embodiment in the configuration of the resistor RP4 and the Zener diode DP in the upper arm circuit 50. Since the other configuration of the inverter drive circuit 2 according to the second embodiment is the same as that of the inverter drive circuit 1 according to the first embodiment, the same reference numerals are attached and the outline description of the configuration is omitted. . In addition, the principle that the gate voltage of the output transistor and the detection transistor changes due to the process performed by the inverter drive circuit 2 according to the second embodiment and the change of the output voltage VM is also the inverter drive circuit according to the first embodiment. The description is omitted because it is the same as 1.

  The drain of the upper arm detection transistor TP2 is connected to the ground (GND) via a resistor RP4 and a Zener diode DP connected in series. The Zener diode DP has an anode connected to the ground (GND) and a cathode connected to the resistor RP4. The detection voltage Vep applied to the lower arm circuit 20 is a voltage that appears at the connection point between the resistor RP4 and the Zener diode DP.

  With the configuration of the resistor RP4 and the Zener diode DP, the detection voltage Vep that appears at the drain of the upper arm detection transistor TP2 that has been turned on becomes the Zener voltage that the Zener diode DP has regardless of the power supply voltage VH that is applied to the source. Therefore, if the Zener voltage of the Zener diode DP is appropriately set, even if the power supply voltage used in the lower arm drive unit 21 is equal to or lower than the power supply voltage VH, the lower arm drive unit 21 can operate normally with respect to the detection voltage Vep. It can be carried out.

  As described above, according to the inverter drive circuit 2 according to the second embodiment of the present invention, the high level of the detection voltage Vep output from the upper arm detection transistor TP2 to the lower arm drive unit 21 is set. As a result, regardless of the power supply voltage VH applied to the upper arm detection transistor TP2, the detection voltage Vep at a voltage level at which the lower arm drive unit 21 can operate normally can be applied to the lower arm drive unit 21.

  The configuration of the present invention can be used for an inverter drive circuit or the like in which a MOS transistor is configured as a push-pull in an output stage, particularly when it is desired to prevent a short-circuit breakdown by eliminating a through current due to the simultaneous ON operation of output stage transistors. Useful for.

1, 2, 101 Inverter driving circuit 10, 110 Upper arm circuit 11, 111 Upper arm driving unit 12, 112 Upper arm buffer 13 Upper arm gate voltage control unit 20, 120 Lower arm circuit 21, 121 Lower arm driving unit 22, 122 Lower arm buffer 23 Lower arm gate voltage controller 30, 40, 130, 140 Terminals CN, CNp, CP, CPp Capacitance DP Zener diodes RN2, RN3, RN103, RP2-RP4, RP103, Zn, ZTN1 Resistance TN1, TN101 Lower arm Output transistors TN2, TN102 Lower arm detection transistors TP1, TP101 Upper arm output transistors TP2, TP102 Upper arm detection transistors

Claims (5)

The upper arm circuits and outputs the input signal thus an upper limit voltage as a high voltage of the output signal to the output terminal, and the input signal thus a lower limit voltage to a low voltage of the output signal in the lower arm circuit to be output to the output terminal An inverter drive circuit comprising:
The upper arm circuit and the lower arm circuit are respectively
An output MOS transistor that outputs a power supply voltage applied to a source as the upper limit voltage or the lower limit voltage to the output terminal via a drain during an ON operation based on the input signal;
A detection MOS transistor for turning off the output MOS transistor included in the other arm circuit during the on operation;
A change in voltage appearing at the output terminal, and a gate voltage control unit for controlling the gate voltage of the detection MOS transistor,
The gate voltage control unit, the amount of change per unit time of the gate voltage with a change in the voltage appearing at the output terminal a higher gate voltage than before SL output MOS transistor is input to the gate of the detection MOS transistor, Inverter drive circuit. Said detection MOS transistor is characterized in that the switching threshold is the voltage level of the ON operation is the output MOS transistor and the like, an inverter driving circuit according to claim 1. The gate voltage controller is
A resistor R inserted between the gate of the detection MOS transistor and the gate of the output MOS transistor;
2. The inverter drive circuit according to claim 1, further comprising a capacitor C inserted between the gate of the detection MOS transistor and the drain of the output MOS transistor. Assuming that a resistor equivalently added to the gate of the output MOS transistor is a resistor Zn, and a parasitic capacitance inserted between the gate and drain of the output MOS transistor is a capacitor Cp, the resistor R and the capacitor C are as follows. The inverter drive circuit according to claim 3, wherein the inverter drive circuit is set to a value satisfying the expression.
C × (Zn + R)> Cp × Zn   The detection MOS transistor of the upper arm circuit outputs a cathode voltage of a Zener diode connected to a drain via a resistor as a voltage for turning off the output MOS transistor included in the lower arm circuit. The inverter drive circuit according to 1.

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