JP5672111B2 - Ultrasonic diagnostic equipment - Google Patents

Description

  The present invention relates to a beam former that performs phasing addition of signals obtained by transmitting and receiving ultrasonic waves. The present invention also relates to an ultrasonic diagnostic apparatus that displays an ultrasonic tomographic image having a beamformer, and an image generation method based on phasing and addition signals.

  As a conventional beam former of an ultrasonic diagnostic apparatus, there is one in which a delay in units of a sampling period is executed by controlling a time for reading data from a memory, and a more precise delay within the sampling period is generated by interpolation data. (For example, see Patent Document 1).

  FIG. 2 shows a conventional ultrasonic diagnostic apparatus described in Patent Document 1. In FIG.

  The ultrasonic diagnostic apparatus in FIG. 2 converts an ultrasonic signal received by the probe 1 from an analog signal to a digital signal by the A / D converters 21 to 2n for each reception channel. Then, the received signal converted into the digital signal is subjected to beam forming by adjusting the phase by the delay circuit from the first channel delay circuit 31 to the n-th channel delay circuit 3n and adding by the adder circuit 4. The sound ray signal is generated. Then, using the generated sound ray signal, the signal processing unit 5 converts the sound ray signal into an image, and the display unit 6 displays an ultrasonic image.

  FIG. 3 is a block diagram of the first channel delay circuit 31 in FIG. The received signal converted into a digital signal by the A / D converter 21 is stored in the memory 7 as data of the sampling interval ΔT of the A / D converter. Then, four digital data having a sampling time in the vicinity of a time T1 that is an integral multiple of the sampling interval ΔT and a time shifted by τ1 smaller than T1 from a certain target time T0 is read from the memory 7 and read out from the data register. 91-94. The multipliers 101 to 104 multiply the four digital data stored in the memory 7 by predetermined weighting factors w1 to w4. The adder 11 calculates delay interpolation data by adding the digital data multiplied by a predetermined weight.

  Here, it is described that the interpolation coefficients of the mixed spline interpolation are set for the predetermined weighting coefficients w1 to w4, respectively, and that the virtual time can be set to the previous time by T1 + τ1 by appropriately setting the interpolation coefficients. Yes.

  As described above, Patent Document 1 discloses that, using mixed spline interpolation, delay interpolation data is calculated using data at four points before and after the interpolation point among sampling time data.

Japanese Patent No. 3283053

  However, in the conventional configuration, when digital data at the target time tk is obtained, interpolation or mixed spline interpolation is used using four points of data near the sampling time tk. In such a high frequency, when the values of adjacent points are greatly different, there is a problem that accuracy is lowered.

  The present invention solves the above-described conventional problems. Compared to the conventional technique, the present invention solves the above-described problem, and performs a stratified addition process with higher accuracy while suppressing the amount of calculation. The purpose is to provide.

In order to solve the above-described conventional problems, an ultrasonic diagnostic apparatus of the present invention includes an ultrasonic probe having a plurality of receiving elements and a reception signal obtained from the ultrasonic probe at a predetermined sampling interval ΔT. An A / D converter that performs sampling and generates time-series digital data; a memory that stores digital data generated by the A / D converter; and a beamform unit that performs a delay process on the digital data; the a, the beam form unit, said a delay calculator for calculating a delay time between reception focus point from the position of the receiving element, from the focus position address memory the address of the reception signal from the reception focusing point specify the read start address for reading the digital data, add the digital data to include the focus position address An address controller for selecting a source, a delay control unit including a coefficient calculation unit for calculating a correction coefficient corresponding to the selected digital data, and an all-pass filter process for the digital data corresponding to the selected address. An all-pass filter processing unit is provided.

  With this configuration, a highly accurate phasing addition process can be performed by performing an all-pass filter process for performing an accurate delay process.

  In the ultrasonic diagnostic apparatus of the present invention, the all-pass filter in the all-pass filter processing unit is a primary all-pass filter.

  With this configuration, the calculation amount of the all-pass filter process can be reduced.

  The ultrasonic diagnostic apparatus of the present invention is characterized in that the address controller designates the address so that digital data corresponding to the focus position address is located at a final address of the selected digital data. Have.

  With this configuration, the accuracy of data at the focus point is increased when delay addition is performed at one normal focus point.

  The ultrasonic diagnostic apparatus of the present invention is characterized in that the address controller designates an address so that digital data corresponding to the focus position address is present at a substantially central position of the selected digital data. .

  This configuration provides the best accuracy when all the data to be read is used.

  In the ultrasonic diagnostic apparatus of the present invention, the address controller designates the address so that digital data corresponding to the focus position address is located in the latter half of the center position of the selected digital data. It has the characteristics.

  This configuration improves the accuracy when using a plurality of points near the focus point.

  The ultrasonic diagnostic apparatus of the present invention is characterized in that the address controller designates an address based on the delay time so that the length of designated digital data changes.

  With this configuration, the number of data used for the all-pass filter can be changed by the coefficient of the all-pass filter.

  In the ultrasonic diagnostic apparatus according to the present invention, the address controller may select the first delay time when the decimal part of the delay time is larger than the second delay time when the first delay time is larger than the second delay time. The address is designated such that the length of the data is longer than the length of the digital data selected for the second delay time.

  With this configuration, the calculation amount of the all-pass filter process can be made efficient.

  In the ultrasonic diagnostic apparatus of the present invention, when the fractional part of the delay time is 0.95 or more, the coefficient calculation unit sets the correction coefficient to 0, and the all-pass filter processing unit sets the delay amount of the integer part to +1. It has the feature that.

  With this configuration, it is possible to reduce the amount of calculation in a portion where the amount of calculation is required to obtain an accurate value of the all-pass filter.

  According to the beamformer having the precise delay control unit of the present invention, it is possible to perform phasing addition processing with higher accuracy than in the past. Therefore, it is possible to improve the image quality of an ultrasonic image in an ultrasonic apparatus that generates an image using a signal subjected to phasing addition using this beamformer.

The block diagram of the beam form part in Embodiment 1 of this invention Block diagram of ultrasonic wave diagnostic apparatus in Embodiment 1 of the present invention Block diagram of conventional delay circuit (A) Conceptual diagram of reception dynamic focus processing, (b) A diagram showing a received signal obtained by the receiving element b, (c) A diagram showing a received signal obtained by the receiving element c, (d) Obtained by the receiving element b The figure which shows the signal which delayed the received signal (A) The figure which shows receiving sampling data, (b) The figure which shows the sampling data after performing all-pass filter processing The block diagram of the delay control part in Embodiment 1 of this invention Diagram showing the positional relationship between the selected digital data and the focus point Diagram showing the output of the all-pass filter depending on the delay amount Diagram showing the number of data until convergence by all-pass filter coefficients

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 2 is a block diagram of the ultrasonic diagnostic apparatus according to Embodiment 1 of the present invention.

  The analog ultrasonic signal input from the probe 1 is converted from an analog signal to a digital signal by the A / D converters 21 to 2n. The delay circuits from the first channel delay circuit 31 to the n-th channel delay circuit 3n perform beam forming by adjusting the phase of the received signal converted into the digital signal and adding it by the adder circuit 4. In this way, the sound ray signal is generated, the sound processing unit 5 converts the sound ray signal into an image, and the display unit 6 displays the ultrasonic image.

  The ultrasonic diagnostic apparatus performs reception dynamic focus processing while scanning the focus point from the vicinity of the receiving element to the deep part, and generates one line of the sound ray signal to be drawn by the ultrasonic diagnostic apparatus.

  Here, the reception dynamic focus processing in which the phase adjustment is performed by the delay circuit will be described with reference to FIGS. When a focus point that is a distance a from the center of the aperture is drawn using a plurality of reception element signals, a delay amount from the focus point to each reception element is obtained. For example, the receiving element b at the center of the aperture receives the received signal earliest (see (b) in the upper right of FIG. 4). The farthest receiving element c receives the received signal with a delay of time d compared to the receiving element b (see (c) in the middle right of FIG. 4). In this case, if the received signal b is delayed by d and the signal shown in FIG. 4D and the signal shown in FIG. 4C are added, the phases of the two signals become in-phase, and the level of the received signal can be increased. it can. In this way, the delay processing calculates the delay amount of the signal received by each receiving element from the position of the focus point and the positional relationship (distance) of the receiving element, and delays and adds the signal by the delay amount, Increase the small reflected signal.

  Here, since the received signal is digital data, when the theoretical value d of the delay amount has a decimal point, for example, 6.4 samples (the white circle in FIG. 5 indicates the theoretical value of the delay amount, In general, the digital signal of the sixth sample is approximated or used, or the values of two adjacent sampling points are used by using an interpolation process or the like. The value of the sample was calculated by interpolation calculation. Therefore, accurate delay processing cannot be performed.

  In the present embodiment, all-pass filter processing is performed on received data in order to improve the accuracy of the phasing addition processing. The all-pass filter is a filter that changes only the phase characteristic without changing the amplitude characteristic. By using an all-pass filter, it is more appropriate to change the phase corresponding to the delay value (hereinafter referred to as the decimal part) that is shifted by a sampling period or less from a point that is an integral multiple of the sampling frequency (hereinafter referred to as the sampling point). It is possible to perform delay processing.

  However, performing all-pass filtering increases the accuracy of delay processing, but increases the amount of calculation required for phasing addition. In particular, in the case of an ultrasonic diagnostic apparatus, the signal is a spherical wave region in order to see a short distance. Therefore, it is necessary to perform an all-pass filter process for each focus point. Therefore, there arises a problem that the calculation amount is greatly increased. The focus point means each drawing point where drawing is performed by the ultrasonic diagnostic apparatus.

  Therefore, the beamform unit of the present invention uses the focus point address to determine data to be subjected to all-pass filtering.

  FIG. 1 is a block diagram of a beamform unit (delay circuit) according to Embodiment 1 of the present invention. The beamform unit receives the memory 7 that stores the digital reception signal input from the A / D converter, the data register 13 that stores the digital data to be subjected to the all-pass filter processing, and the data stored in the data register 13. The APF unit (also referred to as an all-pass filter processing unit) 14 that performs all-pass filter processing and the data register unit 15 that stores data processed by the APF unit 14 are provided.

  Here, the beamform unit includes a delay control unit 12, and the delay control unit 12 calculates a memory address value of the focus point and a read start address from the receiving element position and the focus point. Further, the delay control unit 12 calculates an all-pass filter coefficient w1 used for the data stored in the data register. The APF unit 14 performs the all-pass filter process using the all-pass filter coefficient w1 calculated by the delay control unit 12.

  Next, the actual operation will be described with reference to FIGS.

  FIG. 6 illustrates the configuration of the delay control unit 12.

  The delay control unit 12 includes a delay calculation unit 121, and the delay calculation unit 121 calculates the theoretical delay amount in each reception element as a positional relationship between the focus point and the reception element position, specifically, between the focus point and the reception element. It is calculated in sample units according to the distance. The theoretical delay amount at this time also has a value after the decimal point.

  Next, the fractional part of the delay amount calculated by the delay calculating unit 121 is subtracted from 1.0. For example, when the decimal part is 0.4, it becomes 0.6 (1.0−0.4 = 0.6). Next, the APF coefficient calculation unit 123 calculates the coefficient (w1) of the all-pass filter that makes this processing delay amount (0.6 in the example). The coefficients of the all-pass filter may be not only a first-order all-pass filter but also a second-order or more-all-pass filter depending on the amount of calculation. By increasing the order, delay processing with higher accuracy becomes possible. Further, the coefficients of the all-pass filter may be obtained in advance with a certain degree of accuracy (for example, by dividing between 0 and 1 by 256), and a value obtained in advance may be set according to the input delay amount. . As a result, the calculation amount for coefficient calculation can be reduced.

  The APF unit 14 delays the input data by the delay amount processed by the all-pass filter. FIG. 5A shows an example of data before the all-pass filter process, and FIG. 5B shows an example of the data after the all-pass filter process. The value at the position of 6.4 samples is placed at the position of 7 samples by the all-pass filter. This eliminates the delay after the decimal point.

The address controller 122 adds the delay amount +1 increased by the all-pass filter to the value of the integer part of the theoretical delay amount calculated by the delay calculation unit 121, and obtains the address position (af) corresponding to the digital data at the focus point. calculate. The address controller calculates a read head address position that is the head when reading received data from the memory 7 from the calculated address position af of the focus point. When the number of data used for the all-pass filter is n, when the beamforming process is a delay addition process, the read head address a1 is
a1 = af−n + 1
Is calculated. As described above, when the read head address is set, the digital data corresponding to the focus point is located at the last address among the data stored in the data register 13 as shown in FIG. In the all-pass filter process, since convergence gradually approaches the true value from the first point, it converges most at the position of the last point of the data register. Therefore, by arranging the digital data corresponding to the focus point at the last stage of the data to be subjected to the all-pass filter processing, it is possible to achieve a unique effect of approaching the true value.

  Further, as shown in FIG. 7B, the focus point may be positioned at the approximate center of the data to be subjected to the all-pass filter processing. The arrangement of the focus point digital data does not converge as compared with FIG. 7A, but it is most efficient when digital data before and after the focus point, in particular, all data in the data register is used. It becomes a typical configuration.

  Further, as shown in FIG. 7C, the digital data corresponding to the focus point may be arranged at the subsequent stage from the center of the data to be subjected to the all-pass filter processing. With this configuration, digital data before and after the converged focus point can be used.

  In the above-described form, the address controller 122 designates both the address corresponding to the digital data at the focus point and the address of the read data. However, the address controller 122 may specify only the number of data. In any case, as long as the address of the designated data includes the address of the digital data corresponding to the focus point, the detailed setting of the address controller 122 is not limited to any one method.

  The number of digital data selected by the address controller 122 is preferably about 15 to 20 taps. Increasing the number of digital data increases the accuracy of delay processing, but increases the amount of calculation. In consideration of both the accuracy of delay processing and the amount of calculation required, it is preferable to appropriately set the number of data n.

  As described above, when the address af of the focus position and the read start address a1 are calculated by the address controller 122, data is stored in the data register 13 from the memory 7 in accordance with the address. Further, the APF coefficient calculated by the APF coefficient calculation unit 123 is set in the APF 14. The APF unit 14 executes the APF process using the data set in the data register 13 and the APF coefficient, and the data after the delay process is stored in the data register 15. For example, as shown in FIG. 7A, when the digital data at the focus point is set in the second stage of the digital data subjected to the all-pass filter, the final delay data is output as the final data of the data register 15. The data registers 13 and 15 may use the same area.

  As a characteristic of the all-pass filter, when the delay amount is small, the convergence is fast, and when the delay amount is large, the convergence is slow. FIG. 8 shows the output of the all-pass filter depending on the delay amount. However, the delay amount is adjusted to make the degree of convergence easier to see. As can be seen from FIG. 8, the convergence is delayed as the delay amount is increased, and the convergence is delayed as the delay amount approaches 1.0. For this reason, the number of data to be delayed by the all-pass filter may be changed according to the delay amount. For example, the delay amount is small for 0.1 taps and the like, and may be variable such that 5 samples are used, and 20 samples are used for 0.9 taps. That is, the address controller determines that the first delay time is greater than the first delay time when the decimal point portion of the delay time is greater than the second delay time (a value different from the first delay time). The address may be specified so that the length of the digital data to be selected is longer than the length of the digital data to be selected for the second delay time.

  Note that the larger the amount of delay in the decimal part (the closer it is to 1), the larger the number of data samples to be subjected to delay processing (the number of data stored in the data register 13) may be set.

  In this way, by changing the number of data samples according to the delay amount of the decimal part, it is possible to calculate delay data in a state where the convergence of the all-pass filter has been completed.

  Also, at 0.95 samples or more, which is very close to 1.0 samples, the time required for convergence becomes very long. FIG. 9 shows the delay amount and the number of taps necessary for convergence. In particular, when the number of samples is 0.95 or more, the number of data of 20 taps or more is required. Therefore, when there is a delay of 0.95 samples or more, the APF coefficient calculation unit 123 may set the coefficient to 0 and increase the delay amount of the integer part by 1. By doing in this way, it is possible to perform the calculation efficiently with a small calculation amount.

  According to such a configuration, since the delay circuit can be processed with an all-pass filter, the delay circuit can also perform a delay process of a decimal number or less, so that a highly accurate phasing addition can be performed as compared with the conventional one. Can be provided.

(Other variations)
Although the present invention has been described based on the above embodiment, it is needless to say that the present invention is not limited to the above embodiment. The following cases are also included in the present invention.

  (1) Each of the above devices is specifically a computer system including a microprocessor, a ROM, a RAM, a hard disk unit, a display unit, a keyboard, a mouse, and the like. A computer program is stored in the RAM or hard disk unit. Each device achieves its functions by the microprocessor operating according to the computer program. Here, the computer program is configured by combining a plurality of instruction codes indicating instructions for the computer in order to achieve a predetermined function.

  (2) A part or all of the constituent elements constituting each of the above-described devices may be configured by one system LSI (Large Scale Integration). The system LSI is an ultra-multifunctional LSI manufactured by integrating a plurality of components on a single chip, and specifically, a computer system including a microprocessor, ROM, RAM, and the like. . A computer program is stored in the RAM. The system LSI achieves its functions by the microprocessor operating according to the computer program.

  (3) Part or all of the constituent elements constituting each of the above devices may be configured from an IC card that can be attached to and detached from each device or a single module. The IC card or the module is a computer system including a microprocessor, a ROM, a RAM, and the like. The IC card or the module may include the super multifunctional LSI described above. The IC card or the module achieves its function by the microprocessor operating according to the computer program. This IC card or this module may have tamper resistance.

  (4) The present invention may be the method described above. Further, the present invention may be a computer program that realizes these methods by a computer, or may be a digital signal composed of the computer program.

  The present invention also provides a computer-readable recording medium such as a flexible disk, hard disk, CD-ROM, MO, DVD, DVD-ROM, DVD-RAM, BD (Blu-ray Disc). ), Recorded in a semiconductor memory or the like. The digital signal may be recorded on these recording media.

  In the present invention, the computer program or the digital signal may be transmitted via an electric communication line, a wireless or wired communication line, a network represented by the Internet, a data broadcast, or the like.

  The present invention may be a computer system including a microprocessor and a memory, wherein the memory stores the computer program, and the microprocessor operates according to the computer program.

  In addition, the program or the digital signal is recorded on the recording medium and transferred, or the program or the digital signal is transferred via the network or the like, and executed by another independent computer system. It is good.

  (5) The above embodiment and the above modifications may be combined.

  The ultrasonic diagnostic apparatus according to the present invention has a delay circuit that can also perform a delay process of a decimal or less, and can perform highly accurate phasing addition, which is useful for improving image quality.

DESCRIPTION OF SYMBOLS 1 Probe 21, 2n A / D converter 31 1st channel delay circuit 3n n-channel delay circuit 4 Adder circuit 5 Signal processing part 6 Display part 7 Memory 8 Reading control means 13, 15, 91, 92, 93, 94 Data Registers 101, 102, 103, 104 Multiplier 11 Adder 12 Delay control unit 121 Delay calculation unit 122 Address controller 123 APF coefficient calculation unit

Claims (8)

An ultrasonic probe having a plurality of receiving elements;
An A / D converter that samples the received signal obtained from the ultrasonic probe at a predetermined sampling interval ΔT and generates time-series digital data;
A memory for storing digital data generated by the A / D converter;
A beamform unit for performing a delay process on the digital data,
The beamform part is
A delay calculation unit that calculates a delay time from the position of the reception focus point and the reception element;
An address controller that specifies a focus position address that is an address of a reception signal from the reception focus point and a read start address for reading the digital data from the memory, and selects an address of the digital data so as to include the focus position address;
A delay control unit comprising a coefficient calculation unit for calculating a correction coefficient corresponding to the selected digital data;
An all-pass filter processing unit that performs all-pass filter processing on the digital data corresponding to the selected address;
An ultrasonic diagnostic apparatus comprising: The ultrasonic diagnostic apparatus according to claim 1, wherein the all-pass filter in the all-pass filter processing unit is a primary all-pass filter. 3. The super controller according to claim 1, wherein the address controller designates the address so that digital data corresponding to the focus position address is located at a final address of the selected digital data. 4. Ultrasonic diagnostic equipment. The address controller, digital data corresponding to the focus position address is any one of claims 1 to 3, characterized by specifying the address to be in the approximate center of the digital data to be the selected 1 The ultrasonic diagnostic apparatus according to item. The address controller, digital data corresponding to the focus position address is to be located in the second half of the center position of the digital data to be the selected of claim 1-4, characterized by specifying the address The ultrasonic diagnostic apparatus of any one of Claims. The address controller, based on the delay time, ultrasonic diagnosis according to any one of claims 1 to 5, characterized in that designating the address so that the length of the digital data indicating changes apparatus. If the first delay time is larger than the second delay time when the fractional part of the delay time is larger than the second delay time, the address controller selects the length of the digital data as the second delay time. The ultrasonic diagnostic apparatus according to claim 6 , wherein the address is specified so as to be longer than the length of digital data selected for the control. When the fractional part is less than 0.95 of the delay time, the coefficient calculating unit is set to 0 the correction coefficient, the all-pass filter processing section to claim 6, characterized in that the +1 delay amount of the integer part The ultrasonic diagnostic apparatus as described.

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