JP5666473B2 - マルチスレッド式データ処理システム - Google Patents

マルチスレッド式データ処理システム Download PDF

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JP5666473B2
JP5666473B2 JP2011545792A JP2011545792A JP5666473B2 JP 5666473 B2 JP5666473 B2 JP 5666473B2 JP 2011545792 A JP2011545792 A JP 2011545792A JP 2011545792 A JP2011545792 A JP 2011545792A JP 5666473 B2 JP5666473 B2 JP 5666473B2
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instruction
hardware
thread
execute
available
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JP2012515386A (ja
JP2012515386A5 (enExample
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アンドリュー ウェバー
アンドリュー ウェバー
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イマジネイション テクノロジーズ リミテッド
イマジネイション テクノロジーズ リミテッド
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009Thread control instructions
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802Instruction prefetching
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818Decoding for concurrent execution
    • G06F9/382Pipelined decoding, e.g. using predecoding
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818Decoding for concurrent execution
    • G06F9/3822Parallel decoding, e.g. parallel decode units
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00Indexing scheme relating to G06F9/00
    • G06F2209/50Indexing scheme relating to G06F9/50
    • G06F2209/507Low-level

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP2011545792A 2009-01-16 2010-01-18 マルチスレッド式データ処理システム Active JP5666473B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0900769.1 2009-01-16
GB0900769A GB2466984B (en) 2009-01-16 2009-01-16 Multi-threaded data processing system
PCT/GB2010/000062 WO2010082032A1 (en) 2009-01-16 2010-01-18 Multi-threaded data processing system

Publications (3)

Publication Number Publication Date
JP2012515386A JP2012515386A (ja) 2012-07-05
JP2012515386A5 JP2012515386A5 (enExample) 2013-03-07
JP5666473B2 true JP5666473B2 (ja) 2015-02-12

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JP2011545792A Active JP5666473B2 (ja) 2009-01-16 2010-01-18 マルチスレッド式データ処理システム

Country Status (5)

Country Link
US (2) US9612844B2 (enExample)
EP (1) EP2387748A1 (enExample)
JP (1) JP5666473B2 (enExample)
GB (1) GB2466984B (enExample)
WO (1) WO2010082032A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9798548B2 (en) 2011-12-21 2017-10-24 Nvidia Corporation Methods and apparatus for scheduling instructions using pre-decode data
US20130166882A1 (en) * 2011-12-22 2013-06-27 Jack Hilaire Choquette Methods and apparatus for scheduling instructions without instruction decode
US20140201409A1 (en) * 2013-01-17 2014-07-17 Xockets IP, LLC Offload processor modules for connection to system memory, and corresponding methods and systems
US9207944B1 (en) 2013-03-15 2015-12-08 Google Inc. Doubling thread resources in a processor
US9537776B2 (en) * 2013-03-15 2017-01-03 Innovasic, Inc. Ethernet traffic management apparatus
US9575802B2 (en) * 2014-10-28 2017-02-21 International Business Machines Corporation Controlling execution of threads in a multi-threaded processor
US11080064B2 (en) * 2014-10-28 2021-08-03 International Business Machines Corporation Instructions controlling access to shared registers of a multi-threaded processor
US10719420B2 (en) * 2015-02-10 2020-07-21 International Business Machines Corporation System level testing of multi-threading functionality including building independent instruction streams while honoring architecturally imposed common fields and constraints
KR102464678B1 (ko) * 2016-03-18 2022-11-11 한국전자통신연구원 매니코어 시스템에서 쓰레드를 스케줄링 하는 방법 및 그 장치
GB2563589B (en) 2017-06-16 2019-06-12 Imagination Tech Ltd Scheduling tasks
US11243880B1 (en) * 2017-09-15 2022-02-08 Groq, Inc. Processor architecture
CN111757168B (zh) * 2019-03-29 2022-08-19 腾讯科技(深圳)有限公司 音频解码方法、装置、存储介质及设备
CN111541646A (zh) * 2020-03-24 2020-08-14 成都国泰网信科技有限公司 一种增强密码机安全服务接入能力的方法
US12039337B2 (en) * 2020-09-25 2024-07-16 Advanced Micro Devices, Inc. Processor with multiple fetch and decode pipelines

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862407A (en) * 1987-10-05 1989-08-29 Motorola, Inc. Digital signal processing apparatus
US5487022A (en) * 1994-03-08 1996-01-23 Texas Instruments Incorporated Normalization method for floating point numbers
US5847022A (en) * 1995-03-27 1998-12-08 Dainippon Ink And Chemicals, Inc. Radiation curable resin composition and method therefor
GB2311882B (en) * 1996-04-04 2000-08-09 Videologic Ltd A data processing management system
US6076159A (en) * 1997-09-12 2000-06-13 Siemens Aktiengesellschaft Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline
US7007153B1 (en) * 2000-03-30 2006-02-28 Agere Systems Inc. Method and apparatus for allocating functional units in a multithreaded VLIW processor
GB2372847B (en) * 2001-02-19 2004-12-29 Imagination Tech Ltd Control of priority and instruction rates on a multithreaded processor
GB2374950B (en) * 2001-04-23 2005-11-16 Imagination Tech Ltd Expanded functionality of processor operations within a fixed width instruction encoding
US6950929B2 (en) * 2001-05-24 2005-09-27 Samsung Electronics Co., Ltd. Loop instruction processing using loop buffer in a data processing device having a coprocessor
US8146823B2 (en) * 2002-01-18 2012-04-03 Microscan Systems, Inc. Method and apparatus for rapid image capture in an image system
US6895497B2 (en) * 2002-03-06 2005-05-17 Hewlett-Packard Development Company, L.P. Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority
US7100060B2 (en) * 2002-06-26 2006-08-29 Intel Corporation Techniques for utilization of asymmetric secondary processing resources
JP3799423B2 (ja) * 2002-07-30 2006-07-19 財団法人理工学振興会 命令制御装置、機能ユニット、プログラム変換装置および言語処理装置
US7117389B2 (en) * 2003-09-18 2006-10-03 International Business Machines Corporation Multiple processor core device having shareable functional units for self-repairing capability
US7472390B2 (en) * 2003-10-01 2008-12-30 Intel Corporation Method and apparatus to enable execution of a thread in a multi-threaded computer system
US7555703B2 (en) * 2004-06-17 2009-06-30 Intel Corporation Method and apparatus for reducing false error detection in a microprocessor
US7237094B2 (en) * 2004-10-14 2007-06-26 International Business Machines Corporation Instruction group formation and mechanism for SMT dispatch
US7962725B2 (en) * 2006-05-04 2011-06-14 Qualcomm Incorporated Pre-decoding variable length instructions
JP2008084009A (ja) * 2006-09-27 2008-04-10 Toshiba Corp マルチプロセッサシステム
US20080163230A1 (en) * 2006-12-29 2008-07-03 Fernando Latorre Method and apparatus for selection among multiple execution threads
US8230425B2 (en) * 2007-07-30 2012-07-24 International Business Machines Corporation Assigning tasks to processors in heterogeneous multiprocessors
US9311085B2 (en) * 2007-12-30 2016-04-12 Intel Corporation Compiler assisted low power and high performance load handling based on load types
GB2458487B (en) 2008-03-19 2011-01-19 Imagination Tech Ltd Pipeline processors
US8561073B2 (en) * 2008-09-19 2013-10-15 Microsoft Corporation Managing thread affinity on multi-core processors

Also Published As

Publication number Publication date
GB2466984A (en) 2010-07-21
US20170192779A1 (en) 2017-07-06
US10318296B2 (en) 2019-06-11
JP2012515386A (ja) 2012-07-05
US9612844B2 (en) 2017-04-04
GB0900769D0 (en) 2009-03-04
US20120124338A1 (en) 2012-05-17
GB2466984B (en) 2011-07-27
WO2010082032A1 (en) 2010-07-22
EP2387748A1 (en) 2011-11-23

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