JP5662184B2 - Epitaxial substrate for semiconductor device and method for manufacturing epitaxial substrate for semiconductor device - Google Patents

Description

  The present invention relates to an epitaxial substrate for a semiconductor device, and more particularly to an epitaxial substrate configured using a group III nitride.

  Nitride semiconductors have a wide band gap of direct transition type, a high breakdown electric field, and a high saturation electron velocity. Therefore, semiconductors for light emitting devices such as LEDs and LDs, and high frequency / high power electronic devices such as HEMTs. It is attracting attention as a material. For example, a HEMT (High Electron Mobility Transistor) element formed by laminating a barrier layer made of AlGaN and a channel layer made of GaN has a laminated interface due to a large polarization effect (spontaneous polarization effect and piezoelectric polarization effect) peculiar to nitride materials. This utilizes the feature that a high-concentration two-dimensional electron gas (2DEG) is generated at the (heterointerface) (see, for example, Non-Patent Document 1).

  In some cases, a single crystal (heterogeneous single crystal) having a composition different from that of group III nitride, such as silicon carbide (SiC), is used as a base substrate used for an epitaxial substrate for HEMT elements (see, for example, Patent Document 1). In this case, a buffer layer such as a strained superlattice layer or a low temperature growth buffer layer is generally formed on the base substrate as an initial growth layer. Therefore, epitaxially forming the barrier layer, the channel layer, and the buffer layer on the base substrate is the most basic configuration of the HEMT element substrate using the base substrate made of different single crystals. In addition, a spacer layer having a thickness of about 1 nm may be provided between the barrier layer and the channel layer for the purpose of promoting spatial confinement of the two-dimensional electron gas. The spacer layer is made of, for example, AlN. Furthermore, a cap layer made of, for example, an n-type GaN layer or a superlattice layer is formed on the barrier layer for the purpose of controlling the energy level at the outermost surface of the substrate for HEMT elements and improving the contact characteristics with the electrode. Sometimes it is done.

  For HEMT devices and substrates for HEMT devices, there are issues related to performance improvements such as increased power density and higher efficiency, issues related to improved functionality such as normally-off operation, higher reliability and lower costs, etc. There are various issues such as basic issues, and active efforts are being made for each.

  On the other hand, research and development using single crystal silicon (Si) as a base substrate for the fabrication of nitride devices as described above has been conducted for the purpose of reducing the cost of epitaxial substrates and further integrating with silicon-based circuit devices. (For example, refer nonpatent literature 2). When a conductive material such as silicon is selected for the base substrate of the epitaxial substrate for the HEMT device, a field plate effect is imparted from the back surface of the base substrate, so that a HEMT device capable of high withstand voltage and high-speed switching is provided. Design becomes possible.

  Further, it is known that when the resistance of the buffer layer is lowered, improvement of the voltage resistance of the element and improvement of the high-speed operation may be hindered. A technique for improving the withstand voltage of the element by introducing a p-type impurity such as Mg into the buffer layer is already known (see, for example, Patent Document 2 and Patent Document 3).

Japanese translation of PCT publication No. 2002-520880 JP 2006-303475 A JP 2010-171032 A

"Highly Reliable 250W GaN High Electron Mobility Transistor Power Amplifier" Toshihide Kikkawa, Jpn. J. Appl. Phys. 44, (2005), 4896. "High power AlGaN / GaN HFET with a high breakdown voltage of over 1.8kV on 4 inch Si substrates and the suppresion of current collapse", Nariaki Ikeda, Syuusuke Kaya, Jiang Li, Yoshihiro Sato, Sadahiro Kato, Seikoh Yoshida, Proceedings of the 20th International Symposium on Power Semicoductor Devices & IC's May 18-22,2008 Oralando, FL ", pp.287-290

  Patent Document 2 discloses a semiconductor layer (channel layer) made of GaN immediately above a buffer layer made of GaN grown at a low temperature while introducing a p-type impurity such as Mg on a base substrate. The p-type impurity is diffused from the buffer layer when forming the p-type impurity, thereby realizing a state in which the p-type impurity is distributed at an appropriate concentration in the semiconductor layer, thereby reducing leakage current and withstand voltage in the device. This is a method for improving the quality.

  In the case of such a method, since it is premised on the introduction of p-type impurities into a buffer layer having poor crystallinity formed on the base substrate, there is a problem that structural restrictions are large. In particular, as the thickness of the semiconductor layer increases, it becomes difficult to obtain the effect. That is, if it is attempted to diffuse the p-type impurity above the semiconductor layer, it is necessary to introduce a large amount of the p-type impurity into the buffer layer, which causes deterioration of the crystallinity of the semiconductor layer near the buffer layer. As a result, it is difficult to improve the withstand voltage.

  On the other hand, Patent Document 3 discloses that a p-type impurity such as Mg is introduced into the multilayer buffer layer to suppress the generation of two-dimensional electron gas at the AlN / GaN interface in the buffer layer. This is a technique for improving the withstand voltage of the element.

  However, when the method disclosed in Patent Document 3 is used, there is a problem that the crystallinity of the buffer layer is deteriorated and the leakage current is increased due to the Mg concentration in the buffer layer becoming too high.

  The present invention has been made in view of the above problems, and provides an epitaxial substrate for a semiconductor device that has high withstand voltage and is suitably suppressed from deterioration of crystal quality due to diffusion of p-type impurities. Objective.

In order to solve the above-mentioned problems, the invention of claim 1 is such that the (0001) crystal plane is substantially parallel to the substrate surface of the base substrate on the base substrate that is single crystal silicon of (111) orientation. An epitaxial substrate for a semiconductor element formed with a group III nitride layer group, wherein first and second stacked units are alternately stacked, and the uppermost part and the lowermost part are A buffer layer formed of the first stack unit, a channel layer formed immediately above the buffer layer, and a barrier layer formed on the channel layer, A composition modulation layer in which a lamination unit is formed by alternately and alternately laminating a first unit layer and a second unit layer made of a group III nitride having different compositions from the base substrate side in this order ; A first layer formed of a group III nitride containing Al and formed thereon. Wherein an intermediate layer, wherein the first plane lattice constant in the strain-free state towards the second group III nitride constituting the second unit layer than Group III nitride constituting the first unit layer Each of the second unit layers is formed in a coherent state with respect to the first unit layer, and at least one of the plurality of first intermediate layers included in the buffer layer includes Al. A first layer made of a group III nitride, wherein a p-type impurity is intentionally introduced only in the first layer, and the first layer is included in the buffer layer and the channel layer . A p-type impurity diffused from the first layer is present in a second layer which is a layer adjacent to the layer .

The invention according to claim 2 is the epitaxial substrate according to claim 1 , wherein at least the first intermediate layer adjacent to the channel layer among the plurality of first intermediate layers is the first layer. It is characterized by that.

A third aspect of the present invention, an epitaxial substrate according to claim 1, all of the plurality of the first intermediate layer is the first layer, characterized in that.

A fourth aspect of the present invention, an epitaxial substrate according to any one of claims 1 to 3, wherein the first intermediate layer is _{Al y Ga 1-y N (} 0 <y ≦ 0.25) having a composition And the channel layer is made of GaN.

The invention of claim 5, claim 1 to an epitaxial substrate according to claim 4, wherein the first concentration of the p-type impurity in a layer of ^{1 × 10 17 cm -3 ~2 ×} 10 It is characterized by being ¹⁸ cm ⁻³ .

A sixth aspect of the present invention is the epitaxial substrate according to any one of the first to fifth aspects, wherein the first intermediate layer is formed in a coherent state with respect to the composition modulation layer. Features.

A seventh aspect of the present invention is the epitaxial substrate according to any one of the first to sixth aspects, wherein the first unit layer is made of AlN, and the second unit layer is made of Al _x Ga _1-x N ( It is characterized by being made of a group III nitride having a composition of 0 ≦ x ≦ 0.25).

An eighth aspect of the present invention is the epitaxial substrate according to any one of the first to seventh aspects, wherein a termination layer having the same composition as the first unit layer is provided on an uppermost portion of the composition modulation layer. It is characterized by becoming.

A ninth aspect of the present invention is the epitaxial substrate according to any one of the first to eighth aspects, wherein the second stacked unit is more strain-free than the group III nitride constituting the first intermediate layer. It is a second intermediate layer made of a group III nitride having a small in-plane lattice constant in the state.

A tenth aspect of the present invention is the epitaxial substrate according to the ninth aspect , wherein the second intermediate layer is formed of AlN to a thickness of 15 nm or more and 150 nm or less.

The invention of claim 11 is the epitaxial substrate according to claim 9 or 10 , wherein the composition of the first unit layer and the composition of the second intermediate layer are substantially the same. .

A twelfth aspect of the invention is the epitaxial substrate according to any one of the first to eleventh aspects, wherein the first underlayer made of AlN, formed on the undersubstrate, and the first substrate A second underlayer formed on the underlayer and made of Al _p Ga _1-p N (0 ≦ p <1), wherein the first underlayer is a columnar or granular crystal or domain A defect-containing layer composed of at least one of the following: the interface between the first underlayer and the second underlayer is a three-dimensional uneven surface, and is directly above the second underlayer. The buffer layer is formed.

A thirteenth aspect of the invention is the epitaxial substrate according to any one of the first to twelfth aspects, wherein the p-type impurity is Mg.

According to a fourteenth aspect of the present invention, a group III nitride layer group whose (0001) crystal plane is substantially parallel to the substrate surface of the base substrate is formed on the base substrate which is single crystal silicon of (111) orientation. A method for manufacturing an epitaxial substrate for a semiconductor device, comprising: alternately stacking a first stack unit and a second stack unit so that the uppermost part and the lowermost part are the first stack unit. A buffer layer forming step for forming a buffer layer, a channel layer forming step for epitaxially forming a channel layer directly on the buffer layer, and a barrier layer forming step for epitaxially forming a barrier layer on the channel layer, the buffer layer forming step, a step of forming the first stack unit, the a first unit layer and a second unit layer composed of different group III nitride having a composition from a side of the base substrate To include repeating the composition modulation layer forming step of epitaxially forming a composition modulation layer by alternately stacking, and a first intermediate layer forming step of epitaxially forming a first intermediate layer on the composition modulated layer, the composition In the modulation layer forming step, the in-plane lattice constant in the unstrained state of the group III nitride constituting the second unit layer is larger than the group III nitride constituting the first unit layer. And each said 2nd unit layer forms the said composition modulation layer so that it may become a coherent state with respect to the said 1st unit layer, Of several said 1st intermediate | middle layers contained in the said buffer layer A p-type impurity is introduced only when at least one is epitaxially formed.

A fifteenth aspect of the present invention is the epitaxial substrate manufacturing method according to the fourteenth aspect of the present invention, wherein at least the first intermediate layer adjacent to the channel layer among the plurality of first intermediate layers has the p-type. Impurities are introduced.

A sixteenth aspect of the invention is the epitaxial substrate manufacturing method according to the fourteenth aspect , wherein the p-type impurity is introduced into all of the plurality of first intermediate layers.

The invention according to claim 17 is the method for manufacturing an epitaxial substrate according to any one of claims 14 to 16 , wherein the first intermediate layer is formed of Al _y Ga _1-y N (0 <y ≦ 0.25). And the channel layer is formed of GaN.

The invention according to claim 18 is the method for manufacturing an epitaxial substrate according to any one of claims 14 to 17 , wherein the concentration of the p-type impurity is 1 × 10 ¹⁷ cm ⁻³ to 2 × 10 ¹⁸ cm ^{−. The} p-type impurity is introduced so as to be ³ .

The invention according to claim 19 is the method for manufacturing an epitaxial substrate according to any one of claims 14 to 18 , wherein the first intermediate layer forming step is in a coherent state with respect to the composition modulation layer. The first intermediate layer is formed in such a manner.

Invention of Claim 20 is the manufacturing method of the epitaxial substrate in any one of Claim 14 thru | or 19 , Comprising: In the said composition modulation layer formation process, said 1st unit layer is formed with AlN, The second unit layer is formed of a group III nitride having a composition of Al _x Ga _1-x N (0 ≦ x ≦ 0.25).

The invention according to claim 21 is the method for manufacturing an epitaxial substrate according to any one of claims 14 to 20 , wherein a termination layer having the same composition as the first unit layer is formed on the top of the composition modulation layer. And a termination layer forming step to be provided.

The invention of claim 22 is the method of manufacturing an epitaxial substrate according to any one of claims 14 to 21 , wherein the step of forming the second stacked unit comprises forming the first intermediate layer III And a second intermediate layer forming step of forming a second intermediate layer made of a group III nitride having a smaller in-plane lattice constant in a strain-free state than that of the group nitride.

The invention of claim 23 is the method for manufacturing an epitaxial substrate according to claim 22 , wherein the second intermediate layer is formed of AlN to a thickness of 15 nm or more and 150 nm or less.

A twenty-fourth aspect of the invention is a method for manufacturing an epitaxial substrate according to any one of the fourteenth to twenty- third aspects, wherein a first underlayer comprising a first underlayer made of AlN is formed on the undersubstrate. A base layer forming step; and a second base layer forming step of forming a second base layer made of Al _p Ga _1-p N (0 ≦ p <1) on the first base layer. In the first underlayer forming step, the first underlayer is formed as a polycrystalline defect-containing layer composed of at least one of columnar or granular crystals or domains, and the surface is a three-dimensional uneven surface. In the buffer layer forming step, the buffer layer is formed immediately above the second underlayer.

A twenty-fifth aspect of the invention is a method for manufacturing an epitaxial substrate according to any one of the fourteenth to twenty-fourth aspects, wherein the p-type impurity is Mg.

According to the invention of claim 1 to claim 25 , an inexpensive and easily available silicon substrate is used as a base substrate, and an epitaxial substrate having a crack-free crystal quality and a high withstand voltage is obtained. be able to.

1 is a schematic cross-sectional view schematically showing a configuration of an epitaxial substrate 10 according to an embodiment of the present invention. FIG. 4 is a model diagram illustrating a state of a crystal lattice when a second unit layer 32 is formed on a first unit layer 31 in the composition modulation layer 3. FIG. 4 is a diagram showing the relationship between the amount of warpage of the epitaxial substrate that has been performed up to the formation of the first intermediate layer 5 and the thickness of the first intermediate layer 5. It is a figure which illustrates the result of having measured the concentration profile of the p-type impurity in a channel adjacent intermediate | middle layer and the channel layer 9a by SIMS.

<Schematic configuration of epitaxial substrate>
FIG. 1 is a schematic cross-sectional view schematically showing a configuration of an epitaxial substrate 10 according to an embodiment of the present invention.

  The epitaxial substrate 10 includes a base substrate 1, a base layer 2, a plurality of composition modulation layers 3, a termination layer 4, a first intermediate layer 5, and a second intermediate layer 7, and a buffer layer 8. The layer 9 is mainly provided. Hereinafter, each layer formed on the base substrate 1 may be collectively referred to as an epitaxial film. Moreover, the abundance ratio of Al in the group III element may be referred to as an Al mole fraction for convenience.

  The base substrate 1 is a (111) plane single crystal silicon wafer. Although there is no special restriction | limiting in the thickness of the base substrate 1, For convenience of handling, it is preferable to use the base substrate 1 which has a thickness of several hundred micrometers to several mm. The conductivity type of the base substrate 1 is not particularly limited, and p-type and n-type can be selected as appropriate.

  The underlayer 2, the composition modulation layer 3, the termination layer 4, the first intermediate layer 5, the second intermediate layer 7, and the functional layer 9 are each made of wurtzite group III nitride (0001). This is a layer formed by an epitaxial growth technique so that the crystal plane is substantially parallel to the substrate surface of the base substrate 1. These layers are preferably formed by metal organic chemical vapor deposition (MOCVD).

  The underlayer 2 is a layer provided so as to enable the above-described layers to be formed with good crystal quality thereon. Specifically, the underlayer 2 is provided so that the dislocation density is suitably reduced and the crystal quality is good at least near the surface (in the vicinity of the interface with the composition modulation layer 3). Thereby, good crystal quality can be obtained also in the composition modulation layer 3 and in each layer formed thereon.

  In the present embodiment, in order to satisfy such a purpose, the base layer 2 is composed of a first base layer 2a and a second base layer 2b as shown below.

  The first underlayer 2a is a layer made of AlN. The first underlayer 2a is made up of a number of fine columnar crystals and the like (at least one of columnar crystals, granular crystals, columnar domains, or granular domains) grown in a direction substantially perpendicular to the substrate surface of the underlying substrate 1 (film formation direction). It is a composed layer. In other words, the first underlayer 2a is uniaxially oriented in the stacking direction of the epitaxial substrate 10, but contains a large number of crystal grain boundaries or dislocations along the stacking direction and has multiple crystal defects with poor crystallinity. It is a content layer. In the present embodiment, for convenience, the term “crystal grain boundary” including domain grain boundaries or dislocations may be used. The distance between crystal grain boundaries in the first underlayer 2a is about several tens of nm at most.

  The first underlayer 2a having such a configuration has an X-ray rocking curve half-value width of (0002) plane that is a large or small mosaic property with respect to the c-axis tilt component or a slight index of screw dislocation, of 0.5 degrees or more. X-ray rocking curve half-value width of (10-10) plane that is less than 1 degree and is a measure of mosaicity or some degree of edge dislocation with respect to the rotational component of the crystal with c-axis as the rotation axis Is formed to be 0.8 degrees or more and 1.1 degrees or less.

On the other hand, the second underlayer 2b is a layer made of a group III nitride having a composition of Al _p Ga _1-p N (0 ≦ p <1) formed on the first underlayer 2a.

  Further, the interface I1 (the surface of the first ground layer 2a) between the first ground layer 2a and the second ground layer 2b is a three-dimensional uneven surface reflecting the external shape such as a columnar crystal constituting the first ground layer 2a. It has become. It is clearly confirmed in the HAADF (high angle scattered electron) image of the epitaxial substrate 10 that the interface I1 has such a shape. The HAADF image is a mapping image of the integrated intensity of electrons inelastically scattered at a high angle, obtained by a scanning transmission electron microscope (STEM). In the HAADF image, the image intensity is proportional to the square of the atomic number, and the portion where an atom with a large atomic number is present is observed brighter (whiter). Therefore, the second underlayer 2b containing Ga is relatively brighter, and Ga The first underlayer 2a that does not contain is observed relatively dark. Thereby, it is easily recognized that the interface I1 between the two is a three-dimensional uneven surface.

In the schematic cross section of FIG. 1, the protrusions 2c of the first base layer 2a are shown to be positioned at approximately equal intervals. However, this is merely for convenience of illustration, and actually, it is not necessarily at equal intervals. The convex part 2c is not necessarily located. Preferably, in the first base layer 2a, the density of the protrusions 2c is 5 × 10 ⁹ / cm ² or more and 5 × 10 ¹⁰ / cm ² or less, and the average interval between the protrusions 2c is 45 nm or more and 140 nm or less. It is formed. When these ranges are satisfied, it is possible to form the functional layer 9 having particularly excellent crystal quality. In the present embodiment, the convex portion 2c of the first base layer 2a indicates a substantially apex position of an upward convex portion on the surface (interface I1). As a result of experiments and observations by the inventors of the present invention, it is confirmed that the side wall of the convex portion 2c is formed by the (10-11) plane or the (10-12) plane of AlN. .

  In order to form the convex portions 2c satisfying the above-described density and average interval on the surface of the first underlayer 2a, it is preferable to form the first underlayer 2a so that the average film thickness is 40 nm or more and 200 nm or less. When the average film thickness is smaller than 40 nm, it is difficult to realize a state in which AlN completely covers the substrate surface while forming the convex portions 2c as described above. On the other hand, if the average film thickness is to be made larger than 200 nm, planarization of the AlN surface starts to progress, and it becomes difficult to form the convex portions 2c as described above.

  The formation of the first underlayer 2a is realized under predetermined epitaxial growth conditions, but the formation of the first underlayer 2a with AlN does not include Ga that forms a liquid phase compound with silicon. This is preferable in that the interface I1 is easily formed as a three-dimensional uneven surface because the lateral growth is relatively difficult to proceed.

  In epitaxial substrate 10, first base layer 2 a, which is a multi-defect-containing layer having crystal grain boundaries, is interposed between base substrate 1 and second base layer 2 b in the manner described above. The lattice misfit between the base substrate 1 and the second base layer 2b is relaxed, and the accumulation of strain energy due to the lattice misfit is suppressed. The range of the X-ray rocking curve half-value width of the (0002) plane and the (10-10) plane of the first underlayer 2a described above is determined as a range in which the accumulation of strain energy due to the crystal grain boundary is suitably suppressed. It is.

  However, since the first underlayer 2a is interposed, a large number of dislocations originating from crystal grain boundaries such as columnar crystals of the first underlayer 2a propagate to the second underlayer 2b. In the present embodiment, the dislocations are effectively reduced by making the interface I1 between the first base layer 2a and the second base layer 2b a three-dimensional uneven surface as described above.

  Since the interface I1 between the first underlayer 2a and the second underlayer 2b is formed as a three-dimensional uneven surface, most of the dislocations generated in the first underlayer 2a are second to second from the first underlayer 2a. When propagating (penetrating) to the underlying layer 2b, the bent portion is bent at the interface I1 and disappears in the second underlying layer 2b. As a result, among the dislocations starting from the first underlayer 2a, only a few dislocations penetrate the second underlayer 2b.

  The second underlayer 2b is preferably formed along the surface shape (the shape of the interface I1) of the first underlayer 2a at the initial stage of growth, but the surface is gradually flattened as the growth proceeds. Finally, it is formed to have a surface roughness of 10 nm or less. In the present embodiment, the surface roughness is represented by an average roughness ra for a 5 μm × 5 μm region measured by an AFM (atomic force microscope). Incidentally, the fact that the second underlayer 2b is formed of a group III nitride having a composition containing at least Ga, in which the lateral growth is relatively easy, improves the surface flatness of the second underlayer 2b. This is preferable.

  The average thickness of the second base layer 2b is preferably 40 nm or more. This is because when it is formed thinner than 40 nm, the unevenness derived from the first underlayer 2a cannot be sufficiently flattened, and the disappearance due to the mutual combination of dislocations propagated to the second underlayer 2b does not occur sufficiently. This is because problems such as. Note that when the average thickness is 40 nm or more, the dislocation density is reduced and the surface is flattened effectively. Therefore, the upper limit of the thickness of the second underlayer 2b is particularly limited in terms of technology. However, it is preferably formed to a thickness of about several μm or less from the viewpoint of productivity.

  As described above, since the surface of the second underlayer 2b has low dislocations and excellent flatness, each layer formed thereon has good crystal quality.

  The buffer layer 8 has a configuration in which a second intermediate layer 7 is interposed between a plurality of unit structures 6 each formed by laminating a composition modulation layer 3, a termination layer 4, and a first intermediate layer 5 in this order. . In other words, it can be said that the second intermediate layer 7 is provided as a boundary layer between the individual unit structures 6. Alternatively, the buffer layer 8 includes a unit structure 6 that is a first stacked unit and a second intermediate layer 7 that is a second stacked unit in a mode in which the lowermost part and the uppermost part are unit structures 6. It can also be said that it has a structure in which layers are alternately and repeatedly stacked. FIG. 1 illustrates a case where four unit structures 6 (6a, 6b, 6c, 6d) and three second intermediate layers 7 (7a, 7b, 7c) are provided. The number of second intermediate layers 7 is not limited to this.

  The composition modulation layer 3 has a superlattice structure formed by repeatedly laminating first unit layers 31 and second unit layers 32 which are two types of group III nitride layers each having a different composition. It is a site | part which has. A set of one first unit layer 31 and one second unit layer 32 is referred to as a pair layer.

  The first unit layer 31 and the second unit layer 32 are composed of an in-plane lattice constant (lattice state) in a non-strained state (bulk state) of the group III nitride constituting the latter rather than the group III nitride constituting the former. It is formed so as to satisfy the relationship of “long”.

  In the composition modulation layer 3, the second unit layer 32 is formed in a coherent state with respect to the first unit layer 31. Further, the thickness of the second unit layer 32 is larger than the thickness of the first unit layer 31.

  The first unit layer 31 is preferably formed to a thickness of about 3 nm to 20 nm. Typically, it is formed to a thickness of 5 nm to 10 nm. On the other hand, the second unit layer 32 is preferably about 10 nm to 25 nm. Moreover, the repetition number of a pair layer is about 5 to several tens.

Preferably, the first unit layer 31 is made of AlN, and the second unit layer 32 is made of a group III nitride having a composition of Al _x Ga _1-x N (0 ≦ x ≦ 0.25).

  The termination layer 4 is a layer formed of a group III nitride at the uppermost part (at the termination part) of the composition modulation layer 3 with the same composition and thickness as the first unit layer 31. Although the pair layers are not configured, it can be said that the termination layer 4 is substantially a part of the superlattice layer 3. Hereinafter, the composition modulation layer 3 includes the termination layer 4 unless otherwise specified.

The first intermediate layer 5 is a layer made of group III nitride. The first intermediate layer 5 is made of a group III nitride having a larger in-plane lattice constant in a strain-free state than the group III nitride constituting the first unit layer 31. For example, the first intermediate layer 5 is composed of a group III nitride having a composition of Al _y Ga _1-y N (0 ≦ y ≦ 0.25). The first intermediate layer 5 is formed in a coherent state with respect to the termination layer 4. The first intermediate layer 5 preferably has a thickness of approximately 100 nm to 500 nm. In addition, the composition of the 1st intermediate | middle layer 5 with which each unit structure 6 is equipped does not need to be the same.

  Note that p-type impurities are intentionally introduced into at least one of the plurality of first intermediate layers 5 provided in the buffer layer 8. This is performed for the purpose of increasing the voltage resistance of the epitaxial substrate 10. Details of the first intermediate layer 5 including the p-type impurity will be described later.

  The second intermediate layer 7 is a layer made of a group III nitride having a smaller in-plane lattice constant in a strain-free state than the group III nitride constituting the first intermediate layer 5. The second intermediate layer 7 is preferably formed to a thickness of about 15 nm to 150 nm. Preferably, the second intermediate layer 7 is made of a group III nitride having the same composition as the first unit layer 31 of the composition modulation layer 3. More preferably, the second intermediate layer 7 is made of AlN.

  The number of pair layers in the composition modulation layer 3 constituting the unit structure 6, the actual composition and thickness of the first intermediate layer 5, and the like are determined according to the formation mode of the entire buffer layer 8.

  The functional layer 9 is a layer formed of a group III nitride formed on the buffer layer 8, and constitutes a semiconductor element by further forming a predetermined semiconductor layer, electrode, or the like on the epitaxial substrate 10. In this case, the layer exhibits a predetermined function. Therefore, the functional layer 9 is formed of one or more layers having a composition and thickness corresponding to the function. Although FIG. 1 illustrates the case where the functional layer 9 includes a channel layer 9a and a barrier layer 9b, the configuration of the functional layer 9 is not limited to this.

  The channel layer 9a and the barrier layer 9b are functional layers provided to make the epitaxial substrate 10 a substrate for a HEMT element. The channel layer 9a is made of high-resistance GaN and has a thickness of about several tens of nm to several μm. The barrier layer 9b is made of AlGaN, InAlN, or the like and has a thickness of about several tens of nm. A HEMT element is obtained by forming a gate electrode, a source electrode, and a drain electrode (not shown) on the barrier layer 9b. A known technique such as a photolithography process can be applied to the formation of these electrodes. In this case, a spacer layer made of AlN and having a thickness of about 1 nm may be provided between the channel layer 9a and the barrier layer 9b.

<Epitaxial substrate manufacturing method>
Next, an outline of a method for manufacturing the epitaxial substrate 10 will be described by taking the case of using the MOCVD method as an example.

  First, a (111) plane single crystal silicon wafer is prepared as the base substrate 1, and the natural oxide film is removed by dilute hydrofluoric acid cleaning. After that, SPM cleaning is performed, and an oxide film having a thickness of about several mm is formed on the wafer surface. Is formed. This is set in the reactor of the MOCVD apparatus.

Then, each layer is formed under a predetermined heating condition and gas atmosphere. First, the first underlayer 2a made of AlN is made of an aluminum raw material while maintaining a substrate temperature at a predetermined initial layer formation temperature of 800 ° C. or higher and 1200 ° C. or lower and a reactor internal pressure of about 0.1 kPa to 30 kPa. A TMA (trimethylaluminum) bubbling gas and NH ₃ gas are introduced into the reactor at an appropriate molar flow ratio, and the film formation rate is set to 20 nm / min or more and the target film thickness is set to 200 nm or less. be able to.

In the formation of the second underlayer 2b, after the formation of the first underlayer 2a, the substrate temperature is maintained at a predetermined second underlayer formation temperature of 800 ° C. or higher and 1200 ° C. or lower, and the reactor internal pressure is set to 0.1 kPa to 100 kPa. In this state, TMG (trimethylgallium) bubbling gas, TMA bubbling gas, and NH ₃ gas, which are gallium raw materials, are introduced into the reactor at a predetermined flow rate ratio according to the composition of the second underlayer 2b to be produced. This is realized by reacting NH ₃ with TMA and TMG.

The formation of each layer constituting the buffer layer 8, that is, the first unit layer 31 and the second unit layer 32 constituting the composition modulation layer 3, the termination layer 4, the first intermediate layer 5, and the second intermediate layer 7, Subsequent to the formation of the base layer 2b, the substrate temperature is maintained at a predetermined formation temperature corresponding to each layer of 800 ° C. or higher and 1200 ° C. or lower, and the reactor internal pressure is maintained at a predetermined value corresponding to each layer of 0.1 kPa to 100 kPa. In this state, NH ₃ gas and Group III nitride source gas (TMA, TMG bubbling gas) are introduced into the reactor at a flow ratio according to the composition to be realized in each layer. At that time, each layer is formed continuously and with a desired film thickness by switching the flow rate ratio at a timing corresponding to the set film thickness. In addition, in order to introduce p-type impurities when forming the first intermediate layer 5, in addition to the above-described source gas, a p-type impurity to be realized in the first intermediate layer 5 is used as a source gas for p-type impurities. What is necessary is just to supply a reactor with the flow volume according to the density | concentration. For example, when introducing Mg into the first intermediate layer 5, Cp ₂ Mg (cyclopentadienyl magnesium; Mg (C ₅ H ₅ ) ₂ ) may be used as the source gas.

After the buffer layer 8 is formed, the functional layer 9 is formed by keeping the substrate temperature at a predetermined functional layer forming temperature of 800 ° C. or higher and 1200 ° C. or lower, and setting the reactor internal pressure to 0.1 kPa to 100 kPa. , TMA bubbling gas, or at least one of TMG bubbling gas and NH ₃ gas are introduced into the reactor at a flow ratio according to the composition of the functional layer 9 to be produced, and NH ₃ and TMI, TMA, and TMG are introduced. It is realized by reacting with at least one of the following.

  After the functional layer 9 is formed, the epitaxial substrate 10 is cooled to room temperature in the reactor. Thereafter, the epitaxial substrate 10 taken out from the reactor is appropriately subjected to subsequent processing (patterning of the electrode layer, etc.).

<Effect of buffer layer>
As is the case with the present embodiment, in general, when a crystal layer made of a group III nitride is epitaxially grown on a single crystal silicon wafer at a predetermined formation temperature to obtain an epitaxial substrate, a group III nitride is used. thermal expansion coefficient is larger than that of silicon towards: from (e.g., silicon ^{3.4 × 10 -6 /K,GaN:5.5×10 -6 / K} ) that, after the crystal growth, it is cooled to ambient temperature In the process, tensile stress is generated in the crystal layer in the in-plane direction. This tensile stress causes cracks and warpage in the epitaxial substrate. In the present embodiment, the buffer layer 8 is provided on the epitaxial substrate 10 for the purpose of reducing the tensile stress and suppressing the occurrence of cracks and warpage. More specifically, the occurrence of cracks and warpage in the epitaxial substrate 10 are suppressed by the operational effects exhibited by the layers constituting the buffer layer 8. Details will be described below.

(Composition modulation layer)
FIG. 2 is a model diagram showing the state of the crystal lattice when the second unit layer 32 is formed on the first unit layer 31 in the composition modulation layer 3. Now, let the lattice length in the in-plane direction of the group III nitride constituting the second unit layer 32 in an unstrained state be a ₀ and the actual lattice length be a. In the present embodiment, as shown in FIGS. 2A and 2B, the second unit layer 32 grows while maintaining alignment with the crystal lattice of the first unit layer 31. This means that a compressive strain of s = a ₀ −a is generated in the in-plane direction of the second unit layer 32 during crystal growth. That is, the crystal growth of the second unit layer 32 proceeds while maintaining strain energy.

However, since the energy instability increases as the growth proceeds, misfit dislocations are gradually introduced into the second unit layer 32 in order to release strain energy. When a certain critical state is reached, all the strain energy held in the second unit layer 32 is released. At this time, a = a ₀ as shown in FIG.

However, if the formation of the second unit layer 32 is completed in the state of a ₀ > a as shown in FIG. 2B until the state shown in FIG. 32 retains strain energy (including compression strain). In the present embodiment, crystal growth that includes such strain energy is referred to as crystal growth in a coherent state. In other words, the second unit layer 32 is in a coherent state with respect to the first unit layer 31 as long as the second unit layer 32 is formed to a thickness smaller than the critical film thickness at which strain energy is completely released. It can be said that. Alternatively, as long as a ₀ > a holds for the lattice length a of the uppermost surface of the second unit layer 32 (the surface in contact with the first unit layer 31 immediately above), the second unit layer 32 is in relation to the first unit layer 31. It can also be said that it is in a coherent state. As long as the second unit layer 32 includes strain energy in the above-described manner, even if a ₀ = a is partly in the second unit layer 32, the second unit layer 32 is It can be said that it is in a coherent state with respect to one unit layer 31.

  Since the in-plane lattice constant of the group III nitride composing the first unit layer 31 is smaller than the in-plane lattice constant of the group III nitride composing the second unit layer 32, the second energy is maintained while maintaining this strain energy. Even if the first unit layer 31 is formed on the unit layer 32, the coherent state is maintained, and the strain energy held in the second unit layer 32 directly below is not released. Then, if the second unit layer 32 is grown again on the first unit layer 31 in a coherent state, the same compressive strain as described above will also occur in the second unit layer 32.

  Thereafter, similarly, when the formation of the first unit layer 31 and the second unit layer 32 (formation of the pair layer) is repeated while maintaining the growth in the coherent state, the second unit layer 32 of each pair layer is formed. Since the strain energy is maintained, the composition modulation layer 3 is formed as a part including a compressive strain as a whole.

  Since the compressive strain introduced into the composition modulation layer 3 acts in the opposite direction to the tensile stress generated due to the difference in thermal expansion coefficient, it has the effect of offsetting the tensile stress when the temperature is lowered. Generally speaking, the tensile stress is canceled by a force proportional to the product of the magnitude of the compressive strain in one pair layer and the number of repetitions of the pair layer in the composition modulation layer 3. That is, it can be said that the composition modulation layer 3 is a portion formed by introducing compressive strain into the epitaxial substrate 10.

  The first unit layer 31 is interposed between the two second unit layers 32. However, when the thickness is too small, the compressive strain generated in the second unit layer 32 is reduced and the first unit layer 31 is conversely arranged. One unit layer 31 itself tends to contain tensile stress, which is not preferable. On the other hand, when the thickness is too large, the second unit layer 32 itself tends to receive a force in the tensile direction, which is not preferable. The above-mentioned requirement of a thickness of about 3 nm to 20 nm is preferable from the viewpoint that such a problem does not occur.

The first unit layer 31 is made of AlN, and the second unit layer 32 is made of a group III nitride having a composition of Al _x Ga _1-x N (0 ≦ x ≦ 0.25). This requirement is suitable in that a sufficiently large compressive strain can be obtained in each pair layer.

(Termination layer)
The termination layer 4 is made of a group III nitride having the same composition as the first unit layer 31 at the top of the composition modulation layer 3, that is, an in-plane lattice than the group III nitride forming the second unit layer 32. A group III nitride having a small constant is formed with the same thickness as the first unit layer 31. Due to the presence of the termination layer 4 in such an aspect, the compressive strain introduced into the composition modulation layer 3 is suitably maintained even when the first intermediate layer 5 is provided in an aspect described later.

(First intermediate layer)
FIG. 3 is a diagram showing the relationship between the amount of warpage of the epitaxial substrate after the first intermediate layer 5 is formed and the thickness of the first intermediate layer 5. FIG. 3 represents the total film thickness of the epitaxial film on the horizontal axis. In this embodiment, the amount of warpage of the epitaxial substrate is measured with a laser displacement meter.

In the five examples shown in FIG. 3, the conditions other than the thickness of the first intermediate layer 5 are all the same. As the base substrate 1, a (111) single crystal silicon wafer (525 μm thick) having a p-type conductivity and a diameter of 4 inches is used. Furthermore, a first underlayer 2a made of AlN and having an average thickness of 100 nm, a second underlayer 2b made of Al _0.1 Ga _0.9 N and having an average thickness of 40 nm, and a first unit layer 31 made of AlN having a thickness of 5 nm, A composition modulation layer 3 in which a pair layer with a second unit layer 32 made of Al _0.1 Ga _0.9 N having a thickness of 15 nm is repeatedly laminated 20 times, a termination layer 4 (not shown), and a first intermediate layer 5 made of GaN are laminated. It becomes.

  In FIG. 3, when the thickness of the first intermediate layer 5 is 200 nm, the amount of warpage of the epitaxial substrate is minimal. As described above, since the first intermediate layer 5 is formed in a coherent state with respect to the termination layer 4, the result shown in FIG. 3 is that the first intermediate layer 5 formed with a thickness of about 200 nm is a buffer. This suggests that the effect of further strengthening the compressive strain introduced into the epitaxial substrate 10 by the layer 8 is exhibited. Based on this result, in the present embodiment, the first intermediate layer 5 is provided with a thickness of about 100 nm to 500 nm so as to increase the compressive strain introduced in the composition modulation layer 3. Thereby, in the epitaxial substrate 10, the tensile stress is more effectively offset. That is, in the epitaxial substrate 10, the first intermediate layer 5 functions as a strain strengthening layer.

  As shown in FIG. 3, when the thickness of the first intermediate layer 5 becomes too large, the amount of warpage of the epitaxial substrate 10 increases. This is because, as the crystal grows, the strain energy storage is limited and the compressive strain becomes weaker, and it becomes difficult for the lattice to grow in a coherent state, eventually exceeding the critical film thickness. This is because the strain energy is released. Such an increase in the amount of warpage causes cracks. Incidentally, in FIG. 3, the amount of warping when the thickness of the first intermediate layer 5 is 500 nm is larger than that when the first intermediate layer 5 is not provided, but in the actual epitaxial substrate 10 in which a plurality of unit structures 6 are stacked. It has been confirmed by the inventor of the present invention that the compressive strain in the buffer layer 8 is suitably enhanced when the thickness of the first intermediate layer 5 is in the range of 500 nm or less.

(Second intermediate layer)
By forming the composition modulation layer 3 and the first intermediate layer 5 in the above-described manner, the unit structure 6 inherently has compressive strain. Therefore, if a plurality of unit structures 6 are laminated, a large compressive strain sufficient to prevent the occurrence of cracks should be obtained. However, actually, even if another unit structure 6 is formed immediately above a certain unit structure 6, sufficient compression strain cannot be obtained in the upper unit structure 6. This is because the group III nitride constituting the first intermediate layer 5 that is the uppermost layer of the lower unit structure 6 constitutes the first unit layer 31 that is the lowermost layer of the upper unit structure 6. Since the in-plane lattice constant in the unstrained state is larger than that of the group III nitride and the first unit layer 31 is only formed to a thickness of about 3 nm to 20 nm at most, If the first unit layer 31 is directly formed, the first unit layer 31 inherently has tensile strain, and sufficient compressive strain is not introduced into the composition modulation layer 3.

  Therefore, in the present embodiment, by providing the second intermediate layer 7 between the unit structures 6, it is possible to prevent the problems associated with the introduction of the tensile strain as described above and the individual unit structures. 6 has a sufficient compressive strain.

  Specifically, the in-plane lattice constant in the unstrained state is smaller than the group III nitride constituting the first intermediate layer 5 on the first intermediate layer 5 that is the uppermost layer of the unit structure 6. The second intermediate layer 7 is formed of a group nitride. The second intermediate layer 7 provided in such a manner has misfit dislocations due to a difference in lattice constant from the first intermediate layer 5 in the vicinity of the interface with the first intermediate layer 5, but at least in the vicinity of the surface thereof. The lattice is relaxed, and a substantially unstrained state in which no tensile stress acts is realized. Here, “substantially unstrained” means having a lattice constant substantially the same as the lattice constant in the bulk state at least in the vicinity of the interface with the first intermediate layer 5 immediately below. Yes.

  In such a unit structure 6 formed on the substantially unstrained second intermediate layer 7, tensile stress does not act on the first unit layer 31 that is the lowermost layer. Similarly to the unit structure 6 directly below the second intermediate layer 7, the body 6 is also formed in a mode that preferably includes compression strain.

  Preferably, both the first unit layer 31 and the second intermediate layer 7 are made of AlN. In such a case, since the second intermediate layer 7 and the first unit layer 31 are continuously formed, they substantially constitute one layer, so that tensile stress acts on the first unit layer 31. Is more reliably prevented.

  However, if the thickness of the second intermediate layer 7 is too small, a tensile stress acts on the second intermediate layer 7 as in the case where the first unit layer 31 is formed directly on the first intermediate layer 5. Since the composition modulation layer 3 is formed under the influence, the composition modulation layer 3 is not preferable because the compressive strain is suitably not included in the composition modulation layer 3. On the other hand, if the thickness of the second intermediate layer 7 is too large, the influence of the difference in thermal expansion coefficient between the second intermediate layer 7 itself and the silicon that is the base substrate 1 cannot be ignored. The tensile stress resulting from such a difference in thermal expansion coefficient will act, which is not preferable. As described above, when the second intermediate layer 7 is formed to have a thickness of approximately 15 nm to 150 nm, the second intermediate layer 7 is formed in a substantially unstrained state, and the first unit layer 31 immediately above the second intermediate layer 7 is formed. This is suitable as a requirement that tensile stress does not act on.

  Even when a larger number of unit structures 6 are provided, compressive strain is suitable for all the unit structures 6 by interposing the second intermediate layer 7 between the unit structures 6 in the same manner as described above. The state inherent in is realized. In addition, if the structure of the unit structure 6 is the same, the greater the number of unit structures 6 that are repeatedly stacked, the greater the compressive strain inherent in the buffer layer 8.

  In the epitaxial substrate 10 provided with the buffer layer 8 configured as described above, the buffer layer 8 inherently has a large compressive strain, thereby causing a difference in thermal expansion coefficient between silicon and the group III nitride. A state in which the resulting tensile stress is suitably offset is realized. Thereby, in the epitaxial substrate 10, crack free is realized. In addition, since the tensile stress is offset in such a manner, the epitaxial substrate 10 is warped to 100 μm or less.

  That is, in epitaxial substrate 10 according to the present embodiment, unit structure 6 in which termination layer 4 and first intermediate layer 5 as a strain enhancement layer are formed on composition modulation layer 3 as a strain introduction layer, By providing the buffer layers 8 in such a manner that the unstrained second intermediate layers 7 are alternately stacked, a large compressive strain is inherent in the buffer layers 8 and the difference in thermal expansion coefficient between silicon and group III nitride The tensile stress generated in the epitaxial substrate 10 due to the above is suitably reduced. Thereby, in the epitaxial substrate 10, a crack free is implement | achieved and curvature is also reduced.

  Since the buffer layer 8 is formed on the second underlayer 2b in a state where the accumulation of strain energy is suppressed as described above, the tensile stress canceling effect is accumulated in the second underlayer 2b. It is not disturbed by the strain energy.

  Moreover, repeatedly laminating the unit structure 6 and the second intermediate layer 7 increases the total film thickness of the epitaxial film itself. In general, when a HEMT element is manufactured using the epitaxial substrate 10, the breakdown voltage of the HEMT element increases as the total film thickness increases. Therefore, the configuration of the epitaxial substrate 10 according to the present embodiment is such a breakdown. It also contributes to an increase in voltage.

<Introduction of p-type impurities into the first intermediate layer>
Next, details regarding intentional introduction of p-type impurities into the first intermediate layer 5 will be described.

As described above, in epitaxial substrate 10 according to the present embodiment, each of a plurality of stacked unit structures 6 has a composition III of Al _y Ga _1-y N (0 <y ≦ 0.25). A first intermediate layer 5 made of a group nitride is provided. For the purpose of increasing the voltage resistance of the epitaxial substrate 10, p-type impurities are intentionally introduced into at least one of the first intermediate layers 5. In the present embodiment, intentionally introduced means to exclude the case where p-type impurities are mixed even though artificial introduction is not performed. The p-type impurity is, for example, Mg, Zn or the like. Preferably, the p-type impurity is Mg. In the following, the case where the p-type impurity is introduced only into the first intermediate layer 5 (hereinafter referred to as the channel adjacent intermediate layer) adjacent to the channel layer 9a is referred to as the first mode (introduction of the p-type impurity). The case where p-type impurities are introduced into all the first intermediate layers 5 is referred to as a second mode (introduction of p-type impurities).

The concentration of the p-type impurity in the first intermediate layer 5 is preferably about 1 × 10 ¹⁷ / cm ³ to 2 × 10 ¹⁸ / cm ³ . By viewing such a concentration range, the epitaxial substrate 10 can achieve a higher withstand voltage than an epitaxial substrate having the same composition except that it does not contain p-type impurities. For example, in the case of the epitaxial substrate 10 in which the p-type impurity is introduced in the first mode, the withstand voltage value is increased by about 20% to 30%. In the present embodiment, the withstand voltage is a voltage value at which a leakage current of 1 mA / cm ² is generated when a voltage is applied to epitaxial substrate 10 while increasing the value from 0V. Further, the greater the number of first intermediate layers 5 into which p-type impurities are introduced, the greater the value of withstand voltage. For example, the withstand voltage value of the epitaxial substrate 10 into which the p-type impurity is introduced in the second mode is about 50% larger than the withstand voltage of the epitaxial substrate into which the p-type impurity is not introduced.

  Strictly speaking, in the process of manufacturing the epitaxial substrate 10 by the process as described above, particularly when the epitaxial substrate 10 being manufactured is heated, the p-type impurity introduced into the first intermediate layer 5 is It diffuses into its adjacent layer. Therefore, a small amount of the p-type impurity layer is also present in the adjacent layer.

  In the case of the first mode, since a small amount of p-type impurities are also present in the channel layer 9a, the resistance of the channel layer 9a is increased by this, which improves the withstand voltage of the epitaxial substrate 10. It is thought that it contributes to.

  However, if the p-type impurity is excessively diffused into the channel layer 9a, the crystallinity of the channel layer 9a is deteriorated, and as a result, a sufficient withstand voltage cannot be obtained. Therefore, the diffusion of the p-type impurity into the channel layer 9a only needs to be sufficient to improve the voltage resistance.

In the present embodiment, in view of such a point, as described above, the matrix layer into which p-type impurities are introduced includes a group III containing Al having a composition of Al _y Ga _1-y N (0 <y ≦ 0.25). By using only the first intermediate layer 5 made of nitride, high withstand voltage is realized while suitably suppressing diffusion of the first intermediate layer 5 including the channel layer 9a into adjacent layers.

FIG. 4 shows the epitaxial substrate 10 configured in the first mode, and the epitaxial substrate in which the first intermediate layer 5 is configured by GaN, and p-type impurities are introduced only into the channel adjacent intermediate layer as in the first mode. 10 is a diagram illustrating the result of measuring the concentration profile of the p-type impurity in the channel adjacent intermediate layer and the channel layer 9a by SIMS (secondary ion mass spectrometry) for 10 (see the examples for details). In the figure, the former profile is indicated by the symbol A, and the latter profile is indicated by the symbol B. Mg is used as the p-type impurity, and the Mg element concentration in the first intermediate layer 5 is set to 2 × 10 ¹⁸ / cm ³ .

Comparing the two profiles shown in FIG. 4, in the first intermediate layer 5, the concentrations of both the A and B profiles are 2 × 10 ¹⁸ / cm ³ and are substantially constant. However, in the channel layer 9a, in the profile A, the Mg element concentration is reduced to 1 × 10 ¹⁶ / cm ³ or less, which is below the detection limit, at approximately 0.2 μm from the interface with the adjacent channel intermediate layer. On the other hand, in the profile of B, the Mg element concentration is 1 × 10 ¹⁶ / cm ³ or more from the interface with the channel adjacent intermediate layer to about 0.3 μm. The difference in the profiles is that the diffusion of the p-type impurity is less likely to occur when the p-type impurity is introduced using the first intermediate layer 5 made of Group III nitride containing Al as the matrix layer as in the present embodiment. Show.

  Moreover, the withstand voltage of the epitaxial substrate having the A profile is about 800V, whereas the withstand voltage of the epitaxial substrate having the B profile is about 500V. This indicates that a higher withstand voltage can be obtained by limiting the diffusion of the p-type impurity as in the former epitaxial substrate. Furthermore, this also means that it is not necessary to introduce excessive p-type impurities into the first intermediate layer 5 in order to promote the diffusion of p-type impurities into the channel layer 9a.

  On the other hand, in the case of the second embodiment, the p-type impurity is introduced not only into the channel adjacent intermediate layer but also into the first intermediate layer 5 located between the composition modulation layers 3. As a result, the energy potential of the entire buffer layer 8 is increased, and generation of two-dimensional electron gas at the interface between the first unit layer 31 and the second unit layer 32 of each composition modulation layer 3 is suppressed. It is considered that the withstand voltage of the substrate 10 is further improved.

  Of course, also in the case of this second mode, the introduction of more p-type impurities than necessary into the first intermediate layer 5 and the excessive diffusion of the p-type impurity layer from the first intermediate layer 5 to the adjacent layer may cause a breakdown voltage. This is unnecessary because it does not contribute to the improvement of crystallinity and causes deterioration of the crystallinity of the epitaxial film. As an extreme example, if the p-type impurity is uniformly introduced into the entire buffer layer 8, the withstand voltage of the epitaxial substrate 10 is lowered rather than not introducing the p-type impurity.

It should be noted that the withstand voltage of epitaxial substrate 10 increases as the number of layers containing Al in buffer layer 8 increases. In particular, the second unit layer 32 is formed of a group III nitride having a composition of Al _x Ga _1-x N (0.1 ≦ x ≦ 0.25), and the first intermediate layer is formed of Al _y Ga _1-y. It is preferable to form a group III nitride having a composition of N (0.1 ≦ y ≦ 0.25). It can be said that introduction of p-type impurities as in the present embodiment has an effect of further increasing the withstand voltage.

  As described above, according to the present embodiment, a plurality of unit structures each including a composition modulation layer, a termination layer, and a first intermediate layer and including compression strain are stacked between the base substrate and the functional layer. The buffer layer is formed, and the first intermediate layer is made of a group III nitride containing Al, and at least one of the first intermediate layers is introduced with a p-type impurity, thereby reducing the cost. It is possible to obtain an epitaxial substrate having a large-diameter silicon substrate that is readily available as a base substrate, crack-free, excellent crystal quality, and high withstand voltage.

  In particular, an epitaxial substrate having a high withstand voltage and having a maintained crystal quality can be obtained without introducing a p-type impurity into the low crystalline layer. In addition, even when a p-type impurity is introduced into the first intermediate layer adjacent to the channel layer, an epitaxial substrate having a high withstand voltage and a maintained crystal quality can be obtained.

In addition, the epitaxial substrate 10 may include an interface layer (not shown) between the base substrate 1 and the first base layer 2a. The interface layer has a thickness of about several nm and is preferably made of amorphous SiAl _u O _v N _w .

When an interface layer is provided between the base substrate 1 and the first base layer 2a, the lattice misfit between the base substrate 1 and the second base layer 2b is more effectively mitigated, and each layer formed thereon The crystal quality is further improved. That is, when the interface layer is provided, the AlN layer that is the first underlayer 2a has the same uneven shape as the case where the interface layer is not provided, and there is an inherent grain boundary as compared with the case where the interface layer is not provided. It is formed so as to decrease. In particular, the first underlayer 2a having an improved X-ray rocking curve half-width value on the (0002) plane is obtained. This is because AlN, which forms the first underlayer 2a when the first underlayer 2a is formed on the interface layer, as compared with the case where the first underlayer 2a is formed directly on the undersubstrate 1. As a result, it is difficult to proceed with nucleation, and as a result, lateral growth is promoted as compared with the case where there is no interface layer. The interface layer is formed with a thickness not exceeding 5 nm. When such an interface layer is provided, the first underlayer 2a may be formed so that the half width of the X-ray rocking curve of the (0002) plane is in the range of 0.5 degrees or more and 0.8 degrees or less. it can. In this case, it is possible to form a functional layer with further excellent crystal quality, in which the (0002) plane X-ray rocking curve half-width is 800 sec or less and the screw dislocation density is 1 × 10 ⁹ / cm ² or less. .

  In the formation of the interface layer, after the silicon wafer reaches the first underlayer formation temperature, prior to the formation of the first underlayer 2a, only the TMA bubbling gas is introduced into the reactor, and the wafer is placed in the TMA bubbling gas atmosphere. It is realized by exposing to.

  In addition, when the first underlayer 2a is formed, at least one of Si atoms and O atoms is diffused and dissolved in the first underlayer 2a, or at least one of N atoms and O atoms is diffused and solidified in the undersubstrate 1. It may be an embodiment formed by melting.

  As an example, a plurality of types of epitaxial substrates 10 with different layer configurations of the buffer layer 8 were produced. Table 1 shows the basic configuration of the epitaxial substrate 10 according to the example.

  In the following examples, as shown in Table 1, a plurality of types of epitaxial substrates 10 in which three unit structures 6 were laminated were produced. However, all the epitaxial substrates 10 were the same except for the composition of the first intermediate layer 5 adjacent to the channel layer 9a and the mode of introduction of Mg as a p-type impurity (set concentration at the time of fabrication).

  Table 2 shows the composition, Mg concentration, and withstand voltage of the first intermediate layer 5 adjacent to the channel layer 9a.

In Tables 1 and 2, the Mg concentration in the first intermediate layer 5 adjacent to the channel layer 9a is α (/ cm ³ ), and the Mg concentration in the other first intermediate layers 5 is β (/ cm ³ ). The Mg concentration in the layers other than the first intermediate layer 5 of the unit structure 6 is denoted by γ.

Example 1
In the present example, the composition of the intermediate layer adjacent to the channel (specifically, the value of y of Al _y Ga _1-y N) and its Mg concentration α are variously different from each other under the same conditions. Epitaxial substrate 10 (samples a-1 to a-11) was produced, and the withstand voltage was measured. In all samples, β = γ = 0. That is, Mg is introduced only in the channel adjacent intermediate layer. Samples a-5 to a-7 and a-9 to a-11 correspond to the first aspect described above.

  First, as the base substrate 1, a 4-inch (111) plane single crystal silicon wafer (hereinafter, silicon wafer) having a p-type conductivity type with a substrate thickness of 525 μm was prepared. The prepared silicon wafer was washed with dilute hydrofluoric acid with a composition of hydrofluoric acid / pure water = 1/10 (volume ratio) and sulfuric acid / hydrogen peroxide solution = 1/1 (volume ratio). An SPM cleaning with a cleaning liquid was performed to form an oxide film having a thickness of several millimeters on the wafer surface, which was set in the reactor of the MOCVD apparatus. Next, the reactor was heated to a hydrogen / nitrogen mixed atmosphere, the reactor pressure was set to 15 kPa, and the substrate temperature was heated to 1100 ° C., which is the first underlayer formation temperature.

When the substrate temperature reached 1100 ° C., NH ₃ gas was introduced into the reactor, and the substrate surface was exposed to an NH ₃ gas atmosphere for 1 minute.

Thereafter, TMA bubbling gas was introduced into the reactor at a predetermined flow ratio, and NH ₃ and TMA were reacted to form the first underlayer 2a having a three-dimensional uneven shape on the surface. At that time, the growth rate (deposition rate) of the first underlayer 2a was 20 nm / min, and the target average film thickness of the first underlayer 2a was 100 nm.

When the first underlayer 2a is formed, subsequently, the substrate temperature is set to 1100 ° C., the pressure in the reactor is set to 15 kPa, TMG bubbling gas is further introduced into the reactor, and the reaction of NH ₃ with TMA and TMG An Al _0.1 Ga _0.9 N layer as the first underlayer 2b was formed so as to have an average film thickness of about 40 nm.

Subsequent to the formation of the second underlayer 2b, the buffer layer 8 was formed. In this example, as shown in Table 1, in all samples, the first unit layer 31, the termination layer 4, and the second intermediate layer 7 were all formed of AlN. All the second unit layers 32 were formed of Al _0.15 Ga _0.85 N. Further, the first intermediate layer 5 not adjacent to the channel layer 9a was all formed of Al _0.2 Ga _0.8 N. Then, only the channel adjacent intermediate layer was formed with the composition shown in Table 1, and Mg as a p-type impurity was introduced at the Mg concentration shown in Table 2. Specifically, for the channel adjacent intermediate layer, the value of y was changed to four levels of 0, 0.1, 0.15, and 0.2. Moreover, Mg density | concentration (alpha) is four levels, 1.0 * 10 < ¹⁷ > / cm < ³ >, 5.0 * 10 < ¹⁷ > / cm < ³ >, 2.0 * 10 < ¹⁸ > / cm < ³ >, 2.0 * 10 < ¹⁹ > / cm < ³ >. I made a mistake. The substrate temperature was 1100 ° C., and the reactor internal pressure was 15 kPa. The source gas other than Cp ₂ Mg used for introducing Mg is the same as that used for forming the underlayer 2.

In any sample, after the buffer layer 8 was formed, a channel layer 9a made of GaN was formed to a thickness of 700 nm, and subsequently, a barrier layer 9b made of Al _0.2 Ga _0.8 N was formed to a thickness of 25 nm. In the formation of the channel layer 9a and the barrier layer 9b, the substrate temperature was 1100 ° C., and the reactor internal pressure was 15 kPa. In either case, the source gas used is the same as that used for forming the underlayer 2.

Thus, the epitaxial substrate 10 was obtained. In any epitaxial substrate 10, no crack was confirmed. A voltage was applied to the obtained epitaxial substrate 10 while increasing the value from 0 V, and a voltage value at which a leakage current of 1 mA / cm ² was generated was specified as a withstand voltage.

  As shown in Table 2, first, the withstand voltages of the samples a-1 to a-3 in which the channel adjacent intermediate layer is made of GaN not containing Al are all 500V or less, and the higher the Mg concentration, the higher the Mg concentration becomes. There was a tendency for the withstand voltage to decrease. From these results, it is confirmed that when the channel adjacent intermediate layer does not contain Al, the effect of improving the withstand voltage cannot be obtained even if Mg is introduced into the channel adjacent intermediate layer.

  On the other hand, the withstand voltages of Samples a-4 and a-8 were both over 580V. From these results, it is confirmed that the withstand voltage is higher than that of the above-described a-1 to a-3 not containing Al by configuring the channel adjacent intermediate layer with the group III nitride containing Al. .

  And the withstand voltages of a-5 to a-7 and a-9 to a-11 were in the range of 762V to 806V. From these results, it is confirmed that the withstand voltage is further increased by introducing Mg as a p-type impurity into the channel adjacent intermediate layer made of Group III nitride containing Al.

  From the above results, it is effective for increasing the withstand voltage that the first intermediate layer 5 is formed of group III nitride containing Al and the epitaxial substrate 10 is configured in the above-described first mode. It is shown that.

(Example 2)
In this embodiment, the composition (specifically, the value of y) and the Mg concentration are the same for all the first intermediate layers 5, while the Mg concentration in the layers other than the first intermediate layer 5 of the unit structure 6. Two types of epitaxial substrates 10 (samples b-1 to b-2) with different values were prepared in the same procedure as in Example 1, and the withstand voltage was measured. In any sample, y = 0.2 and α = 2.0 × 10 ¹⁸ / cm ³ . In sample b-1, β = 2.0 × 10 ¹⁸ / cm ³ (= α) and γ = 0. In sample b-2, β = γ = 2.0 × 10 ¹⁸ / cm ³ (= α). That is, the sample b-1 corresponds to the second aspect described above. In the sample b-2, Mg is uniformly introduced into the entire buffer layer 8.

  In any of the obtained epitaxial substrates 10, no crack was confirmed.

  Looking at the evaluation results of the withstand voltage shown in Table 2, the sample b-1 has a higher withstand voltage of 905 V, which is higher than the value of 806 V of the sample a-11 that differs only in the value of β. That is confirmed. This result indicates that the withstand voltage increases as the first intermediate layer 5 into which the p-type impurity is introduced increases. On the other hand, sample b-2 has only a withstand voltage of 558 V, which is lower than a-8 in which Mg is not introduced. This result shows that the effect of improving the withstand voltage cannot be obtained even if the p-type impurity is uniformly introduced into the entire buffer layer 8. That is, considering the results of samples b-1 and b-2 together, it is possible to realize a state in which a small amount of p-type impurities are diffused into the adjacent layer by introducing p-type impurities only into the first intermediate layer 5. Therefore, it is judged to be effective in improving the withstand voltage of 10. Note that when the p-type impurity is uniformly introduced into the entire buffer layer 8, a lower withstand voltage can be obtained than when the p-type impurity is not introduced. This is thought to be due to the deterioration of the material.

DESCRIPTION OF SYMBOLS 1 Ground substrate 2 Ground layer 2a 1st ground layer 2b 2nd ground layer 3 Composition modulation layer 4 Termination layer 5 1st intermediate layer 6 Unit structure 7 2nd intermediate layer 8 Buffer layer 9a Channel layer 9b Barrier layer 10 Epitaxial substrate 31 First unit layer 32 Second unit layer

Claims (25)

For a semiconductor device in which a group III nitride layer group is formed on a base substrate that is single crystal silicon of (111) orientation so that the (0001) crystal plane is substantially parallel to the substrate surface of the base substrate An epitaxial substrate of
A buffer layer in which the first stack unit and the second stack unit are alternately stacked, and the uppermost part and the lowermost part are both configured by the first stack unit;
A channel layer formed immediately above the buffer layer;
A barrier layer formed on the channel layer;
With
The first stack unit is
A composition modulation layer formed by alternately and alternately laminating a first unit layer and a second unit layer made of a group III nitride having different compositions from the base substrate side in this order ;
A first intermediate layer formed on the composition modulation layer and made of a group III nitride containing Al;
Including
The in-plane lattice constant in the unstrained state of the second group III nitride constituting the second unit layer is larger than that of the first group III nitride constituting the first unit layer,
Each of the second unit layers is formed in a coherent state with respect to the first unit layer,
At least one of the plurality of first intermediate layers included in the buffer layer is a first layer made of a group III nitride containing Al;
A p-type impurity is intentionally introduced only in the first layer, and the layer included in the buffer layer and the channel layer are adjacent to the first layer, and the second layer is adjacent to the first layer. P-type impurities diffused from the first layer are present,
An epitaxial substrate for a semiconductor device characterized by the above. The epitaxial substrate according to claim 1,
Of the plurality of first intermediate layers, at least the first intermediate layer adjacent to the channel layer is the first layer.
An epitaxial substrate for a semiconductor device characterized by the above. The epitaxial substrate according to claim 1,
All of the plurality of first intermediate layers are the first layers;
An epitaxial substrate for a semiconductor device characterized by the above. The epitaxial substrate according to any one of claims 1 to 3, wherein
The first intermediate layer is made of a group III nitride having a composition of Al _y Ga _1-y N (0 <y ≦ 0.25);
The channel layer is made of GaN;
An epitaxial substrate for a semiconductor device characterized by the above. The epitaxial substrate according to any one of claims 1 to 4, wherein
The concentration of the p-type impurity in the first layer is 1 × 10 ¹⁷ cm ⁻³ to 2 × 10 ¹⁸ cm ⁻³ .
An epitaxial substrate for a semiconductor device characterized by the above. An epitaxial substrate according to any one of claims 1 to 5,
An epitaxial substrate for a semiconductor device, wherein the first intermediate layer is formed in a coherent state with respect to the composition modulation layer . The epitaxial substrate according to any one of claims 1 to 6,
The first unit layer is made of AlN, and the second unit layer is made of a group III nitride having a composition of Al _x Ga _1-x N (0 ≦ x ≦ 0.25) . Epitaxial substrate. The epitaxial substrate according to any one of claims 1 to 7,
An epitaxial substrate for a semiconductor device , wherein a termination layer having the same composition as that of the first unit layer is provided on the top of the composition modulation layer . The epitaxial substrate according to any one of claims 1 to 8, wherein
The second stacked unit is a second intermediate layer made of a group III nitride having a smaller in-plane lattice constant in a strain-free state than the group III nitride constituting the first intermediate layer.
An epitaxial substrate for a semiconductor device characterized by the above. An epitaxial substrate according to claim 9 , wherein
An epitaxial substrate for a semiconductor device, wherein the second intermediate layer is formed of AlN to a thickness of 15 nm or more and 150 nm or less . The epitaxial substrate according to claim 9 or 10, wherein
An epitaxial substrate for a semiconductor device , wherein the composition of the first unit layer and the composition of the second intermediate layer are substantially the same . Claims 1 an epitaxial substrate according to claim 11,
A first base layer made of AlN formed on the base substrate;
A second underlayer formed on the first underlayer and made of Al _p Ga _1-p N (0 ≦ p <1);
Further comprising
The first underlayer is a polycrystalline defect-containing layer composed of at least one of columnar or granular crystals or domains,
The interface between the first underlayer and the second underlayer is a three-dimensional uneven surface;
The buffer layer is formed immediately above the second underlayer.
An epitaxial substrate for a semiconductor device characterized by the above. The epitaxial substrate according to any one of claims 1 to 12,
The p-type impurity is Mg;
An epitaxial substrate for a semiconductor device characterized by the above. (111) on the underlying substrate is a single crystal silicon of orientation, the substrate surface of the base substrate with respect to (0001) crystal plane of a semiconductor device epitaxial substrate formed by forming a substantially parallel III nitride layer group A manufacturing method comprising :
A buffer layer forming step of forming a buffer layer by alternately stacking the first stack unit and the second stack unit so that the uppermost part and the lowermost part are the first stack unit;
A channel layer forming step of epitaxially forming a channel layer directly on the buffer layer;
A barrier layer forming step of epitaxially forming a barrier layer on the channel layer;
With
As the step of forming the first stacked unit in the buffer layer forming step,
A composition modulation layer forming step for epitaxially forming a composition modulation layer by alternately and alternately laminating a first unit layer and a second unit layer made of a group III nitride having different compositions from the base substrate side in this order;
A first intermediate layer forming step of epitaxially forming a first intermediate layer on the composition modulation layer;
Including
In the composition modulation layer forming step, the in-plane lattice constant in the unstrained state of the group III nitride constituting the second unit layer is larger than the group III nitride constituting the first unit layer. And forming the composition modulation layer such that each of the second unit layers is in a coherent state with respect to the first unit layer,
A p-type impurity is introduced only when at least one of the plurality of first intermediate layers included in the buffer layer is epitaxially formed;
Method of manufacturing epitaxial substrate for semiconductor device, characterized in that. A method for producing an epitaxial substrate according to claim 14 ,
The p-type impurity is introduced into at least the first intermediate layer adjacent to the channel layer among the plurality of first intermediate layers.
A method for producing an epitaxial substrate for a semiconductor device, comprising: A method for producing an epitaxial substrate according to claim 14 ,
Introducing the p-type impurity into all of the plurality of first intermediate layers;
A method for producing an epitaxial substrate for a semiconductor device, comprising: A method for manufacturing an epitaxial substrate according to any one of claims 14 to 16 , comprising:
The first intermediate layer is formed of a group III nitride having a composition of Al _y Ga _1-y N (0 <y ≦ 0.25),
Forming the channel layer from GaN;
A method for producing an epitaxial substrate for a semiconductor device, comprising: A method for manufacturing an epitaxial substrate according to any one of claims 14 to 17,
Introducing the p-type impurity so that the concentration of the p-type impurity is 1 × 10 ¹⁷ cm ⁻³ to 2 × 10 ¹⁸ cm ⁻³ ;
A method for producing an epitaxial substrate for a semiconductor device, comprising: A method for manufacturing an epitaxial substrate according to any one of claims 14 to 18, comprising:
In the first intermediate layer forming step, the first intermediate layer is formed so as to be coherent with the composition modulation layer.
A method for producing an epitaxial substrate for a semiconductor device, comprising: A method for manufacturing an epitaxial substrate according to any one of claims 14 to 19, comprising:
In the composition modulation layer forming step, the first unit layer is formed of AlN, and the second unit layer is a group III nitride having a composition of Al _x Ga _1-x N (0 ≦ x ≦ 0.25). is formed by,
A method for producing an epitaxial substrate for a semiconductor device, comprising: A method for manufacturing an epitaxial substrate according to any one of claims 14 to 20, comprising:
A termination layer forming step of providing a termination layer having the same composition as the first unit layer on the top of the composition modulation layer;
Further method for producing an epitaxial substrate for semiconductor device, characterized in that it comprises a. A method for manufacturing an epitaxial substrate according to any one of claims 14 to 21, comprising:
As the step of forming the second stacked unit,
A second intermediate layer forming step of forming a second intermediate layer made of a group III nitride having an in-plane lattice constant in an unstrained state smaller than that of the group III nitride constituting the first intermediate layer;
Method for manufacturing an epitaxial substrate for semiconductor device, characterized in that it comprises a. The method for manufacturing an epitaxial substrate according to claim 22 ,
A method for producing an epitaxial substrate for a semiconductor device, wherein the second intermediate layer is formed of AlN to a thickness of 15 nm to 150 nm . 24. The method of manufacturing an epitaxial substrate according to claim 14 , wherein
A first foundation layer forming step of forming a first foundation layer made of AlN on the foundation substrate;
A second underlayer forming step of forming a second underlayer made of Al _p Ga _1-p N (0 ≦ p <1) on the first underlayer;
Further comprising
In the first underlayer forming step, the first underlayer is formed as a polycrystalline defect-containing layer composed of at least one of columnar or granular crystals or domains and having a three-dimensional uneven surface. ,
In the buffer layer forming step, the buffer layer is formed immediately above the second underlayer.
A method for producing an epitaxial substrate for a semiconductor device, comprising: 25. A method of manufacturing an epitaxial substrate according to any one of claims 14 to 24, comprising:
The p-type impurity is Mg;
A method for producing an epitaxial substrate for a semiconductor device, comprising:

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