JP5649663B2 - ビット値の格納されているカウントを使用してデータの誤りを訂正するシステムおよび方法 - Google Patents

ビット値の格納されているカウントを使用してデータの誤りを訂正するシステムおよび方法 Download PDF

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JP5649663B2
JP5649663B2 JP2012551186A JP2012551186A JP5649663B2 JP 5649663 B2 JP5649663 B2 JP 5649663B2 JP 2012551186 A JP2012551186 A JP 2012551186A JP 2012551186 A JP2012551186 A JP 2012551186A JP 5649663 B2 JP5649663 B2 JP 5649663B2
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bits
group
bit
count
value
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JP2012551186A
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JP2013518345A (ja
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アントニオ ドブリュー，マヌエル
アントニオ ドブリュー，マヌエル
スカラ，スティーブン
ジョセフ ゴンザレス，カルロス
ジョセフ ゴンザレス，カルロス
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サンディスク テクノロジィース インコーポレイテッド
サンディスク テクノロジィース インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Read Only Memory (AREA)
JP2012551186A 2010-01-27 2011-01-07 ビット値の格納されているカウントを使用してデータの誤りを訂正するシステムおよび方法 Expired - Fee Related JP5649663B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/695,038 2010-01-27
US12/695,038 US8429468B2 (en) 2010-01-27 2010-01-27 System and method to correct data errors using a stored count of bit values
PCT/US2011/020533 WO2011094051A1 (fr) 2010-01-27 2011-01-07 Système et procédé de correction d'erreurs de données à l'aide d'un compte stocké de valeurs de bit

Publications (2)

Publication Number Publication Date
JP2013518345A JP2013518345A (ja) 2013-05-20
JP5649663B2 true JP5649663B2 (ja) 2015-01-07

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JP2012551186A Expired - Fee Related JP5649663B2 (ja) 2010-01-27 2011-01-07 ビット値の格納されているカウントを使用してデータの誤りを訂正するシステムおよび方法

Country Status (7)

Country Link
US (1) US8429468B2 (fr)
EP (1) EP2529305B1 (fr)
JP (1) JP5649663B2 (fr)
KR (1) KR101696389B1 (fr)
CN (1) CN102725738A (fr)
TW (1) TW201145296A (fr)
WO (1) WO2011094051A1 (fr)

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US20140325315A1 (en) * 2012-01-31 2014-10-30 Hewlett-Packard Development Company, L.P. Memory module buffer data storage
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US9064575B2 (en) 2012-08-03 2015-06-23 Micron Technology, Inc. Determining whether a memory cell state is in a valley between adjacent data states
RU2012134916A (ru) * 2012-08-15 2014-02-20 ЭлЭсАй Корпорейшн Способ выбора подходящего кода ldcp
KR102168096B1 (ko) * 2013-03-15 2020-10-20 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 데이터 쓰기 방법
US9218890B2 (en) * 2013-06-03 2015-12-22 Sandisk Technologies Inc. Adaptive operation of three dimensional memory
US20150046772A1 (en) * 2013-08-06 2015-02-12 Sandisk Technologies Inc. Method and device for error correcting code (ecc) error handling
KR102081588B1 (ko) 2013-08-08 2020-02-26 삼성전자 주식회사 Ecc 디코더의 동작 방법 및 그것을 포함하는 메모리 컨트롤러
US9270296B1 (en) * 2013-11-13 2016-02-23 Western Digital Technologies, Inc. Method and system for soft decoding through single read
US9305663B2 (en) * 2013-12-20 2016-04-05 Netapp, Inc. Techniques for assessing pass/fail status of non-volatile memory
US9570198B2 (en) * 2014-05-16 2017-02-14 SK Hynix Inc. Read disturb detection
US10089177B2 (en) 2014-06-30 2018-10-02 Sandisk Technologies Llc Multi-stage decoder
US9614547B2 (en) 2014-06-30 2017-04-04 Sandisk Technologies Llc Multi-stage decoder
KR102023121B1 (ko) * 2014-10-31 2019-11-04 에스케이하이닉스 주식회사 에러를 보정하는 메모리 장치 및 그의 에러 보정 방법
US10147500B2 (en) * 2015-05-22 2018-12-04 SK Hynix Inc. Hybrid read disturb count management
US20160378591A1 (en) * 2015-06-24 2016-12-29 Intel Corporation Adaptive error correction in memory devices
US10303536B2 (en) * 2015-10-28 2019-05-28 Via Technologies, Inc. Non-volatile memory device and control method thereof
US9853661B2 (en) * 2015-12-08 2017-12-26 Apple Inc. On-the-fly evaluation of the number of errors corrected in iterative ECC decoding
KR102375060B1 (ko) * 2016-10-18 2022-03-17 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
US10528422B2 (en) * 2017-11-13 2020-01-07 Stmicroelectronics International N.V. Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM)
US11036578B2 (en) * 2018-04-12 2021-06-15 Samsung Electronics Co., Ltd. Semiconductor memory devices and memory systems including the same
JP7182373B2 (ja) * 2018-04-24 2022-12-02 ラピスセミコンダクタ株式会社 半導体集積回路、記憶装置及びエラー訂正方法
CN110444243A (zh) * 2019-07-31 2019-11-12 至誉科技（武汉）有限公司 存储设备读错误纠错能力的测试方法、系统及存储介质
CN113380303B (zh) * 2020-03-10 2024-06-11 华邦电子股份有限公司 内存存储装置及数据访问方法
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Also Published As

Publication number Publication date
EP2529305A1 (fr) 2012-12-05
KR101696389B1 (ko) 2017-01-13
TW201145296A (en) 2011-12-16
JP2013518345A (ja) 2013-05-20
US20110185251A1 (en) 2011-07-28
EP2529305B1 (fr) 2013-11-27
WO2011094051A1 (fr) 2011-08-04
KR20120114366A (ko) 2012-10-16
US8429468B2 (en) 2013-04-23
CN102725738A (zh) 2012-10-10

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