JP5647843B2 - Manufacturing method of semiconductor light emitting device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor light emitting device such as a light emitting diode (LED) and a semiconductor light emitting device manufactured by the method, and more particularly, to a laser lift-off (growing) a growth substrate used for crystal growth of a semiconductor growth layer. The present invention relates to a manufacturing method having a step of removing by an LLO (Laser Lift Off) method and a semiconductor light emitting device manufactured thereby.

  Semiconductor light emitting devices such as light emitting diodes (LEDs) have been improved in efficiency and output due to recent technological advances. However, as the output increases, the amount of heat generated from the semiconductor light emitting element also increases, resulting in a decrease in reliability.

  In order to solve the above-mentioned problems, a technique is used in which a growth substrate having a relatively low thermal conductivity is removed and a semiconductor growth layer is supported by a support substrate having a relatively high thermal conductivity instead of the growth substrate. It has been. By using such a technique, the heat dissipation of the semiconductor light emitting device can be improved, and further, the emission efficiency, particularly the light extraction efficiency can be expected to increase with the removal of the growth substrate. In other words, it is possible to suppress light absorption that occurs when light passes through the growth substrate, and to reduce the component of the light that is totally reflected at the interface due to the refractive index difference between the semiconductor growth layer and the growth substrate. become.

When peeling off the growth substrate from the GaN-based semiconductor growth layer, a laser lift-off (LLO) method is generally used. Here, the LLO method irradiates a wafer on which a semiconductor growth layer such as GaN is formed on a growth substrate with YAG laser light or excimer laser light from the growth substrate side, and the energy of the laser light is increased. The GaN layer formed on the growth substrate is decomposed into metal Ga and N ₂ gas by being absorbed at the interface between the growth substrate and the semiconductor growth layer and further converting the absorbed energy into heat. This is a peeling method that utilizes this.

When the above-described LLO method is used, there is a problem that cracks or chips occur in the GaN layer due to the pressure of the N ₂ gas generated when the GaN layer is decomposed. As a method for solving such a problem, a method for forming a path for releasing the N ₂ gas generated when the GaN layer is decomposed to the outside of the wafer is formed before the laser beam irradiation, thereby preventing the occurrence of cracks and chips in the GaN layer. It has been known. For example, Patent Document 1 and Patent Document 2 disclose a manufacturing method in which an element dividing groove that penetrates a GaN-based semiconductor growth layer and reaches a sapphire substrate as a growth substrate is formed, and then the sapphire substrate is peeled off by an LLO method. It is disclosed.

  In order to improve the light emission efficiency and the light extraction efficiency, a method is known in which a concavo-convex pattern is formed on a growth substrate and a semiconductor growth layer is stacked on the concavo-convex pattern. The reason for forming the concavo-convex pattern on such a growth substrate is that crystal defects in the semiconductor growth layer can be reduced by forming the semiconductor growth layer on the concavo-convex pattern, and the semiconductor growth layer also corresponds to the concavo-convex pattern on the growth substrate. In some cases, the external quantum efficiency can be improved by scattering / diffracting light emitted from the active layer by the uneven pattern of the semiconductor growth layer. For example, Patent Document 3 discloses a manufacturing method in which a GaN-based semiconductor growth layer is formed on a sapphire substrate on which a concavo-convex pattern is formed, and then the sapphire substrate is peeled off by an LLO method.

JP 2007-534164 A JP 2007-134415 A JP 2007-36240 A

When the growth substrate is completely removed from the GaN-based semiconductor growth layer using the LLO method, the bonding metal material is scattered from the support during laser light irradiation, and the semiconductor growth layer exposed to the N ₂ gas emission path is exposed. Metal material may adhere to the side. Such adhesion of the metal material causes a leak failure of the semiconductor light emitting device, and the yield of the manufacturing process is reduced.

  In order to solve such a problem, a method of covering a part of the side surface of the semiconductor growth layer exposed in the emission path with a protective film is conceivable. In such a case, in order to form the protective film easily and with high precision, the side surface of the semiconductor growth layer is inclined with respect to the surface of the growth substrate so that the emission path width gradually decreases toward the growth substrate. It becomes important. Further, depending on the element dividing method, an inclined side surface may be provided without intention.

However, when the growth substrate is removed by the LLO method from the semiconductor growth layer formed on the concavo-convex pattern of the growth substrate as described above, the semiconductor growth layer formed on the growth substrate having no concavo-convex pattern is used. Compared with the case where the growth substrate is removed by the LLO method, the pressure of the N ₂ gas generated when the GaN layer is decomposed is applied in the thickness direction (ie, growth direction) of the semiconductor growth layer. This is because N ₂ gas is released to the outside along the direction perpendicular to the thickness direction of the semiconductor growth layer (hereinafter referred to as the lateral direction) at the interface between the growth substrate without the uneven pattern and the semiconductor growth layer. This is because the N ₂ gas is less likely to be released laterally by the uneven pattern at the interface between the growth substrate having the uneven pattern and the semiconductor growth layer. When the pressure of the N ₂ gas is easily applied in the thickness direction of the semiconductor growth layer, the thickness of the semiconductor growth layer around the bottom of the emission path as described above (that is, the portion where the growth substrate is exposed) is thin. Cracks are likely to occur in such thin layer portions, and the yield and reliability of the semiconductor light emitting device are reduced.

  The present invention has been made in view of the above points, and its purpose is to prevent adhesion of foreign materials such as metal materials when removing a growth substrate having a concavo-convex pattern formed on the surface by the LLO method. It is another object of the present invention to provide a method for manufacturing a semiconductor light emitting device capable of preventing the occurrence of cracks in the semiconductor growth layer and a semiconductor light emitting device manufactured thereby.

  In order to solve the above-described problem, a method for manufacturing a semiconductor light emitting device, comprising: a plurality of device formation regions on a surface of a growth substrate; device partition regions surrounding the device formation regions; A step of partitioning an uneven surface forming region provided inside and an uneven surface partition region surrounding the uneven surface forming region and having a flat shape, and forming a plurality of convex portions or recesses in the uneven surface forming region; Forming a semiconductor growth layer by sequentially growing a first semiconductor layer, an active layer, and a second semiconductor layer on the surface of the growth substrate; and the step on the uneven surface partition region and the element partition region. Etching the semiconductor growth layer, forming an element dividing groove reaching the surface of the growth substrate while gradually reducing the opening toward the growth substrate, and an inner portion provided on the uneven surface forming region and the unevenness Area A step of forming a plurality of element portions each including a taper portion provided thereon, a step of bonding a support body supporting the plurality of element portions to the plurality of element portions, and a laser from the back side of the growth substrate. And irradiating light to peel off the growth substrate.

  In the method for manufacturing a semiconductor light emitting device of the present invention, a plurality of element formation regions, an element partition region surrounding the plurality of element formation regions, and an uneven surface formation region provided inside the element formation region are formed on the surface of the growth substrate. After partitioning, a plurality of convex portions or concave portions are formed in the uneven surface forming region, and a semiconductor growth layer is formed on the surface of the growth substrate. Further, the flat region defining the uneven surface forming region and the semiconductor growth layer on the element partition region are etched to form an element dividing groove reaching the surface of the growth substrate while gradually decreasing the opening toward the growth substrate. . Thereby, when the growth substrate having the concavo-convex pattern is removed by the subsequent LLO method, it is possible to prevent the occurrence of chipping and cracks in the side portion where the layer thickness of the element portion is thin.

(A) is sectional drawing of the semiconductor light-emitting device based on the Example of this invention, (b) is sectional drawing which shows the structure of the semiconductor growth layer which comprises a semiconductor light-emitting device, (c) is a semiconductor light-emitting device. It is a top view of the n side electrode formation surface of the semiconductor growth layer to comprise. It is sectional drawing which shows each manufacturing process in the manufacturing method of the semiconductor light-emitting device based on the Example of this invention. (A) is a top view of the growth board | substrate in the growth board | substrate preparation process of the manufacturing method of the semiconductor light-emitting device based on the Example of this invention, (b) is the area | region enclosed with the dashed-dotted line of FIG. 3 (a). It is an enlarged view of 3b. It is sectional drawing which shows the semiconductor growth layer which carried out crystal growth on the sapphire substrate. FIG. 3 is a plan view of a growth substrate and a semiconductor growth layer in the step of FIG. It is sectional drawing which shows each manufacturing process in the manufacturing method of the semiconductor light-emitting device based on the Example of this invention. It is sectional drawing which shows each manufacturing process in the manufacturing method of the semiconductor light-emitting device based on the Example of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  First, the structure of the semiconductor light emitting device according to this example will be described with reference to FIGS. 1 (a), (b), and (c). 1A is a cross-sectional view of the semiconductor light emitting device according to the present embodiment, FIG. 1B is an enlarged cross-sectional view of a semiconductor growth layer constituting the semiconductor light emitting device, and FIG. 1C is a semiconductor light emitting device. It is a top view of the n side electrode formation surface of the semiconductor growth layer which comprises an element.

  As shown in FIG. 1A, the semiconductor light emitting device 10 includes a support 11, a bonding layer 12, a p-side electrode 13, an n-side electrode 14, a protective layer 15, and an element unit 20. Further, as shown in FIG. 1B, the element unit 20 includes a p-GaN layer 21, a p-AlGaN cladding layer 22, an active layer 23, and an n-side electrode 14 from the p-side electrode 13 to the n-side electrode 14. It has a stacked structure in which n-GaN layers 24 are sequentially stacked.

  The element part 20 is an inner part 20a having a quadrangular prism shape, which is a region obtained by vertically projecting the p-side surface to the n-side surface, and an outer part formed so as to surround the inner part 20a. And a tapered portion 20b (a portion surrounded by a broken line in FIG. 1A). In the inner part 20a of the element part 20, the surface on which the p-side electrode 13 is formed (p-side surface) is flat. On the other hand, the surface on which the n-side electrode 14 is formed (n-side surface) is partially recessed, and the n-side surface has an uneven shape. That is, a plurality of concave portions 25 are formed on the n-side surface of the inner portion 20a. On the other hand, in the taper portion 20b of the element portion 20, the n-side surface is flat. That is, as shown in FIGS. 1A and 1C, the n-side surface of the element portion 20 is an uneven surface region 26 that is a surface region of the inside 20a and a surface region of the tapered portion 20b. And a flat surface region 27. The uneven surface region 26 has a square shape with a side of about 1020 micrometers (μm), and the flat surface region 27 has a width of about 10 μm. In this embodiment, the concavo-convex surface is formed by the concave portion 25, but the concavo-convex surface may be formed by forming a plurality of protrusions instead of the concave portion 25.

  The recesses 25 are formed in a matrix of 7 columns in the x-axis direction in FIG. 1C and 7 rows in the y-axis direction orthogonal to the x-axis, that is, 7 rows × 7 columns. Moreover, the recessed part 25 has a cylindrical shape, the depth is about 1 micrometer, and the diameter of the bottom face is about 1 micrometer. The center point interval (pitch) between the recesses 25 is about 2 μm. The distance from the edge of the element portion 20 to the outermost concave portion 25 is about 20 μm. In FIG. 1, the recesses 25 are provided in 7 rows × 7 columns, but this is for the sake of simplification and is actually more, for example, about 1000 rows × 1000 columns. Note that the shape of the recess 25 may be various shapes such as a pyramid, a cone, a lens shape, and a hemisphere. Moreover, the dimension and quantity of the recessed part 25 are not limited to the content mentioned above, According to the characteristic of the semiconductor light-emitting device 10, it can adjust suitably. For example, the depth of the recess 25 can be set in the range of 1 to 2 μm, the diameter of the bottom surface is 0.5 to 3 μm, and the pitch is in the range of 1 to 5 μm.

  The taper portion 20b of the element portion 20 has an inclined surface (hereinafter referred to as a taper surface 28) in which the side portion of the element portion 20 gradually spreads from the p-side surface to the n-side surface. In the tapered portion 20b, the angle formed by the n-side surface and the tapered surface 28 is, for example, about 30 degrees. The angle formed by the n-side surface (that is, the surface in the flat surface region 27) and the tapered surface 28 can be set within a range of 30 degrees to 40 degrees, for example.

  The support 11 is a semiconductor substrate such as silicon. The bonding layer 12 is made of an AuSnNi alloy, and the support 11 and the p-side electrode 13 and a part of the protective layer 15 are bonded together while electrically connecting the support 11 and the p-side electrode 13.

  The p-side electrode 13 is formed on the surface on which the p-GaN layer 21 is located (that is, the p-side surface). In addition, the n-side electrode 14 is formed at the central portion on the uneven surface region 25 of the surface on which the n-GaN layer 24 is located (that is, the n-side surface). The p-side electrode 13 has a structure in which Pt, Ag, Ti, and Au are sequentially stacked, and the n-side electrode has a structure in which Ti, Pt, and Au are sequentially stacked.

The protective layer 15 is an oxide film made of silicon dioxide (SiO ₂ ). The protective layer 15 is formed on part of the tapered surface 28 and part of the p-side surface of the element unit 20. The reason why the entire taper surface 28 is not covered with the protective layer 15 is that N ₂ gas generated during laser lift-off (LLO), which will be described later, is easily released to the outside of the element unit 20. It is. The protective layer 15 is formed so as to surround the periphery of the p-side electrode 13.

  Next, with reference to FIGS. 2 to 7, a method for manufacturing the semiconductor light emitting device according to this example will be described in detail.

[Growth substrate preparation process]
In the present embodiment, a metal organic chemical vapor deposition method (MOCVD: Metal Organic Chemical Vapor Deposition ) by _{Al x In y Ga z N (} 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1, x + First, a C-plane sapphire substrate 30 (hereinafter simply referred to as a sapphire substrate 30) is prepared as a substrate (growth substrate) for forming a semiconductor growth layer of y + z = 1) (FIG. 2A). Here, FIG. 2 is a cross-sectional view showing each manufacturing step in the method for manufacturing the semiconductor light emitting device 10. Note that the growth substrate is not limited to the C-plane sapphire substrate of this embodiment, and an R-plane sapphire substrate or a substrate such as MgAl ₂ O ₄ can also be used.

  Next, an uneven pattern is formed on the surface of the sapphire substrate 30 (FIGS. 2B, 3A, and 3B). Here, FIG. 3A is a plan view of the sapphire substrate 30 in this step, and FIG. 3B is an enlarged view of a region 3b surrounded by a one-dot chain line in FIG.

As a specific process, first, a plurality of element formation regions 30a (for example, a square region having a side of about 1040 μm) are defined on the surface of the sapphire substrate 30 (FIGS. 2B and 3A). Further, the uneven surface forming region 30c (a square region having a side of about 1000 μm) is defined by the flat region 30b, and the uneven surface forming region 30c is provided inside the element forming region 30a (FIGS. 2B and 3B). )). The flat region 30b is a region that surrounds the uneven surface forming region 30c included in the element forming region 30a (an uneven surface partition region), and a region (element partition region) that will be described later between adjacent element forming regions 30a. It consists of. Subsequently, a resist is applied on the sapphire substrate 30, and then the resist is patterned by photolithography. In the present embodiment, the convex portions are formed so as to be arranged in a matrix of 7 rows × 7 columns in each of the uneven surface forming regions 30 c on the sapphire substrate 30. Here, the element formation region 30a is a region where the element portion 20 is formed, and an element isolation groove described later is located between the element formation region 30a and another element formation region 30a adjacent thereto. Thereafter, using the patterned resist as a mask, reactive ion etching (RIE) using BCl ₃ and Ar is performed to form a protrusion 30 d on the surface of the sapphire substrate 30. Thereafter, the resist is removed, and the formation of the concavo-convex pattern including the convex portions 30d arranged in a matrix of 7 rows × 7 columns is completed in each of the concavo-convex surface forming regions 30c on the sapphire substrate 30 (FIG. 2B). ), FIG. 3 (b)).

  In this embodiment, the protrusions 30d are cylindrical protrusions having a diameter of about 1 μm and a height of about 1 μm, and the center point interval (pitch) between the protrusions 30d is about 2 μm. The width of the concave portion 30e, which is the interval between the convex portions 30d, is equal to the distance obtained by removing the diameter of the convex portion 30d from the center point interval. In addition, the dimension of the convex part 30d is not restricted to this, For example, the diameter of the convex part 30d can be set to the range of 0.5-3 micrometers, the depth is 1-2 micrometers, and the pitch is 1-5 micrometers. it can. In FIGS. 2 and 3, the protrusions 30d are provided in 7 rows × 7 columns, but this is for simplification, and actually more, for example, approximately 1000 rows × 1000 columns. is there.

  In terms of design, for example, the convex portion 30d is preferably formed at a position spaced about 1.5 μm from the outer edge so that the side surface of the concave portion 30e surrounding the convex portion 30d does not coincide with the outer edge of the concave-convex surface forming region 30c. . This is because a variation in the thickness of the semiconductor growth layer formed on the sapphire substrate 30 causes a shift between the inner portion 20a and the tapered portion 20b for each element formed on the sapphire substrate 30. This is because the surface area of the tapered portion 20b is completely flattened in any area on the wafer in consideration of the shift width. In addition, the distance from the side surface of the convex part 30d to an outer edge is not limited to the distance mentioned above, For example, it can set in the range of 1.0-11 micrometers.

In the present embodiment, the cylindrical convex portion 30d is formed, but depending on the shape of the concave portion 25 of the element portion 20, the shape of the convex portion 30d is changed to various shapes such as a pyramid, a cone, a lens shape, and a hemisphere. be able to. In this embodiment, a resist is used as an etching mask, but SiO ₂ or metal may be used instead of the resist. Furthermore, although the element forming region 30a and the concavo-convex surface forming region 30c are square, other shapes such as a circle or a triangle may be used.

  In this embodiment, a region (element partition region), which will be described later, between the adjacent element formation regions 30a is flattened. However, even if a concave or convex portion is formed in the element partition region. Good.

[Semiconductor growth layer formation process]
Next, thermal cleaning is performed by heating the sapphire substrate 30 on which the concavo-convex pattern is formed in a hydrogen atmosphere at 1000 degrees Celsius (1000 ° C.) for 10 minutes. Next, the low temperature buffer layer 41, the underlying GaN layer 42, the n-GaN layer 24, the active layer 23, the p-AlGaN cladding layer 22, and the p-GaN are formed on the surface of the sapphire substrate 30 on which the concavo-convex pattern is formed by MOCVD. A semiconductor growth layer 40 composed of the layer 21 is formed (FIGS. 2C and 4). Here, each semiconductor layer constituting the semiconductor growth layer 40 is sequentially stacked on the sapphire substrate 11 along the C-axis direction of the wurtzite crystal structure by MOCVD. FIG. 4 is a cross-sectional view showing the semiconductor growth layer 40 grown on the sapphire substrate 30.

Specifically, the substrate temperature (growth temperature) is set to 500 ° C., TMG (trimethylgallium) (flow rate 10.4 μmol / min) and NH ₃ (flow rate 3.3 LM) are supplied for about 3 minutes, and the low-temperature buffer layer 41 made of GaN. Is formed on the sapphire substrate 30. Thereafter, the substrate temperature is raised to 1000 ° C. and held for about 30 seconds to crystallize the low temperature buffer layer 41. Subsequently, while maintaining the substrate temperature at 1000 ° C., TMG (flow rate 45 μmol / min), NH ₃ (flow rate 4.4 LM) and SiH ₄ (flow rate 2 × 10 ⁻⁴ mol / min) as a dopant gas are supplied for about 20 minutes. Then, a base GaN layer 42 having a thickness of 1 μm is formed.

Next, TMG (flow rate 45 μmol / min), NH ₃ (flow rate 4.4 LM), and SiH ₄ (flow rate 2.7 × 10 ⁻⁹ mol / min) as a dopant gas are supplied for about 90 minutes at a substrate temperature of 1000 ° C. Then, an n-GaN layer 24 having a thickness of 6 μm is formed. Subsequently, an active layer 23 is formed on the n-GaN layer 24. In this example, a multiple quantum well structure made of InGaN / GaN was used as the active layer 23. That is, five cycles of growth are performed with InGaN / GaN as one cycle. Specifically, the substrate temperature is set to 700 ° C., TMG (flow rate 3.6 μmol / min), TMI (trimethylindium) (flow rate 10 μmol / min), NH ₃ (flow rate 4.4 LM) are supplied for about 33 seconds, and the film thickness 2 A 2 nm InGaN well layer is formed. Subsequently, TMG (flow rate 3.6 μmol / min) and NH ₃ (flow rate 4.4LM) are supplied for about 320 seconds to form a GaN barrier layer having a thickness of 15 nm. The active layer 23 is formed by repeating such growth for five periods.

Next, the substrate temperature was raised to 870 ° C., TMG (flow rate 8.1 μmol / min), TMA (trimethylaluminum) (flow rate 7.5 μmol / min), NH ₃ (flow rate 4.4 LM), and Cp ₂ Mg (bis -cyclopentadienyl Mg) (flow rate 2.9 × 10 ⁻⁷ μmol / min) is supplied for about 5 minutes to form a p-AlGaN cladding layer 22 having a thickness of about 40 nm. Subsequently, while maintaining the substrate temperature, TMG (flow rate 18 μmol / min), NH ₃ (flow rate 4.4 LM), and Cp ₂ Mg (flow rate 2.9 × 10 ⁻⁷ μmol / min) as a dopant were supplied for about 7 minutes, A p-GaN layer 21 having a thickness of about 150 nm is formed. On the sapphire substrate 30, a semiconductor growth layer 40 composed of these semiconductor layers is formed (FIG. 4).

[Element division groove forming process, taper surface forming process]
Next, element dividing grooves 43 for partitioning individual semiconductor light emitting elements are formed in the semiconductor growth layer 40 positioned only in the flat region 30b partitioned on the surface of the sapphire substrate 30.

  As a specific process, first, a resist 50 is applied uniformly (layer thickness: about 10 μm) on the surface of the semiconductor growth layer 40 using a spin coater. Subsequently, an opening 51 is formed by photolithography, and the resist 50 is patterned in a lattice shape. Here, patterning is performed so that each planar shape of the resist remaining on the semiconductor growth layer 40 becomes a square of about 1040 μm × 1040 μm (FIG. 2D). Further, the patterning is performed so that the bottom surface of the opening 51 (the region where the semiconductor growth layer 40 is exposed by the opening 51) is located only directly above the flat region 30b. In this embodiment, since the semiconductor growth layer 40 transmits visible light and the sapphire substrate 30 is provided with an uneven pattern, the photolithography mask can be positioned using the uneven pattern. Thereby, the precision of the patterning of the resist 50 can be improved. Thereafter, the patterned resist 50 is post-baked, and the side surfaces of the remaining square resist 50 are inclined. Here, the inclination angle of the side portion of the resist (inclination angle of the side surface of the resist 50 with respect to the surface of the semiconductor growth layer 40) is about 30 degrees.

Next, the wafer on which the resist 50 having the above-described shape is formed is put into a reactive ion etching apparatus, and the resist 50 having the above-described shape is used as a division groove forming mask, and dry etching using Cl ₂ plasma is performed on the semiconductor growth layer 40. To apply. Here, the width of the opening 51 of the resist 50 that is the dividing groove forming mask is smaller than the width of the resist (flat surface forming mask) formed on the flat region 30 b when the convex portion 30 d is formed on the sapphire substrate 30. As a result, lattice-shaped element dividing grooves 43 reaching the sapphire substrate 30 are formed in the semiconductor growth layer 40 (FIGS. 2E and 5). As shown in FIG. 2E, the formation width of the element dividing groove 43 (the distance between the element portion 20 and another element portion 20 adjacent thereto) is narrower than the width of the flat region 30b. The element dividing groove 43 is formed in a region immediately above the flat region 30b.

  In the present embodiment, the minimum width of the element dividing groove 43 (exposed width of the sapphire substrate 30) is about 100 μm, and the semiconductor dividing layer 40 is formed by, for example, an element piece (element region) having a side of about 1040 μm. It is divided into a certain element unit 20.

  In this embodiment, since the above-mentioned dry etching selection ratio is about 1, the inclined shape of the resist side portion used as the dry etching mask is transferred to the semiconductor growth layer 40. That is, the opening width of the element dividing groove 43 is gradually reduced from the p-side surface of the semiconductor growth layer 40 toward the sapphire substrate 30. Due to the shape of the element dividing groove 43, the cross-sectional shape of the element portion 20 is substantially trapezoidal, and the side portion of the element portion 20 is inclined so as to gradually spread from the p-side surface to the n-side surface. doing. That is, by forming the element isolation groove 43, the side portion of the element unit 20 has a tapered surface 28 that is inclined with respect to the sapphire substrate 30.

  Further, as shown in FIGS. 2 (e) and 5, the tapered portion 20 b (the portion surrounded by the broken line in FIG. 2 (e)) that is the side portion having the tapered surface 28 is formed on the sapphire substrate 30. It does not face the uneven surface forming region 30c. That is, the taper portion 20b is formed only above the flat region 30b of the sapphire substrate 30, that is, only on the uneven surface partition region. Moreover, the uneven surface forming region 30c is included on the surface of the inner portion 20a. Here, FIG. 5 is a plan view of the sapphire substrate 30 and the semiconductor growth layer 40 in the step of FIG.

  If the taper portion 20b and the uneven surface forming region 30c have the positional relationship described above, the element isolation groove 43 can be formed by appropriately adjusting the thickness and the inclination angle of the resist 50.

[Protective layer forming step]
Next, the protective layer 15 that covers the p-side surface of the element portion 20 and the tapered surface 28 is formed. (FIG. 6A). FIG. 6 is a cross-sectional view showing each manufacturing process in the method for manufacturing the semiconductor light emitting device 10.

Specifically, first, a resist is applied so as to cover the element portion 20 and the sapphire substrate 30, and then the resist is patterned by photolithography. In this embodiment, the resist is patterned so that the opening is located in the region where the protective layer 15 is to be formed. Subsequently, SiO ₂ is deposited using a known deposition technique such as sputtering, chemical vapor deposition (CVD), or vapor deposition. Here, in order to ensure electrical insulation, adhesion and strength, the layer thickness of SiO ₂ is about 0.3 μm. Further, the protective layer 15 is completed by removing the patterned resist and unnecessary SiO ₂ . Here, the protective layer 15 is formed so as to cover a part of the p-side surface of the element part 20 and a part of the tapered surface 28 of the element part 20. More specifically, in consideration of adhesion of a foreign material such as a metal material during LLO, which will be described later, and destruction of the semiconductor growth layer 40, the protective layer 15 is exposed from the surface on the p side of the element portion 20 to the exposed region of the active layer Is preferably formed so as to cover at least the sapphire substrate 30 and not to contact the sapphire substrate 30. For example, a gap of about 1 μm is preferably formed between the sapphire substrate 30 and the protective layer 15 in order to secure an N ₂ gas emission path.

Although the lift-off method is used in the protective layer forming method described above, SiO ₂ may be formed first, and etching may be performed so that the formed SiO ₂ has a desired shape. Moreover, the layer thickness of a protective layer can be set within the range of 0.1-0.6 micrometer, for example.

[P-side electrode forming step]
Next, the p-side electrode 13 is formed in a desired region on each surface of the element portion 20 (FIG. 6B). More specifically, first, a resist is applied so as to cover the protective layer 15, the element unit 20, and the sapphire substrate 30. Subsequently, the resist is patterned by photolithography. Pt (1 nm), Ag (150 nm), Ti (100 nm), Pt (200 nm), and Au (200 nm) are sequentially deposited by electron beam evaporation on the opening portion of the patterned resist. Thereafter, the p-side electrode 13 is completed by removing the resist. In this embodiment, the resist is patterned so that the p-side electrode 13 is not formed on the protective layer 15, the tapered surface 28 of the element portion 20, and the sapphire substrate 30.

  Note that the p-side electrode 13 has excellent adhesion and ohmic properties with the element portion 20 and excellent bonding characteristics with the support described later, due to the structure described above. In addition, the p-side electrode 13 can efficiently reflect the light emitted from the active layer 23, and can prevent the deposited metal from diffusing with high accuracy (particularly, prevention of mixing into the element portion 20). Furthermore, although the formation process of the p-side electrode 13 described above is performed after the protective layer 15 is formed, the p-type electrode 13 may be formed first, and then the protective layer 15 may be formed.

[Lamination process]
After the p-type electrode 13 is formed, the wafer obtained through the above steps and the prepared support 11 are bonded to each other through the bonding layer 12 (FIG. 6C).

  As a specific process, first, a support 11 including a conductive support substrate (for example, a silicon substrate to which boron is added) and an electrode layer is prepared. As a more specific structure, an electrode layer is formed by sputtering on the surface (first main surface) of the conductive support substrate. The electrode layer is a multilayer film composed of, for example, titanium and platinum. Here, the film thickness of titanium is about 25 nm, and the film thickness of platinum is about 100 nm. Next, a solder layer serving as a connection layer is formed on the surface of the support 11 by solidification after melting. More specifically, a solder layer in which Ni, Au, and AuSn are sequentially stacked is formed by sputtering on a surface (second main surface) facing the first main surface of the conductive support substrate. Ni constituting the solder layer has a role of absorbing Sn when AuSn is melted. Further, Ni has an effect of suppressing peeling during re-solidification after AuSn is melted. Furthermore, the Ni film thickness is desirably about 100 nm or more from the viewpoint of improving wettability to AuSn and suppressing peeling. In addition, since Pt or Pd (palladium) also has an effect of suppressing peeling at the time of resolidification after AuSn is melted, a layer made of Pt or Pd may be formed instead of Ni. Au constituting the solder layer has an effect of improving wettability of AuSn and preventing oxidation of Ni. The film thickness of Au is, for example, about 30 nm. The composition ratio of Au and Sn of AuSn constituting the solder layer is, for example, about 8: 2 by weight and about 7: 3 by atomic ratio. The film thickness of AuSn is about 600 nm, for example.

Next, the solder layer described above is closely adhered to the p-side electrode 13 and the protective layer 15 formed on the element unit 20. Thereafter, the closely adhered sapphire substrate 30 and the support 11 are thermocompression bonded in a nitrogen atmosphere. The thermocompression bonding conditions are, for example, a pressure of about 300 to 500 N / cm ² , a temperature of about 280 ° C. to 370 ° C., and a pressure bonding time of about 10 minutes. By this thermocompression bonding, AuSn is melted and dissolved in AuSn in which Au and Ni are melted. Furthermore, Au and Sn diffuse and are absorbed by Ni. Subsequently, the molten AuSn is solidified to form the bonding layer 12 made of an AuSnNi alloy, and the bonding (bonding) of the support 11 to the p-side electrode 13 and the protective layer 15 is completed.

[Growth substrate removal process]
Next, the sapphire substrate 30 is peeled from the element portion 20 by the LLO method. More specifically, excimer laser light is irradiated from the back surface (surface on which the element portion 20 is not formed) side of the sapphire substrate 11. The wavelength of the excimer laser light is about 248 nm, and the energy density is about 850 mJ / cm ² . Further, a KrF excimer laser light source was used as a light source of excimer laser light. The irradiation range of one shot is set so as to include the entire interface between the element unit 20 and the sapphire substrate 30 as shown in FIG. That is, after excimer laser light is irradiated to one element part 20, excimer laser light is sequentially irradiated to the other element parts 20 adjacent to the element part 20 irradiated with the laser light. Here, FIG. 7 is a cross-sectional view showing each manufacturing step in the method for manufacturing the semiconductor light emitting device 10.

As described above, the excimer laser light is transmissive to sapphire 30 while being absorbed by GaN constituting the element portion 20. Therefore, in this embodiment, part of the low-temperature buffer layer 41 and the underlying GaN layer 42 is decomposed into metal Ga and N ₂ gas near the interface with the sapphire substrate 30. Thereby, the sapphire substrate 30 is peeled from the element part 20 in the laser light irradiation part.

In addition, the element isolation groove 43 functions as a discharge path for N ₂ gas generated from the element unit 20 by laser light irradiation in this step. That is, the generated N ₂ gas is released outside the wafer via the element isolation groove 43 without staying at the interface between the element unit 20 and the sapphire substrate 30. Thereby, the pressure of the N ₂ gas acting on the element part 20 is relaxed, and it becomes possible to prevent the occurrence of cracks.

Furthermore, the tapered portion 20 b of the element portion 20 does not oppose the uneven surface forming region 30 c of the sapphire substrate 30 and is formed only on the flat surface of the sapphire substrate 30. For this reason, even if N ₂ gas or the like is generated during the LLO, a large pressure is not applied between the tapered portion 20b and the sapphire substrate 30 in the growth direction which is the thickness direction of the semiconductor growth layer 40, The generated N ₂ gas or the like is released to the outside of the wafer along a direction orthogonal to the growth direction. Therefore, even in a thin layer portion such as the taper portion 20b, problems such as chipping and breakage do not occur during LLO.

  Further, in the LLO, foreign substances such as a metal material constituting the bonding layer 12 are scattered, but the protective layer 15 is formed on the tapered surface 28 where the active layer 23 is exposed. It does not adhere to the active layer 23. Thereby, the characteristic defect of the semiconductor light emitting element due to the metal material adhesion is reduced.

  By irradiating the entire area of the wafer with laser light, the sapphire substrate 30 can be completely separated from the element portion 20 (FIG. 7B). Further, when the sapphire substrate 30 is peeled off, the concave portion 25 of the element portion 20 formed so as to correspond to the convex portion 30d of the sapphire substrate 30 is exposed.

  In this embodiment, a KrF excimer laser is used as the laser light source, but an ArF excimer laser with a wavelength of 193 nm or an Nd: YAG laser with a wavelength of 266 nm can also be used. Further, the n-side surface of the element portion 20 exposed by the decomposition of the GaN is a C-plane (N plane).

[N-side electrode forming step]
Next, a resist is applied so as to cover the n-GaN layer 24 constituting the element unit 20. Subsequently, the resist is patterned by photolithography. Ti (25 nm), Pt (100 nm), and Au (800 nm) are sequentially deposited by electron beam evaporation on the opening of the patterned resist. Thereafter, the resist is removed, and an n-side electrode 14 is formed (FIG. 7C). Since the exposed surface of the n-GaN layer 24 becomes a light emitting surface, the n-side electrode 14 may be formed so that the n-side electrode 14 has a minimum area required for wire bonding when the semiconductor light emitting device is mounted. preferable. In this embodiment, the resist is patterned so that the n-side electrode 14 is positioned at the center of the n-GaN layer 24 of each semiconductor light emitting element.

[Element isolation process]
Next, the support 11 is cut by dicing, and the wafer that has undergone the above steps is separated into chips (chips) for each semiconductor light emitting element. The method of dividing into pieces is not limited to dicing, and point scribe / breaking, laser scribe, or the like can be used.

  The semiconductor light emitting device 10 according to this example is completed through the above steps.

  As described above, in the method for manufacturing the semiconductor light emitting device of this example, the surface of the sapphire substrate 30 is divided into the plurality of element formation regions 30a and the uneven surface formation region 30c provided inside the element formation region 30a. A plurality of convex portions 30d are formed in the surface forming region 30c, and the semiconductor growth layer 40 is formed on the surface on which the convex portions 30d are formed. Further, the semiconductor growth layer 40 on the flat region 30b that partitions the uneven surface forming region 30c is etched to form an element dividing groove 43 that reaches the surface of the sapphire substrate 30 as the opening gradually decreases toward the sapphire substrate 30. . Thereby, when removing the sapphire substrate 30 having the concavo-convex pattern by the subsequent LLO method, it is possible to prevent the side portion (taper portion 20b) where the layer thickness of the element portion 20 is thin and the occurrence of cracks. it can.

  Further, in the method for manufacturing a semiconductor light emitting device of the present invention, since the active layer 23 exposed at the side portion of the element portion 20 is covered with the protective layer 15, foreign materials such as a metal material generated at the time of LLO are exposed to the active layer 15. Can be prevented.

  In this embodiment, the upper and lower electrodes are provided, but a flip chip is also conceivable. Before the bonding step, the n-side electrode is exposed, and the n-side electrode and the p-side electrode are separated and provided on the support side to form a flip chip. At this time, it is preferable that an insulator is provided so as not to conduct between the n-side electrode and the p-side electrode.

DESCRIPTION OF SYMBOLS 10 Semiconductor light emitting element 11 Support body 12 Bonding layer 13 P side electrode 14 N side electrode 15 Protective layer 20 Element part 20a Inner part 20b Tapered part 25 Recessed part 28 Tapered surface 30 Sapphire substrate 30a Element formation area 30b Flat area 30c Uneven surface formation area 30d Convex 40 Semiconductor growth layer

Claims (2)

A method for manufacturing a semiconductor light emitting device, comprising:
A plurality of element formation regions on the surface of the growth substrate, an element partition region surrounding the plurality of element formation regions, an uneven surface formation region provided inside the element formation region, and a flat surface surrounding the uneven surface formation region Partitioning the uneven surface partition region having a shape, and forming a plurality of protrusions or recesses in the uneven surface formation region;
Forming a semiconductor growth layer by sequentially growing a first semiconductor layer, an active layer, and a second semiconductor layer on the surface of the growth substrate;
Etching the semiconductor growth layer on the uneven surface partition region and the element partition region, forming an element dividing groove that reaches the surface of the growth substrate as the opening gradually decreases toward the growth substrate, Forming a plurality of element parts composed of an inner part provided on the uneven surface forming region and a tapered part provided on the uneven surface partition region;
Bonding a support that supports the plurality of element portions to the plurality of element portions;
And a step of peeling the growth substrate by irradiating a laser beam from the back surface side of the growth substrate. The protrusions or recesses are provided at regular intervals,
The convex portion or concave portion at the extreme end of the concave / convex surface forming region is provided on the inner side by an interval of the convex portion or concave portion than the outer edge of the concave / convex surface forming region,
The manufacturing method according to claim 1, wherein a portion between the convex portion or the concave portion at the extreme end of the uneven surface forming region and the outer edge is provided as the same plane as the uneven surface partition region.

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