JP5646402B2 - Nonvolatile memory page management method - Google Patents

Description

  The present invention relates to a page management method for a nonvolatile memory, and more particularly to a method for storing and initializing a logical page address-physical page address conversion table used for accessing a nonvolatile memory.

  One of the non-volatile memories that are currently widely used is a NAND flash memory, which is applied to various types of storage devices such as an SSD (Solid State Drive) and an SD (Secure Digital) memory card.

  The unit for reading and writing to the NAND flash memory is a unit called a page composed of memory cells of several hundred bytes to several kilobytes, and cannot be read or written in byte units. In order to write data again on a page where data has been written, it is necessary to erase the previous stored contents before rewriting in units called blocks composed of a plurality of pages. For this reason, when data at the same page address is overwritten, in addition to the time for erasing the block to which the page belongs, the time for saving the data of all pages other than the overwriting target in the same block to the other memory area is the same. It takes a long time to erase a block, and it takes time to write new data to the erased block and write back the data of all saved pages. In addition, since the number of times that a block can be erased is limited, the above-described overwrite method increases the possibility of affecting the reliability of the NAND flash memory.

  In order to avoid the above-described load and reliability problems, the address conversion table is effective. When data is overwritten in the NAND flash memory, new data is written in an empty page other than the page where the original data is stored. Therefore, even if the page where the new data is written is different from the original data, the address that the access source recognizes (hereinafter referred to as the logical address) so that the latest data overwritten by the access source can be read with a consistent address. ) And the address of the page where the latest data corresponding to the address is physically stored on the NAND flash memory (hereinafter referred to as a physical address) is an address conversion table. Patent Document 1 is a prior art document related to the address conversion table.

  The memory system of Patent Document 1 includes a logical-physical page address conversion table called a SAT (sector allocation table) arranged in the order of logical addresses on a nonvolatile memory, and a continuous area including the most recently accessed SAT entry is a cache memory. Is temporarily stored. Also, a list of logical addresses written with data called WSL (write sector list) is provided in the temporary storage area. When the WSL becomes full, the SAT is updated, and then the WSL is erased. Then, the updated contents of the SAT are written in a block called ASB (additional SAT block), and when the ASB becomes full, the SAT is reconstructed and written back to the SAT block. Furthermore, after the last ASB writing, the control block is provided with information on the destination to which data is written for the first time. At initialization, the logical address written in the header is acquired in the range from the physical address pointed to by the control block to the physical address where data was written immediately before the power is turned off, and the WSL is reconstructed.

Special Table 2002-537596

  However, in the above-described prior art, as the range of logical addresses to which data is written before the WSL becomes full from empty, the range of writing to the ASB on the non-volatile memory or the reconstruction of the ASB to the SAT is increased. There is a risk that the update range of the SAT may cover the entire range in the worst case.

  Therefore, the data write performance when the WSL is full is greatly affected by the range of logical addresses to which data has been written so far.

  The outline of the means for solving the above-mentioned problems is as follows. That is, the page management method according to the present invention includes a logical-physical page address conversion table for all areas of the nonvolatile memory arranged in the order of logical page addresses on the volatile memory, and erases a logical page address allocation history described later. For every fixed period from when the data is filled, one area in the logical-physical page address conversion table is stored in the nonvolatile memory regardless of the range of logical addresses to which data has been written.

  At the time of initialization, each area in the logical-physical page address conversion table is sequentially read from the non-volatile memory to the storage source area on the volatile memory from the oldest storage timing to the logical-physical page address. Restore the translation table. In each of the areas, the latest version is read. Here, as described above, the entire area of the logical-physical page address conversion table is not stored at a moment when the power is turned off, but is partially stored at periodic timing. The means for returning the logical-physical page address conversion table read in step 1 to the state at the time of the previous power-off is required.

  There are two means for that. First, a combination of a write destination logical page address and a write destination physical page address to which data has been written since the previous save was completed at the same timing as one area in the logical-physical page address conversion table is saved. A logical page address allocation history composed of all of the above is stored in the nonvolatile memory.

  Each time each area in the logical-physical page address conversion table is read onto the volatile memory, the logical page address stored in the nonvolatile memory after one cycle from the timing when it is stored in the nonvolatile memory The allocation history is referred to, and the read destination area of the logical-physical page address conversion table is overwritten with the write destination physical page address corresponding to the write destination logical page address recorded therein. Thus, the logical-physical page on the volatile memory is alternately repeated by repeating the read cycle of each area in the logical-physical page address conversion table and the cycle of reflecting the logical page address allocation history. The address conversion table can be returned to the state at the time when the area in the logical-physical page address conversion table was last saved in the nonvolatile memory before the previous power failure.

  After reading the area in the logical-physical page address conversion table stored in the non-volatile memory at the last timing before the previous power interruption to the volatile memory, the logical page address allocation history as described above Therefore, the second means for returning the logical-physical page address conversion table on the volatile memory to the state immediately before the previous power-off is required. Specifically, the write destination logical page address of the data write destination physical page is included in the write content. The pointer information to the physical page is stored in the nonvolatile memory at the same timing as the previous area in the logical-physical page address conversion table is stored in the nonvolatile memory.

  After reading the area in the logical-physical page address conversion table stored in the nonvolatile memory at the last timing before the previous power shutdown to the volatile memory, at the last timing before the last power shutdown. The pointer information stored in the nonvolatile memory is referred to, and the read destination area of the logical-physical page address conversion table is overwritten with the physical page address indicated by the pointer information. The overwriting position is specified with reference to the write destination logical page address recorded in the physical page pointed to by the pointer information.

  By the means described so far, at the time of initialization, the logical-physical page address conversion table can be restored to the state immediately before the previous power-off.

  According to the present invention, the logical-physical page address conversion table is stored in the non-volatile memory in such a manner that the logical-physical page address conversion table is divided into a plurality of areas at a specific cycle and can be restored to the state immediately before the previous power-off at initialization. Data can be written with stable performance.

It is a figure which shows the structure of embodiment of this invention. It is a figure which shows an example of the logical-physical page address conversion table in embodiment of this invention. It is a figure which shows an example of the logical page address allocation log | history in embodiment of this invention. It is a figure which shows an example of the pointer information in embodiment of this invention. 6 is a flowchart illustrating a flow of data writing and updating and saving of a logical-physical page address conversion table, a logical page address assignment history, and pointer information in the embodiment of the present invention. It is a figure which shows the result of having repeated the writing of data in the embodiment of this invention, and the update and preservation | save of a logical-physical page address conversion table, a logical page address allocation history, and pointer information in time series. 7 is a flowchart illustrating a flow of restoring a logical-physical page address conversion table to a state immediately before the previous power-off at the time of initialization in the embodiment of the present invention. It is a flowchart following FIG. (A)-(i) is a figure which shows the middle course of the flow which restores a logical-physical page address conversion table to the state just before the last power-off at the time of initialization, and a time series in embodiment of this invention. It is.

  Hereinafter, an embodiment of a page management method according to the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to these embodiments.

<< First Embodiment >>
The configuration of the first embodiment of the present invention is shown in FIG. The page management method according to the present invention is executed by the integrated circuit 101 and the software 141 on the volatile memory 103.

  The integrated circuit 101 includes a CPU (Central Processing Unit) 111, a bus controller 112, a host I / F (interface) 113, a volatile memory I / F 114, and a nonvolatile memory I / F 115. / F 113, volatile memory I / F 114, and nonvolatile memory I / F 115 communicate via the address bus 121 and the data bus 122 via the bus controller 112. Further, the bus controller 112 is a chip for selecting a receiving side block of communication via the address bus 121 and the data bus 122 from the host I / F 113, the volatile memory I / F 114, and the nonvolatile memory I / F 115. A select signal 123 is used. Hereinafter, communication among the CPU 111, the bus controller 112, the host I / F 113, the volatile memory I / F 114, and the nonvolatile memory I / F 115 will be described as relaying the bus controller 112.

  The host I / F 113 is a block that transmits and receives data to and from the host device 102 via the bus 131, and writes data from the host device 102 to the temporary data storage area 142 in the volatile memory 103 under the control of the CPU 111. The read data on the data temporary storage area 142 is transferred to the host device 102. In order for the CPU 111 to start the control, it may be conditional on the host I / F 113 notifying the CPU 111 of an interrupt when a read or write request is received from the host device 102, or the CPU 111 may be a condition for the host I / F 113. It is also possible to make a condition that polling is performed to detect a read or write request. The mechanism of data transfer with the volatile memory 103 will be described later in the description of the volatile memory I / F 114.

  The volatile memory I / F 114 is a block that controls the reading / writing of the volatile memory 103 via the address bus 151 and the data bus 152 and the execution of the software 141 stored on the volatile memory 103. Is performed in response to a read / write request or software execution request from the CPU 111, the host I / F 113, and the nonvolatile memory I / F 115. Hereinafter, the CPU 111, the host I / F 113, and the nonvolatile memory I / F 115 will be described as being performed via the volatile memory I / F 114, and the CPU 141 executes the software 141 with respect to the volatile memory 103.

  The non-volatile memory I / F 115 is a block that performs reading / writing to one or more non-volatile memories 104 via the bus 161, and performs reading / writing under the control of the CPU 111. The content read from the nonvolatile memory 104 is transferred to any one of the data temporary storage area 142, the logical-physical page address conversion table 143, and the logical page address allocation history 144 on the volatile memory 103. The target of writing to the nonvolatile memory 104 is any of the data on the temporary data storage area 142, the logical-physical page address conversion table 143, and the logical page address allocation history 144. The nonvolatile memory I / F 115 uses the chip select signal 162 to select the nonvolatile memory 104 that can use the bus 161. Hereinafter, the reading and writing to the nonvolatile memory 104 by the CPU 111 will be described as being performed via the nonvolatile memory I / F 115.

  The CPU 111 executes the software 141 to perform control related to the above-described reading or writing, and updates and creates the logical-physical page address conversion table 143, the logical page address assignment history 144, and the pointer information 145.

  FIG. 2 is an example of the logical-physical page address conversion table 143. The logical page address is written in column 201, and the physical page address where the corresponding data is stored is written in column 202, respectively. The total number of rows in the logical-physical page address conversion table 143 is equal to a value obtained by multiplying the number of nonvolatile memories 104 connected to the nonvolatile memory I / F 115 by the number of pages per one nonvolatile memory 104. . In column 201, all possible logical page address values are written in ascending order. In column 202, the physical page address in which the data is stored is written only when data exists in the logical page address, and blank when there is no data.

  When reading data, the physical page address written in the column 202 in the row equal to the logical page address of the read destination counted from the top is regarded as the storage destination of the read data. For example, when the host device 102 requests reading of data from the logical page address 0x13CA, 0xD82 written in the 0x13CA line becomes a physical page address from which data is read. “0x” means that the subsequent numerical value is expressed in hexadecimal (the same applies hereinafter).

  When writing data, the physical page address that is the storage destination of new data is written in the column 202 in a row that is equal to the logical page address of the write destination counted from the top. For example, when the host device 102 requests to write data to the logical page address 0x13C8, 0xB087 written in the 0x13C8 line is overwritten with another physical page address. On the other hand, when data writing to the logical page address 0x13C9 is requested, the physical page address that is the data storage destination is written in the blank portion of the 0x13C9 line. Here, the physical page address to be written in the column 202 is selected from the range of the physical page address indicated in the pointer information 145.

  Since the logical-physical page address conversion table 143 can uniquely associate a logical page address with a row, the column 201 can be omitted to reduce the capacity of the volatile memory 103.

  FIG. 3 is an example of the logical page address assignment history 144. A physical page address in which data is written is written in a column 301, and a corresponding logical page address is written in a column 302. When writing data, in the top blank row 311, the physical page address that is the data storage destination is written in the column 301, and the logical page address is written in the column 302. Here, it is assumed that the physical page address written in the column 301 is selected from the range of the physical page address indicated in the pointer information 145 regardless of the search result.

  FIG. 4 is an example of the pointer information 145. As described above, when writing data, the write destination physical pages are selected in order from the top within the range of the physical page addresses 0x1024 to 0x2047 shown here.

  FIG. 5 shows a procedure for updating the logical-physical page address conversion table 143, the logical page address assignment history 144, and the pointer information 145 that the software 141 causes the CPU 111 to perform. This procedure starts when a data write request from the host device 102 is generated.

  First, the CPU 111 acquires the physical page address of the data write destination from the specific line of the pointer information 145 (step S501). Here, a variable x is defined as a line number for acquiring a physical page address from the pointer information 145.

  Next, the CPU 111 acquires the logical page address of the data writing destination from the host I / F 113 (step S502), and writes the data to the physical page indicated by the address acquired in step S501. Here, the logical page address acquired in step S502 is simultaneously written in the margin of the same physical page (step S503).

  After writing to the physical page, the CPU 111 updates the logical-physical page address conversion table 143. Specifically, the physical page address acquired in step S501 is written in the row corresponding to the logical page address acquired in step S502 counted from the top (step S504).

  After updating the logical-physical page address conversion table 143, the CPU 111 adds the physical page address acquired in step S501 and the logical page address acquired in step S502 to the x-th row of the logical page address assignment history 144 (step S502). S505). If the value of x is not (the total number of lines in the logical page address allocation history 144 −1) (branch to No in step S506), the CPU 111 adds 1 to the value of x (step S508), and from the host device 102 Wait for the next data write request. On the other hand, if the value of x is (the total number of rows in the logical page address allocation history 144 -1) (branch to Yes in step S506), the processing proceeds to the following.

  The CPU 111 saves all of the logical page address assignment history 144 in the nonvolatile memory 104 and erases it from the volatile memory 103 after the saving is completed (step S507). The method for specifying the area for storing the logical page address allocation history 144 on the nonvolatile memory 104 may be any method as long as the address range of the area and the order of storage can be uniquely specified at the time of initialization. For example, a specific one is selected from the non-volatile memory 104, the area designation information is written to the physical page of the fixed address in the non-volatile memory 104, and the first blank physical page in order from the area indicated by the area designation information. A method of writing the logical page address assignment history 144 to the storage area can be considered.

  Next, the CPU 111 stores one of the logical-physical page address conversion table 143 divided into equal sizes in the nonvolatile memory 104. Specifically, the y-th to (y + N−1) -th lines of the logical-physical page address conversion table 143 are saved (step S509). Here, N is a constant, and the total number of rows in the logical-physical page address conversion table 143 is divisible by N. On the other hand, y is a variable and can take a value obtained by subtracting 1 from any of N multiples. Note that the method for designating the area for storing the divided logical-physical page address conversion table 143 on the nonvolatile memory 104 can uniquely specify the address range of the same area and the order of storage at initialization, and the logical page address. Any method can be used as long as it can be distinguished from the storage area of the allocation history 144.

  Thereafter, the CPU 111 searches for a free physical page, that is, a physical page that is no longer used due to overwriting of a blank physical page or logical page, by using an arbitrary method, and erases non-blank pages (step S510). The pointer information 145 is updated with the address, and the updated pointer information 145 is stored in the nonvolatile memory 104 (step S511). The search continues until the same number of free physical pages as the total number of rows in the logical page address assignment history 144 are found. Note that the method for specifying the area for storing the pointer information 145 on the nonvolatile memory 104 can uniquely specify the address range and the storage order of the area at the time of initialization, and the storage area of the logical page address allocation history 144. Any method may be used as long as it can be distinguished from the storage area of the divided logical-physical page address conversion table 143.

  When the storage of the pointer information 145 is completed, the CPU 111 initializes the value of x with 0 (step S512). As a result, when next data write is requested from the host device 102, the physical page address acquisition source in step S501 returns to the first line of the pointer information 145, and the physical page address and logical page address in step S505. To the first line of the logical page address assignment history 144.

  Next, the CPU 111 determines whether the value of (y + N) has reached the maximum value (that is, whether storage in the nonvolatile memory 104 has been completed up to the last row of the logical-physical page address conversion table 143) (step S513). If reached (branch to Yes in step S513), the value of y is initialized to 0 (step S514). As a result, when next data write is requested from the host device 102, the storage target area of the logical-physical page address conversion table 143 is returned to the top in step S509. If the value of (y + N) has not reached the maximum value (branch to No in step S513), the CPU 111 adds N to the value of y (step S515). As a result, when the next data write is next requested from the host device 102, the storage target area of the logical-physical page address conversion table 143 is one backward from the area stored in the current data write in step S509. .

  After completing the above processing, the CPU 111 waits for the next data write request from the host device 102.

  The result of repeating the processing of FIG. 5 is shown in FIG. 6 in time series. In accordance with a request from the host device 102, data and a logical page address are written to the physical page pointed to by the pointer information 145. When the logical page address allocation history 144 becomes full, the logical page address allocation history 144 is divided into the logical-physical page address conversion table. 143, the cycle of saving the pointer information 145 in the nonvolatile memory 104 is repeated.

  In this way, the logical-physical page address conversion table 143 is divided into equal sizes, and each divided area is periodically cycled and stored in the nonvolatile memory 104. Therefore, information other than data is stored in each cycle. The processing load stored in the non-volatile memory 104 becomes constant, so that data can be written with stable performance. Further, the divided logical-physical page address conversion table 143 saved in the nonvolatile memory 104 in a certain cycle causes a difference from the latest contents on the volatile memory 103 by subsequent data writing. By storing the page address allocation history 144 and the pointer information 145 together, the logical-physical page address conversion table 143 on the volatile memory 103 is converted into the logical page address allocation history 144 and the pointer information 145 at the time of initialization. Using the logical page address written in the physical page pointed to by the pointer information 145, it is possible to correct the state just before the previous power-off.

  FIG. 6 shows an example in which the logical-physical page address conversion table 143 is divided into four. When the divided head area is stored and the logical page address allocation history 144 is full, the power is cut off. Represents. Here, each symbol from T601 to T604 is time, and is referred to in the second embodiment.

<< Second Embodiment >>
The configuration of the second embodiment of the present invention is based on the configuration of FIG. 1 shown in the first embodiment, and the software 141 on the volatile memory 103 adds the functions shown in FIGS. I have.

  FIGS. 7 and 8 are diagrams showing a procedure for restoring the logical-physical page address conversion table 143 to the state just before the previous power-off, which the software 141 causes the CPU 111 to perform. This procedure is performed during the initialization process after the power is turned on.

  As shown in FIG. 7, the CPU 111 first substitutes the variable z for the number divided when the logical-physical page address conversion table 143 is stored in the nonvolatile memory 104 (step S701). As will be described later, the variable z is a variable for managing the order in which the divided logical-physical page address conversion table 143 and the logical page address assignment history 144 are read from the nonvolatile memory 104.

  The following steps from S702 to S714 are repeated until the value of the variable z becomes 1 (branch to Yes in step S705).

  In the repetition, the CPU 111 first specifies the storage location of the divided logical-physical page address conversion table 143 stored in the nonvolatile memory 104 for the zth time retroactively from the previous power-off (step S702). ). The specific method may be any method. For example, a specific one is selected from the non-volatile memory 104 at the time of saving, and the area designation information is written in the physical page of the fixed address in the nonvolatile memory 104, and the first blank physical page within the area indicated by the area designation information If the method of writing the logical-physical page address conversion table 143 divided in order from is used and the division size is equal to or smaller than the physical page size, in step S702, area designation information is first read from the physical page of the fixed address, and the area A physical page address that is searched for the first blank page in the area indicated by the designation information and goes back by z pages can be specified as a storage location of the desired divided logical-physical page address conversion table 143.

  Next, the CPU 111 specifies a reading destination when the divided logical-physical page address conversion table 143 whose storage location has been specified in step S702 is read out to the volatile memory 103 (step S703). The specific method may be any method. For example, when the above method is used for specifying the storage location in step S702, the logical-physical page address conversion table 143 indicates the number of pages from the first physical page of the region pointed to by the region designation information to the storage location specified in step S702. What is necessary is just to obtain | require a reading destination from the remainder divided by the division | segmentation number. If the total number of rows in the logical-physical page address conversion table 143 is L, the number of divisions is M, and the remainder is N, the read destination is for the logical-physical page address conversion table 143 on the volatile memory 103. In this area, the range is from the (N × (L / M)) line to the ((N + 1) × (L / M) −1) line.

  Further, the CPU 111 reads the divided logical-physical page address conversion table 143 from the storage location on the non-volatile memory 104 specified at step S702 to the read destination on the volatile memory 103 specified at step S703 (step S703). S704).

  When the reading of the divided logical-physical page address conversion table 143 is completed, the CPU 111 determines that the value of the variable z is 1, that is, the divided logical-physical page address conversion table 143 read in step S704 is the previous power-off. It is determined whether it was saved at the previous last timing. If not (if branched to No in step S705, and later branched to Yes), the process proceeds to the following.

  When the value of the variable z is not 1, the CPU 111 first specifies the storage location of the logical page address assignment history 144 stored in the nonvolatile memory 104 for the (z−1) th time after the previous power-off (step S706). The logical page address assignment history 144 is read from the specified storage location to the volatile memory 103 (step S707). The storage location specifying method in step S706 may be any method as in the case of the divided logical-physical page address conversion table 143.

  When the reading of the logical page address assignment history 144 is completed, the CPU 111 repeats the following steps S709 to S714 to restore the read logical-physical page address conversion table 143. First, the CPU 111 assigns the logical page address written in the i-th line of the read logical page address assignment history 144 to the variable l (step S709). Here, i is a variable and is initialized to 0 in step S708. That is, when the logical page address allocation history 144 is read, the 0th line is first referred to.

  Next, the CPU 111 substitutes the physical page address written in the i-th line of the read logical page address assignment history 144 for the variable p (step S710).

  After the assignment to the variables l and p, the CPU 111 writes the value of the variable p in the l-th line of the area for the logical-physical page address conversion table 143 on the volatile memory 103 (step S711). By this step, the contents of the divided logical-physical page address conversion table 143 that has been read on the volatile memory 103 can be returned to a new state only once for writing.

  Thereafter, the CPU 111 determines whether the variable i has reached the maximum value, that is, (the total number of lines in the logical page address allocation history 144 −1). If not, the CPU 111 sets the value of the variable i to the value of the variable i. 1 is added (step S714), and the process returns to step S709. If it has been reached (branch to Yes in step S712), the variable z is decremented by 1 (step S713), and the process returns to step S702. In these processes, the values of the physical page addresses written from the 0th line to the last line of the logical page address assignment history 144 read in step S707 are converted into the logical-physical page address conversion table on the volatile memory 103. By sequentially writing to the area for 143, the contents of the divided logical-physical page address conversion table 143 that has been read on the volatile memory 103 are updated to a new state for one period of the storage period in the nonvolatile memory 104. The divided logical-physical page address conversion table stored in the non-volatile memory 104 at a timing closer to the previous power-off for one cycle than the previously read divided logical-physical page address conversion table 143 This means that the process proceeds to the reading process 143.

  When the reading of the divided logical-physical page address conversion table 143 stored in the nonvolatile memory 104 immediately before the previous power-off, that is, the reading when the value of the variable z is 1, the logical page address allocation that can be read is completed. Since there is no more history 144, the process proceeds from S715 to S726 described below, and logical-physical page address conversion is performed based on the logical page address written together with the data at the physical page address of the data storage destination. The table 143 is restored to the latest state immediately before the previous power shutdown, and the logical page address allocation history 144 is restored to the latest status just before the previous power shutdown (branch to Yes in step S705: FIGS. 7 to 8). Go to).

  Therefore, as shown in FIG. 8, the CPU 111 first erases the logical page address assignment history 144 read to the volatile memory 103 (step S715).

  In addition, the CPU 111 adds 1 to the final row number of the read destination when the divided logical-physical page address conversion table 143 is last read on the volatile memory 103 in step S704, and further, the logical-physical page address. The remainder obtained by dividing the total number of rows in the conversion table 143 is substituted into the variable y (step S716). Here, the variable y is the same as that used in the procedure of FIG. 5, so that when the step S 509 of FIG. 5 is executed next, the power-off in the divided logical-physical page address conversion table 143. It becomes possible to save one area after the last area previously stored in the non-volatile memory 104, so that the cyclicity of the order in which the logical-physical page address conversion table 143 is stored is maintained even when the power is cut off. Be drunk.

  Next, the CPU 111 specifies the storage location of the pointer information 145 stored in the nonvolatile memory 104 immediately before the previous power interruption (step S717), and reads the pointer information 145 from the specified storage location to the volatile memory 103 ( Step S718). The storage location specifying method in step S717 may be any method as in the case of the divided logical-physical page address conversion table 143 and logical page address assignment history 144.

  When the reading of the pointer information 145 is completed, the CPU 111 repeats the following steps S720 to S726. First, the CPU 111 assigns the physical page address written in the j-th line of the read pointer information 145 to the variable p (step S720). Here, j is a variable and is initialized to 0 in step S719. That is, when the pointer information 145 is read, the 0th row is first referred to.

  Next, the CPU 111 reads the physical page pointed to by the variable p (step S721), and if the content is not blank (branch to No in step S722; if branched to Yes, will be described later), the logical page address written there Is substituted for variable l (step S723).

  After the assignment to the variables p and l, the CPU 111 overwrites the value of the variable p on the l line for the logical-physical page address conversion table 143 read to the volatile memory 103 (step S724), The values of the variable p and the variable l are added to the j-th line of the logical page address assignment history 144 on the memory 103 (step S725). By these steps, the contents of the logical-physical page address conversion table 143 read onto the volatile memory 103 and the contents of the logical page address allocation history 144 on the volatile memory 103 are updated to a new state only once. Can be returned.

  Thereafter, the CPU 111 determines whether or not the variable j has reached the maximum value, that is, (the total number of lines of the pointer information 145 −1). If not, the CPU 111 adds 1 to the value of the variable j (branch to No in step S726). (Step S729) Return to Step S720, and if it has been reached (branch to Yes in Step S726), the logical page address allocation history 144 is full, the logical-physical page address conversion table 143, the logical page address allocation history 144 and the pointer information 145 are considered to have been interrupted before the storage is completed, and the storage is started or restarted in the same procedure as S507 to S515 in FIG. 5 (step S727). ) 0 is substituted into the variable x (step S728). Here, the variable x is the same as that used in the procedure of FIG. When completed, the CPU 111 ends the process and is ready to accept data writing and reading.

  If the branch is Yes in step S722 described above, that is, if the physical page read in step S721 is blank, the CPU 111 stores the logical-physical page address conversion table 143 and the logical page address allocation history 144 in the previous time. It is assumed that the state has been restored to the state immediately before the power is turned off, the value of the variable j is substituted for the variable x (step S730), the process is terminated, and the state where the writing and reading of data can be accepted.

  An example of the progress and results of the processing in FIGS. 7 and 8 in time series are as shown in FIGS. 9A to 9I. FIG. 9A to FIG. 9I show the flow of power-on / initialization from the power-off state shown in FIG.

  The content shown in FIG. 6 represents a situation in which a power failure occurs after the top area of the logical-physical page address conversion table 143 divided into four is stored in the nonvolatile memory 104. FIG. As a result of the steps S702 and S703, the second area of the four divisions is first read to the volatile memory 103. Including this, through the following steps (a) to (i), the logical-physical page address conversion table 143 is restored to the state immediately before the previous power-off.

  (A) The logical-physical page address conversion table 143 is read out to the volatile memory 103 (second among the four divisions; steps S702 to S704 in FIG. 7).

  (B) Overwrite the logical-physical page address conversion table 143 with the physical page address written in the logical page address assignment history 144 stored in the nonvolatile memory 104 between times T601 and T602 in FIG. The area read in (a) is returned to the state at time T602 in FIG. 6 (steps S706 to S714 in FIG. 7).

  (C) The logical-physical page address conversion table 143 is read out to the volatile memory 103 (the third of the four divisions; steps S702 to S704 in FIG. 7).

  (D) Overwrite the logical-physical page address conversion table 143 with the physical page address written in the logical page address assignment history 144 stored in the nonvolatile memory 104 between times T602 and T603 in FIG. The area read in (a) and (c) is returned to the state at time T603 in FIG. 6 (steps S706 to S714 in FIG. 7).

  (E) The logical-physical page address conversion table 143 is read out to the volatile memory 103 (fourth of four divisions; steps S702 to S704 in FIG. 7).

  (F) Overwriting the logical-physical page address conversion table 143 with the physical page address written in the logical page address assignment history 144 stored in the nonvolatile memory 104 between times T603 and T604 in FIG. The area read in (a), (c) and (e) is returned to the state at time T604 in FIG. 6 (steps S706 to S714 in FIG. 7).

  (G) The logical-physical page address conversion table 143 is read out to the volatile memory 103 (the first of four divisions; steps S702 to S704 in FIG. 7).

  (H) The logical-physical page address conversion table 143 is overwritten on the basis of all physical page addresses to which data has been written after time T604 in FIG. 6 and logical page addresses written to these physical pages ( Steps S717 to S729 in FIG.

  (I) Restoration is completed (step S730 in FIG. 8).

  The present invention can be applied to various types of storage devices including a non-volatile memory such as an SSD and an SD memory card, and can perform data with stable performance without being affected by an increase in the size of a logical-physical page address conversion table due to an increase in capacity. Therefore, it is easy to achieve both large capacity and high speed.

DESCRIPTION OF SYMBOLS 101 Integrated circuit 102 Host apparatus 103 Volatile memory 104 Non-volatile memory 111 CPU
112 Bus controller 113 Host I / F
114 Volatile memory I / F
115 Nonvolatile memory I / F
121 Address bus 122 Data bus 123 Chip select signal 131 Bus 141 Software 142 Data temporary storage area 143 Logical-physical page address conversion table 144 Logical page address assignment history 145 Pointer information 151 Address bus 152 Data bus 161 Bus 162 Chip select signal

Claims (4)

A page management method for controlling access to one or more pages of a non-volatile memory that reads and writes in units of pages,
Based on the logical page address specified by the access source, the data corresponding to the logical page address is arranged in the order of logical page addresses used to obtain the physical page address where the data is physically arranged on the nonvolatile memory. Place the logical-physical page address conversion table on volatile memory,
A step of identifying a physical page address to which the data is written each time an access source requests data writing; Specifying a recording position of the address, and converting the logical-physical page address by recording the write destination physical page address at the recording position of the specified physical page address in the logical-physical page address conversion table. Updating the table; adding the write destination logical page address and the write destination physical page address to the volatile memory; adding the data and the write destination logical page address to the write destination physical page; Step to write and Run,
Storing a logical page address allocation history composed of all the combinations of the write destination logical page address and the write destination physical page address on the volatile memory in the nonvolatile memory at regular intervals; and Erasing the logical page address allocation history on the volatile memory, storing one area in the logical-physical page address conversion table in the non-volatile memory, and writing data within the next cycle Repeating the steps of securing an area in the nonvolatile memory and storing pointer information to the secured nonvolatile memory area in the nonvolatile memory;
The period is one period from when the logical page address allocation history is erased until it is filled with a combination of the write destination logical page address and the write destination physical page address,
The page management method, wherein the write destination physical page address is specified from within a range indicated by pointer information stored in the non-volatile memory in a previous cycle. The page management method according to claim 1,
A step of reading the latest version of each area in the logical-physical page address conversion table stored in the nonvolatile memory to the storage source area on the volatile memory at the time of initialization; The order of reading each area in the physical page address conversion table is earlier as the timing of storage on the nonvolatile memory is older,
Each time one area in the logical-physical page address conversion table is read, the logical page stored in the nonvolatile memory after one period from the one area in the logical-physical page address conversion table that has been read. A step of reading an address assignment history, and a physical corresponding to the write destination logical page address included in the read logical page address assignment history from the logical-physical page address conversion table area on the volatile memory Executing the step of overwriting all the recording positions of page addresses with the write destination physical page address included in the read logical page address allocation history, thereby reading the logical-physical data already read on the volatile memory. Each area in the page address conversion table Back to one period of the new state of the serial cycle,
When reading of all areas in the logical-physical page address conversion table to be read is completed, pointer information to the nonvolatile memory area stored in the nonvolatile memory at the last timing before the previous power-off is obtained. A step of reading the write destination logical page address from one or more physical pages that point to, and the write destination logical page read from the physical page from the logical-physical page address conversion table area on the volatile memory The restoration of the logical-physical page address conversion table immediately before the previous power-off is completed by executing the step of overwriting all the recording positions of the physical page address corresponding to the address with the physical page address indicated by the pointer information. A page management method characterized by:   An integrated circuit in which the page management method according to claim 1 or 2 is implemented in a form controlled by software.   Software for controlling the integrated circuit according to claim 3.

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