JP5644432B2 - Behavioral synthesis system, behavioral synthesis method, behavioral synthesis program, and semiconductor device - Google Patents

Description

  The present invention relates to a behavioral synthesis system, a behavioral synthesis method, a behavioral synthesis program, and a semiconductor device, and in particular, a behavioral synthesis system that generates an RTL description for executing the operations in parallel based on the behavioral descriptions in which the behaviors are described in series. The present invention relates to a behavioral synthesis method, a behavioral synthesis program, and a semiconductor device designed using the behavioral synthesis program.

  In recent years, in a semiconductor device including a logic circuit, the circuit scale has been increased, and a prolonged design period has become a problem. Therefore, a behavioral synthesis system that synthesizes an RTL (Register Transfer Level) description from a behavioral description that describes the operational procedure of a logic circuit is used. Design efficiency can be increased by using this behavioral synthesis system.

  The behavioral description is described in, for example, a software programming language such as C language, C ++ language, Java (registered trademark) language, or a software programming language such as SystemC or SpecC, which has been extended for semiconductor circuit design.

  In order to synthesize a high-performance semiconductor circuit from such a behavioral description written in a software program language, it is desirable to synthesize a semiconductor circuit that can execute loop processing in the behavioral description at high speed. . This is because the processing speed of the loop processing in the behavioral description greatly affects the overall processing performance.

  As an example of a behavioral synthesis technique for a circuit that can execute a single loop at high speed, there is a loop pipeline technique (also called a loop folding technique or a pipeline technique). The loop pipeline technique performs a “pipeline operation” in which the execution of the next process (iteration) is started before the process of the loop (hereinafter referred to as iteration) is completed. This is a technique for synthesizing a circuit that executes a single loop at high speed. A number of methods for realizing the loop pipeline technique such as Patent Documents 1 to 8 and Non-Patent Documents 1 and 2 have been proposed.

  As a method for realizing the loop pipeline technique, it is desirable to be able to deal with various loop structures, and in particular, it is desirable to be applicable to multiple nested loops. Reference 9 discloses a method for realizing a loop pipeline technique for multiple nested loops.

  However, the current behavioral synthesis technology focuses on the synthesis of a circuit that can execute a single loop at a high speed, such as the loop pipeline technique, and executes a plurality of loops described sequentially in parallel. It is not possible to automatically synthesize a circuit that executes processing at high speed.

  If multiple sequential loop processes cannot be executed in parallel, the subsequent loop processes can only be started after waiting for the completion of the preceding loop. The entire described circuit cannot be processed at high speed.

  For example, the behavioral description is described along the description of the programming language. The description of the programming language generally takes the form of describing the operation from the top to the bottom even if the operation can be performed in parallel. Therefore, when the behavioral description includes the loop processes L1 to L4, the circuit generated by the behavioral synthesis is configured to sequentially process the loop processes L1 to L4. In such a circuit, the processing time is the sum of the processing times of the loop processing L1 to L4. On the other hand, when the loop processing L1 to L4 is processed in parallel, the processing time of the circuit becomes a longer processing time among the processing times of the loop processing L1 to L4.

  Therefore, Non-Patent Document 3 discloses a behavioral synthesis technique capable of synthesizing a circuit that executes a plurality of loops described in series in parallel. Referring to FIG. 4.6 of Non-Patent Document 3, a state in which a plurality of loops described in series are executed in parallel is illustrated (see FIG. Loop-level parallelism).

  Further, referring to section 4.3.2 of Non-Patent Document 3 and FIGS. 4.7 and 4.8, an outline of a logic circuit synthesized by the behavioral synthesis technique is illustrated. In the behavioral synthesis technique, execution of one loop is realized by one processing element (processing array; PA). This PA is realized by a fixed architecture called a Very Long Instruction Word (VLIW) processor type. The PA has a control circuit realized by a finite state machine, and execution of processing in the loop is controlled by the control circuit. Execution of a plurality of PAs is controlled by a timing controller.

  Patent Document 10 discloses a behavioral synthesis technique for synthesizing a circuit that can execute a plurality of loops in parallel by dividing the loop. In the technique of Patent Document 10, a loop statement having a description related to an array is automatically detected from a source written in a description that allows behavioral synthesis, and the number of loops having a description related to substitution and the number of loops having a description related to reference are detected. To divide the circuit structure into groups.

  Patent Documents 11 and 12 describe a behavioral synthesis technique for synthesizing a circuit in which threads are executed in parallel from a behavioral description in which thread-to-thread synchronous communication is described in advance.

  Patent Document 13 discloses a behavioral synthesis technique for synthesizing a circuit that can execute a plurality of loops in parallel by merging the loops. In the technique of Patent Document 13, when there is a dependency between the first loop and the second loop, the two loops are partially or completely merged with each other and merged as one loop. .

Japanese Patent Laid-Open No. 08-44773 JP 2003-30261 A JP 2007-272797 A JP 2007-287044 A JP 2004-326463 A Japanese Patent Laid-Open No. 06-60147 JP 2009-25973 A JP 2006-350849 A JP 2009-238085 A JP 2002-269162 A JP 2000-57180 A JP 2001-43251 A Special table 2008-501185

John P. Elliott, "Understanding Behavioral Synthesis", Kluwer Academic Publishers, pp. 26-40 Cheng-Tsung Hwang et al., `` Scheduling for Functional Pipelining and Loop Winding '', 28th, ACM / IEEE Design Automation Conference, p764-769. Philippe Coussy and Adam Morawiec, “High-Level Synthesis, From Algorithm to Digital Circuit”, Springer, pp. 53-74

  However, in the techniques described in Non-Patent Document 3 and Patent Documents 10 to 13, there is a problem that a certain restriction is imposed on a circuit that can be synthesized when there is a loop process having a dependency relationship, and design efficiency is lowered. The specific contents of the problems with each technology are shown below.

  In Non-Patent Document 3, the synthesized circuit is fixed to an architecture called a VLIW processor type, and the degree of freedom is low. Further, Non-Patent Document 3 is because a special control circuit called a timing controller is required for controlling execution of a plurality of PAs, that is, controlling execution of a plurality of loops. That is, in the technique described in Non-Patent Document 3, there are limitations on the types of loop processing that can be handled, and there is a problem of complicated control (and an increase in circuit area).

  Patent Document 10 is applicable only when a special relationship is established between the number of executions of two loops. For example, it cannot be applied to a description in which the number of loop executions is not known in advance. In other words, the technique described in Patent Document 10 has a problem that the number of circuits that can be synthesized is limited.

  In Patent Documents 11 and 12, the operation description must be described in advance regarding synchronous communication between threads. That is, in Patent Documents 11 and 12, a circuit in which loops operate in parallel cannot be synthesized from an operation description in which inter-thread synchronous communication is not described. That is, the problem with the techniques of Patent Documents 11 and 12 is that the circuits that can be synthesized are limited.

  In Patent Document 13, the structure of the loop is complicated, and it cannot be applied when the loops cannot be merged. That is, the problem of the technique of Patent Document 13 is that the circuits that can be synthesized are limited.

  One aspect of the behavioral synthesis system according to the present invention is a behavioral synthesis system that synthesizes an RTL (Register Transfer Level) description from a behavioral description, and analyzes the dependency between loop processes included in the behavioral description. An inter-loop dependency analysis processing unit that extracts dependency loop processing execution conditions having dependency relationships with other loop processing and generates inter-loop dependency relationship information, and scheduling that determines a control step for executing an operation during the loop processing A scheduling and binding processing unit that performs processing, a calculation unit that performs a calculation in the loop process, and a binding process that determines a register that stores data; and controls an execution state of the control step in the loop process Execution of the loop process based on the first control logic and the execution condition of the loop process A control circuit including a second control logic that controls a state, a control circuit creation processing unit that generates a control circuit according to a processing result of the scheduling and binding processing unit and the inter-loop dependency relationship information, the arithmetic unit, An RTL description generation processing unit that generates a data path using a register and generates an RTL description including the data path and the control circuit;

  One aspect of the behavioral synthesis method according to the present invention is a behavioral synthesis method for synthesizing an RTL (Register Transfer Level) description from a behavioral description. A computing unit that extracts the execution condition of the dependency loop process having a dependency relationship with the loop process of the loop, generates inter-loop dependency relationship information, determines a control step for executing the operation of the loop process, and performs the operation of the loop process And a register for storing data, and control the execution state of the loop process based on the first control logic for controlling the execution state of the control step in the loop process and the execution condition of the loop process A control circuit including a second control logic according to the processing result of the scheduling and binding processing unit and the inter-loop dependency relationship information. Form, to create a data path with said and said arithmetic unit register, generates a RTL description including said data path and the control circuit.

  One aspect of the behavioral synthesis program according to the present invention is a behavioral synthesis in which an RTL (Register Transfer Level) description is synthesized from a behavioral description executed in an arithmetic circuit and stored in a storage device, and the RTL description is stored in the storage device. A loop for analyzing dependency relations between loop processes included in the behavior description and extracting execution conditions of dependent loop processes having dependency relations with other loop processes to generate inter-loop dependency relation information An inter-dependency analysis process, a control step for executing the operation of the loop process, a scheduling binding process for determining an arithmetic unit for the operation of the loop process and a register for storing data, First control logic for controlling the execution state of the control step, and the execution condition of the loop processing A control circuit creating process for generating a control circuit including a second control logic that controls an execution state of the loop process based on a processing result of the scheduling and binding processing unit and the inter-loop dependency relationship information; A data path is created using the arithmetic unit and the register, and an RTL description generation process for generating an RTL description including the data path and the control circuit is performed.

  According to one aspect of the semiconductor device of the present invention, a first loop processing circuit that executes a first loop process that does not have a dependency relationship with another loop process and a dependency relationship between the other loop process. A second loop processing circuit that executes the second loop processing, a first control logic that controls an execution state of the control step of the first and second loop processing circuits, and a processing result of another loop processing. And a control circuit including a second control logic for controlling the execution state of the second loop process.

  According to the behavioral synthesis system, behavioral synthesis method, behavioral synthesis program, and semiconductor device according to the present invention, parallelization is performed even when there is a data dependency between a plurality of loops described sequentially, and the loops are simultaneously processed. A circuit that can be executed can be synthesized.

1 is a block diagram of a behavioral synthesis system according to a first exemplary embodiment. 3 is a flowchart showing a procedure of a logic synthesis method in the behavioral synthesis system according to the first exemplary embodiment; FIG. 3 is a diagram illustrating an example of behavioral descriptions handled by the behavioral synthesis system according to the first exemplary embodiment. FIG. 4 is a diagram illustrating a dependency relationship between loop processes in the behavioral description illustrated in FIG. 3. It is a figure which shows an example of the result as which the scheduling and binding process part of the behavioral synthesis system concerning Embodiment 1 processed the loop L1. It is a figure which shows an example of the result as which the scheduling and binding process part of the behavioral synthesis system concerning Embodiment 1 processed the loop L2. It is a figure which shows an example of the result as which the scheduling and binding process part of the behavioral synthesis system concerning Embodiment 1 processed the loop L3. It is a figure which shows an example of the result as which the scheduling and binding process part of the behavioral synthesis system concerning Embodiment 1 processed the loop L4. FIG. 3 is a state transition diagram of a first control logic that controls execution of steps in a loop generated by a control circuit creation processing unit of the behavioral synthesis system according to the first exemplary embodiment; FIG. 3 is a state transition diagram of a first control logic that controls execution of steps in a loop generated by a control circuit creation processing unit of the behavioral synthesis system according to the first exemplary embodiment; FIG. 3 is a state transition diagram of a first control logic that controls execution of steps in a loop generated by a control circuit creation processing unit of the behavioral synthesis system according to the first exemplary embodiment; FIG. 3 is a state transition diagram of a first control logic that controls execution of steps in a loop generated by a control circuit creation processing unit of the behavioral synthesis system according to the first exemplary embodiment; FIG. 13 is a state transition diagram of a control logic including a second control logic that controls execution of a loop generated by the control circuit creation processing unit of the behavioral synthesis system according to the first exemplary embodiment and the first control logic of FIG. 12. 4 is an example of a circuit diagram of a semiconductor device generated based on an RTL description synthesized from the behavioral description shown in FIG. 3 by the logic synthesis system according to the first embodiment; FIG. FIG. 3 is a block diagram of a logic synthesis system according to a second exemplary embodiment. 10 is a flowchart showing a procedure of a logic synthesis method in the logic synthesis system according to the second exemplary embodiment; It is a figure which shows an example of the result as which the scheduling and binding process part of the behavioral synthesis system concerning Embodiment 2 processed the loop L4. FIG. 10 is a state transition diagram of first control logic that controls execution of steps in a stage generated by a control circuit creation processing unit of the behavioral synthesis system according to the second exemplary embodiment; FIG. 10 is a state transition diagram of first control logic that controls execution of steps in a stage generated by a control circuit creation processing unit of the behavioral synthesis system according to the second exemplary embodiment; FIG. 10 is a state transition diagram of first control logic that controls execution of steps in a stage generated by a control circuit creation processing unit of the behavioral synthesis system according to the second exemplary embodiment; FIG. 10 is a state transition diagram of first control logic that controls execution of steps in a stage generated by a control circuit creation processing unit of the behavioral synthesis system according to the second exemplary embodiment; FIG. 10 is a state transition diagram of first control logic that controls execution of steps in a stage generated by a control circuit creation processing unit of the behavioral synthesis system according to the second exemplary embodiment; FIG. 10 is a state transition diagram of a third control logic that controls execution of a stage generated by a control circuit creation processing unit of the behavioral synthesis system according to the second exemplary embodiment; FIG. 10 is a state transition diagram of a third control logic including a second control logic that controls execution of a loop generated by the control circuit creation processing unit of the behavioral synthesis system according to the second exemplary embodiment;

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. In the following, in the behavioral synthesis system according to the present invention, a storage device that stores information used in processing is used. However, these are not essential components, and are appropriately provided in the configuration of the system. FIG. 1 shows a block diagram of a behavioral synthesis system 1 according to the first exemplary embodiment. As illustrated in FIG. 1, the behavioral synthesis system 1 includes a storage device 10 and a processing device 20.

  The storage device 10 stores data and programs. Here, examples of the storage device 10 include a semiconductor storage device such as a random access memory (RAM), a read only memory (ROM), or a flash memory. The storage device 10 may be an external storage device (storage) such as an HDD (Hard Disk Drive) or an SSD (Solid State Drive). Alternatively, the storage device 10 may be a storage medium (media) such as a DVD (Digital Versatile Disk) or a memory card. The storage device 10 is not limited to a storage device built in the computer main body, but is a storage device installed in a peripheral device (such as an external HDD) or an external server (such as a storage server), or a NAS (Network Attached Storage). ) However, actually, it is not limited to these examples.

  In the behavioral synthesis system 1, the storage device 10 includes the behavior description storage unit 11, the inter-loop dependency relationship information storage unit 12, and the RTL description storage unit 13. The behavioral description storage unit 11 stores in advance a behavioral description that is input to the behavioral synthesis system. The inter-loop dependency relationship information storage unit 12 stores inter-loop dependency relationship information indicating a dependency relationship between loops described in the behavior description. The RTL description storage unit 13 stores an RTL (Register Transfer Level) description that is finally output by the behavioral synthesis system.

  The processing device 20 operates under program control. Here, as an example of the processing apparatus 20, a processing apparatus such as a CPU (Central Processing Unit) or a microprocessor, or a semiconductor integrated circuit (IC) having a similar function is assumed. The processing device 20 may be a computer such as a PC (personal computer), a thin client terminal / server, a workstation, a mainframe, or a supercomputer. However, actually, it is not limited to these examples. The processing device 20 includes an inter-loop dependency relationship analysis processing unit 21, a scheduling / binding processing unit 22, a control circuit creation processing unit 23, and an RTL description generation processing unit 24.

  The inter-loop dependency relationship analysis processing unit 21 reads out the behavior description from the behavior description storage unit 11 of the storage device 10, analyzes the dependency relationship between the loop processes included in the behavior description, and determines the dependency relationship with other loop processes. The execution condition of the dependency loop processing that has is extracted. Then, the inter-loop dependency relationship analysis processing unit 21 generates inter-loop dependency relationship information indicating the extracted dependency relationship. The inter-loop dependency relationship information is stored as inter-loop dependency relationship information in the inter-loop dependency relationship information storage unit 12 of the storage device 10.

  The scheduling and binding processing unit 22 performs a scheduling process for determining a control step for executing an operation in the loop process. Further, the scheduling and binding processing unit 22 performs a binding process for determining an arithmetic unit that performs an operation during the loop process and a register that stores data.

  The control circuit creation processing unit 23 generates a control circuit including the first control logic and the second control logic in accordance with the processing result of the scheduling / binding processing unit 22 and the inter-loop dependency relationship information. The first control logic controls the execution state of the control step in the loop process. The second control logic controls the execution state of the loop process based on the execution condition of the loop process.

  The RTL description generation processing unit 24 creates a data path from the arithmetic unit and the register determined by the scheduling and binding processing unit 22, and includes the data path and a control circuit created by the control circuit creation processing unit 23. The RTL description is created and stored in the RTL description storage unit 13 of the storage device.

  Subsequently, an operation of the behavioral synthesis system 1 according to the first exemplary embodiment will be described. FIG. 2 is a flowchart showing the processing procedure of the behavioral synthesis system 1. As shown in FIG. 2, in the behavioral synthesis system 1, first, inter-loop dependency relationship analysis processing (step S <b> 1) is performed by the inter-loop dependency relationship analysis processing unit 21. In the inter-loop dependency analysis process, first, the behavior description is read from the behavior description storage unit 11. Then, the dependency relation between the loop processes included in the behavior description is analyzed, the execution condition of the dependency loop process having the dependency relation with the other loop processes is extracted, and the inter-loop dependency relation information is generated.

  The execution condition included in the inter-loop dependency relationship information includes a condition that enables the control step included in the dependency loop process to be executed. For example, information indicating “no dependency” is recorded in the inter-loop dependency relationship information when there is no dependency relationship between the loops. In addition, if there is a dependency relationship between the loops and the execution of the subsequent loop can be started before the execution of the preceding loop is completed, the information of “when the subsequent loop can be executed” is recorded. The The timing at which the subsequent loop can be executed is expressed by the magnitude relationship of variables read and written in the loop. Also, for example, it is expressed with a magnitude relationship between loop control variables (loop variables). In addition, it is expressed with the magnitude relation of the variables used for the subscript of the array variable accessed in the loop. The inter-loop dependency relationship information is stored in the inter-loop dependency relationship information storage unit 12. That is, in the inter-loop dependency relationship analysis processing, which loop processing can be executed at which timing is analyzed.

  The inter-loop dependency analysis processing unit 21 performs, for example, Dr E. Maydan et al., “Efficient and exact data dependence analysis”, Proceedings of conference on Programming language design and implementation, pp. 1- 14, the existing technology described in 1991 may be used.

  Next, scheduling and binding processing (step S2) by the scheduling and binding processing unit 22 is performed. In the scheduling and binding process, the behavioral description is read from the behavioral description storage unit 11 of the storage device 10. In the scheduling and binding process, a control step for executing an operation for each loop process included in the behavioral description is determined (this process is referred to as a scheduling process), and an arithmetic unit for performing the operation of each loop process and data are stored. A register is determined (this process is called a binding process). More specifically, in the scheduling process of the scheduling and binding process, a CDFG (Control Data Flow Graph) is created from the operation description. This CDFG describes a loop processing control step.

  For example, John P. Elliott, “Understanding Behavioral Synthesis”, Kluwer Academic Publishers, pp. 25-40. The existing technology described in (1) may be used.

  Next, a control circuit creation process (step S3) is performed by the control circuit creation processing unit 23. In the control circuit creation process, a control circuit is generated based on the processing result of the scheduling / binding process and the inter-loop dependency information. The control circuit generated in the control circuit creation process includes a first control circuit and a second control circuit. The control circuit creation process includes step S31 for generating the first control circuit and step S32 for generating the second control circuit. First, in step S31, a first control logic for controlling the execution state of the control step in the loop process is created. Here, the first control logic is created according to the result of the scheduling and binding process. This first control logic is implemented as a first control circuit. The first control circuit includes, for example, a finite state machine (FSM) that transitions a plurality of predetermined states in a predetermined order according to a predetermined condition. The first control circuit controls whether or not to execute each control step of the loop process.

  Next, in step S32, a second control logic for controlling the execution state of the loop process is created based on the execution condition of the loop process. Here, the execution condition of the loop processing is included in the inter-loop dependency relationship information. This second control logic is implemented as a second control circuit. The second control circuit is implemented as a control circuit that controls whether or not to give processing start conditions to the first control circuit. The second control circuit may be configured, for example, by changing the execution condition of the first control circuit created in step S31 according to the execution condition of the loop process. In this case, the second control circuit is configured to be incorporated in the first control circuit as a wiring and a circuit constituting the finite state machine. The second control logic is configured to control whether to start executing the loop process or wait without starting regardless of the implementation.

  The second control logic that controls the execution of the loop process is configured to check the start condition of the loop in the head state of the loop process, for example. Further, the start condition of the loop may be inspected in all states of the loop processing. Further, the loop start condition may be inspected only in a specific state where the loop processing is performed. It should be noted that when there is no preceding loop having a dependency relationship with respect to the loop processing, execution of the loop is unconditionally started.

  Next, RTL description generation processing (step S4) is performed by the RTL description generation processing unit 24. In the RTL description generation process, a data path is created using an arithmetic unit and a register determined by the binding process, and an RTL description including the data path and the control circuit generated by the control circuit creation process is generated. This RTL description is stored in the RTL description storage unit 13.

  Next, the processing procedure of the behavioral synthesis system 1 described above will be described more specifically. First, an example of the behavioral description handled by the behavioral synthesis system 1 is shown in FIG. The behavioral description shown in FIG. 3 is expressed using “System C language”, but a part not related to the description of the present invention is partially omitted.

  In the operation description, R (Red), G (Green), and B (Blue) components of a color image are input from an input terminal, respectively, and Y (luminance signal), U (color difference signal (Cb)), and V (color difference signal) are input. (Cr)) The components are calculated and stored in the corresponding arrays. It is assumed that 16 RGB data are sequentially given from the input terminal, and the YUV components are stored in the order of input from address 0 to address 15 in the array.

  The terminal information is illustrated in the first to eleventh lines (FIG. 3) of the behavior description. The operation description includes sc_int <8> type input terminals r_in, g_in, and b_in, respectively. In addition, arrays r_ary [], u_ary [] and v_ary [] having a sc_uint <8> type and a capacity of 16 words are provided. The sc_uint <8> type is an integer type having an 8-bit width and no sign.

  In addition, behavior information is illustrated in the 12th to 31st lines (FIG. 3) of the behavior description. First, 16 pieces of data are read from the input terminal r_in by the loop processing L1 of the 15th row and stored in the array r_ary []. Similarly, the values read from the input terminals g_in and b_in are stored in the arrays g_ary [] and b_ary [] by the loop process L2 on the 19th line and the loop process L3 on the 23rd line, respectively.

  Next, by loop processing L4 on the 27th line, values are read from the arrays r_ary [], g_ary [] and b_ary [] (line 28), and the functions y_gen () and u_gen are used with these values as arguments. () And v_gen () are called. The values calculated by the function are stored in arrays y_ary [], u_ary [] and v_ary [] (from the 29th line to the 31st line). In the behavioral description shown in FIG. 3, these processes are repeated for each element of the array.

  The functions y_gen (), u_gen (), and v_gen () described above are assumed to be functions for calculating the YUB component from the RGB components of the color image, but are not directly related to the present invention, and thus are detailed. Is omitted. 3 is stored in the operation description storage unit 11 of the storage device 10 in advance. Next, a specific example when the processing of steps S1 to S4 in FIG. 2 is performed on the behavioral description shown in FIG.

  First, a specific example of the inter-loop dependency analysis processing (step S1) by the inter-loop dependency analysis processing unit 21 will be described. In the inter-loop dependency analysis process, the behavior description is read from the behavior description storage unit 11. Next, the inter-loop dependency analysis processing unit 21 analyzes the inter-loop dependency based on the behavioral description and determines which loop can be executed at which timing. The analysis result is shown in FIG.

  Referring to FIG. 3, in the loop processes L1, L2, and L3, the input terminals for reading values and the arrays for writing the read values do not overlap each other. Accordingly, the loop processes L1, L2, and L3 have no dependency relationship. Therefore, in the inter-loop dependency relationship information shown in FIG. 4, there is no dependency between the preceding loop process L1 and the subsequent loop processes L2 and L3, and the preceding loop process L2 and subsequent It is shown that there is no dependency relationship with the loop L3.

  On the other hand, the loop process L4 reads values from the arrays r_ary [], g_ary [], b_ary []. The values of these arrays are written by loop processing L1, L2, and L3, respectively. That is, the loop process L4 has a dependency relationship with the loop processes L1, L2, and L3. Therefore, the inter-loop dependency relationship information shown in FIG. 4 indicates that there is a dependency relationship between the preceding loop processes L1, L2, and L3 and the subsequent loop L4.

  Further, when attention is paid to the variable i and the variable l which are subscripts of the array r_ary [], if the relationship i> l is established between the variable i of the loop processing L1 and the variable l of the loop processing L4, the loop Even if there is a dependency between the process L1 and the loop process L4, the loop process L4 can be executed. In the loop processing L1, if the writing to the 0th element r_ary [0] of the array r_ary [] is completed in the loop processing L1 and the value of the variable i is 1, This means that a value can be read from the element r_ary [0]. Similarly, if the relationship j> l is established between the loop processing L2 and the loop processing L4, and the relationship k> l is established between the loop processing L3 and the loop processing L4, the loop processing L4 is executed. be able to. Therefore, in the example shown in FIG. 4, the “timing at which the subsequent loop can be executed” of the subsequent loop processing L4 with respect to the preceding loop processing L1, L2, and L3 is i> l, j> l, and k, respectively. It is shown that> 1.

  Next, a specific example of scheduling and binding processing (step S2) by the scheduling and binding processing unit 22 will be described. In the scheduling and binding process, a scheduling process and a binding process are performed. Therefore, the operation description of the control step obtained as a result of processing the operation description shown in FIG. 3 in the scheduling process is shown in FIGS. 5 to 8 are operation descriptions of control steps corresponding to the loop processes L1 to L4, respectively.

  As shown in FIG. 5, the loop process L1 includes the processes of steps L1_S1, L1_S2, and L1_S3. The 11th, 21st, and 31st lines in FIG. 5 each represent the name of a step. A variable RG_i represents a storage element (register) corresponding to the variable i. In step L1_S1, an operation for initializing the register RG_i to 0 is described (line 12). In step L1_S2, a value is read from the input terminal r_in and written to the element indicated by the value stored in the register RG_i of the array r_ary [] (line 22). Thereafter, the value of the register RG_i is updated to one larger value (the 23rd line). Step L1_S3 is a step in which all the processes of the loop process L1 are completed, and nothing is performed.

  As shown in FIG. 6, the loop process L2 is configured by the processes of steps L2_S1, L2_S2, and L2_S3. The 11th, 21st, and 31st lines in FIG. 6 each represent the name of a step. A variable RG_j represents a storage element (register) corresponding to the variable j. In step L2_S1, an operation for initializing the register RG_j to 0 is described (line 12). In step L2_S2, a value is read from the input terminal g_in and written to the element indicated by the value stored in the register RG_j of the array g_ary [] (line 22). Thereafter, the value of the register RG_j is updated to one larger value (the 23rd line). Step L2_S3 is a step in which all the processes of the loop process L2 are completed, and nothing is performed.

  As shown in FIG. 7, the loop process L3 is configured by the processes of steps L3_S1, L3_S2, and L3_S3. The 11th, 21st, and 31st lines in FIG. 7 each represent the name of a step. A variable RG_k represents a storage element (register) corresponding to the variable k. In step L3_S1, an operation for initializing the register RG_k to 0 is described (line 12). In step L3_S2, a value is read from the input terminal b_in and written to an element indicated by the value stored in the register RG_k of the array b_ary [] (line 22). Thereafter, the value of the register RG_k is updated to one larger value (the 23rd line). Step L3_S3 is a step in which all the processes of the loop process L3 are completed, and nothing is performed.

  As shown in FIG. 8, the loop process L4 is configured by the processes of steps L4_S1 to L4_S5. In step L4_S1, an operation for initializing the value of the register RG_l to 0 is described (line 12). In step L4_S2, the element indicated by the value of the register RG_l in the arrays r_ary [], g_ary [] and b_ary [] is read and stored in the registers RG_r, RG_g and RG_b, respectively (line 22 to line 24). In step L4_S3, the functions y_gen (), u_gen () and v_gen () are called with the values of the registers RG_r, RG_g and RG_b as arguments, and the return values are stored in the registers RG_y, RG_u and RG_v, respectively (from the 32nd line to the 34th line). Line). In step L4_S4, the values of the registers RG_y, RG_u, and RG_v are stored in the elements indicated by the values stored in the register RG_l in the arrays y_ary [], u_ary [], and v_ary [], respectively (line 42). 44th line from the eyes). Further, in step L4_S4, the value of the register RG_l is updated to one larger value (45th line). Step L4_S5 is a step in which all the processes of the loop process L4 are completed, and nothing is performed.

  Next, a specific example of the control circuit creation processing (step S3) by the control circuit creation processing unit 23 will be described. As described above, the control circuit creation process includes two processing steps, step S31 and step S32. Therefore, in the following, the control circuit creation process will be described separately in step S31 and step S32.

  First, in step S31, the first control logic for controlling the execution state of the control step in the loop process is generated. In the behavioral synthesis system 1 according to the first exemplary embodiment, the first control logic is configured as a finite state machine. Therefore, FIGS. 9 to 12 show state transition diagrams of the first control logic generated by the control circuit creation processing unit. The state transition diagrams shown in FIGS. 9 to 12 correspond to the loop processes L1 to L4, respectively.

  FIG. 9 shows a state transition diagram of a finite state machine (FSM) that controls the control steps belonging to the loop process L1. The finite state machine of the loop process L1 has states A11, A12, A13 and transitions B11, B12, B13. In states A11 and A12, steps L1_S1 and L1_S2 are executed, respectively. State A13 is a step after execution of all the loop processing L1, and nothing is performed.

  A transition B11 indicating a state transition from the state A11 to the state A12 is executed unconditionally following the state A11. When the value of the register RG_i is smaller than 16 in the state A12, the transition B12 that returns from the state A12 to the state A12 is executed. On the other hand, when the value of the register RG_i is 16 or more, a transition B13 indicating a state transition from the state A12 to the state B13 is executed.

  FIG. 10 shows a state transition diagram of a finite state machine (FSM) that controls the control steps belonging to the loop process L2. The finite state machine of the loop process L2 has states A21, A22, A23 and transitions B21, B22, B23. In states A21 and A22, steps L2_S1 and L2_S2 are executed. State A23 is a step after execution of all the processes of the loop process L2, and nothing is performed.

  A transition B21 indicating a state transition from the state A21 to the state A22 is executed unconditionally following the state A21. When the value of the register RG_i is smaller than 16 in the state A22, the transition B22 that returns from the state A22 to the state A22 is executed. On the other hand, when the value of the register RG_i is 16 or more, a transition B23 indicating a state transition from the state A22 to the state B23 is executed.

  FIG. 11 shows a state transition diagram of a finite state machine (FSM) that controls the control steps belonging to the loop process L3. The finite state machine of the loop process L3 has states A31, A32, A33 and transitions B31, B32, B33. In states A31 and A32, steps L3_S1 and L3_S2 are respectively executed. State A33 is a step after execution of all the loop processing L3 is completed, and nothing is performed.

  A transition B31 indicating a state transition from the state A31 to the state A32 is executed unconditionally following the state A31. When the value of the register RG_i is smaller than 16 in the state A32, the transition B32 that returns from the state A32 to the state A32 is executed. On the other hand, when the value of the register RG_i is 16 or more, a transition B33 indicating a state transition from the state A32 to the state B33 is executed.

  FIG. 12 shows a state transition diagram of a finite state machine (FSM) that controls the control steps belonging to the loop process L4. The finite state machine of the loop process L4 has states A41 to A45 and transitions B31 to B35. In states A41 to A44, steps L4_S1 to L4_S4 are respectively executed. State A45 is a step after execution of all the loop processing L4, and nothing is performed.

  A transition B41 indicating a state transition from the state A41 to the state A42 is executed unconditionally following the state A41. A transition B42 indicating a state transition from the state A42 to the state A43 is executed unconditionally following the state A42. A transition B43 indicating a state transition from the state A43 to the state A44 is executed unconditionally following the state A43. When the value of the register RG_i is smaller than 16 in the state A44, the transition B44 returning from the state A44 to the state A42 is executed. On the other hand, when the value of the register RG_i is 16 or more, a transition B45 indicating a state transition from the state A44 to the state B45 is executed.

  That is, in step S31, the first control logic that makes the state transition shown in FIGS. 9 to 12 is created, and a first control circuit based on the first control logic is generated.

  Next, in step S32, second control logic for controlling the execution state of the loop process is generated based on the execution condition of the loop process. In the control circuit creation processing, the inter-loop dependency stored in the inter-loop dependency relationship information storage unit 12 of the storage device 10 is read. Then, the second control logic is configured based on the execution status of each of the loop processes L1 to L3 having a dependency relationship with the loop process L4 and the conditions under which the loop process L4 can be executed. In the behavioral synthesis system 1 according to the first exemplary embodiment, the first control logic is configured as a finite state machine, whereas the second control logic is configured as a control circuit that gives a state transition condition to the first control logic. .

  In the behavioral description shown in FIG. 3, as shown in FIG. 4, the loop processes L1 to L3 have no dependency with other loop processes, and the loop process L4 has a dependency with the loop processes L1 to L3. Have Therefore, the behavioral synthesis system 1 that processes the behavioral description shown in FIG. 3 does not generate the second control logic for the loop processing L1 to L3. On the other hand, in the behavioral synthesis system 1, since the loop process L4 has a dependency relationship with the loop processes L1 to L3, the second control logic is generated as the logic for controlling the execution state of the loop process L4. Here, the second control logic is generated based on the inter-loop dependency relationship information shown in FIG. As shown in the inter-loop dependency relationship information in FIG. 4, the execution condition of the loop processing is determined by the execution status of the preceding loop processing having a dependency on the loop processing L4.

  As shown in FIG. 8, the loop process L4 requires the processing results of the loop processes L1 to L3 in step L4_S2. Therefore, in the control circuit creation process, when the execution condition of the loop process L4 in FIG. 4 is satisfied, a second control logic is generated that sets the start signal S0 for the first control logic corresponding to the loop process L4 to the enable state EN. To do. The second control logic compares the values of the registers RG_i, RG_j, RG_k and the value of the register RG_l, and when the register RG_l is smaller than all of the registers RG_i, RG_j, RG_k, the start signal is sent to the first control logic. S0 is given. That is, the second control logic generated in the present embodiment controls whether or not to execute the loop process L4. Note that the second control circuit implements the second control logic.

  In the control circuit creation process, the loop process L4 is modified so that the state transition is performed according to the start signal S0 generated by the second control logic. More specifically, in the control circuit creation process, state A42 in which step L2_S2 is executed in the first control logic corresponding to loop process L4 is set as state A46. Further, in the control circuit creation process, a transition B46 is added to transition from the state A46 to the state A46 when the start signal S0 is not the enable state EN. Furthermore, in the control circuit creation process, the transition B42 in FIG. 12 is modified to a transition B47 that transitions from the state A46 to the state A43 when the start signal S0 is in the enable state EN. FIG. 13 shows a state transition diagram of the first control logic corresponding to the loop process L4 modified in this way.

  Note that the second control logic can also be generated by modifying the first control logic. In this case, the second control logic corrects the first control logic corresponding to the loop process L4 so that the process of step L4_S2 is performed when the execution condition of the loop process L4 is satisfied. Generated.

  Next, a specific example of the RTL description generation process (step S4) by the RTL description generation processing unit 24 will be described. In the RTL description generation process, a data path is created from the arithmetic units and registers determined by the scheduling and binding processing unit 22, and the RTL description is based on the control circuit created by the control circuit creation processing unit 23 and the data path. Create Then, the created RTL description is stored in the RTL description storage unit 13 of the storage device 10.

  A specific example of a block diagram of a semiconductor device generated based on the RTL description generated through the above processing is shown in FIG. As shown in FIG. 14, the semiconductor device includes finite state machines 34, 44, 54, 64 corresponding to the first control circuit and a control circuit 71 corresponding to the second control circuit. Each element of the semiconductor device shown in FIG. 14 has the following correspondence.

  Input terminals r_in, g_in, and b_in correspond to r_in in the second row in FIG. 3, g_in in the third row in FIG. 3, and b_in in the fourth row in FIG. 3, respectively. The registers 32, 42, 52, and 62 are respectively a register RG_i on the 12th line in FIG. 5, a register RG_j on the 12th line in FIG. 6, a register RG_k on the 12th line in FIG. 7, and a register RG_l on the 12th line in FIG. Corresponding to The registers 36, 46, and 56 correspond to the register RG_r on the 22nd line in FIG. 8, the register RG_g on the 23rd line in FIG. 8, and the register RG_b on the 24th line in FIG. The registers 38, 48, and 58 correspond to the register RG_y on the 32nd line in FIG. 8, the register RG_u on the 33rd line in FIG. 8, and the register RG_v on the 34th line in FIG. The adders 33, 43, 53, and 63 are the adder in the 23rd row in FIG. 5, the adder in the 23rd row in FIG. 6, the adder in the 23rd row in FIG. 7, and the adder in the 45th row in FIG. Corresponding to the vessel. The memories 35, 45, and 55 correspond to the array r_ary on the 22nd line in FIG. 5, the array g_ary on the 22nd line in FIG. 6, and the array b_ary on the 22nd line in FIG. The memories 39, 49, and 59 correspond to the array y_ary on the 42nd row in FIG. 8, the array u_ary on the 43rd row in FIG. 8, and the array v_ary on the 44th row in FIG. The submodules 37, 47, and 57 respectively correspond to the function y_gen on the 32nd line in FIG. 8, u_gen on the 33rd line in FIG. 8, and v_gen on the 34th line in FIG. The multiplexers 31, 41, 51, 61 are controlled by the finite state machines 34, 44, 54, 64, and are used to initialize the values of the registers RG_i, RG_j, RG_k, RG_l.

  In the semiconductor device shown in FIG. 14, the finite state machine 34 receives the value output from the adder 33, and controls the multiplexer 31, the register 32, the adder 33, the memory 35, and the input terminal r_in to operate the loop process L1. To control. The finite state machine 34 controls the loop processing L1 to be executed from the state A11 (step L1_S1) according to the first clock. The finite state machine 34 performs control to assign a value 0 to the register 32 (RG_i) in the state A11. Further, the finite state machine 34 stores the value read from the input terminal r_in in the array indicated by the value of the register 32 (RG_i) in the array of the memory 35 as control corresponding to the state A12 (step L1_S2). At the same time, the finite state machine 34 updates the value of the register 32 (RG_i) to one larger value. The updated value is communicated to the finite state machine 34. Further, the finite state machine 34 controls to execute the state A12 again when the update value is smaller than 16, and when the update value is 16 or more, the state A12 is changed to the state A13 (step L1_S3). To control.

  The finite state machine 44 receives the value output from the adder 43, and controls the operation of the loop processing L2 by controlling the multiplexer 41, the register 42, the adder 43, the memory 45, and the input terminal g_in. The finite state machine 44 controls the loop process L2 to be executed from the state A21 (step L2_S1) according to the first clock. The finite state machine 44 performs control to substitute the value 0 into the register 42 (RG_j) in the state A21. Further, the finite state machine 44 stores the value read from the input terminal g_in in an array indicated by the value of the register 42 (RG_j) in the array of the memory 45 as control corresponding to the state A22 (step L2_S2). At the same time, the finite state machine 44 updates the value of the register 42 (RG_j) to one larger value. The updated value is communicated to the finite state machine 44. Further, the finite state machine 44 controls to execute the state A22 again when the update value is smaller than 16, and when the update value is 16 or more, the state A22 is changed to the state A23 (step L2_S3). To control.

  The finite state machine 54 receives the value output from the adder 53 and controls the operation of the loop processing L3 by controlling the multiplexer 51, the register 52, the adder 53, the memory 55, and the input terminal b_in. The finite state machine 54 controls the loop process L3 to be executed from the state A31 (step L3_S1) according to the first clock. The finite state machine 54 performs control for substituting the value 0 into the register 52 (RG_k) in the state A31. Further, the finite state machine 54 stores the value read from the input terminal b_in in the array indicated by the value of the register 52 (RG_k) in the array of the memory 55 as control corresponding to the state A32 (step L3_S2). At the same time, the finite state machine 54 updates the value of the register 52 (RG_k) to one larger value. The updated value is communicated to the finite state machine 54. Further, the finite state machine 54 performs control so that the state A32 is executed again when the update value is smaller than 16, and when the update value is 16 or more, the state A32 is changed to the state A33 (step L3_S3). To control.

  The finite state machine 64 receives the value from the adder 63 and controls the multiplexer 61, the adder 63, the registers 62, 36, 46, 56, 38, 48, 58, and the memories 35, 45, 55, 39, 49, 59. Then, the operation of the loop processing L4 is controlled. The finite state machine 64 is controlled by the control circuit 71.

  First, the finite state machine 64 operates to assign a value 0 to the register 62 (RG_l) as control corresponding to the state A41 (step L4_S1) regardless of the state of the start signal S0 output from the control circuit 71. . Then, the state of the finite state machine 64 transitions from the state A41 to the state A42. In this state A42, the finite state machine 64 does not execute the state A42 and maintains the waiting state until the start signal S0 output from the control circuit 71 is enabled. The control circuit 71 reads the values of the registers 32, 42, and 52, and sets the start signal S0 to the enable state EN when the value of the register 62 (RG_l) is smaller than any of the values of the registers 32, 42, and 52. Then, the finite state machine 64 performs control for realizing the operation of Step L4_S2 corresponding to the state A42 in response to the start signal S0 becoming the enable state EN. In this control, the elements stored in the array indicated by the value of the register 62 (RG_l) among the arrays of the memories 35, 45, and 55 are stored in the registers 36, 46, and 56, respectively.

  Then, the state transition from the state A42 to the state A43 is performed according to the updated values of the registers 36, 46, and 56, and the processing of the state A44 is performed according to the processing of the state A43 being further performed. Done. That is, after step L4_S2, the processes of step L4_S3 and step L4_S4 are performed continuously.

  In step L4_S3, all the submodules 37, 47, and 57 read the values (RG_r, RG_g, and RG_b) of the registers 36, 46, and 56. Then, the submodules 37, 47, and 57 store values obtained after processing in the corresponding registers among the registers 38, 48, and 49 (RG_y, RG_u, and RG_v).

  In step L4_S4, the value stored in the register 38 (RG_y) is stored in the array of values indicated by the register 62 (RG_l) in the array of the memory 39. The value stored in the register 48 (RG_u) is stored in the array of values indicated by the register 62 (RG_l) in the array of the memory 49. The value stored in the register 58 (RG_v) is stored in the array of values indicated by the register 62 (RG_l) in the array of the memory 59. Further, in step L4_S4, the adder 63 updates the value of the register 62 to one larger value. The updated value is communicated to the finite state machine 64.

  Further, the finite state machine 64 performs control so that when the updated value is smaller than 16 in the state A44, the state is again shifted to A42 and step L4_S2 is executed. On the other hand, when the update value is 16 or more, the finite state machine 64 performs control so that the state is changed from the state A44 to the state A45 and step L4_S5 is executed.

  From the above description, the behavioral synthesis system 1 according to the first embodiment analyzes the dependency relationship between the loop processes in the behavior description by the inter-loop dependency relationship analysis process. Then, the behavioral synthesis system 1 generates a first control logic for controlling the execution state for each control step during the loop processing and a second control logic for controlling the execution state of the loop processing based on the analysis result. . Thereafter, the behavioral synthesis system 1 generates an RTL description including a control circuit including the first control logic and the second control logic, and an arithmetic unit and a register that perform processing according to the behavior description. As a result, the behavioral synthesis system 1 can generate an RTL description that has all loop processing as independent circuits and that can operate in consideration of the dependency between loops. That is, according to the behavioral synthesis system 1, even when there is a data dependency between a plurality of loops described sequentially, it is possible to synthesize a circuit that can execute loop processing in parallel by parallelizing the loop processing. .

  The behavioral synthesis system 1 can generate the RTL description as described above regardless of the complexity of the dependency between loop processes. This is because a control circuit that performs control in consideration of the dependency between loop processes is provided separately from the circuit related to the loop processes.

  In addition, a semiconductor device formed based on the RTL description generated by the behavioral synthesis system 1 includes a first loop processing circuit that executes a first loop process that does not have a dependency relationship with other loop processes, and others. A second loop processing circuit that executes a second loop processing having a dependency relationship with the loop processing of the first loop, a first control logic that controls an execution state of a control step of the first and second loop processing circuits, And a control circuit including a second control logic that controls an execution state of the second loop process in accordance with a processing result of another loop process. In this semiconductor device, since loop processing is parallelized, one process can be processed in a short time. That is, according to the behavioral synthesis system 1, it is possible to synthesize a semiconductor device with high processing performance.

  In the above embodiment, the example in which the behavioral synthesis system 1 is realized by hardware has been described. However, processing corresponding to the processing of the hardware can also be realized by software. This behavioral synthesis program is executed in an arithmetic circuit, synthesizes an RTL description from a behavioral description stored in a storage device, and stores the RTL description in the storage device.

Embodiment 2
The behavioral synthesis system 2 according to the second exemplary embodiment synthesizes an RTL description that performs pipeline processing from a behavioral description including a loop process having a dependency relationship with other loop processes. A block diagram of this behavioral synthesis system 2 is shown in FIG. As illustrated in FIG. 15, the behavioral synthesis system 2 includes a processing device 20a in which the control circuit creation processing unit 23 of the behavioral synthesis system 1 according to the first embodiment is replaced with a control circuit creation processing unit 23a. In the description of the behavioral synthesis system 2 according to the second embodiment, the same components as those in the behavioral synthesis system 1 according to the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted.

  The control circuit creation processing unit 23a is included in the loop processing based on the control step determined by the scheduling / binding processing unit 22 and the inter-loop dependency information stored in the inter-loop dependency information storage unit 12. The control steps are grouped for each stage of the pipeline processing, the first control logic for controlling the execution of the steps in the stage, the third control logic for controlling the execution state for each stage, and the execution of the loop are controlled. A control circuit having a third control logic is created.

  Next, the operation of the behavioral synthesis system 2 according to the second exemplary embodiment will be described. FIG. 16 is a flowchart showing the operation procedure of the behavioral synthesis system 2. As shown in FIG. 16, in the behavioral synthesis system 2, processes other than the control circuit creation process (steps S1, S2, and S4 in FIG. 16) are the same as those in the flowchart shown in FIG. Therefore, in the following, description of steps S1, S2, and S4 will be omitted, and control circuit creation processing (step S5) of the control circuit creation processing unit 23a that is characteristic in the behavioral synthesis system 2 will be described.

  Step S5 has four processing steps of steps S51 to S54. Step S51 performs stage determination processing. In step S51, the control circuit creation processing unit 23a assigns the control step determined by scheduling to the pipeline processing stage. This stage is assigned with a group of a plurality of control steps executed in a single or continuous manner among control steps belonging to one loop process. The number of steps included in one group is equal to or less than a predetermined initiation interval. In the loop processing to which the loop pipeline technique is applied, the operation is performed so that the next iteration is started before the end of one iteration. At this time, the time (number of clocks) from the start of one iteration to the start of the next iteration is called an initiation interval. Focusing on one step, there is a property that it is not executed until the time (number of clocks) of the initiation interval elapses after execution for the first iteration. When a plurality of control steps executed in succession are grouped by the number of clocks in the initiation interval, one iteration moves the stage one by one in each initiation interval. At this time, it is desirable to consider in advance at the time of binding so that operations belonging to different stages do not share the same arithmetic unit. Furthermore, it is desirable to consider in advance when binding so that registers are not shared between different stages.

  Next, in step S52, the control circuit creation processing unit 23a creates first control logic for controlling the execution of the control step belonging to that stage for each stage. The first control logic is constituted by, for example, a finite state machine (FSM). The first control logic is created for each stage, and is configured to sequentially execute control steps belonging to the stage.

  Next, in step S53, the control circuit creation processing unit 23a creates a third control logic for controlling the execution of the stage. The third control logic is configured to check the start condition of the stage and control whether to start execution of the first control step belonging to the stage or to wait without starting. The first condition for starting a stage is determined by the execution status (end status) of the immediately preceding stage or loop. Also, the second condition for starting the stage is determined by the stage immediately following or the execution status of the loop processing. The third control logic is configured to start execution of the stage when both start conditions of the first and second conditions are met.

  Next, in step S54, the control circuit creation processing unit 23a creates a second control logic that controls execution of the loop processing. As in the first embodiment, the second control logic is a start signal for notifying the first and second control logic corresponding to the loop process to be controlled of the start of the process according to the execution status of other loop processes. It is generated as a control circuit that outputs S0. The second control logic can also be configured by changing the execution conditions of the first and second control circuits created in steps S52 and S53. The second control logic is configured to check a start condition of the loop process and control whether to start executing the loop process or wait without starting.

  The start condition of the loop process is determined by the execution status of the preceding loop having a dependency relationship with the loop. That is, the inter-loop dependency relationship information stored in the inter-loop dependency relationship information storage unit 12 is read, and the execution status and the conditions (loops) that enable execution of each loop process that has a dependency relationship with the loop process. The control logic is configured based on the processing start condition). For example, the second control logic for controlling the execution of the loop is configured to check the start condition of the loop process in the head state of the loop process. Further, for example, the start condition of the loop process may be inspected in all the states of the loop process. Further, for example, the start condition of the loop process may be inspected in a specific state where the loop process is performed. In addition, when there is no preceding loop having a dependency relationship with the loop process, the loop process is unconditionally started.

  Next, a specific example of the operation procedure of the behavioral synthesis system 2 described above will be described. In this description, the behavioral description system according to the second embodiment is also given the same behavioral description (FIG. 3) as in the first embodiment, and the loop pipeline is applied at the initiation interval 1 to the loop processing L4. Shall be.

  In the second embodiment, since the loop pipeline is applied to the loop process L4, the control steps determined in the scheduling and binding process in step S2 are different from those in the first embodiment. Therefore, FIG. 17 shows an example of description indicating the operation of the control step determined in step S2 of the second embodiment. As shown in FIG. 17, in the operation of step L4_S2 in the second embodiment, register RG_l2 is newly added to the operation of step L4_S2 in the description of the operation shown in FIG. 8, and the value of register RG_l is added to this register RG_l2. Is different (line 25). Further, as shown in FIG. 17, in the operation of step L4_S3 of the second embodiment, register RG_l3 is newly added to the operation of step L4_S3 in the description of the operation shown in FIG. 8, and the value of register RG_l2 is substituted. Is different (line 35). As shown in FIG. 17, the operation of step L4_S4 in the second embodiment is different from the operation of step L4_S4 in the description of the operation shown in FIG. 8 in that the subscripts of the array y_ary, u_ary, v_ary to be written are The point that has been changed to. Note that the result of applying the scheduling and binding process to the loop processes L1, L2, and L3 is the same as the example corresponding to the first embodiment of the present invention (FIGS. 5 to 7).

  Next, the control circuit creation processing unit 23a assigns the step determined by scheduling to the stage (step S51). Since the processing of the loop processing L4 applies the loop pipeline technique at the initiation interval 1, the number of steps included in each stage is one. Therefore, the control circuit creation processing unit 23a first groups each step of the loop processing L4 as one stage. Grouping is performed so that step L1_S11 is performed in stage ST1, step L4_S2 is performed in stage ST2, step L4_S3 is performed in stage ST3, step L4_S4 is performed in stage ST4, and step L4_S5 is performed in stage ST5.

  Next, the control circuit creation processing unit 23a creates, for each stage, first control logic that controls execution of the steps belonging to that stage (step S52). The first control logic is constituted by, for example, a finite state machine (FSM). The first control logic is created for each stage, and is configured to sequentially execute the steps belonging to the stage. Thus, state transition diagrams of the first control logic are shown in FIGS. In FIG. 18, the first control logic for the stage ST1 is expressed as a finite state machine. The finite state machine of stage ST1 has one state A51 and two transitions B51 and B52. Step L4_S1 is executed when the transition B51 is executed, and nothing is executed when the transition B52 is executed. The execution conditions for the transitions B51 and B52 have not been specified yet. Similarly, in FIGS. 19 to 22, the first control logic of each stage corresponding to steps L4_S2 to L4_S5 is represented as a state transition diagram of a finite state machine. Each finite state machine is the same as the finite state machine of stage ST1 except that the steps to be executed are different.

  Next, the control circuit creation processing unit 23a creates, for each stage, third control logic that controls execution of that stage (step S53). The third control logic is configured to check the execution condition of the stage and control whether to start execution of the first step of the stage or to wait without starting. Therefore, FIG. 23 shows a state transition diagram of the third control logic. The state transition diagram shown in FIG. 23 shows the state transition conditions between the stages.

  Specifically, since there is no previous stage in stage ST1, stage ST1 starts execution unconditionally. The stage ST2 executes the transition A61 when the end of the immediately preceding stage ST1 is notified (that is, executes step L4_S2), and if the end of the stage ST1 is not notified, executes the transition B62 (ie, , Do nothing). The stage ST3 executes the transition B71 when it is notified that the immediately preceding stage ST2 is finished and the register RG_l is smaller than 16 (that is, the step L4_S3 is executed), the stage ST2 is finished and the register RG_l If it is not notified that is smaller than 16, it is controlled to execute the transition B72 (that is, do nothing). The stage ST4 executes the transition B82 when notified of the end of the immediately preceding stage ST3 (that is, executes step L4_S4), and executes the transition B82 when not notified of the end of the stage ST3 (that is, , Do nothing). Since the stage ST5 is a stage after the execution of the loop process L4 is completed, after the completion of the process of the immediately preceding loop process L4 is notified, the stage ST5 is controlled to continue executing the transition B92. Note that the notification of the completion of the process of the loop process L4 means that the stage ST2 is completed and the value of the register RG_l is 16 or more.

  Next, the control circuit creation processing unit 23a creates a second control logic that controls execution of the loop processing (step S54). In step S54, the first control logic shown in FIG. 22 is modified so that state transition is performed in accordance with the start signal S0 generated by the second control logic. More specifically, in step S54, the transition condition of step L2_S2 included in stage ST2 in the first control logic corresponding to loop process L4 is corrected. The first control logic corresponding to step L4_S2 after correction has transitions B61a and B62a. Then, when the start signal S0 is in the enabled state, the transition B61a is executed to execute step L4_S1, and when the start signal S0 is in the disabled state, the transition B62a is executed to do nothing. Become. FIG. 24 shows a state transition diagram of the third control logic corresponding to the loop process L4 including the first control logic modified in this way.

  From the above description, in the behavioral synthesis system 2 according to the second embodiment, in the control circuit creation process, the third control logic for controlling the execution state for each stage of the pipeline process is created corresponding to the pipeline process. . In the control circuit creation process, the first and second control logics are created together with the third control logic as in the first embodiment. Note that the first control logic in the second embodiment controls the execution state of the control steps in the stage.

  The RTL description generated by the behavioral synthesis system 2 has a control circuit including third control logic. That is, in the behavioral synthesis system 2, it is possible to synthesize a circuit that executes a plurality of loops in parallel after performing individual loop processing in a pipeline.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, in the control circuit, the first control logic, the second control logic, and the third control logic do not need to be configured as independent circuits, and the circuit can perform operations based on the control logic. As long as the is formed.

DESCRIPTION OF SYMBOLS 1, 2 Behavior synthesis system 10 Memory | storage device 11 Behavior description memory | storage part 12 Inter-loop dependence information storage part 13 RTL description memory | storage part 20, 20a Processor 21 Inter-loop dependence analysis part 22 Scheduling and binding process part 23, 23a Control circuit Creation processing unit 24 RTL description generation processing unit 31, 41, 51, 61 Multiplexer 32, 42, 52, 62 Register 33, 43, 53, 63 Adder 34, 44, 54, 64 Finite state machine 35, 45, 55 Memory 36, 46, 56 Registers 37, 47, 57 Submodules 38, 48, 58 Registers 39, 49, 59 Memory 71 Control circuit

Claims (9)

A behavioral synthesis system that synthesizes an RTL (Register Transfer Level) description from a behavioral description including loop processing ,
By analyzing the dependencies between the loop processing, the loop between the dependency analysis processing unit that generates dependency information between loop extracts the execution conditions of the dependent loop having a dependency relationship with another loop,
A scheduling and binding processing unit for performing a scheduling process for determining a control step for executing an operation in the loop process; and a binding process for determining an arithmetic unit for performing the operation in the loop process and a register for storing data; ,
A control circuit including a first control logic that controls an execution state of the control step in the loop process, and a second control logic that controls the execution state of the loop process based on the execution condition of the loop process Generating a control circuit according to the processing result of the scheduling and binding processing unit and the inter-loop dependency relationship information;
An RTL description generation processing unit that generates a data path using the arithmetic unit and the register, and generates an RTL description including the data path and the control circuit;
A behavioral synthesis system.   The behavioral synthesis system according to claim 1, wherein the inter-loop dependency relationship information includes an execution condition in which a control step included in the dependency loop process is executable.   The behavioral synthesis system according to claim 1, wherein the control circuit is a state machine that transitions a plurality of predetermined states in a predetermined order according to a predetermined condition.   4. The behavioral synthesis system according to claim 1, wherein the first control logic controls whether or not the first control logic is executed for each control step of the loop processing. 5. Including multiple stages, pipeline processing is performed for each stage,
The control circuit creation processing unit groups control steps included in the loop processing for each stage of pipeline processing, and generates the control circuit including a third control logic for controlling an execution state for each stage. Item 5. The behavioral synthesis system according to any one of Items 1 to 4 . A behavioral synthesis method for synthesizing an RTL (Register Transfer Level) description from a behavioral description including loop processing by processing in the arithmetic circuit in a behavioral synthesis system having a storage device and an arithmetic circuit ,
By analyzing the dependencies between the loop processing, generates dependency information between loop extracts the execution conditions of the dependent loop having a dependency relationship with another loop,
Determine a control step for executing the calculation of the loop processing,
Performs scheduling and binding processing to determine a computing unit that performs the computation of the loop processing and a register that stores data,
A control circuit including a first control logic that controls an execution state of the control step in the loop process, and a second control logic that controls the execution state of the loop process based on the execution condition of the loop process Is generated according to the processing result of the scheduling binding process and the inter-loop dependency relationship information,
Create a data path using the arithmetic unit and the register,
A behavioral synthesis method for synthesizing an RTL description including the data path and the control circuit. A behavioral synthesis program for synthesizing an RTL (Register Transfer Level) description from a behavioral description executed in an arithmetic circuit and stored in a storage device, and storing the RTL description in the storage device,
By analyzing the dependencies between loop process included in the operation description, the loop between dependence analyzing to generate dependency information between loop extracts the execution conditions of the dependent loop having a dependency relationship with another loop processing Processing,
Determining a control step for executing the operation of the loop processing; scheduling binding processing for determining an arithmetic unit for performing the operation of the loop processing and a register for storing data;
A control circuit including a first control logic that controls an execution state of the control step in the loop process, and a second control logic that controls the execution state of the loop process based on the execution condition of the loop process A control circuit creating process for generating the process according to the processing result of the scheduling and binding processing unit and the inter-loop dependency relationship information;
RTL description generation processing for generating a data path using the arithmetic unit and the register, and generating an RTL description including the data path and the control circuit;
A behavioral synthesis program. A first loop processing circuit that executes the first loop processing that does not have a dependency relationship with other loop processing;
A second loop processing circuit for executing a second loop processing having a dependency relationship with other loop processing;
A first control logic for controlling the execution state of the control step of the first and second loop processing circuits , and a second for controlling the execution state of the second loop processing according to the processing results of other loop processing A control circuit comprising:
A semiconductor device. The first and second loop processing circuits execute the first and second loop processing by pipeline processing,
The semiconductor device according to claim 8, wherein the control circuit includes a third control logic that controls an execution state of the second loop processing for each stage of the pipeline processing.

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