JP5641570B2 - Slave station communication device and power control method - Google Patents

Description

  The present invention relates to a slave station communication device and a power control method, and can be applied to an optical communication network system employing, for example, 10GE-PON (Gigabit Ethernet-Passive Optical Network; Ethernet is a registered trademark).

  In an optical communication network system adopting a conventional 10GE-PON (IEEE802.3av (Non-patent Document 1 etc.)), one OLT (Optical Line Terminal) and a plurality of ONUs (Optical Network Unit) are branched by an optical splitter. It connects with an optical fiber and becomes a structure connected to one to several.

  In general, in PON, signal transmission (frame transmission) in the direction from the OLT to the ONU (hereinafter referred to as “downward direction”) and the direction from the ONU to the OLT (hereinafter referred to as “upstream direction”) are different. Multiplexing is performed using a WDM (Wavelength Division Multiplexing) method using a wavelength of λ. Further, since one optical fiber is shared by a plurality of ONUs, signal transmission from each ONU is avoided by using a TDI (Time Division Multiple Access) system for uplink signal transmission.

  In the conventional 10GE-PON, a control function called MPCP (Multi Point Control Protocol) is defined for TDMA access control, and a control frame called a MAC control frame is transmitted and received between the OLT and the ONU. MPCP control is realized with this.

  Further, in the conventional ONU, there are technologies described in Patent Documents 1 and 2 as technologies for reducing power by cutting off the power of ICs or LSIs that perform communication control of the ONU in accordance with MPCP control.

JP 2007-89027 A JP 2008-113193 A IEEE edition, “Physical Layer Specifications and Management Parameters for 10 Gb / s Passive Optical Networks (IEEE Std 802.3avTM-2009)”, [Online], INTERNET [retrieved on December 15, 2010], <URL: http: // standards.ieee.org/getieee802/download/802.3av-2009.pdf>

  ITU-T G.Supp45 (G-PON Power saving), which defines the power saving of the devices that make up the PON, speeds up the transition operation between the normal operating state of the ONU and the sleep operating state (power saving state). (ONU Fast Sleep) is required.

  However, Patent Documents 1 and 2 only describe power saving by turning off the power of ICs or LSIs that perform communication control of ONUs, and a case of shifting from a power saving state to a normal operation state. The transition speed greatly depends on the performance of the power supply circuit (for example, the power-up sequence), which requires a complicated power supply circuit and is difficult to realize.

  Therefore, in a slave station communication device (for example, ONU) that is connected to and accommodated by a master station communication device (for example, OLT), a transition between a normal operation state and a power saving operation state (sleep operation state) A slave station communication device and a power control method that can be easily increased in speed are desired.

According to a first aspect of the present invention, in a slave station communication device connected to the master station communication device by a PON and accommodated under the master station communication device, (1) communication of the slave station communication device using a communication control circuit A communication control means for performing a control process, and (2) the communication control circuit performs at least (2-1) a process for holding a downlink frame from the master station side network to which the master station communication apparatus is connected. A frame holding unit; (2-2) an uplink frame holding unit that performs processing to hold an uplink frame from the slave station network accommodated by the slave station communication device; and (2-3) the communication control circuit. An operation state data storage register for storing operation state data related to the operation state of the above constituent elements, and (3) a parameter of sleep time information related to sleep control in the downstream frame holding unit Triggered by the detection of the control frame including the above, by setting a part or all of the power saving target processing part in the reset state on the communication control circuit except for the uplink frame holding part, The system further comprises power saving control means for operating the communication control circuit with lower power consumption than in the normal operation state. (4) In the communication control circuit, the circuit to be reset by the power saving control means is in the reset state. Before, the operation state data relating to the operation state of the circuit of the part is autonomously stored in the operation state data storage register, and the circuit of the part to be reset by the power saving control unit is in the reset state. When returning from the operation state, autonomously read the operation state data stored in the operation state data storage register and based on the operation state data Characterized in that it starts to work.

The second of the present invention is connected by the master station communication device and PON, the power control method of the contained benzalkonium station communication apparatus under the above master station communication device, (1) said child station communication apparatus, a communication control Communication control means for performing communication control processing of the slave station communication device using a circuit, (2) the communication control circuit is at least (2-1) a downlink from the master station side network to which the master station communication device is connected A downlink frame holding unit that performs processing to hold a frame in the direction, and (2-2) an uplink frame holding unit that performs processing to hold an uplink frame from the slave station side network accommodated by the slave station communication device. And (2-3) an operation state data storage register for storing operation state data relating to the operation states of the components on the communication control circuit, and (3) the power saving control means includes the downlink frame When a control frame including a parameter of sleep time information related to sleep control is detected in the holding unit, a part or all of the part excluding the uplink frame holding unit on the communication control circuit By setting the power saving target processing portion to the reset state, the communication control circuit is operated with lower power consumption than the normal operation state. (4) In the communication control circuit, the power saving control means Before the circuit enters the reset state, it autonomously stores the operation state data related to the operation state of the circuit in the part in the operation state data storage register, and is reset by the power saving control unit. When the circuit of the part returns from the reset state, it autonomously reads the operation state data stored in the operation state data storage register. Characterized in that it starts an operation based on said operating state data.

  ADVANTAGE OF THE INVENTION According to this invention, in the slave station communication apparatus connected and accommodated with a master station communication apparatus by PON, the transition between a normal operation state and a power saving operation state can be easily accelerated.

It is the block diagram shown about the functional structure of ONU which concerns on 1st Embodiment. It is the block diagram shown about the whole structure of the optical communication network system which concerns on 1st Embodiment. It is explanatory drawing shown about the structural example of the extended MAC control frame which concerns on 1st Embodiment. In the optical communication network system according to the first embodiment, it is a sequence diagram showing an operation when no upstream frame is generated while the ONU is in the sleep operation state. In the optical communication network system according to the first embodiment, it is a sequence diagram showing an operation when an upstream frame is generated while an ONU is in a sleep operation state. It is the sequence diagram which detailed the operation | movement in ONU in the optical communication network system of 1st Embodiment. It is the block diagram shown about the functional structure of ONU which concerns on 2nd Embodiment.

(A) First Embodiment Hereinafter, a first embodiment of a slave station communication device and a power control method according to the present invention will be described in detail with reference to the drawings. Note that the slave station communication device of the first embodiment is an ONU.

(A-1) Configuration of the First Embodiment FIG. 2 is a block diagram showing the overall configuration of this embodiment.

  In the optical communication network system 1, an OLT 2 and n ONUs 3 (3-1 to 3-n) are arranged. Note that the number of ONUs 3 to be arranged is not limited.

  The OLT 2 and each ONU 3 are connected by an optical fiber 4 branched by an optical splitter 5 (which may be a plurality of branches). That is, a PON is formed by the OLT 2 and each ONU 3. The communication between the OLT 2 and each ONU 3 will be described assuming that a configuration conforming to 10GE-PON (IEEE 802.3av) is adopted.

  In FIG. 2, it is assumed that the OLT 2 is connected to an upper network (not shown), and each ONU 3 is connected to a lower network (user network) (not shown). That is, in the optical communication network system 1, data transmission is performed between a lower-side network (not shown) and an upper-side network (not shown) by the OLT 2 and the ONU 3.

  As the OLT 2, since the same OLT as that in the conventional 10GE-PON can be applied, a detailed description is omitted here.

  Next, the internal configuration of the ONU 3 will be described with reference to FIG.

  In FIG. 1, ONU3-1 to ONU3-n are all shown as having the same configuration.

  The ONU 3 includes an optical transceiver 31, a SerDes (Serializer / Deserializer) processing unit 32, an LSI 33, a power supply unit 34, a CPU 35, and a UNI (User-Network Interface) 36.

  The optical transceiver 31 and the SerDes processing unit 32 have an interface function for connecting to the optical fiber 4 (PON side) in the ONU 3.

  The optical transceiver 31 converts the electrical signal given from the SerDes processing unit 32 into an optical signal and sends it to the optical fiber 4 (PON side). In addition, when the optical transceiver 31 receives an optical signal transmitted from the OLT 2 via the optical fiber 4, the optical transceiver 31 converts the optical signal into an electrical signal and supplies the electrical signal to the SerDes processing unit 32. As the optical transceiver 31, the same one as the ONU in the existing 10GE-PON can be applied.

  The SerDes processing unit 32 performs conversion between a parallel signal used inside the ONU 3 and a serial signal used on the PON (on the optical fiber 4). The SerDes processing unit 32 converts a parallel signal (electrical signal of a frame to be transmitted to the OLT 2) given from the LSI 33 in the ONU 3 into a serial signal and gives it to the optical transceiver 31. In addition, when a serial signal (electrical signal of a frame transmitted from the OLT 2) is given from the optical transceiver 31, the SerDes processing unit 32 converts the signal into a parallel signal and gives it to the LSI 33. As the SerDes processing unit 32, the same ONU as that in the existing 10GE-PON can be applied.

  The UNI 36 is an interface (physical port) connected to the lower network in the ONU 3 and is connected to a communication device (eg, personal computer, router, hub, etc.) belonging to the lower network. The type of interface applied to the UNI 36 is not limited. For example, a physical port of an interface corresponding to 10GE can be applied.

  The power supply unit 34 supplies power to each component (functional block) in the ONU 3. As the power supply unit 34, the same one as the ONU in the existing 10GE-PON can be applied.

  The CPU 35 controls the operation of each part of the ONU 3. Further, the CPU 35 controls the ONU 3 to shift to a normal operation state (hereinafter also referred to as “active operation state”) or a state in which the ONU 3 is operated with lower power consumption than the active operation state (hereinafter also referred to as “sleep operation state”). (Hereinafter also referred to as “sleep control”). Details of the sleep control processing by the CPU 35 will be described later.

  As for the CPU 35 and the program executed by the CPU 35, the same program as the ONU in the existing 10GE-PON can be applied except for the configuration for performing sleep control related to the LSI 33 described later.

  The LSI 33 performs communication control processing related to the PON in the ONU 3, and is disposed between the SerDes processing unit 32 that constitutes the PON side interface and the UNI 36 that is an interface of the lower side network. Specifically, the LSI 33 performs communication control processing for uplink and downlink user data frames transferred by the ONU 3 and control frames (such as frames related to MPCP control).

  The LSI 33 includes a downstream PON-PCS processing unit 33a, a downstream PON-MAC processing unit 33b, a downstream Bridge unit 33c, an upstream PON-PCS processing unit 33d, an upstream PON-MAC processing unit 33e, an upstream Bridge unit 33f, an MPCP termination unit 33g, An MPCP insertion unit 33h, an uplink monitoring unit 33i, and a buffer 33j are included.

  The downstream PON-PCS processing unit 33 a and the upstream PON-PCS processing unit 33 d are responsible for processing related to the PON PCS (Physical Coding Sublayer) in the ONU 3.

  The downstream PON-PCS processing unit 33a performs processing related to the PCS such as data decoding processing and error bit correction for the downstream frame. The upstream PON-PCS processing unit 33d performs processing related to the PCS on upstream frame data.

  In addition, the process itself concerning PCS which the downstream PON-PCS processing part 33a and the upstream PON-PCS processing part 33d perform can apply the same process as the ONU in the existing 10GE-PON.

  The downstream PON-MAC processing unit 33b and the upstream PON-MAC processing unit 33e are responsible for processing related to the multipoint MAC control sublayer, such as MPCP control in the ONU 3.

  The downlink PON-MAC processing unit 33b and the uplink PON-MAC processing unit 33e perform, for example, MPCP as a process related to the multipoint MAC control sublayer, and control of sleep control of the ONU and transmission control of the uplink signal of the ONU 3 Etc. The MPCP control in the ONU 3 is performed by exchanging a control frame related to MPCP with the OLT 2 (hereinafter referred to as “MPCP control frame”).

  Note that the processing related to the multipoint MAC control sublayer performed by the downlink PON-MAC processing unit 33b and the uplink PON-MAC processing unit 33e can apply the same processing as the ONU in the existing 10GE-PON.

  Specific formats of MPCP control frames (for example, frames for sleep control) transmitted and received by the downlink PON-MAC processing unit 33b and the uplink PON-MAC processing unit 33e are described in Non-Patent Document 1 (IEEE802.3av, An extended MAC control frame described in Annex 31C) can be used.

  FIG. 3 is an explanatory diagram showing a format example of an MPCP control frame (a frame used also for sleep control) transmitted and received by the downlink PON-MAC processing unit 33b and the uplink PON-MAC processing unit 33e. FIG. 3 shows a frame configuration of an extended MAC control frame (extension MAC control).

  In the LSI 33, the CPU 35 monitors and grasps the contents of the MPCP control frame received by the downlink PON-MAC processing unit 33b via the MPCP termination unit 33g. The CPU 35 is connected to the upstream PON-MAC processing unit 33e via the MPCP insertion unit 33h, and issues an MPCP control frame transmission instruction to the OLT 2 via the MPCP insertion unit 33h.

  The upstream Bridge unit 33f and the downstream Bridge unit 33c perform communication control related to Ethernet of frames transmitted and received by the ONU 3, and include, for example, a buffer for frame transfer, VLAN-Tag addition deletion for VLAN identification, Address (MAC address, IP address, etc.) learning, priority processing, etc. are performed.

  The uplink Bridge unit 33f performs communication control related to the Ethernet for the uplink frame provided from the UNI 36, and delivers the frame to the uplink PON-MAC processing unit 33e. Further, the downlink Bridge unit 33 c performs communication control related to the Ethernet for the downlink frame given from the downlink PON-MAC processing unit 33 b, and delivers the frame to the UNI 36.

  In addition, about the process which concerns on Ethernet which the upstream Bridge part 33f and the downward Bridge part 33c perform, the process substantially the same as ONU in the existing 10GE-PON is applicable. However, the uplink Bridge unit 33f may temporarily hold the stored uplink frame in the buffer j without providing the uplink frame to the uplink PON-MAC processing unit 33e under the control of the CPU 35.

  The buffer j is a buffer unit that holds data of an upstream frame from the upstream Bridge unit 33f when the upstream frame data is provided. The buffer j delivers the held frame data to the upstream Bridge unit 33f under the control of the CPU 35.

  The upstream monitoring unit 33 i monitors upstream frame reception (frame reception from a lower-side network (not shown)) in the ONU 3 according to the control of the CPU 35. Here, the upstream monitoring unit 33i monitors the UNI 36 in the LSI 33, detects upstream frame reception, and supplies the detection result to the CPU 35. However, the method for detecting upstream frame reception is as follows. However, the present invention is not limited to this.

  Next, the configuration of sleep control (power saving control) in the ONU 3 will be described.

  The CPU 35 controls the ONU 3 to an active operation state (normal operation state) or a sleep operation state (power saving state) in accordance with an MPCP instruction or the like from the OLT 2.

  When the CPU 35 performs control to shift the ONU 3 from the active operation state to the sleep operation state, the CPU 35 operates at least with respect to the components that are sleep control targets (power saving control targets) in the LSI 33. Control to shift to the sleep operation state. In FIG. 1, components in a range surrounded by a broken line are illustrated as components for sleep control. That is, here, the components to be subjected to sleep control include the downlink PON-PCS processing unit 33a, the downlink PON-MAC processing unit 33b, the downlink Bridge unit 33c, the uplink PON-PCS processing unit 33d, and the uplink PON-MAC processing unit 33e. Assume that the MPCP termination unit 33g and the MPCP insertion unit 33h are targeted. In other words, in the LSI 33, the constituent elements excluding the constituent elements for buffering the frames in the upstream direction (the upstream bridge section 33f, the upstream monitoring section 33i, and the buffer 33j) are the constituent elements for sleep control.

  Specifically, the CPU 35 continues the reset state for each component of the sleep control target in the LSI 33, thereby causing each component of the sleep control target to operate in a sleep operation state in which the power is operated more efficiently than in the normal operation. To do.

  Next, an example of a specific configuration in which the CPU 35 resets each component of the sleep control target in the LSI 33 will be described.

  The LSI 33 is provided with a reset terminal (signal line) for resetting each component subject to sleep control, and these reset terminals are connected to the CPU 35. That is, the CPU 35 is configured to be able to control the component for sleep control to be reset through the above-described reset terminal.

  Each component that is subject to sleep control is in a reset state (operation stopped state) when a signal (hereinafter referred to as a “reset signal”) for controlling to a reset state is supplied from the CPU 35, and is in a normal operation state It becomes a state that is more power saving than.

  Then, in each of the components subject to sleep control, when a signal for releasing the reset state (hereinafter referred to as “reset release signal”) is supplied from the CPU 35 while the reset state is set, the reset state is started. Return to normal operation. In the LSI 33, the configuration in which the reset state is continued for each component subject to sleep control is not limited to the above-described example, and a configuration in which a part of a circuit configuring an existing semiconductor device is reset is applied. Can do.

  Here, a configuration for individually resetting each component to be controlled by sleep is described, but a circuit for resetting each component to be controlled by sleep is separately provided (inside the LSI 33 or externally). However, it may be controlled collectively.

  When the CPU 35 shifts each component to be controlled to sleep to the sleep operation state (reset state), a part of the data held by each component to be controlled (at least the operation of each component) Read all data (hereinafter referred to as “operation state data”). Then, the CPU 35 stores the operation state data read from each component in a predetermined storage unit (for example, a memory used when the CPU 35 executes a program). Note that it is natural that the CPU 35 does not need to hold the operation state data for the sleep control target components that do not have data to be held before the reset.

  Then, the CPU 35 holds at least before entering the reset state when shifting each sleep control target component from the sleep operation state (reset state) to the active operation state (reset is released). Operating state data is given to each component to be read. As described above, the CPU 35 causes each component subject to sleep control to return from the sleep operation state to the active operation state.

  Here, the process in which the CPU 35 reads the operation state data from each component of the LSI 33 and the process to read the operation state data are performed using the signal line for the above-described reset control. The method for exchanging the operation state data with the LSI 33 is not limited to this, and various methods can be used. For example, a separate data transmission terminal (bus) may be provided in the LSI 33 and the CPU 35.

  As for the details of the operation state data, it is only necessary to include the minimum necessary data in the operation after each component subject to sleep control is returned to the active operation state. For example, the operation is performed in an LSI mounted on an existing PON. Apply the necessary data. As described above, the ONU 3 corresponds to IEEE 802.3av here, and therefore, for example, the following item data needs to be included in the operation state data.

  For example, the data held by the uplink PON-MAC processing unit 33e includes information related to MPCP control (parameters related to MPCP control frames) described in Non-Patent Document 1. As information related to MPCP control held by the upstream PON-MAC processing unit 33e, for example, Discovery information (hereinafter referred to as “Discovery”) defined in “77.4.2 ONU speed-specific registration” of Non-Patent Document 1 is used. Information ”), information defined in“ 77.3.6.3 REGISTER_REQ description ”in Non-Patent Document 1 (hereinafter referred to as“ Register request information ”), and“ 77.3.6.4 REGISTER description ”in Non-Patent Document 1. Information defined (hereinafter referred to as “Register information”) and the like.

(A-2) Operation of the First Embodiment Next, operations of the OLT 2 and the ONU 3 (the power control method of the embodiment) in the optical communication network system 1 of the first embodiment having the above-described configuration will be described. .

  Here, first, an outline of processing of the ONU 3 and the OLT 2 will be described.

  In the ONU 3, when an MPCP control frame (MPCP control frame of a Request signal; hereinafter also referred to as “Request frame”) indicating that the sleep operation state may be set is given from the OLT 2, a process of shifting the ONU 3 to the sleep operation state is started. To do. Not only the above-mentioned Request frame but also the content of the MPCP control frame performed between the ONU 3 and the OLT 2 itself can be the same format as the existing 10GE-PON (Non-patent Document 1). it can.

  In the ONU 3, when a request frame is given from the OLT 2, the downstream PON-MAC processing unit 33b recognizes it, and further, the CPU 35 controls the control parameters (Discovery information, Register request information, Register information, etc.) inserted in the MPCP control frame. ) Is extracted.

  The ONU 3 shifts to the sleep operation state according to the sleep time (Sleep_Time; hereinafter referred to as “allocated sleep time”) notified by the Request frame from the OLT 2.

  Then, the CPU 35 obtains the operation state data from each component to be controlled by sleep, and then sends a reset signal to each component to be controlled by the LSI 33 so as to be reset.

  In the CPU 35, the elapsed sleep time (elapsed time since the reset state was started) is counted by the sleep timer 35a. Then, when the sleep timer 35a times out (allocation sleep time elapses), the CPU 35 sends a reset release signal to each sleep control target component that is in the reset state. Then, each component subject to sleep control that has received the reset release signal releases the reset state.

  Here, it is assumed that the operation state data held before reset is given to each component to be controlled by sleep together with the reset release signal, but the operation state after each component to be controlled by sleep is restarted by the reset release signal. Data may be given.

  Then, after restarting each component subject to sleep control, the CPU 35 asks the OLT 2 whether there is data destined for the device (downlink frame data) (MPCP control frame of the configuration signal; MPCP control frame; (Hereinafter also referred to as “Configuration frame”) is transmitted to the upstream PON-MAC processing unit 33e. When the OLT 2 receives the configuration frame, the OLT 2 checks whether the data addressed to the ONU 3 (downlink frame data) is buffered in its own device. Then, when data addressed to the ONU 3 is buffered, the OLT 2 transmits a frame of the data to the ONU 3. On the other hand, when the data addressed to the ONU 3 is not buffered, the OLT 2 transmits a request frame to the ONU 3 again. Then, the ONU 3 that has received the Request frame shifts to the sleep operation state again according to the notified allocated sleep time, as described above.

  When the ONU 3 receives an upstream frame from the lower network during the sleep operation state (when the upstream Bridge unit 33f receives the upstream frame), the ONU 3 gives the frame to the buffer 33j. To accumulate.

  Then, in the ONU 3, after returning from the sleep operation state to the active operation state (after the allocated sleep time has elapsed), information indicating that there is an upstream frame waiting for transmission to the OLT 2 (Discovery information, Register) An MPCP control frame (MPCP control frame of Report signal; hereinafter also referred to as “Report frame”) for notifying request information, Register information, etc.) is transmitted.

  Then, the OLT 2 returns an MPCP control frame (an MPCP control frame of the Grant signal (GATE_UP); hereinafter also referred to as “Grant frame”) that permits uplink frame transmission as a response to the notification (Report frame) from the ONU 3. . Then, the ONU 3 sends out the frames accumulated in the buffer 33j toward the OLT 2 at a timing according to the control of the OLT 2. Although the detailed description is omitted here, it is assumed that the timing at which the ONU 3 transmits a frame to the OLT 2 is a timing controlled by MPCP from the OLT 2.

  Next, a detailed operation when an upstream frame (traffic data) does not occur and when it occurs while the ONU 3 is in the sleep operation state will be described. Hereinafter, processing between the ONU 3-1 and the OLT 2 will be described, but the same operation is performed in the other ONUs 3, so description thereof will be omitted.

  First, an operation when an upstream frame is not generated while the ONU 3-1 is in the sleep operation state will be described with reference to the sequence diagram of FIG.

  First, it is assumed that the ONU 3-1 is in an active operation state, and a downstream frame (a frame in which user data is inserted) is transmitted from the ONU 3-1 to the OLT 2 (S101).

  Then, when there is no data to be transmitted to the ONU 3-1, the OLT 2 notifies the ONU 3-1 of a request frame indicating that the sleep operation state may be set during the allocated sleep time Ts (S102).

  Next, the ONU 3-1 transmits an MPCP control frame (ACK signal) for confirming that the sleep operation state is set to the OLT 2 (S103), and then the ONU 3-1 operates for the allocated sleep time Ts. It becomes a state.

  When the sleep operation state is canceled after the allocated sleep time Ts elapses, the ONU 3-1 transmits a confirmation frame to the OLT 2 and whether there is data destined for the own device (downlink frame data) in the OLT 2. (S104).

  When the OLT 2 receives the configuration frame from the ONU 3-1, the OLT 2 checks whether data addressed to the ONU 3-1 is buffered in its own device. Here, it is determined that the data addressed to the ONU 3-1 is not buffered (no data) in the OLT 2, and a request frame indicating that the sleep operation state may be set is again notified to the ONU 3-1 during the allocated sleep time Ts. (S105).

  Next, the ONU 3-1 transmits an MPCP control frame (ACK signal) that acknowledges that it is in the sleep operation state to the OLT (S106), and then the ONU 3-1 performs the sleep operation for the allocated sleep time Ts. It becomes a state.

  When the ONU 3-1 returns from the sleep operation state after the lapse of the allocated sleep time Ts, the ONU 3-1 transmits a confirmation frame to the OLT 2 and inquires of the OLT 2 whether there is data addressed to itself (S <b> 107).

  When the OLT 2 receives the configuration frame from the ONU 3-1, the OLT 2 checks whether the data addressed to the ONU 3-1 is buffered in its own device. This time, it is determined in the OLT 2 that the data addressed to the ONU 3-1 is buffered (data is present), and a request frame (notifying the allocated sleep time “0” to notify that the sleep operation state is to be stopped (not to be performed). "Request signal)" is transmitted to the ONU 3-1 (S108).

  Next, the ONU 3-1 transmits an MPCP control frame (ACK signal) of an acknowledgment to the OLT (S109), and then the ONU 3-1 waits in an active operation state for frame reception from the OLT 2.

  Then, the buffered data frame is transmitted from the OLT 2 to the ONU 3-1 (S110). The subsequent operation between the OLT 2 and the ONU 3-1 is the same as the operation from step S101 described above.

  Next, an operation when upstream traffic data is generated while the ONU 3-1 is in the sleep operation state will be described with reference to the sequence diagram of FIG.

  First, it is assumed that the OLT 2 and the ONU 3-1 perform the same operations (S201 to S206) as the above-described steps S101 to S106, and then the ONU 3-1 enters the sleep operation state.

  Then, the ONU 3-1 continues the sleep operation state during the allocated sleep time Ts. In this case, it is assumed that the upstream frame is received from the lower network (not shown) by the ONU 3-1 during the sleep operation state. As described above, in the ONU 3-1, when the upstream Bridge unit 33f receives this upstream frame during the sleep operation state, the data of this frame is temporarily stored in the buffer 33j.

  Then, when the sleep operation state is canceled and the active operation state is restored after the lapse of the allocated sleep time Ts, the ONU 3-1 transmits a report frame that notifies the OLT 2 that an upstream frame has occurred (S207). ).

  Then, a Grant frame (GATE_UP) for permitting upstream frame transmission is transmitted from the OLT 2 to the ONU 3-1 (S208).

  Next, the upstream frame stored in the buffer 33j is transmitted by the ONU 3-1 at a timing according to the control from the OLT 2 (S209).

  Next, further details of the processing inside the ONU 3 will be described.

  FIG. 6 shows the details of the processing in the ONU 3 with respect to the processing shown in the sequence diagrams shown in FIGS. 4 and 5 described above.

  First, during the allocated sleep time Ts from the OLT 2 to the ONU 3-1, a request frame indicating that the sleep operation state may be set is transmitted (S301), and detected by the downstream PON-MAC processing unit 33b of the ONU 3-1 (S302). Shall.

  Then, the CPU 35 collects and holds the operation state data from each component subject to sleep control (S303).

  Next, the CPU 35 stores the stored operation state data in a predetermined storage means (memory or the like) (S304), supplies a reset signal to each component to be controlled by sleep, Each component to be controlled is controlled to the reset state (S305), and the reset state is continued for the allocated sleep time Ts.

  During the allocated sleep time Ts, the CPU 35 controls the upstream monitoring unit 33i to monitor upstream frame reception (monitoring for the UNI 36) (S306). When the upstream monitoring unit 33i detects the reception of an upstream frame (S307), the upstream frame is provided from the upstream bridge unit 33f to the buffer 33j and stored (S308).

  Then, when the allocated sleep time Ts elapses (S309), the CPU 35 supplies the reset release signal and the operation state data acquired in step S303 described above to each sleep control target component, Control to release the reset state of the component is performed (S310).

  Then, the CPU 35 determines whether or not one or more upstream frames are accumulated in the buffer 33j (S311). If it is determined that the frames are accumulated, the operation starts from step S316 described later, and so on. Otherwise, the operation starts from step S312 described later.

  If it is determined in step S311 described above that no upstream frame is stored in the buffer 33j, the CPU 35 instructs the upstream PON-PCS processing unit 33d and there is no data addressed to the own device in the OLT 2. A confirmation frame for inquiring is sent (S312).

  Then, in the OLT 2 that has received the confirmation frame, it is confirmed whether or not the data addressed to the ONU 3-1 has been accumulated. If it is determined that the data has not been accumulated, the operation starts from the process of step S301 described above and is accumulated. If so, the operation starts from step S314 described later.

  In the above-described step S313, when it is confirmed that the data addressed to the ONU 3-1 is accumulated in the OLT 2, the frame of the data is transmitted from the OLT 2 to the ONU 3-1 (S314) and received by the ONU 3-1. (S315). The OLT 2 operates from the process of step S301 described above, and the ONU 3-1 operates from the process of step S302 described above.

  On the other hand, if it is determined in the above-described step S313 that the data addressed to the ONU 3-1 is not accumulated in the OLT 2, the OLT 2 operates from the processing in the above-described step S301. Although not shown in the flowchart, in this case, the ONU 3-1 also operates from the process of step S302 described above.

  If it is determined in step S311 described above that the upstream data is stored in the buffer 33j, the CPU 35 instructs the upstream PON-MAC processing unit 33e to transmit to the OLT 2 the transmission waiting state. A Report frame notifying information indicating that direction data exists is transmitted (S316).

  Then, the OLT 2 that has received the Report frame transmits a Grant frame permitting uplink frame transmission to the ONU 3-1 (S317).

  In the ONU 3-1, the grant frame is received by the downstream PON-MAC processing unit 33 b, and the grant frame is acquired by the CPU 35. Then, the CPU 35 instructs the upstream PON-MAC processing unit 33e to transmit the upstream frame stored in the buffer 33j (S318, S319), and receives (transfers to the upper network) by the OLT 2 (S320).

  Thereafter, when the data transmission in step S319 ends, the ONU 3-1 operates from the processing in step S302 described above. Here, the ONU 3-1 may be operated from the above-described step S 312, and if there is downstream data from the OLT 2, the data frame may be received. Further, it is assumed that the OLT 2 operates from the process of step S301 described above when the data reception process of step S320 described above is completed.

(A-3) Effects of First Embodiment According to the first embodiment, the following effects can be achieved.

  In the ONU 3, the LSI 33 is put into the sleep operation state (by setting the sleep control target components other than the configuration in which the LSI 33 holds the frame in the upstream direction (uplink Bridge unit 33 f, uplink monitoring unit 33 i, buffer 33 j). (Power saving operation state). Thereby, in the ONU 3, the power consumption of the LSI 33 is reduced.

  In the prior art, since the sleep operation state is controlled by controlling the power supply itself to the LSI, the configuration (the power-up sequence, etc.) when returning from the sleep operation state to the active operation state is complicated. On the other hand, in the ONU 3 of the first embodiment, as described above, the LSI 33 is set in the sleep operation state by setting the components to be controlled to sleep, so that the LSI 33 is returned from the sleep operation state. Therefore, it is only necessary to release the reset state of the sleep control target component and supply the operation state data, and it is possible to easily speed up the return from the sleep operation state to the active operation state.

  In the first embodiment, the configuration (uplink Bridge unit 33f, uplink monitoring unit 33i, and buffer 33j) that holds an upstream frame even in the sleep operation state is excluded from the sleep control targets. As a result, even if an upstream frame is generated in the sleep operation state, the ONU 3 can transmit after returning to the active operation state, so that communication quality can be maintained.

(B) Second Embodiment Hereinafter, a second embodiment of the slave station communication device and the power control method according to the present invention will be described in detail with reference to the drawings. Note that the slave station communication device of the second embodiment is an ONU.

  The optical communication network system 1A of the second embodiment can also be described with reference to FIG. In FIG. 2, the reference numerals in parentheses are used only in the second embodiment. Hereinafter, the difference between the second embodiment and the first embodiment will be described.

  The optical communication network system 1A is different from the first embodiment in that each ONU 3 is replaced with an ONU 3A.

  Next, the configuration of the ONU 3A will be described.

  FIG. 7 is a block diagram showing a functional configuration of the ONU 3A.

  The ONU 3A is different from the first embodiment in that the LSI 33 is replaced with the LSI 33A. The LSI 33A is different from the first embodiment in that a setting holding register 33k is added.

  In the first embodiment, the CPU 35 collects and holds operation state data from each component before resetting each component to be subjected to sleep control, and when reset is released (when returning to the active operation state), The operation state data held was supplied to each component and read.

  On the other hand, in the second embodiment, when a reset signal is supplied from the CPU 35, each component subject to sleep control stores the operation state data in the setting holding register 33k, and then the reset state. Become. Then, when a reset release signal is supplied from the CPU 35, each component subject to sleep control reads the operation state data stored in the setting holding register 33k, registers it in itself, and returns from the reset state.

  The setting holding register 33k is a storage means (memory) for storing operation state data on the LSI 33A, and its configuration is not limited. Here, since the setting holding register 33k is a component for sleep control, it is desirable to apply a memory (non-volatile memory) in which the stored content does not volatilize even when it is in the reset state. In FIG. 7, the setting holding register 33k is illustrated as a component subject to sleep control, but may be excluded.

  As a result, in the ONU 3A of the second embodiment, the CPU 35 performs operation state data from each sleep control target component when performing a process for resetting each sleep control target component or a process for canceling the reset state. It is easy to perform high-speed processing because only processing in the LSI 33A is required without performing processing for reading and supplying data.

(C) Other Embodiments The present invention is not limited to the above-described embodiments, and may include modified embodiments as exemplified below.

(C-1) In each of the above embodiments, the ONU and the optical communication network system have been described as having a configuration conforming to 10GE-PON (802.3av). However, other PON standards and formats have been adopted. You may make it replace with a thing.

(C-2) In each of the above embodiments, on the ONU, the communication control means related to the PON is configured by a circuit (communication control circuit) using one LSI (semiconductor device). (Semiconductor device) or a circuit (communication control circuit) in which other elements (for example, a resistor, a capacitor, etc.) are combined may be used. Even in this case, the functional configuration of the above-described LSI can be shown as in FIG. 1 or FIG.

(C-3) In each of the above embodiments, sleep control (power saving control) of an LSI that performs communication control related to the PON mounted on the ONU has been described. At the same time, components other than the LSI (for example, an optical transceiver, The SerDes processing unit or the like) may be in the sleep operation state (power saving operation state).

(C-4) In each of the above embodiments, in the LSI, the components other than the configuration (uplink Bridge unit, uplink monitoring unit, buffer) that holds the uplink frame are the sleep control targets. You may make it exclude a part of component used as sleep control object in a form. That is, in the LSI, the combination of the components to be subjected to sleep control is not limited except for the configuration that holds the frame in the uplink direction (uplink Bridge unit, uplink monitoring unit, buffer).

  For example, you may make it exclude the thing which needs to acquire operation state data from sleep control object in each said embodiment from sleep control object. As a result, when the sleep control target is set to the reset state or when the reset is canceled, it is not necessary to perform processing related to the operation state data, so that the sleep control can be performed at higher speed in the ONU.

(C-5) In each of the above-described embodiments, the upstream Bridge section and the buffer are described as separate components, but may be mounted inside the upstream Bridge section.

(C-6) In each of the above embodiments, the ONU has been described as an example of a sleep operation state in accordance with an instruction (Request frame) from the OLT. However, the ONU voluntarily requests the OLT to enter the sleep operation state. You may make it do.

  DESCRIPTION OF SYMBOLS 1 ... Optical communication network system, 2 ... OLT 3, 3-1 to 3-n ... ONU, 31 ... Optical transceiver, 32 ... SerDes processing part, 33 ... LSI, 33a ... Downstream PON-PCS processing part, 33b ... Downstream PON-MAC processing unit, 33c ... downlink bridge unit, 33d ... uplink PON-PCS processing unit, 33e ... uplink PON-MAC processing unit, 33f ... uplink bridge unit, 33g ... MPCP termination unit, 33h ... MPCP insertion unit, 33i ... Uplink monitoring unit, 33j ... buffer, 34 ... power supply unit, 35 ... CPU, 35a ... sleep timer, 36 ... UNI, 4 ... optical fiber, 5 ... optical splitter.

Claims (3)

Connect the master station communication device and PON, in Turkey station communication device is housed under the master station communication device,
Communication control means for performing communication control processing of the slave station communication device using a communication control circuit ,
The communication control circuit is at least
A downlink frame holding unit that performs processing to hold a frame in the downlink direction from the master station side network to which the master station communication device is connected;
An uplink frame holding unit that performs processing to hold an uplink frame from the slave station side network accommodated by the slave station communication device;
An operation state data storage register for storing operation state data relating to the operation state of the components on the communication control circuit;
In the downlink frame holding unit, triggered by the control frame containing a parameter of the sleep time information relating to the sleep control is detected on the communication control circuit, among the portion excluding the uplink frame holding section, one A power saving control means for causing the communication control circuit to operate with lower power consumption than in a normal operation state by setting a part or all of the power saving target processing parts to a reset state ;
In the communication control circuit, before the circuit of the part to be reset by the power saving control means enters the reset state, the operation state data relating to the operation state of the circuit of the part autonomously is stored in the operation state data storage register. When the circuit of the part to be reset by the power saving control means returns from the reset state, it autonomously reads the operation state data stored in the operation state data storage register. Start an operation based on the operation state data
A slave station communication device.   The communication control circuit, when the slave station communication device returns from the power saving state, if the uplink frame holding unit holds one or more uplink frames, The slave station communication apparatus according to claim 1, wherein a process of transmitting to the master station communication apparatus is performed. Connect the master station communication device and PON, the power control method is housed under the master station communication device benzalkonium station communication apparatus,
The slave station communication device includes communication control means for performing communication control processing of the slave station communication device using a communication control circuit,
The communication control circuit is at least
A downlink frame holding unit that performs processing to hold a frame in the downlink direction from the master station side network to which the master station communication device is connected;
An uplink frame holding unit that performs processing to hold an uplink frame from the slave station side network accommodated by the slave station communication device;
An operation state data storage register for storing operation state data relating to the operation state of the components on the communication control circuit;
The power saving control means is configured to trigger the uplink frame holding unit on the communication control circuit when the downlink frame holding unit detects a control frame including a parameter of sleep time information related to sleep control. By setting a part or all of the power saving target processing part to the reset state, the communication control circuit is operated with lower power consumption than the normal operation state.
In the communication control circuit, before the circuit of the part to be reset by the power saving control means enters the reset state, the operation state data relating to the operation state of the circuit of the part autonomously is stored in the operation state data storage register. When the circuit of the part to be reset by the power saving control means returns from the reset state, it autonomously reads the operation state data stored in the operation state data storage register. A power control method characterized by starting an operation based on the operation state data .

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