JP5631022B2 - Processing device, processing allocation method, and program - Google Patents

Description

  The present invention relates to a processing apparatus capable of executing a plurality of processes in a time division manner.

  Conventionally, there is a data processing device that executes a program execution unit called a task in parallel and provides a plurality of functions (for example, Patent Document 1 and Patent Document 2). When the number of CPUs is one, the CPU executes a plurality of tasks in a time division manner, so that the number of tasks executed by the CPU per unit time decreases as the number of tasks increases. As a result, the time required for processing performed by one task becomes long.

JP 2005-301890 A JP 2007-149001 A

  There is a method of increasing the number of tasks executed per unit time by executing a plurality of tasks physically in parallel using a multi-core processor in which a plurality of CPU cores are mounted on a plurality of CPUs or a single package. .

  However, even in this method, when there are a large number of tasks exceeding the number of CPUs, each of the plurality of CPUs executes a plurality of tasks in a time-sharing manner, as in the case of one CPU. For this reason, the time required for processing performed in one task may be increased.

  Depending on the type of data processing apparatus, there is a case where it is desired to avoid a long time for processing performed in a specific task. For example, in a printing apparatus that executes printing based on a print job, if it takes time to generate image data from the print job, it takes time to print out. Therefore, in order to prevent the time required for the process of generating image data from the print job from increasing, it is desired to use the CPU for a longer time for the task of generating image data from the print job, even when there are many tasks.

  In order to solve such a problem, an object of the present invention is to allow more specific processes to be executed without completely stopping the execution of other processes.

A processing apparatus according to the present invention executes a first processing means capable of executing a plurality of processes in a time division, a second processing means capable of executing a plurality of processes in a time division, and And assigning means for allocating the processing to be performed to each of the first processing means and the second processing means, and when the processing to be executed is a predetermined specific process, already a process that is assigned to a processing unit and assigned directly to the second processing means, allocating the specific processing to the first processing means, in the specific process until the particular processing is completed It is characterized by restricting newly assigning no processing to the first processing means .

The allocation method according to the present invention includes a first processing unit capable of executing a plurality of processes in time division and a second processing unit capable of executing a plurality of processes in time division. If the process to be executed is a predetermined specific process, the process already assigned to the first processing means is assigned to the second processing means. If the first allocating step to reassign, to be executed process is the particular process, have a second allocation step of allocating the specific processing to the first processing means, the specific processing It is characterized in that it is limited to newly assign a process that is not the specific process to the first processing means until the process is completed .

The program according to the present invention includes a first processing unit capable of executing a plurality of processes in time division and a second processing unit capable of executing a plurality of processes in time division. If the process to be executed is a computer-readable program that assigns a process to be executed and the process to be executed is a predetermined specific process, the process already assigned to the first processing means is assigned to the second process. A first assigning step for reassigning to the processing means, and a second assigning step for assigning the specific process to the first processing means if the process to be executed is the specific process. And restricting newly assigning a process that is not the specific process to the first processing means until the specific process is completed .

  According to the present invention, in a processing apparatus having a plurality of processing means capable of executing a plurality of processes in a time division manner, more specific processes are executed without completely stopping the execution of other processes. Can be able to.

It is a figure which shows the internal structure of a data processor. It is a conceptual diagram for demonstrating task processing. It is a figure which shows an example of task information. It is a flowchart which shows a task input process. It is a flowchart which shows a task schedule process. It is a figure which shows an example of an internal structure of a multi-core CPU.

  Embodiments according to the present invention will be described.

  FIG. 1 is a diagram showing an internal configuration of a data processing apparatus to which the present invention can be applied. The data processing apparatus is roughly composed of a main board 100 and a sub board 108. Although it is possible to make them one board without dividing the main board and sub board, in the following, the case where the data processing device is composed of two boards, the main board 100 and the sub board 108, will be described. explain.

  The main board 100 includes a CPU 101, a nonvolatile memory 102, a volatile memory 103, a bus controller 104, a disk controller 105, and a USB controller 106.

  The CPU 101 is an arithmetic device that executes a startup program and other programs. The CPU 101 is configured as a multiprocessor composed of a plurality of chips or as a multicore processor in which a plurality of arithmetic devices are incorporated in a single chip. In FIG. 1, CPU # 1 and CPU # 2 are used. If the OS can handle a plurality of CPUs, a plurality of single CPUs may be prepared separately. In the following, each of the plurality of CPU cores is also referred to as a CPU.

  A non-volatile memory (BOOT ROM) 102 stores a boot program and an OS (operating system). The OS may be stored in the hard disk device 107 described later. A volatile memory 103 temporarily stores programs and data.

  A bus controller 104 is connected to the sub board 108 and controls communication with the sub board 108. A disk controller (Disk Controller) 105 controls a hard disk device (HDD) 107. The hard disk device 107 stores various application programs and various data, and the disk controller 105 controls writing and reading thereof. A USB controller 106 controls a USB device (not shown) such as a USB memory.

  The sub board 108 includes a nonvolatile memory 109, a CPU 110, a volatile memory 111, a bus controller 112, a device controller 113, and an image processor 114.

  A non-volatile memory (BOOT ROM) 109 stores a startup program. The CPU 110 is an arithmetic device that executes a startup program and other programs. Volatile memory 111 temporarily stores programs and data.

  A bus controller (Bus Controller) 112 is connected to the main board 100 and controls communication with the main board 100. A device controller (Device Controller) 113 controls the image processing device and causes the image processing device to execute different image processing. In FIG. 1, a scanning device 115, a printing device 116, and a facsimile device 117 are connected to the device controller 113 as image processing devices. An image processor 114 executes image forming processing such as image data generation at high speed.

  FIG. 2 is a conceptual diagram for explaining a task (program execution unit) execution process performed by the CPU 101.

  In an OS (multitask OS) capable of executing a plurality of processes in parallel at the same time, a multitask operation is realized by repeating control for occupying the CPU with one task for a specified time called a time slice. That is, the CPU executes one task for a specified time and executes a plurality of tasks in a time division manner. This is called multitask scheduling.

  In FIG. 2, the network task 202 is currently being executed in the CPU # 1 (201), and the storage task 205 is currently being executed in the CPU # 2 (204).

  The task scheduler 207, which is a part of the OS, saves the execution state of the network task 202 currently being executed in the execution queue 203 as task information due to the progress of time slices or the occurrence of an interrupt. That is, the task information of the network task in the execution queue 203 is updated with the register value of the CPU. On the other hand, the task information of the UI control task in the execution queue 203 is set in the CPU # 1, and the UI control task is executed by the CPU # 1. Similarly, the task scheduler 207 saves the execution state of the currently executing storage task 205 in the task information of the execution queue 206 due to the progress of the time slice or the occurrence of an interrupt. That is, the task information of the storage task in the execution queue 206 is updated with the register value of the CPU. On the other hand, the task information of the scan task in the execution queue 206 is set in the CPU # 2, and the scan task is executed by the CPU # 2. Such switching of task execution in the CPU is called a task switch. Details of the task information will be described later (FIG. 4).

  There is only one task scheduler 207 as a program, but there are two logically by being executed independently by each of CPU # 1 and CPU # 2. Therefore, task scheduler # 1 controls task scheduling in CPU # 1, and task scheduler # 2 controls task scheduling in CPU # 2.

  In such multitask scheduling, assuming that all tasks use up the time slice completely, one task is executed by the CPU as the number of tasks placed in the execution queue increases. After that, the time until the next execution becomes longer.

  For example, the PDL processing task develops a print job received from the information processing apparatus via a local area network (LAN) or the like into image data, and transmits the image data to the CPU 110 of the sub board 108. Thereafter, the printing device 116 prints an image based on the image data on a paper medium under the control of the CPU 110, the image processor 114, and the device controller 113. As the number of tasks placed in the execution queue 206 increases, the number of times (or time) that the PDL processing task can occupy the CPU # 2 per unit time decreases, so the PDL processing task expands the print job into image data. It takes longer to do. Then, the PPM value (Page Per Minute: the number of printed pages per minute), which is one of the performance indexes of the data processing apparatus, may decrease.

  The occupation task 208 in FIG. 2 will be described later.

  FIG. 3 is a diagram illustrating an example of task information of tasks arranged in the execution queue 203 or 206. Task information as shown in FIG. 3 exists for each of a plurality of tasks.

  The task ID 301 is an identifier that uniquely identifies the task. Task state 302 indicates the state of the task. The code / address list 303 shows a memory address group in which the execution code of the task itself is arranged. The data address list 304 shows a memory address group in which data used by the task is arranged. Register information 305 indicates the register value of the CPU when the task is being executed.

  The task scheduler 207 executes task switching by referring to the task information arranged in the execution queue 203 or 206 and setting or operating the CPU register value or the like.

  Below, the task control processing performed in the main board 100 is demonstrated, referring the flowchart of FIG.4 and FIG.5.

  FIG. 4 is a flowchart showing a task input process executed by the task scheduler 207 when the main board 100 has two CPUs, CPU # 1 and CPU # 2. Here, the task scheduler 207 assigns a task to be executed to either the CPU # 1 or the CPU # 2.

  First, the task scheduler 207 determines whether or not the task is an occupied task when the task is submitted to execute a certain task (S401).

  The occupied task is a task that can continuously occupy the CPU. A CPU that is occupied by an occupied task is called an occupied CPU. It is possible to specify which task is to be an exclusive task or which CPU is to be an exclusive CPU. The specified task is registered as an exclusive task, and the specified CPU is registered as an exclusive CPU. In the example of FIG. 2, the PDL processing task is an occupied task and CPU # 2 is an occupied CPU.

  If the task is an exclusive task, the task scheduler 207 updates the task information in the execution queue 206 for the task being executed by the CPU # 2. Furthermore, the task information of each task arranged in the execution queue 206 of CPU # 2 is moved to the execution queue 203 of CPU # 1, which is another CPU (S402). In the example of FIG. 2, the task information of each of the storage task, scan task, fax task, and print task is moved from the execution queue 206 to the execution queue 203.

  Next, the task scheduler 207 places task information of the PDL processing task, which is an exclusive task, in the execution queue 206 of the CPU # 2 (S403). Further, the task scheduler 207 sets the exclusive task operation mode flag to 1 (S404). This exclusive task operation mode flag is stored in the volatile memory 103, and its initial value is 0 (zero).

  If it is determined in S401 that the task is not an exclusive task, the task scheduler 207 determines whether the exclusive task operation mode flag is 1 (S405). If the occupied task operation mode flag is 1, the occupied task occupies CPU # 2, so the task scheduler 207 places task information of the task in the execution queue 203 of CPU # 1 (S406). If the occupied task operation mode flag is not 1, since neither CPU is occupied by the occupied task, the task scheduler 207 places the task information of the task in the execution queue with the fewer waiting tasks ( S407). When the number of tasks waiting for execution is the same between the execution queue 203 and the execution queue 206, the task scheduler 207 arranges task information of the task in the execution queue 203 of the CPU # 1 that is not the exclusive CPU. And However, the present invention is not limited to this.

  FIG. 5 is a flowchart showing task schedule processing executed by the task scheduler 207. In the task schedule processing, the task scheduler 207 selects one task from the execution queue at each CPU, and performs task scheduling for causing the CPU to execute the task during a time slice.

  The task scheduler 207 determines whether the processing of the task currently being executed by the CPU is completed (S501). When the processing of the task is completed, the task scheduler 207 deletes the task information of the task from the execution queue (S502). Further, the task scheduler 207 determines whether the task is an exclusive task (S503). If the task is an exclusive task, the task scheduler 207 sets the exclusive task operation mode flag to 0 (zero) (S504).

  If it is determined in S501 that the task processing has not been completed, the task scheduler 207 determines whether or not the time slice has ended (step S505). Whether the time slicing has ended can be determined by decrementing the counter whose initial value is the specified time, whether the counter has reached 0, or by measuring the time with a hardware timer. It may be determined whether time has passed.

  If the time slice has not ended, the task can use the CPU, and the task scheduler 207 causes the CPU to execute the task (S508).

  On the other hand, if the time slice has been completed, the task scheduler 207 determines that the CPU has used up the CPU for a specified time, and stores the current CPU register value and the like as task information in the execution queue. (S506). Further, in order to cause the CPU to execute a new task, the task scheduler 207 selects one task from the execution queue and sets task information of the task as a register value of the CPU (S507). Then, the task scheduler 207 causes the CPU to execute the task (S508).

  When the task scheduler 207 starts executing a task registered as an exclusive task, the task information of the task placed in the execution queue of the CPU designated as the exclusive CPU is awaited to be executed by another CPU. You can move to the matrix. At that time, by setting the exclusive task operation mode flag to 1, other tasks are assigned to other CPUs without being assigned to the exclusive CPU, and the exclusive tasks are assigned until the task processing is completed. Is always feasible. Therefore, desired execution performance can be realized.

  When the processing of the dedicated task is completed, the dedicated task operation mode flag is set to 0 (zero), and thereafter, the task can be allocated to the CPU with fewer tasks waiting to be executed. The load is leveled.

  FIG. 6 is a diagram illustrating an example of the internal configuration of the multi-core CPU. FIG. 6A shows a format in which a plurality of CPUs share the L2 cache. FIG. 6B shows a format for separating the L2 cache for each of a plurality of CPUs.

  In this embodiment, a specific task is executed by a specific CPU by moving task information from the execution queue of the specific CPU to the execution queue of the other CPU. Therefore, if the execution queue is constructed on the L2 cache and the L2 cache can be shared by a plurality of CPUs (in the form shown in FIG. 6A), the other CPU can access the task information at a relatively high speed. It is. On the other hand, when a plurality of CPUs each have an L2 cache (the form shown in FIG. 6B), the movement that has not been written to the memory yet to be used by this CPU in the L2 cache on the specific CPU side. There is task information that should be done. Even if it is attempted to refer to the moved task information, the task information is not stored in the L2 cache on the other CPU side. Therefore, access may be delayed. For this reason, it is desirable to suppress the delay of access to the task information by the other CPU by flushing the L2 cache prior to moving the task information and confirming the writing of data from the L2 cache to the memory. . Conversely, when the L2 cache is shared, the other CPU can refer to the task information in the L2 cache, so it is desirable not to flush the L2 cache when the task information is moved.

  As described above, according to the present embodiment, a task that continuously occupies a CPU core or CPU is registered in advance as an occupancy task. When the execution of the dedicated task is started, the dedicated task is executed by a specific CPU core or a specific CPU, and other tasks are controlled to be executed by another CPU core or another CPU. When the processing of the occupied task is completed, other tasks can be executed by a specific CPU core or a specific CPU. By doing this, even when a plurality of tasks are executed in parallel by the CPU, a specific task is preferentially executed and a predetermined performance in the data processing device (for example, a performance presented in a product catalog etc.) ) Can be realized.

[Second Embodiment]
In the above embodiment, when the execution of a task registered as an exclusive task is started, the task information of another task is moved to the execution queue of another CPU. However, if the occupied task enters a state of waiting for an event from another task (event waiting state) after the dedicated task is input, no further processing is performed until an event notification is received from the other task. In this case, although the dedicated task does not need to monopolize the dedicated CPU, other tasks cannot use the dedicated CPU. This reduces the CPU utilization efficiency.

  For example, when the PDL processing task is an exclusive task and the PDL processing task is waiting for a job arrival event indicating that a print job has been received from the job management task, the PDL processing task does not perform processing. .

  In order to deal with such a problem, a counter that counts the number of times the occupied task is executed per unit time may be provided. This count value is stored in the volatile memory 103.

  When the task scheduler 207 determines in S401 that the task is an exclusive task, the task scheduler 207 starts counting the number of executions of the exclusive task per unit time. While the count value is below the first threshold (for example, 5 times), the task information of other tasks arranged in the execution queue of the dedicated CPU is not moved to the execution queue of the other CPU. That is, the task information of other tasks is not moved, but the other tasks are executed by the dedicated CPU until the processing of the occupied tasks starts in earnest. The first threshold can be designated as appropriate.

  According to the second embodiment, the number of executions of the occupied task per unit time is measured, and while this is less than the number of times designated in advance, the task information of tasks other than the occupied task is awaited to be executed by another CPU. Do not move to the queue. For example, until the PDL processing task receives the print job and starts developing the image data, other tasks can be executed by the dedicated CPU. By doing so, it is possible to prevent the CPU utilization efficiency from being lowered.

  As long as the frequency of execution of the occupied task per unit time is measured, the execution time per unit time may be used in addition to the number of executions per unit time.

[Third Embodiment]
In the above embodiment, since all tasks other than the dedicated task are assigned to the CPU # 1, the load on the CPU # 1 becomes large when a large number of tasks are operating in parallel. For example, if the processing of a task that needs to promptly receive an instruction from the user and promptly display information necessary for the instruction, such as a UI control task that controls the local UI, is delayed. Will drop significantly.

  In order to deal with such a problem, a counter that counts the number of executions of a specific task other than the occupied task per unit time may be provided. This count value is stored in the volatile memory 103.

  If a specific task other than the exclusive task is a UI control task, the task scheduler 207 counts the number of executions per unit time of the UI control task in response to determining in S401 that the task is a UI control task. Begin to. When the count value falls below a second threshold value (for example, 3 times), 0 (zero) is set in the occupied task operation mode flag in order to release the occupied task operation mode. In this way, when the operation of tasks other than the dedicated task becomes too slow, other tasks can be executed by the dedicated CPU. The second threshold can be designated as appropriate.

  Note that there are cases where you want to print at high speed even if the operability temporarily declines, so you can select whether to activate the function to release the exclusive task operation mode based on the second threshold. It is desirable to configure.

  Moreover, as long as the frequency of execution per unit time of the UI control task is measured, the number of executions per unit time or the execution time per unit time may be used.

  According to the third embodiment, the number of executions per unit time of a specific task other than the occupied task is measured, and the occupied task operation mode is canceled when the number of executions falls below a predetermined number. By doing so, it is possible to prevent, for example, the operability from being significantly lowered.

[Other Embodiments]
In the above embodiment, the case where there are two CPU cores or CPUs has been described. However, the present invention is applicable even when there are three or more CPU cores or CPUs.

  The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

100 main board 101 CPU
102 Nonvolatile Memory 103 Volatile Memory 104 Bus Controller 105 Disk Controller 106 USB Controller 107 Hard Disk Device 108 Subboard 109 Nonvolatile Memory 110 CPU
111 Volatile Memory 112 Bus Controller 113 Device Controller 114 Image Processor 115 Scanning Device 116 Printing Device 117 Facsimile Device

Claims (12)

A first processing means capable of executing a plurality of processes in a time-sharing manner;
A second processing means capable of executing a plurality of processes in a time-sharing manner;
The processing to be executed and a assigning means for assigning to each of said second processing means and the first processing means,
If processing to be executed is a specific processing determined in advance, the allocation means, the already assigned process to the first processing means is assigned directly to the second processing unit, the specific processing Is assigned to the first processing means, and the processing apparatus is restricted from newly assigning a process that is not the specific process to the first processing means until the specific process is completed .   The processing apparatus according to claim 1, further comprising registration means for registering at least one process as the specific process.   3. The processing apparatus according to claim 1, wherein, when the specific process ends, the assigning unit can assign a process that is not the specific process to the first processing unit. 4. Measuring means for measuring the execution frequency per unit time of the specific process;
When the process to be executed is the specific process and the execution frequency measured by the measuring unit exceeds a predetermined value, the allocating unit is already allocated to the first processing unit. operation being a processing device according to any one of claims 1 to 3, wherein the assigned scores directly to the second processing means. A second measuring unit that measures an execution frequency per unit time of the process that is not the specific process;
When the execution frequency measured by the second measuring unit is less than a second predetermined value, the allocating unit can allocate a process that is not the specific process to the first processing unit. The processing apparatus according to claim 1, wherein the processing apparatus is characterized.   Select whether or not to activate a function that allows a process other than the specific process to be assigned to the first processing means when the execution frequency measured by the second measuring means falls below a second predetermined value. 6. The processing apparatus according to claim 5, further comprising selection means for enabling. An execution queue for processing to be executed by the first processing means and a queue for processing to be executed by the second processing means;
7. The apparatus according to claim 1, wherein the allocating unit moves a process queued in the execution queue of the first processing unit to a queue of the second processing unit. 8. Processing equipment. The first processing means and the second processing means are CPUs capable of executing a plurality of tasks as program execution units in a time-sharing manner,
The processing apparatus according to claim 1, wherein the processing executed by the first processing unit and the second processing unit is processing performed by a task. The processing device according to claim 1, wherein the assigning unit determines whether or not a process to be executed is the specific process. When the process to be executed is the specific process, the assigning unit sets a process that is not the specific process to a mode that is not assigned to the first processing unit, and when the specific process is completed, The processing apparatus according to claim 1, wherein the mode is canceled. An allocation method for allocating a process to be executed to each of a first processing means capable of executing a plurality of processes in a time-sharing manner and a second processing means capable of executing a plurality of processes in a time-sharing manner. There,
A first assigning step for reassigning a process already assigned to the first processing means to the second processing means when the process to be executed is a predetermined specific process;
If processing to be executed is the particular process, it has a second allocation step of allocating the specific processing to the first processing means,
An assignment method characterized by restricting the assignment of a process that is not the specific process to the first processing means until the specific process is completed . By assigning a process to be executed to each of a first processing means capable of executing a plurality of processes in a time division and a second processing means capable of executing a plurality of processes in a time division, by a computer A readable program,
A first assigning step for reassigning a process already assigned to the first processing means to the second processing means when the process to be executed is a predetermined specific process;
When the process to be executed is the specific process, the computer is caused to execute a second assignment step of assigning the specific process to the first processing unit ,
A program for restricting newly assigning a process that is not the specific process to the first processing means until the specific process is completed .

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