JP5630352B2 - Register arrangement optimization method, register arrangement optimization program, and register arrangement optimization apparatus - Google Patents

Description

  The present invention relates to a technology for speeding up a data processing apparatus.

  A data processing apparatus such as an image encoding apparatus is required to operate at high speed. Therefore, in a program executed by the processor of such a data processing apparatus, the processing speed is increased as follows in order to satisfy the target performance. For example, processing is optimized (tuning work) by assigning (arranging) frequently used variables or variables whose reuse timing is close in time to a register, thereby speeding up the processing. On the other hand, although there is a difference for each processor, there is a limit to the number of registers that can be used. Therefore, variables that cannot be placed in registers are placed in a memory having a slower access speed than the registers.

The following techniques are known as techniques relating to high-speed processing.
For example, in the instruction transmission path from the instruction fetch unit of the processor to the decode unit, when the instruction fetched by the instruction fetch unit is a byte code, it is supplied to the byte code accelerator and converted into a native code, and output to the subsequent stage There is technology that has been made to do.

  Further, for example, in the program conversion apparatus, the setting of the value in the source program, the analysis of the reference position, etc. are performed, and hardware resources such as a register and a memory are allocated to each variable based on the analysis result. There is a technology.

JP 2005-44336 A JP-A-11-175351

  As described above, the technique for optimizing the processing by allocating a frequently used variable or a variable whose reuse timing is close in time to the register to increase the speed has the following problems.

  In a program, for example, a function in which different processing is performed according to input data, such as branch processing, the processing route is different according to input data. In this case, a variable that is frequently used or a variable whose reuse timing is close in time also varies depending on the processing route. Therefore, in the above technique, the process is optimized based on the process route corresponding to the average input data. However, in this case, if the input data changes and the processing route is different, variables that are frequently used and variables that are close in time to reuse will also differ. There is a risk of lowering.

  In view of the above circumstances, the present invention has an object to provide a register arrangement optimization method, a register arrangement optimization program, and a register arrangement optimization apparatus capable of speeding up processing even when input data changes. And

  According to one aspect of the method, a method is provided for optimizing variables placed in a register in a processor including a processor core that executes instruction code and a register. In this method, a variable table defined in a function in the program is referred to and a conversion table including information on the frequency of use is referenced. Based on the information on the frequency of use of the variable, a variable with a high frequency of use is given priority. The placement destination of the variable is determined in the register or the memory so as to be placed in the register. The determined variable placement destination is reflected in the variable placement destination information included in the conversion table. Based on the information on the variable placement destination included in the conversion table, the pseudo instruction code in which the operand placement destination of the operation instruction is not specified is converted into an instruction code executable by the processor core. Information on the frequency of use of variables included in the conversion table is updated according to the variables used when the processor core executes the converted instruction code.

  According to one aspect of the program, there is provided a program that optimizes variables arranged in a register in a processor including a processor core that executes an instruction code and a register. This program causes a computer to execute the following processing. By referring to the conversion table that contains information on the variable location and usage frequency defined in the functions in the program, the frequently used variable is preferentially allocated to the register based on the usage frequency information of that variable. As described above, the placement destination of the variable is determined in the register or the memory. The determined variable placement destination is reflected in the variable placement destination information included in the conversion table. Based on the information on the variable placement destination included in the conversion table, the pseudo instruction code in which the operand placement destination of the operation instruction is not specified is converted into an instruction code executable by the processor core. Information on the frequency of use of variables included in the conversion table is updated according to the variables used when the processor core executes the converted instruction code.

  According to one aspect of the apparatus, there is provided an apparatus for optimizing a variable arranged in a register in a processor including a processor core that executes an instruction code and a register. This apparatus includes a conversion table and an instruction conversion unit. The conversion table includes information on the location and frequency of use of variables defined in the functions in the program. The instruction conversion unit converts the pseudo instruction code in which the operand placement destination of the operation instruction is not specified into an instruction code that can be executed by the processor core, based on the information on the placement destination of the variable included in the conversion table. Further, the instruction conversion unit determines the variable placement destination in the register or the memory so that the frequently used variable is preferentially placed in the register based on the use frequency information of the variable included in the conversion table. . Further, the determined variable placement destination is reflected in the variable placement destination information included in the conversion table. In addition, the variable usage frequency information included in the conversion table is updated according to the variable used when the processor core executes the converted instruction code.

  The disclosed method, program, and apparatus have an effect that the processing speed can be increased even if input data changes.

It is a figure which shows an example of a data processor. It is a figure which shows the structural example of a processing program typically. It is a figure which shows typically an example of the access speed in a register | resistor, an internal memory, and a main memory part. It is a figure which shows an example of the subject about the arrangement | positioning method of a variable. It is a figure which shows an example of the arrangement | positioning operation | movement of the variable in the technical example 1. FIG. 10 is a diagram illustrating an example of a problem of Technical Example 1. FIG. It is a figure which shows an example of the arrangement | positioning operation | movement of the variable in the technical example 2. FIG. It is a figure which shows an example of the subject of the technical example 2. FIG. It is a figure which shows an example of the subject at the time of combining the technical example 1 and the technical example 2. FIG. 1 is a diagram illustrating an example of a data processing apparatus including a register arrangement optimizing apparatus according to a first embodiment. It is a figure which shows the example of conversion of a pseudo instruction code. It is a figure which shows an example of a conversion map table. It is a flowchart which shows an example of the operation | movement which concerns on the update of the information of the past usage frequency contained in the conversion map table. It is a figure explaining an example of the update procedure of the conversion map table performed with execution of a processing program. It is a flowchart which shows the process example of a rearrangement process (S201). (a) is a figure which shows the example of variable arrangement | positioning by the method 1, (b) is a figure which shows the example of variable arrangement | positioning by the method 2. 1 is a diagram illustrating a configuration example of an image encoding device including a register arrangement optimization device according to Embodiment 1. FIG. It is a figure which shows typically the outline | summary of the flow of a process of the image coding apparatus shown in FIG. It is a figure which shows an example of the operation | movement sequence of the image coding apparatus shown in FIG. It is a figure which shows an example of the program development period in the case of the conventional case, and the program development period at the time of employ | adopting the register arrangement optimization apparatus based on Example 1. FIG. (a) is a flowchart showing a basic processing example of the input data feature calculation unit, and (b) and (c) are flowcharts showing specific examples thereof. FIG. 10 is a diagram illustrating a configuration example of an image encoding device including a register arrangement optimizing device according to a second embodiment. It is a figure which shows typically the outline | summary of the flow of a process of the image coding apparatus shown in FIG. It is a figure which shows an example of the operation | movement sequence of the image coding apparatus shown in FIG. It is a figure which shows the example of the some conversion map table in which each contains the information of a conversion map table selection value. It is a figure which shows the structural example of a computer system.

<Example 1>
FIG. 1 is a diagram illustrating an example of a data processing apparatus.
1 includes a processor CPU (Central Processing Unit) unit 110, a main memory unit 120, a memory controller unit 130, a peripheral input / output I / F (InterFace) unit 140, and a communication I / F (InterFace) unit. 150 and the system bus 160.

  The processor CPU unit 110 includes a processor core (arithmetic / control unit) 111, a register 112, an instruction cache 113, a data cache 114, a system bus controller 115, and an internal memory 116. The processor core 111 executes a processing program (instruction code). The register 112 is a high-speed register that is accessed by the processor core 111. The instruction cache 113 is a cache memory for instruction codes. The data cache 114 is a cache memory for data codes. The system bus controller 115 is a controller of the system bus 160 that connects each unit. The internal memory 116 is a small-capacity memory used in the processor CPU unit 110.

The main memory unit 120 includes a processing program storage area 121, a processing data storage area 122, and a processing result storage area 123.
The memory controller unit 130 performs read / write control of the main memory unit 120.

The peripheral input / output I / F unit 140 performs input / output I / F processing with an external device. The communication I / F unit 150 performs I / F processing with an external device via a communication line.
The system bus 160 is an address / data bus connected to the processor CPU unit 110, the memory controller unit 130, the peripheral input / output I / F unit 140, the communication I / F unit 150, and the like.

  In the data processing apparatus illustrated in FIG. 1, processing target data is input from an external device via the peripheral input / output I / F unit 140 or from a communication line via the communication I / F unit 150. The input processing target data is stored in the processing data storage area 122 of the main memory unit 120 via the system bus 160 and the memory controller unit 130. The stored processing target data is processed by the processor CPU unit 110 executing a processing program loaded in the main memory unit 120. The processing program is, for example, an image processing program that performs processing such as filtering and image compression. In the processing program, an instruction code for realizing the processing contents of the processor CPU unit 110 is stored in the main memory unit 120 or the internal memory 116. The instruction code is directly written in an assembler language, or is written in a high-level language such as C language and converted by a compiler. The processor CPU unit 110 is provided with a cache memory (instruction cache 113 and data cache 114) for speeding up memory access, and an instruction code executed by the processor core 111 is appropriately copied to the instruction cache 113 in advance. Is done. The processor CPU unit 110 is provided with a register 112 for storing or temporarily storing data to be calculated. Arithmetic instructions executed by the processor core 111 are executed using the data in the register 112 and the memory (the internal memory 116 or the main memory unit 120) as an operation target (operand). The calculation result is stored in the processing result storage area 123 of the main memory unit 120 via the system bus 160 and the memory controller unit 130. The final result is output to an external device via the peripheral input / output I / F unit 140 or to a communication line via the communication I / F unit 150 as necessary.

FIG. 2 is a diagram schematically illustrating a configuration example of the processing program.
The processing program in which the processing order is described as the instruction code is divided into functions and subroutine modules (for example, function [1] to function [n]) as shown in FIG. Realize the function. Variables used in each function are arranged in the register 112 or the memory (the internal memory 116 or the main memory unit 120), and are specified as operands of operation instructions. In the example shown in FIG. 2, for example, in the function [1], the variables [1] to [6] specified as the operands of the operation instruction are arranged in the registers (register-1 to register-5) 112. Is shown. Further, the variable [7] and the variable [8] indicate that they are arranged in the memory (the internal memory 116 or the main memory unit 120).

  FIG. 3 is a diagram schematically illustrating an example of access speeds in the register 112, the internal memory 116, and the main memory unit 120. Here, an example in which the main memory unit 120 is a DRAM (Dynamic Random Access Memory) is shown.

  As shown in FIG. 3, the access speed is different between the register 112 and the memory (internal memory 116 and DRAM). The DRAM provided outside the processor CPU unit 110 requires several tens to several hundred times the access time for the register 112, and the internal memory 116 of the processor CPU unit 110 requires two to four times the access time. Therefore, the variable used in the function can be processed at a higher speed if it is arranged in the register 112 as much as possible. However, since the number of registers that can be used is limited, variables that cannot be arranged in the register 112 are arranged in the memory (the internal memory 116 or the main memory unit 120). Note that the number of registers to be limited is different for each processor, for example.

  Therefore, in a program that requires high-speed operation, in order to satisfy the target performance, optimize the processing by assigning more frequently used variables or variables whose reuse timing is close in time to the register, etc. The processing is speeded up. In this case, for example, there is a technique for speeding up the process by converting an instruction code to operate using a register (hereinafter referred to as “Technical Example 1”). Also, for example, by reading the assembler code, calculating the variable assignment priority based on the length of the variable existing section and the total loop level where the variable exists, and converting the variable placement destination based on the result There is a technology for speeding up (hereinafter referred to as “Technical Example 2”).

On the other hand, the variable assignment method has the following problems.
FIG. 4 is a diagram illustrating an example of a problem regarding a variable arrangement method.
As shown in FIG. 4, the frequency of use and the order of use of variables differ depending on which processing route (processing routes A to C) in the function has passed. This is because processing according to the characteristics of the input data is performed in the function, and therefore the processing route differs when the input data changes. Therefore, variables that optimize the register arrangement by, for example, allocating variables used in the processing route (for example, processing route C) when average point data is input to the register as a main, and are variables that are optimal overall. It is necessary to make arrangements. However, in this case, in the processing route (for example, processing route A or B) when non-average data is input, the register is not used properly, which causes a reduction in processing speed.

FIG. 5 is a diagram illustrating an example of a variable arrangement operation in the first technical example.
As shown in FIG. 5, in the first technical example, the following operation is performed in the instruction transmission path of the processor. First, the instruction code read from the instruction cache (CASHE) 171 is sorted in the instruction fetch unit (FETc) 172. If it is a floating-point byte code, it is sent to the byte code accelerator unit (BCA) 173. Is output. Then, it is converted into an inter-register transfer instruction, which is output to the decoding unit (DECc, DECf) 175 via the selector 174. In the first technical example, the operation speed is increased by such an operation. In the decoding unit 175, DECc decodes all instructions, and DECf recognizes and decodes floating point instructions.

FIG. 6 is a diagram illustrating an example of the problem of the first technical example.
In the first technical example, as described above, a part of instruction codes is converted. Therefore, as shown in FIG. 6, for example, in the case of input data A, there is a floating-point operation, and the arrangement destination is converted, which is an effective method. However, in the case of the input data B in which the input data has changed, the processing route is changed and no floating point arithmetic is performed. In this case, there is no effect of speeding up. As described above, in the first technical example, the presence / absence of the floating-point operation is fixedly determined by the input data, and cannot be dynamically changed.

FIG. 7 is a diagram illustrating an example of a variable arrangement operation in the second technical example.
As shown in FIG. 7, in the technical example 2, the following operation is performed in the program conversion apparatus. First, the processing program (assembler code) is read and analyzed, the length of the variable existence section and the total loop level where the variable exists are calculated, and the assignment priority of each variable is calculated based on the calculation result. . Then, the variable placement destination is converted based on the calculation result. In the technical example 2, the operation speed is increased by such an operation.

FIG. 8 is a diagram illustrating an example of the problem of the second technical example.
In the technical example 2, as described above, the processing program (assembler code) is analyzed, and the arrangement is determined based on the length of the variable existing section on the code and the sum of the loop levels where the variable exists, A processing program is executed. Therefore, as shown in FIG. 8, for example, it is assumed that the most frequently used variable in the processing program is determined as the variable X (see A in FIG. 8), and the placement destination of the variable X is a register. However, after that, the input data is changed, and the variable most frequently used in the execution route for performing the process may be the variable Y instead of the variable X (see the shaded portion in FIG. 8B). As described above, in the case where the input data is changed and the execution route of the processing program is changed, the technical example 2 cannot cope with the change of the existing section of the variable to be used and the number of loops.

FIG. 9 is a diagram illustrating an example of a problem when the above technical example 1 and the technical example 2 are combined.
As shown in FIG. 9, in this case, a processing program (assembler code or the like) is read, and the type of the instruction (floating point), the length of the variable existence section, and the total loop level where the variable exists. The placement destination is converted based on the above. However, in this case, the allocation of registers and memories cannot be changed (optimized) depending on the frequency of use of variables in the function that changes according to input data.

Accordingly, in view of the above-described problem regarding the variable arrangement method, the data processing apparatus including the register arrangement optimization apparatus according to the first embodiment has the following configuration.
FIG. 10 is a diagram illustrating an example of the data processing apparatus including the register arrangement optimizing apparatus according to the present embodiment.

  10, the same elements as those shown in FIG. 1 are denoted by the same reference numerals. In the data processing apparatus shown in FIG. 10, the register arrangement optimizing apparatus according to the present embodiment includes an instruction conversion unit 117 and a conversion map table 118. The instruction conversion unit 117 is an example of an instruction conversion unit, and the conversion map table 118 is an example of a conversion table.

  In the data processing apparatus shown in FIG. 10, the processor CPU unit 110 further includes an instruction conversion unit 117 and a conversion map table 118, which are provided between the instruction cache 113 and the system bus controller 115. The conversion map table 118 can be provided inside or outside the instruction conversion unit 117, and is stored in a storage unit (not shown) in the processor CPU unit 110, for example.

  In addition, the instruction code in the processing program stored in the processing program storage area 121 of the main memory unit 120 is abstracted in which the operand of the arithmetic instruction is not specified (the location of the arithmetic instruction operand is not specified). Pseudo instruction code. That is, the pseudo instruction code does not clearly indicate whether the operand of the operation instruction is arranged in the register 112 or in the memory (the internal memory 116 or the main memory unit 120). A processing program including such a pseudo instruction code is generated in advance and stored in the processing program storage area 121.

As will be described in detail later, the conversion map table 118 includes information such as the location of each variable defined in each function in the processing program, the average usage frequency, and the past usage frequency.
The instruction conversion unit 117 converts the pseudo instruction code into an instruction code that can be interpreted (executable) by the processor core 111 (hereinafter referred to as “normal instruction code”) based on the information on the location of each variable included in the conversion map table 118. "). That is, an abstract pseudo-instruction code in which it is not specified whether the operand of the operation instruction is placed in the register 112 or in the memory (the internal memory 116 or the main memory unit 120) Convert to instruction code. Then, the converted instruction code is loaded into the instruction cache 113. The instruction conversion unit 117 also performs processing such as updating the conversion map table 118, as will be described in detail later.

FIG. 11 is a diagram illustrating a conversion example of the pseudo instruction code.
In the example shown in FIG. 11, the instruction conversion unit 117 converts the addition instruction “ADD val0, val1”, which is a pseudo instruction code, based on the information on the location of each variable included in the conversion map table 118 into a normal instruction. In this example, the code is converted into an addition instruction “add r0, r1” or “add (mem0), r1”.

  Here, an addition instruction “ADD val0, val1” which is a pseudo instruction code indicates an addition instruction of variable 1 (val0) and variable 2 (val1). Thus, the pseudo instruction code does not clearly indicate whether the operand of the operation instruction is placed in the register 112 or in the memory (the internal memory 116 or the main memory unit 120).

  On the other hand, the addition instruction “add r0, r1”, which is the instruction code after conversion, is an example of conversion when variable 1 is placed in register 0 (r0) and variable 2 is placed in register 1 (r1). The addition instruction of the variable 1 arranged in the register 0 (r0) and the variable 2 arranged in the register 1 (r1) is shown. Note that the register 0 (r0) and the register 1 (r1) are areas included in the register 112.

  An addition instruction “add (mem0), r1”, which is an instruction code after conversion, is a conversion example in the case where variable 1 is arranged in memory (mem0) and variable 2 is arranged in register 1 (r1). Yes, it shows an addition instruction for the variable 1 arranged in the memory (mem0) and the variable 2 arranged in the register 1 (r1). The memory (mem0) is an area included in the internal memory 116 or the main memory unit 120.

FIG. 12 is a diagram illustrating an example of the conversion map table 118.
As shown in FIG. 12, the conversion map table 118 includes information such as the location of each variable defined in each function in the processing program, the average use frequency, and the past use frequency. However, in FIG. 12, the past use frequency information is omitted.

The information included in the conversion map table 118 is dynamically updated (changed) as follows with the execution of the processing program.
First, when the processing program is started, the information on the location of each variable is given priority according to, for example, the definition order of the variable in each function in the processing program, and the register 112 or memory ( The internal memory 116 or the main memory unit 120) is determined. Also, the information on the average use frequency and past use frequency of each variable is set to zero.

  Thereafter, when data to be processed by the processing program is input and the execution of the processing program is started, the pseudo instruction code in the processing program is converted by the instruction conversion unit 117 and loaded into the instruction cache 113. At the time of conversion by the instruction conversion unit 117, the conversion map table 118 is referred to, and the following conversion (also referred to as operand conversion) is performed. In the conversion map table 118, a variable whose placement destination is the register (register-1 to register-5) 112 is converted into an instruction sequence in which the placement destination of the instruction code operand is the corresponding register 112. On the other hand, in the conversion map table 118, a variable whose placement destination is a memory (internal memory 116 or main memory unit 120) is converted into an instruction sequence in which the placement destination of the instruction code operand is the corresponding memory.

  When the instruction code converted in this way is executed by the processor core 111 and a variable is used, information on the past use frequency included in the conversion map table 118 is updated for each variable. Average usage frequency information is updated.

  For example, in the conversion map table 118 shown in FIG. 12, the average usage frequency of the variable [2] of the function [1] is “50”, and the average among the variables defined in the function [1] It indicates that the frequency of use is the highest. Such information on the average use frequency is used for changing the variable placement destination. For example, in the conversion map table 118 shown in FIG. 12, the variable [1] of the function [2] has an average usage frequency of “7”, and the variable [5] of the function [2] has an average usage frequency of “20”. It is shown that. In this case, in the function [2], the variable [5] arranged in the memory (the internal memory 116 or the main memory unit 120) has an average usage frequency higher than the variable [1] arranged in the register 112. Since the value is higher, the variable placement destination is changed in the conversion map table 118. That is, in the conversion map table 118, the variable placement destination is changed so that the placement destination of the variable [5] is the register 112 and the placement destination of the variable [1] is the memory (the internal memory 116 or the main memory unit 120). Is done. By exchanging the variable placement destinations in this way, the variable placement destination can be dynamically changed (optimized). Further, the conversion by the instruction conversion unit 117 is performed based on the information on the placement destination of each variable included in the conversion map table 118 after the replacement of the placement destination of the variable in this way, thereby speeding up the processing. Can be achieved.

  In the conversion map table 118, information on the location of each variable at the time of starting the program is stored in the internal memory 116 or the main memory unit 120 in advance, for example, and is read out at the time of starting the program and stored in the conversion map table 118. It is also possible to store them. In this case, the information on the location of each variable at the time of starting the program is determined based on, for example, a static analysis result of the processing program.

FIG. 13 is a flowchart illustrating an example of an operation related to updating past usage frequency information included in the conversion map table 118.
As shown in FIG. 13, when a read request (instruction code load instruction) is made by a controller of an instruction cache 113 (not shown) (S101), the following operation is performed. First, in response to this read request, the pseudo instruction code necessary for the processor core 111 to execute the instruction code is read from the processing program storage area 121 of the main memory unit 120 and transferred to the instruction conversion unit 117 (S102). ). In the instruction conversion unit 117, the transferred pseudo instruction code is converted into a normal instruction code by operand conversion based on the information on the location of each variable included in the conversion map table 118 (S103). Further, when the converted instruction code is executed by the processor core 111 and a variable is used, the past use frequency information included in the conversion map table 118 is so set that the past use frequency for the variable is incremented. Is updated (S104). In the conversion map table 118, the past usage frequency information incremented in this way is used when updating the average usage frequency information, as will be described in detail later.

FIG. 14 is a diagram for explaining an example of a procedure for updating the conversion map table 118 performed in accordance with the execution of the processing program.
Data processing performed by executing the processing program may include continuous data processing. In general, in continuous data processing, a certain process break is defined as one unit (one processing unit), and the entire process is realized by repeatedly executing the unit. For example, in moving image processing, image processing such as object recognition processing and image compression processing is realized by repeatedly executing processing for one screen as one unit. Here, an example of a procedure for updating the conversion map table 118 when such continuous data processing is performed will be described.

  As shown in FIG. 14, in the processing for each processing unit performed during execution of the processing program, first, rearrangement processing is performed (S201). In this rearrangement processing, as will be described in detail later, the placement destination of each variable is determined based on the information on the average use frequency of each variable included in the transformation map table 118, and the transformation map table is reflected so as to reflect it. Information on the location of each variable included in 118 is updated (changed).

  Next, one processing unit of the processing program is executed (S202). Here, as described above, the conversion map table 118 is referred to by the instruction conversion unit 117, conversion from the pseudo instruction code to the normal instruction code is performed, and the converted instruction code is executed by the processor core 111.

  Next, frequency average update processing is performed (S203). In this frequency average update process, information on the frequency of use of variables used when the instruction code is executed by the processor core 111 in S202 is stored in the conversion map table 118 as information on the past frequency of use for one processing unit. Added. As shown in FIG. 14, the conversion map table 118 uses the variables used in the execution of each processing unit for a predetermined number of times in the past (N times) as information on the past usage frequency. Frequency information can be included. For example, “Past data 1” in FIG. 14 indicates information on the frequency of use of variables used in the execution of the current (most recent) one processing unit, and “Past data N” is (N−1) before the processing unit. Information on the frequency of use of variables used in the execution of the processing unit is shown. As described above, the past use frequency information included in the conversion map table 118 is updated according to the variable used when the instruction code is executed by the processor core 111.

  Further, in the frequency average update process of S203, the conversion map table 118 further obtains the average value of the usage frequencies of the variables defined in each function based on the past usage frequency information, and the average usage frequency. Information is updated. In this case, for example, an average value of the usage frequency of each variable defined in each function is obtained based on the usage frequency information for the past M (where M ≦ N) times from the present. For example, the information on the average usage frequency “8” (refer to the shaded portion) of the variable [3] of the function [2] included in the conversion map table 118 shown in FIG. 12 ”,“ 6 ”,“ 6 ”,“ 8 ”,“ 8 ”,“ 8 ”). By using the average usage frequency information thus obtained, it is possible to reduce the influence of sudden (temporary) fluctuations in the usage frequency.

FIG. 15 is a flowchart illustrating a processing example of the above-described rearrangement processing (S201).
The process shown in FIG. 15 is a process performed for each function in one processing unit in the above-described rearrangement process (S201).

  In the processing shown in FIG. 15, Rm indicates a variable relocated register. Rn_max indicates the maximum number of registers in which variables in the function can be arranged. VSi indicates the i-th variable when the variables in the function are arranged in order of average usage frequency.

  As shown in FIG. 15, in this process, first, information on the average use frequency of each variable defined in the target function included in the conversion map table 118 is referred to (S301). In addition, when this process is performed in one processing unit for the second and subsequent times after the processing program is started, the information referred to in S301 is the average usage frequency information updated in S203 in the previous one processing unit. Become. Next, the placement destination of the variable VSi arranged in descending order of the average usage frequency is sequentially determined in the register 112 based on the information on the average usage frequency of each variable defined in the target function (S302). . When the number of registers in which the variable placement destination is determined as the register 112 reaches Rn_max (Yes in S303), the placement destination of the remaining variable VSi is determined in the memory (the internal memory 116 or the main memory unit 120) ( S304). Such processing is repeatedly performed for each function included in one processing unit. Thereby, based on the information on the average use frequency of each variable included in the conversion map table 118, the variable placement destination can be determined so that the variable having the high average use frequency is preferentially rearranged in the register 112. it can.

  As a technique for optimizing register allocation in static compilation, for example, a technique called “linear scan allocation” by Poletto and Sarkar (hereinafter referred to as “method 1”) is known. In Method 1, for example, by further adding the above-described dynamic information (information included in the conversion map table 118) to the register usage period, it is possible to arrange variables more efficiently. (Hereinafter referred to as “Method 2”).

FIG. 16A is a diagram illustrating an example of variable arrangement according to Method 1. FIG. FIG. 16 (b) is a diagram showing an example of variable arrangement according to method 2.
In the example shown in FIG. 16, although the use end timing of the variable A on the source code is the longest among all the variables, it is used in the processing route on the false side of the judgment statement at the time of actual execution. This is an example of a case where it is not used in the processing route on the side. In FIG. 16, R0 and R1 indicate areas included in the register.

  As shown in FIG. 16 (a), in Method 1 in which dynamic information is not taken into account, a spill operation is performed to expel the variable A from the register to the memory. On the other hand, as shown in FIG. 16 (b), in the method 2 in consideration of dynamic information, for example, a processing route to be executed is predicted, and a processing route that is not executed by the determination statement is determined. . As a result, the spill operation of the variable A is not performed, and a more optimal variable arrangement can be achieved.

Next, as a specific example of the data processing apparatus including the register arrangement optimizing apparatus according to this embodiment, an example in which the register arrangement optimizing apparatus according to this embodiment is applied to an image encoding apparatus will be described.
FIG. 17 is a diagram illustrating a configuration example of an image encoding device including the register arrangement optimizing device according to the present embodiment.

  In FIG. 17, the same elements as those shown in FIG. 10 are denoted by the same reference numerals. Further, in the image encoding device shown in FIG. 17, the register arrangement optimizing device according to the present embodiment includes an instruction conversion unit 117 and a conversion map table 118, as in the case of the data processing device shown in FIG. .

  In the image encoding device shown in FIG. 17, the configuration of the image processor 210 is basically the same as that of the processor CPU unit 110 shown in FIG. A video input I / F (InterFace) unit 220 performs input processing of data input from an external camera or the like. A video output I / F (InterFace) unit 230 performs output processing to an external display or the like. Other configurations are basically the same as those of the data processing apparatus shown in FIG.

Next, the operation of the image encoding device illustrated in FIG. 17 will be described with reference to FIGS. 18 and 19.
FIG. 18 is a diagram schematically showing an outline of the processing flow of the image encoding device shown in FIG.

  As shown in FIG. 18, input image data from a camera or the like is stored in the processing data storage area 122 of the main memory unit 120 via the video input I / F unit 220, the system bus 160, and the memory controller unit 130. (See arrow A in FIG. 18). The accumulated image data is read out to the data cache 114 via the memory controller unit 130, the system bus 160, and the system bus controller 115 in units of processed images (see arrow B in FIG. 18). On the other hand, the processing program (including pseudo instruction code) stored in the processing program storage area 121 of the main memory unit 120 is transferred to the instruction conversion unit 117 via the memory controller unit 130, the system bus 160, and the system bus controller 115. Loaded (see arrow C in FIG. 18). In the instruction conversion unit 117, the conversion map table 118 is referred to (see arrow D in FIG. 18), and the pseudo instruction code is converted into a normal instruction code based on the content thereof and transferred to the instruction cache 113 (in FIG. 18). (See arrow E). The transferred instruction code is read by the processor core 111 (see arrow F in FIG. 18), and the instruction code is executed by using, for example, a variable arranged in the register 112 (see FIG. 18). 18 arrow G). When the processing program is executed in this manner, output data is thereby created. Then, the output data passes through the data cache 114, the system bus controller 115, and the system bus 160, and then is output, for example, via the communication I / F unit 150 or the video output I / F unit 230 (FIG. 18). Arrow H). The output data is, for example, compressed image data.

FIG. 19 is a diagram illustrating an example of an operation sequence of the image encoding device illustrated in FIG. 17.
As shown in FIG. 19, the input image data from the camera or the like is accumulated in the processing data storage area 122 of the main memory unit 120 via the video input I / F unit 220 or the like, and the image is saved (S401). ). Next, the processing program (including the pseudo instruction code) stored in the processing program storage area 121 of the main memory unit 120 is activated in units of processed images (S402) and loaded into the instruction conversion unit 117. In the instruction conversion unit 117, the conversion map table 118 is referred to (S403), and the placement destination of each variable defined in each function in the processing program is determined (S404). Further, the pseudo instruction code is converted into a normal instruction code (S405). The converted instruction code is transferred to the instruction cache 113, and then read out by the processor core 111, and the instruction code is executed (S406). On the other hand, in the instruction conversion unit 117, when the instruction code is executed by the processor core 111 and a variable is used, the frequency of use of the variable is incremented (S407) and the information included in the conversion map table 118 is updated. Is done. Then, the processing program is executed in this way, and output data (image data or the like) created by the processing program is transmitted to the communication line or the external via the communication I / F unit 150 or the video output I / F unit 230, for example. (S408).

  As described above, according to the register arrangement optimizing apparatus according to the present embodiment, a frequently used variable is preferentially arranged in the register based on the use frequency of the variable defined in the function in the program. Thus, the variable placement destination can be determined dynamically. Therefore, the variable placement destination can be dynamically optimized, and the processing speed can be increased. Further, such optimization can be performed without any special user operation such as designation of an operation mode.

In addition, the program development period can be shortened for the following reasons.
FIG. 20 is a diagram illustrating an example of a conventional program development period and a program development period when the register arrangement optimizing apparatus according to the present embodiment is employed.

  As shown in FIG. 20, for example, in the conventional case, it is assumed that one month is required for the design period and two months are required for the correction period (tuning work) for speeding up. In this case, when the register arrangement optimizing apparatus according to the present embodiment is employed, a correction period for speeding up becomes unnecessary, and therefore the development period (two months) can be shortened accordingly.

  Further, in the image processing apparatus including the register arrangement optimizing apparatus according to the present embodiment, for example, when a plurality of frames of images are input, it is possible to increase the speed according to the image processing for the plurality of frames of images. .

<Example 2>
The register arrangement optimizing apparatus according to the second embodiment is different from the register arrangement optimizing apparatus according to the first embodiment in that it further includes an input data feature calculation unit and includes a plurality of conversion map tables as the conversion map table 118. The input data feature calculation unit is an example of a table selection unit.

  In the register arrangement optimizing device according to the present embodiment, the input data feature calculation unit calculates the feature of the input data, and selects a corresponding conversion map table from a plurality of conversion map tables according to the calculation result Perform processing such as.

  FIGS. 21A, 21B, and 21C are flowcharts showing an example of processing of the input data feature calculation unit. FIG. 21A is a flowchart showing an example of the basic processing, and FIGS. 21B and 21C are flowcharts showing specific examples thereof.

  As shown in FIG. 21 (a), the basic processing of the input data feature calculation unit is as follows. First, when input data is received (S501), a difference between the input data is calculated (S502). Next, a conversion map table corresponding to the difference is selected from a plurality of conversion map tables (S503), and a notification to that effect is sent to the instruction conversion unit 117 (S504). Thereby, in the instruction conversion unit 117, the pseudo instruction code is converted using the conversion map table selected by the input data feature calculation unit.

  Specifically, for example, as shown in FIG. 21B, when input data (image data) is received (S601), an intra-frame difference of the input data is calculated (S602). It is determined whether or not the difference value is larger than a predetermined value (S603). Here, if the determination result is Yes, a conversion map table for intra-frame processing is selected, and that is notified to the instruction conversion unit 117 (S604). As a result, the instruction conversion unit 117 converts the pseudo instruction code using the conversion map table for intra-frame processing selected by the input data feature calculation unit. On the other hand, when the determination result in S603 is No, the instruction conversion unit 117 is notified that the conversion map table is not changed (S605). As a result, the instruction conversion unit 117 converts the pseudo instruction code using the conversion map table set as default.

  Alternatively, for example, as shown in FIG. 21 (c), when input data (image data) is received (S701), an interframe difference of the input data is calculated (S702), and the value of the interframe difference is calculated. It is determined whether or not is greater than a predetermined value (S703). Here, if the determination result is Yes, a conversion map table for inter-frame processing is selected, and this is notified to the instruction conversion unit 117 (S704). As a result, the instruction conversion unit 117 converts the pseudo instruction code using the conversion map table for inter-frame processing selected by the input data feature calculation unit. On the other hand, if the determination result in S703 is No, the instruction conversion unit 117 is notified that the conversion map table is not changed (S705). As a result, the instruction conversion unit 117 converts the pseudo instruction code using the conversion map table set as default.

  With the processing shown in FIG. 21 (b) or FIG. 21 (c), in an image having a large intra-frame difference or inter-frame difference, the conversion map table is switched, and the switched conversion map table is used. The pseudo instruction code is converted. In this way, for example, even when a fluctuation occurs in image data in a scene change or the like in a moving image, the variable placement destination can be switched without affecting the information included in the conversion map table.

Next, an example in which the register arrangement optimizing apparatus according to the present embodiment is applied to an image encoding apparatus will be described.
FIG. 22 is a diagram illustrating a configuration example of an image encoding device including the register arrangement optimizing device according to the present embodiment.

  In FIG. 22, the same elements as those shown in FIG. 17 are denoted by the same reference numerals. In the image encoding device shown in FIG. 22, the register arrangement optimizing device according to this embodiment includes an instruction conversion unit 117, a plurality of conversion map tables 118, and an input image feature calculation unit 311.

  In the image encoding device shown in FIG. 22, the configuration of the image processor 210 further includes an input image feature calculation unit 311 and includes a plurality of conversion map tables 118. The image processor 210 shown in FIG. And basically the same. The input image feature calculation unit 311 is an example of the input data feature calculation unit. Other configurations are basically the same as those of the image encoding device shown in FIG.

Next, the operation of the image encoding device shown in FIG. 22 will be described with reference to FIGS.
FIG. 23 is a diagram schematically showing an outline of the processing flow of the image encoding device shown in FIG.

  As shown in FIG. 23, input image data from a camera or the like is accumulated in the processing data storage area 122 of the main memory unit 120 via the video input I / F unit 220, the system bus 160, and the memory controller unit 130. (See arrow A in FIG. 23). The accumulated image data is read out to the data cache 114 via the memory controller unit 130, the system bus 160, and the system bus controller 115 in units of processed images (see arrow B in FIG. 23). At the same time, it is input to the input image feature calculation unit 311 (see arrow C in FIG. 23). The input image feature calculation unit 311 calculates an intra-frame difference or an inter-frame difference of input image data. Then, according to the calculation result, notification of selection of the corresponding conversion map table 118 or no change of the conversion map table 118 is made to the instruction conversion unit 117 (see arrow D in FIG. 23). On the other hand, the processing program (including pseudo instruction code) stored in the processing program storage area 121 of the main memory unit 120 is transferred to the instruction conversion unit 117 via the memory controller unit 130, the system bus 160, and the system bus controller 115. Loaded (see arrow E in FIG. 23). In response to the notification from the input image feature calculation unit 311, the instruction conversion unit 117 selects and refers to the corresponding conversion map table 118 (see arrow F in FIG. 23). Then, the pseudo instruction code is converted into a normal instruction code based on the contents of the conversion map table 118 and transferred to the instruction cache 113 (see arrow G in FIG. 23). The transferred instruction code is read by the processor core 111 (see arrow H in FIG. 23), and the instruction code is executed by using, for example, a variable arranged in the register 112 (see FIG. 23). 23, arrow I). When the processing program is executed in this manner, output data is thereby created. The output data passes through the data cache 114, the system bus controller 115, and the system bus 160, and then is output, for example, via the communication I / F unit 150 or the video output I / F unit 230 (FIG. 23). Arrow J). The output data is, for example, compressed image data.

FIG. 24 is a diagram illustrating an example of an operation sequence of the image encoding device illustrated in FIG. 22.
As shown in FIG. 24, input image data from a camera or the like is accumulated in the processing data storage area 122 of the main memory unit 120 via the video input I / F unit 220 or the like, and image storage is performed (S801). ). Next, the processing program (including the pseudo instruction code) stored in the processing program storage area 121 of the main memory unit 120 is activated for each processing image (S802) and loaded into the instruction conversion unit 117. The input image feature calculation unit 311 calculates a difference (intraframe difference or interframe difference) between input image data (S803). Further, according to the calculation result, notification of selection of the corresponding conversion map table 118 or no change of the conversion map table 118 is made to the instruction conversion unit 117 (S804). The instruction conversion unit 117 selects and refers to the corresponding conversion map table 118 in response to the notification from the input image feature calculation unit 311 (S805), and places each variable defined in each function in the processing program. Is determined (S806). Further, the pseudo instruction code is converted into a normal instruction code (S807). The converted instruction code is transferred to the instruction cache 113, and thereafter read out by the processor core 111, and the instruction code is executed (S808). On the other hand, in the instruction conversion unit 117, when the instruction code is executed by the processor core 111 and a variable is used, the frequency of use of the variable is incremented (S809) and the information included in the conversion map table 118 is updated. Is done. Then, the processing program is executed in this way, and output data (image data or the like) created by the processing program is transmitted to the communication line or the external via the communication I / F unit 150 or the video output I / F unit 230, for example. (S810).

As a method for the input image feature calculation unit 311 to notify the instruction conversion unit 117 of the selected conversion map table 118, there are the following methods.
For example, the input image feature calculation unit 311 notifies the instruction conversion unit 117 of information on the conversion map table selection value corresponding to the selected conversion map table 118. Receiving this, the instruction conversion unit selects the corresponding conversion map table 118 based on the information of the conversion map table selection value. In this case, each of the plurality of conversion map tables 118 includes information on a corresponding conversion map table selection value.

FIG. 25 is a diagram illustrating an example of a plurality of conversion map tables 118 each including information of a conversion map table selection value.
As shown in FIG. 25, each of the plurality of conversion map tables 118 includes information on a corresponding conversion map table selection value. For example, the conversion map table 118a includes information whose conversion map table selection value is “1”, and the conversion map table 118b includes information whose conversion map table selection value is “2”. In the conversion map tables 118a and 118b shown in FIG. 25, the past use frequency information is omitted.

  As described above, according to the register arrangement optimizing apparatus according to the present embodiment, the conversion map table 118 used (referenced or updated) by the instruction conversion unit 117 is converted into the conversion map table 118 corresponding to the characteristics of the input data. can do. Therefore, for example, the conversion map table 118 is adaptively used according to the scene of the input image, so that the image processing can be speeded up.

Further, similar to the register arrangement optimizing apparatus according to the first embodiment, the program development period can be shortened.
Further, in the image processing apparatus including the register arrangement optimizing apparatus according to the present embodiment, for example, when a plurality of frames of images are input, it is possible to increase the speed according to the characteristics of the plurality of frames of images.

  In the register arrangement optimizing device according to the first and second embodiments described above, the past of variables included in the conversion map table 118 according to the variables used when the instruction code is executed by the processor core 111 is used. Information on usage frequency and average usage frequency was updated. This can be performed according to, for example, a variable used when the pseudo instruction code is converted by the instruction conversion unit 117.

Further, the register arrangement optimizing device according to the first and second embodiments described above can be realized by, for example, the following computer system.
FIG. 26 is a diagram illustrating a configuration example of the computer system.

  As shown in FIG. 26, this computer system includes a CPU 401, a ROM 402, a RAM 403, a communication interface 404, a storage device 405, an input / output device 406, a portable storage medium reading device 407, and all of these. Includes bus 408. The ROM is a read only memory.

As the storage device 305, various types of storage devices such as a hard disk and a magnetic disk can be used.
For example, when the register arrangement optimizing apparatus according to the first embodiment is realized by this computer system, a program for an operation (processing) performed by the instruction conversion unit 117 or the like is stored in the storage device 405 or the ROM 402. The The RAM 403 stores a conversion map table 118 and the like. Then, by executing the program by the CPU 401, the register arrangement optimizing device according to the first embodiment is realized.

  Further, for example, when the register arrangement optimizing device according to the second embodiment is realized by the computer system, operations (processing) performed by the instruction conversion unit 117, the input data feature calculation unit, and the like in the storage device 405 or the ROM 402. Stores a program and the like. The RAM 403 stores a plurality of conversion map tables 118 and the like. Then, by executing the program by the CPU 401, the register arrangement optimizing device according to the second embodiment is realized.

  Such a program can be stored in, for example, the storage device 405 from the program provider 409 via the network 410 and the communication interface 404 and executed by the CPU 401. Further, it can be stored in a commercially available portable storage medium 411, set in the reading device 407, and executed by the CPU 401. As the portable storage medium 411, various types of storage media such as a CD-ROM, a flexible disk, an optical disk, a magneto-optical disk, a DVD disk, and a USB memory can be used.

In the computer system, the communication interface 404, the storage device 405, the input / output device 406, and the reading device 407 may be omitted.
Although the embodiments have been described above, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be made without departing from the gist of the present invention.

Regarding the above embodiment, the following additional notes are disclosed.
(Appendix 1)
In a processor including a processor core for executing an instruction code and a register, a method for optimizing a variable arranged in the register,
Refers to a conversion table that includes information on the location and usage frequency of variables defined in functions in the program, and preferentially allocates frequently used variables to the registers based on the usage frequency information of the variables. To determine the location of the variable in the register or memory,
Reflecting the determined variable placement destination in the variable placement destination information included in the conversion table,
Based on the information on the placement destination of the variable included in the conversion table, the pseudo instruction code in which the placement destination of the operand of the operation instruction is not specified is converted into an instruction code executable by the processor core,
Updating information on the frequency of use of the variables included in the conversion table according to the variables used when the processor core executes the converted instruction code;
A register arrangement optimizing method characterized by the above.
(Appendix 2)
The information on the frequency of use of the variable included in the conversion table includes information on the average use frequency and past use frequency of the variable,
In the determination, based on the information on the average use frequency of the variable included in the conversion table, the variable placement destination is set to the register or the above so that a variable having a high average use frequency is preferentially placed in the register. Decide on memory,
In the update, according to a variable used when the processor core executes the converted instruction code, information on the past use frequency of the variable included in the conversion table is updated, and the variable Updating information on average usage frequency of the variable included in the conversion table based on information on past usage frequency;
The register arrangement optimizing method according to supplementary note 1, wherein:
(Appendix 3)
The conversion table is a conversion table selected from a plurality of conversion tables according to the characteristics of input data processed by the processor.
The register arrangement optimizing method according to appendix 1 or 2, characterized in that:
(Appendix 4)
The input data is image data;
The selected conversion table is a conversion table selected according to an intra-frame difference or an inter-frame difference of the image data.
The register arrangement optimizing method according to supplementary note 3, characterized in that:
(Appendix 5)
In a processor including a processor core for executing an instruction code and a register, a program for optimizing a variable arranged in the register,
Refers to a conversion table that includes information on the location and usage frequency of variables defined in functions in the program, and preferentially allocates frequently used variables to the registers based on the usage frequency information of the variables. To determine the location of the variable in the register or memory,
Reflecting the determined variable placement destination in the variable placement destination information included in the conversion table,
Based on the information on the placement destination of the variable included in the conversion table, the pseudo instruction code in which the placement destination of the operand of the operation instruction is not specified is converted into an instruction code executable by the processor core,
Updating information on the frequency of use of the variables included in the conversion table according to the variables used when the processor core executes the converted instruction code;
A register placement optimization program that causes a computer to execute the process.
(Appendix 6)
The information on the frequency of use of the variable included in the conversion table includes information on the average use frequency and past use frequency of the variable,
In the determination, based on the information on the average use frequency of the variable included in the conversion table, the variable placement destination is set to the register or the above so that a variable having a high average use frequency is preferentially placed in the register. Decide on memory,
In the update, according to a variable used when the processor core executes the converted instruction code, information on the past use frequency of the variable included in the conversion table is updated, and the variable Updating information on average usage frequency of the variable included in the conversion table based on information on past usage frequency;
The register arrangement optimizing program according to appendix 5, characterized in that:
(Appendix 7)
The conversion table is a conversion table selected from a plurality of conversion tables according to the characteristics of input data processed by the processor.
The register arrangement optimizing program according to appendix 5 or 6, characterized in that:
(Appendix 8)
The input data is image data;
The selected conversion table is a conversion table selected according to an intra-frame difference or an inter-frame difference of the image data.
The register arrangement optimizing program according to appendix 7, wherein
(Appendix 9)
In a processor including a processor core for executing an instruction code and a register, an apparatus for optimizing a variable arranged in the register,
A conversion table containing information on the location and frequency of use of variables defined in the functions in the program;
An instruction conversion unit that converts a pseudo instruction code in which an operand placement destination of an operation instruction is not designated into an instruction code executable by the processor core based on information on a placement destination of the variable included in the conversion table; ,
With
The instruction conversion unit includes:
Based on the information on the frequency of use of the variable included in the conversion table, the variable placement destination is determined in the register or the memory so that the frequently used variable is preferentially placed in the register,
Reflecting the determined variable placement destination in the variable placement destination information included in the conversion table,
Updating information on the frequency of use of the variables included in the conversion table according to the variables used when the processor core executes the converted instruction code;
A register arrangement optimizing device characterized by that.
(Appendix 10)
The information on the frequency of use of the variable included in the conversion table includes information on the average use frequency and past use frequency of the variable,
The instruction conversion unit includes:
Based on the information on the average use frequency of the variable included in the conversion table, the variable placement destination is determined in the register or the memory so that a variable with a high average use frequency is preferentially placed in the register. ,
According to a variable used when the processor core executes the converted instruction code, information on the past use frequency of the variable included in the conversion table is updated, and the past use frequency of the variable is updated. Updating the information on the average use frequency of the variables included in the conversion table based on the information of
The register arrangement optimizing device according to appendix 9, wherein
(Appendix 11)
A table selection unit that selects a conversion table according to the characteristics of the input data processed by the processor from a plurality of conversion tables;
The conversion table referred to and updated by the instruction conversion unit is a conversion table selected by the table selection unit.
The register arrangement optimizing device according to appendix 9 or 10, wherein
(Appendix 12)
The input data is image data;
The table selection unit selects a conversion table corresponding to an intra-frame difference or inter-frame difference of image data processed by the processor from the plurality of conversion tables.
The register arrangement optimizing device according to appendix 11, wherein

110 processor CPU section 111 processor core 112 register 113 instruction cache 114 data cache 115 system bus controller 116 internal memory 117 instruction conversion unit 118 conversion map table 120 main memory section 121 processing program storage area 122 processing data storage area 123 processing result storage area 130 Memory controller unit 140 Peripheral input / output IF unit 150 Communication IF unit 160 System bus 171 Instruction cache 172 Instruction fetch unit 173 Byte code accelerator unit 173
174 Selector 175 Decoding unit 210 Image processor 220 Video input I / F unit 230 Video output I / F unit 311 Input image feature calculation unit

Claims (6)

In a processor including a processor core for executing an instruction code and a register, a method for optimizing a variable arranged in the register,
Refers to a conversion table that includes information on the location and usage frequency of variables defined in functions in the program, and preferentially allocates frequently used variables to the registers based on the usage frequency information of the variables. To determine the location of the variable in the register or memory,
Reflecting the determined variable placement destination in the variable placement destination information included in the conversion table,
Based on the information on the placement destination of the variable included in the conversion table, the pseudo instruction code in which the placement destination of the operand of the operation instruction is not specified is converted into an instruction code executable by the processor core,
Updating information on the frequency of use of the variables included in the conversion table according to the variables used when the processor core executes the converted instruction code;
A register arrangement optimizing method characterized by the above. The information on the frequency of use of the variable included in the conversion table includes information on the average use frequency and past use frequency of the variable,
In the determination, based on the information on the average use frequency of the variable included in the conversion table, the variable placement destination is set to the register or the above so that a variable having a high average use frequency is preferentially placed in the register. Decide on memory,
In the update, according to a variable used when the processor core executes the converted instruction code, information on the past use frequency of the variable included in the conversion table is updated, and the variable Updating information on average usage frequency of the variable included in the conversion table based on information on past usage frequency;
The register arrangement optimizing method according to claim 1. The conversion table is a conversion table selected from a plurality of conversion tables according to the characteristics of input data processed by the processor.
3. The register arrangement optimizing method according to claim 1, wherein the register arrangement is optimized. The input data is image data;
The selected conversion table is a conversion table selected according to an intra-frame difference or an inter-frame difference of the image data.
4. The register arrangement optimizing method according to claim 3, wherein: In a processor including a processor core for executing an instruction code and a register, a program for optimizing a variable arranged in the register,
Refers to a conversion table that includes information on the location and usage frequency of variables defined in functions in the program, and preferentially allocates frequently used variables to the registers based on the usage frequency information of the variables. To determine the location of the variable in the register or memory,
Reflecting the determined variable placement destination in the variable placement destination information included in the conversion table,
Based on the information on the placement destination of the variable included in the conversion table, the pseudo instruction code in which the placement destination of the operand of the operation instruction is not specified is converted into an instruction code executable by the processor core,
Updating information on the frequency of use of the variables included in the conversion table according to the variables used when the processor core executes the converted instruction code;
A register placement optimization program that causes a computer to execute the process. In a processor including a processor core for executing an instruction code and a register, an apparatus for optimizing a variable arranged in the register,
A conversion table containing information on the location and frequency of use of variables defined in the functions in the program;
An instruction conversion unit that converts a pseudo instruction code in which an operand placement destination of an operation instruction is not designated into an instruction code executable by the processor core based on information on a placement destination of the variable included in the conversion table; ,
With
The instruction conversion unit includes:
Based on the information on the frequency of use of the variable included in the conversion table, the variable placement destination is determined in the register or the memory so that the frequently used variable is preferentially placed in the register,
Reflecting the determined variable placement destination in the variable placement destination information included in the conversion table,
Updating information on the frequency of use of the variables included in the conversion table according to the variables used when the processor core executes the converted instruction code;
A register arrangement optimizing device characterized by that.