JP5617761B2 - Computer system, computer, and interrupt processing method for computer system - Google Patents

Description

The present invention, when a plurality of devices to notify the interruption to the computer shares the interrupt signal line, to a computer system to execute the identified interrupt processing device that generated the interrupt.

As a multi-operating computer system that performs interrupt processing by switching between multiple operating systems (OS) when multiple devices share the same interrupt number, the inter-OS controller has conventionally determined the device that generated the interrupt. In some cases, an OS assigned to a device that generates an interrupt is started from a plurality of OSs (see, for example, Patent Document 1).

JP 2001-229038 A

In a system in which a plurality of devices as described above share an interrupt signal line, the inter-OS control unit starts the OS assigned to the device that generated the interrupt, and then the OS checks the device that generated the interrupt. There are many cases.

However, when the device identification register is configured by a register that is cleared by reading, the value of the device identification register is cleared when the inter-OS control unit refers to this register, and then the OS that has started up confirms the interrupt generation device. There was a problem that it was not possible.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a computer system that can confirm an interrupt generation device from an OS regardless of the type of a device identification register.

The computer system according to the present invention is connected to a plurality of devices via an interrupt signal line shared by the plurality of devices, and when an interrupt occurs in the plurality of devices , the computer system starts from any one of the plurality of devices. And a computer that activates an OS corresponding to a device that has generated the interrupt among a plurality of OSs. The computer generates an interrupt among the plurality of devices. When an interrupt occurs from any of the plurality of devices, the information table storing information for determining the device that has determined the device that generated the interrupt with reference to the information table, and the interrupt An interrupt determination unit for transmitting an interrupt generation signal indicating that an interrupt has occurred in the OS corresponding to the generated device; The confirmation signal for confirming the device that has generated the interrupt is transmitted from the OS that has received the generation signal, and the interrupt has generated information on the device that has generated the interrupt determined by the interrupt determination unit. And an interrupt generation simulation unit that transmits to an OS corresponding to the device.

A computer according to the present invention is a computer that is connected to a plurality of devices sharing an interrupt signal line by the interrupt signal line, and activates an OS corresponding to a device in which an interrupt has occurred among the plurality of devices. An information table that stores information for determining the device that has generated an interrupt, and when an interrupt has occurred from any of the plurality of devices, the device that has generated the interrupt is determined by referring to the information table An interrupt determination unit that transmits an interrupt generation signal indicating that an interrupt has occurred in an OS corresponding to the device that has generated the interrupt, and a device that has generated the interrupt transmitted from the OS that has received the interrupt generation signal. A device that has received a confirmation signal for confirmation and has generated the interrupt determined by the interrupt determination unit. Information about scan and having a, interrupt generator simulation part that transmits to the OS.

An interrupt processing method for a computer system according to the present invention is connected to a plurality of devices via an interrupt signal line shared by the plurality of devices, and when an interrupt occurs in the plurality of devices, An interrupt processing method for a computer system, comprising: a computer that determines whether the interrupt is from any one of them and activates an OS corresponding to the device that has generated the interrupt; A determination step of determining a device that has generated an interrupt with reference to an information table that stores information for determining a device that has generated an interrupt among the plurality of devices.
A step of transmitting an interrupt generation signal indicating that an interrupt has occurred in the OS corresponding to the device that has generated the interrupt; and a confirmation signal for confirming the device that has generated the interrupt transmitted by the OS that has received the interrupt generation signal And a response step of transmitting information related to the device that has generated the interrupt determined by the interrupt determination unit to the OS.

According to the present invention, the computer system, the computer , and the interrupt processing method of the computer system have the above-described configuration, so that the interrupt generation device can be confirmed from the OS regardless of the type of the device identification register.

1 is a diagram illustrating a configuration of a computer system according to a first embodiment. 2 is a functional block diagram of a computer system according to Embodiment 1. FIG. 6 is a diagram illustrating an example of a shared interrupt determination table according to Embodiment 1. FIG. 6 is a sequence diagram illustrating a procedure for registering information in a shared interrupt determination table according to Embodiment 1. FIG. FIG. 3 is a sequence diagram illustrating an interrupt processing procedure of the computer system according to the first embodiment. 6 is a sequence diagram illustrating a procedure for deleting information from a shared interrupt determination table according to Embodiment 1. FIG.

Embodiment 1 FIG.
A computer system according to Embodiment 1 for carrying out the present invention will be described with reference to FIGS.

In FIG. 1, a computer system 1 includes a computer 2 and peripheral devices such as a keyboard 31, a mouse 32, a display 33, a printer 34, a scanner 35, and an external hard disk 36 connected to the computer 2 via a cable or a network. A certain device 3 is provided. The computer 2 includes a CPU 4, an interrupt controller 5, a memory 6, an interrupt signal line 7, and the like. Part or all of the device 3 may be built in the computer 2.

Each device 3 provided inside and outside the computer 2 is connected to an interrupt controller 5 via a PCI (Peripheral Component Interconnect) bus 8 and shares an interrupt signal line 7 among a plurality of devices 3. The number of interrupt signal lines 7 provided in the computer 2 is usually smaller than the number of devices 3 connected to the PCI bus. For this reason, each device 3 shares the interrupt signal line 7, but can also be shared when the number of interrupt signal lines 7 is equal to or greater than the number of devices 3 connected by the PCI bus.

FIG. 2 is a functional block diagram illustrating an example of the computer system 1.
The computer system 1 includes a hardware device unit 30, a software virtual machine monitor 10, and an operating system unit 20 (hereinafter referred to as an OS unit 20). The virtual machine monitor 10 and the OS unit 20 configured by software are physically stored in the memory 6 and operate according to a command (instruction) from the CPU 4.
The device unit 30 may be a generic name of the devices 3A to 3C and may not be provided as a physical configuration. Similarly, the OS unit 20 may be a generic name of the OSs 21A to 21C and may not be provided as a physical configuration.

In the example of FIG. 2, the OS unit 20 is provided with three OSs 21A to 21C for operating the devices 3A to 3C of the device unit 30, and each OS has one device driver 22A to 22C as software for recognizing the device. It is prepared one by one. The OS 21A to 21C are software that operates on the computer 2, and include, for example, Microsoft Windows (registered trademark), Linux (registered trademark), and a real-time OS. One OS may include a plurality of device drivers 22A to 22C. The OSs 21A to 21C may include application units 23A to 23C configured by one or a plurality of application programs operating on the OS.

The virtual machine monitor 10 is software that performs switching control of the OS 21A to 21C (or device drivers 22A to 22C) operating on the devices 3A to 3C of the device unit 30, and is also called a hypervisor or an inter-OS control unit.

The virtual machine monitor 10 registers / updates information in the shared interrupt determination table 11 that stores information necessary for determining the device that has generated the interrupt, and in accordance with instructions from the OSs 21A to 21C. The shared interrupt determination table registration unit 12 that performs deletion, the information stored in the shared interrupt determination table 11, and the shared interrupt determination unit 13 that determines which device has generated the interrupt, and the devices 3A to 3C An interrupt generation simulation unit 14 is provided that receives confirmation access from the OS 21A to 21C to the devices 3A to 3C when an interrupt occurs from the OS 3A to 3C, and responds by simulating the interrupt generation of the devices 3A to 3C.

The device unit 30 includes three devices 3A to 3C. The devices 3A to 3C play the same role depending on whether they are built in the computer 2 or externally connected, and are not distinguished in FIG.

FIG. 3 shows an example of the shared interrupt determination table 11. For each device 3, (a) I / O address information of the interrupt generation flag register, (b) a bit mask value for determining whether an interrupt has occurred, (c) a value of the interrupt generation flag register when no interrupt occurs One by one.

The interrupt generation flag register is a register provided in each device 3 for identifying whether or not an interrupt has occurred. Normally, data is read and written in units of a plurality of bits, but the interrupt generation flag register is about 1 bit or several bits. Therefore, (b) is used to mask a register unnecessary for identifying the occurrence of an interrupt among the data corresponding to the I / O address read in (a).

Here, the operation of the computer system 1 will be described.

・ Registering information in the shared interrupt judgment table

As shown in FIG. 4, the OS 21A-21C provided in the OS unit 20 calls the shared interrupt determination table registration unit 12 by transmitting an instruction from a transmission unit (not shown), and the application program 23A- Information on 23C and device drivers 22A to 22C is registered in the shared interrupt determination table 11 (step S101). The call can be made by using a hyper call, which is a service call provided by the virtual machine monitor 10, for example.

The shared interrupt determination table registration unit 12 creates a shared interrupt determination table 11 for each of the devices 3A to 3C in accordance with instructions from the OS 21A to 21C, and registers the received information in the shared interrupt determination table 11 (step S102). If the shared interrupt determination table 11 has already been created, the shared interrupt determination table registration unit 12 updates the received information in accordance with instructions from the OSs 21A to 21C.

・ Overall processing when a shared interrupt occurs

As shown in FIG. 5, when an interrupt occurs in any of the devices 3 </ b> A to 3 </ b> C of the device unit 30, the device 3 that generated the interrupt sends an interrupt signal to the shared interrupt determination unit 13 via the interrupt signal line 7 of the PCI bus 8. Is transmitted (step S111, first transmission step).

When the shared interrupt determination unit 13 receives the interrupt signal, the shared interrupt determination unit 13 refers to the shared interrupt determination table 11, and determines a device that has generated an interrupt based on the reference result (step S112, reception step and determination step).
Specifically, when the shared interrupt determination unit 13 transmits an interrupt signal to the shared interrupt determination table 11, the shared interrupt determination table 11 determines (a) I / O address information of the interrupt generation flag register, and (b) determines whether an interrupt has occurred. A bit mask value to be used and (c) the value of the interrupt generation flag register when no interrupt has occurred are returned as a reference result.

The shared interrupt determination unit 13 accesses the received (a) I / O address of the interrupt generation flag register, and reads the data in the registers in the devices 3A to 3C corresponding to this I / O address. Since the read I / O address data includes values other than the interrupt occurrence flag register, the read I / O address data and the interrupt received from the shared interrupt determination table 11 are determined (b). The logical product (AND) with the bit mask value for this is taken.

Next, the logical product is compared with the value of the interrupt generation flag register received from the shared interrupt determination table 11 (c) when no interrupt occurs, and if they match, it is determined that this device is not the device that generated the interrupt. If they do not match, it is determined that this device is the device that generated the interrupt.

Here, the following description will be given assuming that the device 3A generates an interrupt.
When the shared interrupt determination unit 13 specifies the device 3A that has generated the interrupt, the shared interrupt determination unit 13 notifies the interrupt generation simulation unit 14 of the determination result (step S113). The interrupt generation simulation unit 14 that has received the notification of the determination result sets the virtual machine monitor 10 to be called when the confirmation signal for confirming the occurrence of the interrupt is transmitted from the OS 21A (step S114). For this setting, for example, the memory control unit (MMU) or the privileged mode of the CPU, the I / O access protection function by Intel VT (Virtualization Technology) or AMD-V (Virtualization) function is used to access this I / O address. This can be achieved by providing protection.

When the setting is completed, the interrupt generation simulation unit 14 notifies the shared interrupt determination unit 13 of this, and the shared interrupt determination unit 13 transmits an interrupt generation signal to the OS 21A provided with the device driver 22A corresponding to the interrupt generation device (step). S115, second transmission step).
When the devices that generate interrupts are the devices 3B and 3C, the device drivers 22B and 22C corresponding to these interrupt generating devices and the OS 21B and 21C including the devices operate in the same manner as the device drivers 22A and OS 21A. .

When the OS 21A receives the interrupt generation signal (step S116), the OS 21A confirms whether or not an interrupt has occurred to the device 3A that has generated the interrupt, and a confirmation signal (first step) for reading the interrupt generation flag register provided in the device 3A. 1 confirmation signal) is transmitted from the OS 21A to the device 3A via the device driver 22A or directly from the device driver 22A (step S117, confirmation step).
If the device that generated the interrupt is the device 3B or 3C, a device 3B confirmation signal (second confirmation signal) is transmitted from the device driver 22B or OS21B, and a device 3C confirmation signal is transmitted from the device driver 22C or OS21C. .

When the virtual machine monitor 10 detects this confirmation signal, the virtual machine monitor 10 notifies the interrupt generation simulation unit 14 (step S118), and the interrupt generation simulation unit 14 calls itself when the setting in step S114 is detected, that is, when the confirmation signal is detected. The setting for the monitor 10 is canceled (step S119).

Next, the interrupt generation simulation unit 14 simulates the device 3A that generated the interrupt according to the determination result notified in step S113 with respect to the received confirmation signal, and sets the value of the interrupt generation flag register of this device to the OS 21A or device driver. A reply is made to 22A (step S120, response step).

Upon receiving the value of the interrupt generation flag register from the interrupt generation simulation unit 14, the OS 21A or the device driver 22A confirms the generation of the interrupt of the corresponding device 3A (step S121), and executes interrupt processing for the device 3A (step S121). S122).

・ Deleting information from the shared interrupt judgment table

Here, a deletion procedure when registration information in the shared interrupt determination table 11 becomes unnecessary due to replacement of the device 3 or the like will be described with reference to FIG.

The OS 21 invalidates and unloads the device driver 22, and calls the shared interrupt determination table registration unit 12 according to an instruction (command) from the application unit 23 or the device driver 22 executed in accordance with the invalidation or unload (step S131).

The shared interrupt determination table registration unit 12 notifies the virtual machine monitor 10 of the interrupt generation simulation unit 14 that the setting is canceled when the setting in step S114 (setting to call itself when a confirmation signal is detected) is made. In response to this notification, the interrupt generation simulation unit 14 cancels the setting for the virtual machine monitor 10 (step S133).

When the cancellation of the setting of the interrupt generation simulation unit 14 for the virtual machine monitor 10 is confirmed by the notification from the interrupt generation simulation unit 14 or the virtual machine monitor 10 or by its own detection, the shared interrupt determination table registration unit 12 is shared according to the instruction from the OS 21. Information about the device 3 instructed from the interrupt determination table 11 is deleted (step S134). The information regarding the device 3 includes, for example, the identifier of the device 3, the address information of the I / O register, the bit information of the interrupt generation flag register, the data information when no interrupt of the I / O register has occurred.
Note that the shared interrupt determination table 11 may be deleted when all information related to the device 3 is deleted.

According to the present embodiment, the computer system 1 retains the shared interrupt determination unit 13 that determines the device 3 on which the virtual machine monitor 10 has generated an interrupt, and information on the interrupt generation device, from the OS 21 or the device driver 22. The OS 21 does not directly access the interrupt generation flag register of the device 3 by providing the interrupt generation simulation unit 14 that returns a response simulating the device 3 in response to the interrupt generation confirmation signal that is transmitted. It is possible to confirm whether or not the interrupt of the device 3 has occurred. Thereby, even if the interrupt generation flag register provided in the device 3 is a register that is cleared by reading, the device 3 that has generated the interrupt from the OS 21 can be confirmed.

Even if the device 3 used by the computer system 1 is added, the interrupt of the device 3 can be interrupted by updating the information in the shared interrupt determination table 11 without changing the configuration of the OS unit 20 or the virtual machine monitor 10. It can also be determined.

In the above embodiment, as an example, the “information table” is “shared interrupt determination table”, the “information table registration update unit” is “shared interrupt determination table registration unit”, and the “interrupt determination unit” is “shared interrupt determination”. Part ". The name is not limited to the above, but may be “˜means”, “˜program” or the like as long as the same function is achieved.

1 computer system 2 computers 3, 3A to 3C device 7 interrupt signal line 8 PCI (Peripheral Component Interconnect) bus
10 Virtual machine monitor
11 Shared interrupt judgment table
12 Shared interrupt judgment table registration part
13 Shared interrupt judgment block
14 Interrupt generation simulator
20 OS (Operating System)
21, 21A-21C OS
22, 22A-22C Device driver

Claims (5)

Multiple devices,
Connected via an interrupt signal line shared by the plurality of devices,
A computer that, when an interrupt occurs in the plurality of devices, determines whether the interrupt is from any of the plurality of devices, and activates an OS corresponding to the device that generated the interrupt among the plurality of OSs; ,
In a computer system equipped with
The calculator is
An information table storing information for determining a device in which an interrupt has occurred among the plurality of devices;
When an interrupt is generated from any of the plurality of devices, the information table is referred to determine a device that has generated the interrupt, and indicates that an interrupt has occurred in the OS corresponding to the device that has generated the interrupt An interrupt determination unit for transmitting an interrupt generation signal;
The interrupt that receives the confirmation signal for confirming the device that has generated the interrupt is transmitted from the OS that has received the interrupt generation signal, and the interrupt generates information on the device that has generated the interrupt determined by the interrupt determination unit An interrupt generation simulator that transmits to the OS corresponding to the device
A computer system characterized by comprising: The plurality of devices include an interrupt generation flag register for identifying whether or not an interrupt has occurred,
The information for determining the device in which the interrupt has occurred has address information of the interrupt generation flag register,
The interrupt determination unit, when an interrupt occurs from any of the plurality of devices, refers to the information table, the interrupt generation of the device that has generated the interrupt based on the address information of the interrupt generation flag register The computer system according to claim 1, wherein a device in which an interrupt has occurred is determined by accessing a flag register. The calculator is
2. The computer system according to claim 1, further comprising: an information table registration / updating unit that instructs to register, change, or delete information for determining a device in which the interrupt occurs that is stored in the information table. . In a computer that is connected to a plurality of devices that share an interrupt signal line by the interrupt signal line and that starts an OS corresponding to a device that has generated an interrupt among the plurality of devices,
An information table storing information for determining a device that has generated an interrupt among the plurality of devices;
When an interrupt is generated from any of the plurality of devices, the information table is referred to determine a device that has generated the interrupt, and indicates that an interrupt has occurred in the OS corresponding to the device that has generated the interrupt An interrupt determination unit for transmitting an interrupt generation signal;
The confirmation signal for confirming the device that has generated the interrupt is transmitted from the OS that has received the interrupt generation signal, and information related to the device that has generated the interrupt determined by the interrupt determination unit is transmitted to the OS Interrupt generation simulator
A computer characterized by comprising: Multiple devices,
Connected via an interrupt signal line shared by the plurality of devices,
A computer that, when an interrupt occurs in the plurality of devices, determines whether the interrupt is from any of the plurality of devices, and starts up an OS corresponding to the device that generated the interrupt; In the system interrupt handling method,
When an interrupt occurs from any of the plurality of devices, the information table storing information for determining the device that has generated the interrupt among the plurality of devices is referred to, and the device that has generated the interrupt is determined. A determination step;
Transmitting an interrupt generation signal indicating that an interrupt has occurred to an OS corresponding to the device that has generated the interrupt;
Receiving a confirmation signal for confirming a device that has generated an interrupt transmitted by the OS that has received the interrupt generation signal;
A response step of transmitting, to the OS, information related to the device that has generated the interrupt determined by the interrupt determination unit;
An interrupt processing method for a computer system, comprising:

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