JP5614241B2 - Ferroelectric memory and operation method thereof - Google Patents

Description

  The present invention relates to a ferroelectric memory and an operation method thereof.

  A ferroelectric memory (FeRAM) stores data 0 and 1 by setting the ferroelectric capacitor in different polarization states, and reads out the data using the magnitude of the amount of charge output according to the polarization state. Since the polarization state is maintained even when the power is cut off, the ferroelectric memory is a nonvolatile memory. Further, this nonvolatile memory can be accessed at high speed.

  In the ferroelectric memory, a 1T1C type FeRAM in which a memory cell is composed of one MOSFET and one ferroelectric capacitor, and a memory cell is composed of two MOSFETs and two ferroelectric capacitors. There is 2T2C type FeRAM. In either case, writing is performed by driving a word line connected to the gate of the MOSFET, which is an access gate, so that the ferroelectric capacitor is polarized according to the potential of the bit line. In reading, the word line is driven to make the access gate conductive, the plate line connected to the opposite electrode of the ferroelectric capacitor is driven to output the charge corresponding to the polarization state to the bit line, Data is sensed according to the amount of charge.

  In addition, since the conventional SRAM loses data when the power is cut off, it has been proposed to provide a ferroelectric capacitor in each memory cell. In such SRAM, data in the cell is stored in the ferroelectric capacitor by the store operation, and data stored in the ferroelectric capacitor is written in the memory cell of the SRAM by the recall operation.

JP 2003-59259 A JP 2003-258626 A Japanese Patent Application Laid-Open No. 2004-146048 International Publication No. 2000/70622

  In a ferroelectric memory, in order to polarize a ferroelectric capacitor in a memory cell, the word line is boosted to a voltage higher than the power supply voltage and the power supply voltage is applied to the ferroelectric capacitor in the memory cell. ing.

  However, in recent miniaturized MOSFETs, the gate oxide film becomes thinner, and it has become difficult to apply a boosted voltage higher than the power supply voltage to the gate. As a result, a sufficiently high voltage cannot be applied to the ferroelectric capacitor, and a sufficient charge cannot be output in the read operation, resulting in a decrease in the read margin.

  Accordingly, an object of the present invention is to provide a ferroelectric memory capable of applying a power supply voltage to a ferroelectric capacitor without boosting a word line.

The first aspect of ferroelectric memory is
Multiple word lines,
Multiple plate wires,
Multiple bit line pairs;
Multiple charge lines,
A pair of first conductivity type MOSFETs each having a gate connected to the word line and a first source / drain connected to the bit line pair; a second source / drain of the pair of first conductivity type MOSFETs; A pair of ferroelectric capacitors respectively provided between the plate lines and a pair of second conductivity types provided between the pair of ferroelectric capacitors and the charge line and having a gate and a drain cross-connected to each other A plurality of memory cells each having a MOSFET;
A charge line driving circuit for driving the charge line to a power supply voltage during a read operation and a write operation.

  According to the first aspect, the node in the memory cell can be set to the power supply voltage (VDD) potential by the charge line without boosting the word line, so that a sufficiently polarized state can be written.

It is a circuit diagram of a memory cell of FeRAM. It is a wave form diagram which shows operation | movement of FeRAM of FIG. FIG. 3 is a circuit diagram of a FeRAM memory cell in the present embodiment. FIG. 4 is a diagram showing a read operation and a write operation in the FeRAM in FIG. 3. FIG. 4 is a diagram illustrating another read operation and write operation in the FeRAM of FIG. 3. It is a top view which shows the device structure of the memory cell array of FeRAM in this Embodiment. It is a top view which shows the device structure of the memory cell array of FeRAM in this Embodiment. FIG. 2 is a plan view and a cross-sectional view showing a device structure of a FeRAM memory cell array in the present embodiment. FIG. 2 is a plan view and a cross-sectional view showing a device structure of a FeRAM memory cell array in the present embodiment.

  FIG. 1 is a circuit diagram of a FeRAM memory cell. FIG. 1 shows memory cells MC20 and MC21 in one row and two columns. Each memory cell MC20, MC21 has an N-type MOSFET access gate N21, N22, N23 having a gate connected to the word line WL2 and a first source / drain connected to the bit lines BL20, / BL20, BL21, / BL21, respectively. , N24 and ferroelectric capacitors C21, C22, C23, C24 provided between the second source / drain of the access gates and the plate line PL2.

  A pair of ferroelectric capacitors C21 to C24 of each memory cell are polarized in different directions by the write operation to store complementary data, and the plate line PL2 is driven to the H level in the read operation to cope with the polarization state. This amount of charge is output to the bit line, and the recording data is read out via the bit line pair.

  FIG. 2 is a waveform diagram showing the operation of the FeRAM in FIG. In the read operation, at time t601, the word line WL2 is driven from the ground potential to the power supply voltage VDD and the access gates N21-N24 are conducted, and at time t602, the plate line PL2 is driven from the ground potential to the power supply voltage VDD, and the capacitors C21, Charges corresponding to the polarization state are output from C22 to the bit lines BL20 and / BL20. In this example, when the plate line PL2 is driven, the capacitor C21 operates as a P term, the C22 operates as a U term, and the capacitor C21 outputs more charge. As a result, the bit line BL20 rises higher than the bit line / BL21 out of the bit line pair BL20, / BL20 at the ground potential. At this time, both capacitors are in the same polarization state.

  When the sense amplifier connected to the bit line pair is activated at time t603, the bit line BL20 is driven to the power supply voltage VDD, and the bit line / BL21 is driven to the ground potential. As a result, the data in the memory cell is output from the sense amplifier.

  Further, at time t603 to t605, since the plate line PL2 is at the power supply voltage VDD and the node n22 in the memory cell is at the ground potential, the capacitor C22 remains in the original U-term polarization state. On the other hand, when the plate line PL2 is pulled down from the power supply voltage VDD to the ground at time t606, since the node n21 is at the H level, the capacitor C21 is returned to the original P-term polarization state. In this rewriting operation to the capacitor C21, at time t605, the word line WL2 is boosted from the power supply voltage VDD to the threshold voltage Vth or higher of the access gate N21 which is an NMOSFET. As a result, the node n21 in the memory cell is pulled up to the power supply voltage VDD, and the capacitor C21 can be in a sufficiently polarized state.

  The write operation is equivalent to the read operation at times t611 to t614. Then, at time t614, the write amplifier connected to the bit line is activated, and in this example, the bit line BL20 is inverted and driven to the L level and / BL20 to the H level, respectively. Since the bit line BL20 is driven to the L level, the plate line PL2 is driven to the power supply voltage VDD, so that the inverted data opposite to the original data is written into the capacitor C21. Further, at time t615, the word line WL2 is boosted from the power supply voltage VDD to the threshold voltage Vth or more, and at time t616, the plate line PL2 is pulled down to the ground potential. The node n22 in the memory cell is pulled up to the power supply voltage VDD by the boosting operation of the word line WL2, and data opposite to the original data is written into the capacitor C22. By this write operation, the capacitor C21 is polarized in the U-term state and C22 is polarized in the P-term state.

  As described above, as shown in FIG. 1, the word line WL2 is driven higher than the power supply voltage VDD by a threshold voltage or more at the same timing as when the plate line PL2 is pulled down during the rewrite in the read operation and the write operation. . By driving the word line, the power supply voltage of the bit line can be transmitted to the nodes n21 and n22 in the memory cell, and rewriting or writing can be performed in a sufficiently polarized state.

  However, since the gate oxide film of a miniaturized MOSFET has become thinner in recent years, it is difficult to boost the word line higher than the power supply voltage from the viewpoint of MOSFET reliability. Therefore, it is desirable to drive the node in the memory cell to the power supply voltage without boosting the word line above the power supply voltage so that the capacitor is in a sufficiently polarized state.

  FIG. 3 is a circuit diagram of the FeRAM memory cell according to the present embodiment. FIG. 3 also shows memory cells MC10 and MC11 of 1 row and 2 columns. The word line WL1 extends in the row direction, the bit line pairs BL10, / B10, BL11, / BL11 extend in the column direction, and memory cells MC10, MC11 are arranged at the intersections thereof. Each memory cell has an N-type MOSFET access gate N11, N12, N13, N14 having a gate connected to the word line WL1 and a first source / drain connected to the bit lines BL10, / BL10, BL11, / BL11, respectively. , Ferroelectric capacitors C11, C12, C13, and C14 provided between the second source / drain of the access gates and the plate line PL2. The steps so far are the same as in FIG.

  In this example, the plate line PL1 and the charge line CL1 are provided extending in the row direction together with the word line WL1. However, these extending directions are not limited to this.

  Further, each of the memory cells MC10 and MC11 has P11, P12 and P13, P14 which are P-type MOSFETs whose drains and gates are cross-connected between the internal nodes n11, n12 and n13, n14 and the charge line CL1. Have. The word line WL1 is driven by the word line drive circuit WLDR, the plate line PL1 is driven by the plate line drive circuit PLDR, and the charge line CL1 is driven by the charge line drive circuit CLDR. The bit line pairs BL10, / BL10 and BL11, / BL11 are provided with sense amplifiers and write amplifiers SA0, WA0 and SA1, WA1, respectively.

  The charge line CL is maintained at the ground potential in the memory cell connected to the non-selected word line WL. On the other hand, the charge line CL1 in the memory cell connected to the selected word line is at least a period during which the word line is boosted higher than the power supply voltage in FIG. Or during P-term write during write operation), it is driven to the power supply voltage VDD. As a result, the node on the H level side in the memory cell is boosted to the power supply voltage level of the charge line CL1 by the cross-connected PMOSFET, and the capacitor is written in a sufficiently polarized state. This is because, when the polarization of the ferroelectric capacitor is reversed, applying as high a voltage as possible increases the amount of retained polarization and contributes to the reversal in a short time.

  Outside the above period, the charge line CL1 is maintained at the ground potential. Therefore, an increase in current consumption due to the provision of the charge line CL1 can be minimized.

  Since it is not necessary to boost the selected word line higher than the threshold voltage above the power supply voltage, the word line driving circuit can be simplified and the reliability is improved from the viewpoint of the gate breakdown voltage of the access gate. be able to.

  FIG. 4 is a diagram showing a read operation and a write operation in the FeRAM of FIG. In the example of FIG. 4, time t401 to t407 indicate a read operation (Read) and its rewrite operation, and the P term of the capacitor C11 and the U term of C12 in the memory cell M10 are read. In the example of FIG. 4, time t411 to t418 indicates a write operation (Write), and inverted data is written to the capacitors C11 and C12 in the memory cell M10.

  First, in a read operation (Read), at time t401, the bit lines BL10 and / BL10 are precharged to the ground potential to be in a high impedance state. At time t401, the word line driving circuit WLDR drives the word line WL1 from the ground potential to the power supply voltage VDD. As a result, the access gates N11 to N14 of the NMOSFET become conductive, and the nodes n11 to n14 in the memory cell are connected to the respective bit lines. The power supply voltage VDD may be an internal power supply voltage in the memory cell array, and may be an externally supplied power supply voltage or an internally generated internal power supply voltage.

  Thereafter, at time t402, the plate line drive circuit PLDR drives the plate line PL1 connected to the selected memory cell from the ground potential to the power supply voltage VDD. As a result, a voltage is applied to the capacitors C11 to C14 in the memory cell, and a large amount of charge is output to the bit line BL10 from the capacitor C11 accompanied by polarization inversion (P term), and the bit line BL10 has a relatively high potential. On the other hand, a small amount of charge is output to the bit line / BL10 from the capacitor C12 without polarization inversion (U-term), and the bit line / BL10 becomes a relatively low potential.

  Since the charge line CL1 is at the ground potential so far, the PMOSFETs P11 to P14 are in a non-conducting state, and the operation so far is the same as in FIG.

  Therefore, at time t403, the sense amplifier provided in the bit line pair is activated, the bit line BL10 is raised to the power supply voltage VDD, and the bit line / BL10 is lowered to the ground potential. In response, node n11 in memory cell MC10 rises and node n12 falls to the ground potential. Further, in the example of FIG. 4, at time t403, the charge line drive circuit CLDR drives the charge line CL1 from the ground potential to the power supply voltage VDD simultaneously with the activation of the sense amplifier SA. By driving the charge line CL1 to the power supply voltage VDD, among the PMOSFETs P11 and P12 whose gates and drains are cross-coupled, the PMOSFET P11 side whose gate is connected to the node n12 to be lowered becomes conductive, and the node n11 The voltage rises to VDD. In other words, since the word line WL1 is driven only to the power supply voltage, the node n11 rises only to VDD-Vth (Vth is the threshold voltage of N11) via the NMOSFET N11, but is driven to the power supply voltage VDD by the PMOSFET P11. The On the other hand, PMOSFET P12 is turned off because its gate is higher than VDD-Vth, and node n12 remains at the ground potential.

  From time t403 to t405, a rewrite operation associated with the read operation is performed. From time t403 to t404, since the plate line PL1 is at the power supply voltage VDD and the node n12 is at the ground potential, U-term writing is performed on the capacitor C12, and the polarization direction of the capacitor C12 is positive on the plate line PL1 side and negative on the node n12 side. become. On the other hand, the capacitor C11 is not written because both electrodes are at the power supply voltage VDD and there is no potential difference between the electrodes.

  At time t404, the plate line PL1 is lowered to the ground potential. Therefore, the node n11 becomes the power supply voltage VDD and the plate line PL1 becomes the ground potential, and P-term writing is performed on the capacitor C11. The polarization direction of the capacitor C11 is positive on the node n11 side and negative on the plate line PL1 side. On the other hand, the capacitor C12 is not written because both electrodes are at ground potential and there is no potential difference between the electrodes.

  Next, at time t405, the word line driving circuit WLDR causes the word line WL1 to fall from the power supply voltage VDD to the ground potential, the access gates N11 and N12 become non-conductive, and the nodes n11 and n12 in the memory cell become bit lines. Separated from the pair. Then, at time t406, when the charge line CL1 is pulled down to the ground potential, the node n11 on the H level side is lowered to about VDD-Vth through the PMOSFET P11 which is in a conductive state, and then gradually due to the leakage current. To ground potential.

  At time t407, the sense amplifier SA is deactivated and both bit line pairs are precharged to the ground potential. This completes the read operation cycle. The fall of the word line WL1 at time t405 needs to be performed before the precharge operation to the ground potential of the bit line pair. If the word line WL1 is at the power supply voltage VDD when the bit line pair is precharged to the ground potential, the nodes n11 and n12 are set to the ground potential via the access gates N11 and N12, and the memory becomes indefinite. It is. Further, after the word line WL1 is lowered, the timing of the fall of the charge line CL1 and the timing of precharging the bit line pair to the ground potential may be mixed.

  Next, the write operation (Write) will be described. As described above, before time t411, in the memory cell MC10, the capacitor C11 is written in the P term, and C12 is written in the U term. The bit line pair is precharged to the ground and is in a high impedance state.

  Therefore, the word line WL1 rises from the ground potential to the power supply voltage VDD at time t411, the plate line PL1 rises to the power supply voltage VDD at time t412, and the charge line CL1 rises to the power supply voltage VDD at time t413. This operation is the same as the times t401, t402, and t403 in the read operation.

  At time t414, the sense amplifier SA is deactivated, the write amplifier WA is activated, the bit line BL10 is driven to the ground potential, and the bit line / BL10 is driven to the power supply voltage VDD. That is, the potential of the bit line pair is inverted. This starts rewriting.

  Thereafter, in the period from time t414 to t415, U-term writing is performed on the capacitor C11, and at time t415, the plate line PL1 is lowered from the power supply voltage VDD to the ground potential, similarly to the rewriting in the reading operation. P-term writing is performed on the capacitor C12 during a period of time t415 to t416.

  Further, at time t416, the word line WL1 is lowered to the ground potential, at time t417, the charge line CL1 is lowered to the ground potential, and at time t418, the write amplifier WA is deactivated and the bit line pair is preliminarily set to the ground potential. Charged. The fall of the word line needs to be before the bit line pair is precharged to the ground potential, and after the fall of the word line, the time relationship between the fall of the charge line and the precharge of the bit line pair is arbitrary .

  As described above, in the present embodiment, a pair of PMOSFETs whose gates and drains are cross-connected are provided in the memory cell between the ferroelectric capacitors C11 and C12 and the charge line CL1, and the charge line CL1 is provided as a ferroelectric substance. At the time of writing to the capacitor (including rewriting in the reading operation), the power supply voltage VDD is raised. As a result, even if the word line is driven only to the power supply voltage, one of the nodes n11 and n12 in the memory cell can be driven to the power supply voltage, and a sufficiently polarized state can be written.

  FIG. 5 is a diagram showing another read operation and write operation in the FeRAM of FIG. In the example of FIG. 5, as in FIG. 4, time t501 to t508 indicate the read operation and the rewrite operation, and the P term of the capacitor C11 and the U term of C12 in the memory cell M10 are read. Times t511 to t518 indicate a write operation, and inverted data is written to the capacitors C11 and C12 in the memory cell M10.

  The operation of FIG. 5 differs from FIG. 4 in the following points. In the example of FIG. 5, in the read operation (Read), the timing at which the charge line CL1 rises is not the time t503 for activating the sense amplifier but the time t504 thereafter. In this way, by preventing the charge line CL1 from being raised at the activation timing of the sense amplifier, the operation of the pair of PMOSFETs in the memory cell affects the amplification operation of the sense amplifier connected to the bit line pair. Thus, an operation closer to the amplification operation of the sense amplifier in the read operation shown in FIG. 2 can be expected.

  However, between times t503 and t504, the potential of the node n11 in the memory cell is not the power supply voltage VDD but VDD-Vth. However, during this time, since the plate line PL1 is at the power supply voltage VDD, the U-term write is performed on the capacitor C12 side, and the rewrite to the capacitor C11 is not performed. Therefore, the charge line CL1 does not have to rise.

  Also in the write operation (Write), the timing at which the charge line CL1 rises is not the time t513 for activating the sense amplifier but the time t514 thereafter.

  In FIG. 5, in the read operation (Read), the rising timing of the charge line CL1 may be delayed until the time t505 when the plate line PL1 is lowered. Similarly, in the write operation (Write), the rise timing of the charge line CL1 may be delayed until the time t515 when the plate line PL1 is lowered. At the time of rewriting at the time of reading operation and at the time of writing operation, at least when the plate line PL1 of t505 to t507 and t515 to t518 is lowered from the power supply voltage and P-term writing is performed on one capacitor, at least the charge line CL1 Is driven by the power supply voltage VDD, the node n11 or n12 on the H level side in the cell can be driven by the PMOSFET to the power supply voltage VDD, and a sufficiently polarized state can be written.

  6, FIG. 7, FIG. 8, and FIG. 9 are a plan view and a cross-sectional view showing the device structure of the FeRAM memory cell array in this embodiment. FIG. 6 is a plan view, and of the two bit line pairs BL10, / BL10 and BL11, / BL11, the bit line pair BL11, / BL11 is indicated by a broken line.

  FIG. 7 shows that N-type regions nWELL and P-type regions Psub are alternately formed in a horizontal stripe pattern on the surface of a silicon substrate, and a polysilicon gate layer PolySi and a one-layer metal wiring M1 are formed thereon. The formed configuration is shown. This shows that the word line WL extends in the horizontal direction along with the striped N-type region nWELL and is connected to the gate electrode of the nMOS in the P-type region Psub. The gate electrode of the pMOS in the N-type region nWELL is also composed of a polysilicon gate layer PolySi. The P-type region Psub is a P-type substrate having a high-concentration P-type well region (not shown) on the surface, and the N-type region nWELL is an N-type well region provided in the P-type substrate.

  FIG. 8 shows the same plan view as FIG. 6 and a CC ′ sectional view. With reference to the plan view of FIG. 6 and the plan view of FIG. 7, the CC ′ sectional view in the direction of the bit line BL10 of FIG. 8 will be described. Striped N-type well regions nWELL extending in the horizontal direction in the plan view are formed in the P-type substrate Psub. An N-type source / drain S / D is formed in the P-type substrate Psub to form an NMOSFET. Further, a P-type source / drain is formed in the N-type well region nWELL to form a PMOSFET. Further, a word line WL, gates of NMOSFETs N11-N14, and gates of PMOSFETs P11-P14 are formed by a polysilicon gate layer PolySi formed on a gate oxide film (not shown).

  On the boundary line between the striped N-type well region nWELL and the P-type region Psub, there are a lower electrode layer serving as the lower electrode BEL and plate line PL of the ferroelectric capacitor, a ferroelectric layer, and an upper electrode TEL. Is formed. The upper electrode TEL is connected to the source / drain of the NMOSFETs N11-N14 and the source / drain of the PMOSFETs P11-P14 via the first layer metal wiring M1. That is, the upper electrode TEL corresponds to the nodes n11 and n12 in the cell.

  Then, a charge line CL extending in the horizontal direction in the plan view is formed by the two-layer metal wiring M2, and the charge line CL is connected to the other of the PMOSFETs P11 to P14 in the N-type well region nWELL via the contact VIA. Connected to source / drain region S / D. Bit line pairs BL10, / BL10, BL11, / BL11 extending in the vertical direction of the plan view are formed by the uppermost three-layer metal wiring M3.

  FIG. 9 shows the same plan view as FIG. 6 and d-d ′, e-e ′, and f-f ′ cross-sectional views in the word line WL direction. The dd ′ sectional view shows a P-type substrate Psub, a PMOSFET in an N-type well region nWELL formed therein, a single-layer metal wiring M1, and two layers extending from a horizontal charge line CL. A metal wiring M2 and a three-layer metal wiring M3 constituting the bit line pair BL10, / BL10 are shown.

  The ee ′ cross-sectional view shows a P-type substrate Psub, an N well region nWELL formed therein, a plate line PL also serving as a capacitor lower electrode BEL, an upper electrode TEL, and a one-layer metal wiring M1. , A two-layer metal wiring M2 constituting the charge line CL disposed on the back side of the paper and a three-layer metal wiring M3 constituting the bit line pair BL10, / BL10 are shown.

  ff 'cross-sectional view shows a P-type substrate Psub, source / drain S / D of NMOSFETs N11-N14 formed therein, polysilicon gate layer PolySi constituting the word line WL, and one-layer metal wiring M1, a two-layer metal wiring M2 connected to the contact VIA, and a three-layer metal wiring M3 constituting the bit line pair BL10, / BL10 are shown.

  As can be seen from the plan view of FIG. 7, according to the device structure of the memory cell array of the present embodiment, the stripe-shaped first conductivity type regions nWELL and the second conductive type regions nWELL arranged alternately in the memory cell array of the P-type semiconductor substrate Psub. And a two-conductivity type region Psub. A second conductivity type PMOSFET is formed in the first conductivity type region nWELL, and a first conductivity type NMOSFET is formed in the second conductivity type region Psub. Further, a plurality of plate lines PL are provided on the boundary between the first conductivity type region nWELL and the second conductivity type region Psub.

  Therefore, NMOSFETs N11-N14 and PMOSFETs P11-P14, which are provided in pairs in each memory cell, are arranged in the second conductivity type region Psub extending in a stripe shape and in the first conductivity type region nWELL. Each area is formed efficiently. A plate line PL that also serves as the lower electrode BEL of the capacitor is arranged in the horizontal direction along the boundary line between the two conductivity type regions Psub and nWELL. Therefore, the plate line PL can be arranged avoiding the formation region of the contact VIA connected to the source / drain of the NMOSFET N11-N14 and the PMOSFET P11-P14, and the arrangement efficiency can be increased.

  The above embodiment is summarized as follows.

(Appendix 1)
Multiple word lines,
Multiple plate wires,
Multiple bit line pairs;
Multiple charge lines,
A pair of first conductivity type MOSFETs each having a gate connected to the word line and a first source / drain connected to the bit line pair; a second source / drain of the pair of first conductivity type MOSFETs; A pair of ferroelectric capacitors respectively provided between the plate lines and a pair of second conductivity types provided between the pair of ferroelectric capacitors and the charge line and having a gate and a drain cross-connected to each other A plurality of memory cells each having a MOSFET;
A ferroelectric memory having a charge line driving circuit for driving the charge line to a power supply voltage during a read operation and a write operation.

(Appendix 2)
In Appendix 1, further comprising: a sense amplifier provided in the bit line pair for amplifying a potential difference between the bit line pair;
During the read operation, the word line is driven to conduct the pair of first conductivity type MOSFETs, and after the plate line is driven from a reference potential to a predetermined drive voltage, the sense amplifier sets the bit line pair to the bit line pair. A ferroelectric memory that is driven to the first and second potentials, and the charge line driving circuit drives the charge line to the power supply voltage during a rewrite operation after driving the sense amplifier.

(Appendix 3)
In Appendix 2,
A ferroelectric memory in which the charge line drive circuit drives the charge line to the power supply voltage at least when the plate line is lowered from the predetermined drive voltage to the reference potential during the rewrite operation.

(Appendix 4)
In Appendix 2,
A ferroelectric memory in which the charge line driving circuit maintains the charge line at a reference potential lower than the power supply voltage before the rewrite operation during the read operation.

(Appendix 5)
In Appendix 1,
At the time of the write operation, after the word line is driven and the pair of first conductivity type MOSFETs are turned on, the charge line drive circuit is changed to the first and second potentials different from each other after the bit line pair is set to different first and second potentials. A ferroelectric memory for driving the charge line to the power supply voltage.

(Appendix 6)
In Appendix 5,
A ferroelectric memory in which the charge line drive circuit drives the charge line to the power supply voltage when at least the plate line is lowered from a predetermined drive voltage to the reference potential during the write operation.

(Appendix 7)
In Appendix 5,
Further, a ferroelectric memory having a write amplifier connected to the bit line pair and driving the bit line pair to the first and second potentials during a write operation.

(Appendix 8)
In Appendix 1,
The ferroelectric memory in which the charge line driving circuit maintains the charge line at a reference potential lower than the power supply voltage during a period other than the read operation and the write operation.

(Appendix 9)
In any one of appendices 1 to 8,
And a word line driving circuit for driving the word line,
The word line drive circuit is a ferroelectric memory that drives the word line to the power supply voltage during the read operation and the write operation.

(Appendix 10)
In Appendix 9,
A ferroelectric memory in which the first conductivity type MOSFET is an N type MOSFET and the second conductivity type MOSFET is a P type MOSFET.

(Appendix 11)
In Appendix 10,
The word line, the charge line, and the plate line each extend in a first direction, and the bit line pair extends in a second direction intersecting the first direction.

(Appendix 12)
In Appendix 1 or 10,
A semiconductor substrate;
A memory cell array provided on the semiconductor substrate and provided with the plurality of memory cells;
In the memory cell array, stripe-shaped first conductivity type regions and second conductivity type regions alternately arranged,
The second conductivity type MOSFET is formed in the first conductivity type region, the first conductivity type MOSFET is formed in the second conductivity type region,
A ferroelectric memory in which the plurality of plate lines are provided on a boundary between the first conductivity type region and the second conductivity type region.

(Appendix 13)
In Appendix 12,
A ferroelectric memory in which the word line and the charge line are arranged side by side under the plate line.

(Appendix 14)
In Appendix 12,
A ferroelectric memory in which the first conductivity type is N type and the second conductivity type is P type.

(Appendix 15)
Multiple word lines,
Multiple bit line pairs;
Multiple plate wires,
Multiple charge lines,
A pair of first conductivity type MOSFETs each having a gate connected to the word line and a first source / drain connected to the bit line pair; a second source / drain of the pair of first conductivity type MOSFETs; A pair of ferroelectric capacitors respectively provided between the plate lines and a pair of second conductivity types provided between the pair of ferroelectric capacitors and the charge line and having a gate and a drain cross-connected to each other A method of operating a ferroelectric memory having a plurality of memory cells each having a MOSFET,
During the read operation and the write operation, the word line is driven to conduct the first conductivity type MOSFET, and after the bit line pair is set to different first and second potentials, the charge line is set to the power supply voltage. A method of operating a ferroelectric memory to be driven.

(Appendix 16)
In Appendix 15,
A method of operating a ferroelectric memory, wherein the charge line is maintained at a reference voltage lower than the power supply voltage before the bit line pair is set to different first and second potentials during the read operation and the write operation.

WL1: Word line BL10, / BL10, BL11, / BL11: Bit line pair
PL1: Plate line CL1: Charge line
SA: Sense amplifier WA: Light amplifier
N11-N14: Access gate, first conductivity type MOSFET
C11-C14: Ferroelectric capacitor
P11-P14: Second conductivity type MOSFET

Claims (10)

Multiple word lines,
Multiple plate wires,
Multiple bit line pairs;
Multiple charge lines,
A pair of first conductivity type MOSFETs each having a gate connected to the word line and a first source / drain connected to the bit line pair; a second source / drain of the pair of first conductivity type MOSFETs; A pair of ferroelectric capacitors respectively provided between the plate lines and a pair of second conductivity types provided between the pair of ferroelectric capacitors and the charge line and having a gate and a drain cross-connected to each other A plurality of memory cells each having a MOSFET;
During the read operation and the write operation, the word line is driven to conduct the first conductivity type MOSFET, and after the bit line pair is set to different first and second potentials, the charge line is set to the power supply voltage. A ferroelectric memory having a charge line driving circuit for driving. In Claim 1, It further has a sense amplifier which is provided in the bit line pair and amplifies the potential difference between the bit line pair,
During the read operation, the word line is driven to conduct the pair of first conductivity type MOSFETs, and after the plate line is driven from a reference potential to a predetermined drive voltage, the sense amplifier sets the bit line pair to the bit line pair. A ferroelectric memory that is driven to the first and second potentials, and the charge line driving circuit drives the charge line to the power supply voltage during a rewrite operation after driving the sense amplifier. In claim 2,
A ferroelectric memory in which the charge line drive circuit drives the charge line to the power supply voltage at least when the plate line is lowered from the predetermined drive voltage to the reference potential during the rewrite operation. In claim 2,
A ferroelectric memory in which the charge line driving circuit maintains the charge line at a reference potential lower than the power supply voltage before the rewrite operation during the read operation. In claim 1 ,
A ferroelectric memory in which the charge line drive circuit drives the charge line to the power supply voltage when at least the plate line is lowered from a predetermined drive voltage to the reference potential during the write operation. In claim 1,
The ferroelectric memory in which the charge line driving circuit maintains the charge line at a reference potential lower than the power supply voltage during a period other than the read operation and the write operation. In claim 1,
A semiconductor substrate;
A memory cell array provided on the semiconductor substrate and provided with the plurality of memory cells;
In the memory cell array, stripe-shaped first conductivity type regions and second conductivity type regions alternately arranged,
The second conductivity type MOSFET is formed in the first conductivity type region, the first conductivity type MOSFET is formed in the second conductivity type region,
A ferroelectric memory in which the plurality of plate lines are provided on a boundary between the first conductivity type region and the second conductivity type region. In claim 7 ,
A ferroelectric memory in which the word line and the charge line are arranged side by side under the bit line pair . Multiple word lines,
Multiple bit line pairs;
Multiple plate wires,
Multiple charge lines,
A pair of first conductivity type MOSFETs each having a gate connected to the word line and a first source / drain connected to the bit line pair; a second source / drain of the pair of first conductivity type MOSFETs; A pair of ferroelectric capacitors respectively provided between the plate lines and a pair of second conductivity types provided between the pair of ferroelectric capacitors and the charge line and having a gate and a drain cross-connected to each other A method of operating a ferroelectric memory having a plurality of memory cells each having a MOSFET,
During the read operation and the write operation, the word line is driven to conduct the first conductivity type MOSFET, and after the bit line pair is set to different first and second potentials, the charge line is set to the power supply voltage. A method of operating a ferroelectric memory to be driven. In claim 9 ,
Wherein during the read operation and the write operation, prior to said bit line pair to be different from the first and second potentials, ferroelectric method of operating a memory for maintaining the charge line to the reference voltage lower than the power supply voltage.

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