JP5609137B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device that controls power supply to a three-phase load and a control method thereof, and more particularly to an on / off operation of a switch element in two-phase modulation.

  In the power conversion device that controls the power supply to the three-phase load, for each phase (U phase, V phase, W phase) of the three phase load, a plurality of, for example, a plurality of units connected in series to a predetermined DC power source, for example, It has two switch elements. Among these switch elements, those connected to the anode side of the DC power supply are called upper arm elements, and those connected to the cathode side of the DC power supply are called lower arm elements. Then, for each phase of the three-phase load, a potential between the upper arm element and the lower arm element corresponding to the phase is applied to the phase. In normal operation, both the upper arm element and the lower arm element are not turned on at the same time.

  In the power conversion device having the above structure, each switching element of each phase performs an on / off operation based on the on / off pattern. That is, the on / off pattern defines the on / off state of each switch element of each phase. The on / off pattern is generated, for example, by a carrier comparison method using comparison between a carrier and a command value.

  In this on / off pattern, two-phase modulation may be employed. The two-phase modulation is a modulation method in which the on / off state of each one-phase switch element among the three phases is fixed and the remaining two-phase switch elements are turned on / off. FIG. 13 is a graph showing an example of an on / off pattern in which two-phase modulation is employed in one period T of the carrier H (here, the triangular wave H1). In FIG. 13, the on / off states of the switching elements of the phases U, V, W in the first section K1 of one cycle T are “0”, respectively. This is expressed as (0, 0, 0) in vector notation. Similarly, it is (1, 0, 0) in the second section K2, (1, 1, 0) in the third section K3, (1, 0, 0) in the fourth section K4, In the section K5, it is (0, 0, 0). Note that “0” indicates an on / off state in which the lower arm element is turned on and the upper arm element is turned off, and “1” indicates an on / off state in which the upper arm element is turned on and the lower arm element is turned off.

  Thus, in an on / off pattern in which two-phase modulation is adopted, a voltage vector represented as (0, 0, 0) (a so-called zero voltage vector, usually represented as “V0”) is (0 , 0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0) Any two types of voltage vectors (non-zero voltage vectors: usually expressed as V1, V2, V3, V4, V5, and V6, respectively) are sandwiched between the front and the back. Alternatively, a voltage vector expressed as (1, 1, 1) (which is also a zero voltage vector and is generally expressed as “V7”) sandwiches any two types of non-zero voltage vectors in the front and rear.

  Note that three-phase modulation may be employed in the on / off pattern. In the three-phase modulation, the switching elements of the phases U, V, and W are always switched on and off during one cycle T. FIG. 19 is a graph showing an example of an on / off pattern in which three-phase modulation is employed in one period T. In an on / off pattern in which three-phase modulation is employed, any one of zero voltage vectors V0, V7, one of non-zero voltage vectors V1, V2, V3, V4, V5, V6 and the other in one cycle of carrier H. The zero voltage vector (V0, V7) is sandwiched. Here, one cycle T is divided into sections K11, K12, K13, K14, K15, K16, and K17 in this order, and voltage vectors V0, V4, V6, V7, V6, V4, and V0 are adopted in each.

  In addition, the following patent documents 1-5 are known as a prior art document regarding the power converter device which controls the electric power supply to a three-phase load.

Japanese Examined Patent Publication No. 4-29312 JP 2004-357358 A JP 2005-229714 A JP 2006-174659 A JP 2006-197760 A

When the zero voltage vector adopted in the off pattern Pk of the k-th one period T _k is expressed as Vz ^k, if the two-phase modulation is adopted in the off pattern Pk, either Vz ^k = V0 or Vz ^k = V7 It is. One cycle T shown in FIG. 13 represents an on-off pattern P _n of the n-th one cycle T _n , and the voltage vector V0 is adopted as the zero voltage vector in the on-off pattern P _n . However, as described above, some on / off patterns employing two-phase modulation employ the voltage vector V7 as the zero voltage vector, which may cause the following problems.

Now, in the on / off pattern P _n−1 employed in the (n−1) th one cycle T, the zero voltage vector Vz ⁿ⁻¹ is the zero voltage vector V7, and as illustrated in FIG. When the zero voltage vector Vz ⁿ is the zero voltage vector V0 in the on / off pattern P _n employed in one cycle T, when the voltage vector transitions from the zero voltage vector V7 to the zero voltage vector V0, each phase is switched simultaneously. Operates on and off. In such an on / off operation, noise due to the operation of each of these switch elements is generated at the same time, and there is a possibility of causing a noise failure such as a malfunction of the drive circuit.

  Although it is conceivable to limit the zero voltage vector employed to either one of the voltage vectors V0 and V7 over the entire period of the two-phase modulation, an on / off pattern in such a manner is usually not desired. . One reason for this is that the two-phase modulation employing such an on / off pattern shortens its life due to excessive heat generation of either the upper arm element or the lower arm element.

  In view of the above problems, an object of the present invention is to provide a technique for preventing a switching element from turning on and off simultaneously when driving an inverter by two-phase modulation.

  A first aspect of the power conversion device according to the present invention is a power conversion device that drives and controls a three-phase load (10), and has a predetermined direct current for each phase (U, V, W) of the three-phase load. One of the potentials between the switch elements for each phase, having a plurality of switch elements (SW1, SW2; SW3, SW4; SW5, SW6) connected in series to the power supply (12) And an inverter circuit (14) for applying the potential of each to the three-phase load of each phase, and a control for generating an on / off pattern (P) and performing on / off operation of each switch element for each phase based on the on / off pattern A circuit (16).

Only the switch elements (SW2, SW4, SW6) connected to the cathode side of the DC power supply (12) or only the switch elements (SW1, SW3, SW5) connected to the anode side of the DC power supply. In the on-off pattern, (A) the same zero voltage is set in the ON state (V0, V7) as zero voltage vectors, and other combinations of the ON / OFF operations (V1 to V6) as non-zero voltage vectors. A plurality of the non-zero voltage vectors consecutively sandwiched by vectors (Vz ^{n−2, n−1} , Vz ^{n−1, n} ) form a two-phase modulation pattern together with the zero voltage vector, and (B) each other different pair of the zero-voltage vector ^{(Vz n-1, n,} Vz n, n + 1) a plurality of said non-zero voltage vectors consecutive sandwiched by the one of the pair of the zero-voltage vector Between to the other of the pair of the zero voltage vector, and forming the on-off operation of each once for one phase.

  A second mode of the power converter according to the present invention is the first mode, wherein the control circuit is based on a voltage command vector generation unit (16e) for specifying a voltage command vector and the voltage command vector. An on / off pattern generation unit (16g) for generating the on / off pattern (P), and a control signal generation unit (16h) for performing on / off operation of each switch element based on the on / off pattern generated by the on / off pattern generation unit And have.

  The on / off pattern generation unit is a series of the zero voltage vector (V0, V7) and the non-zero voltage vector (Vα, Vβ: α, β = 1 to 6) for expanding the voltage command vector by two-phase modulation. When the arrangement pattern is determined, and the pair of zero voltage vectors different from each other in the arrangement pattern continues without the non-zero voltage vector, the order of the pair of zero voltage vectors is later (V7) is changed to the first one of the pair of zero voltage vectors (V0), and the first non-zero voltage vector (V6) immediately after the one zero voltage vector; The order of the second non-zero voltage vector (V2) immediately after the first non-zero voltage vector is changed to correct the arrangement pattern, and Wherein generating the on-off pattern (P) to be.

  A third mode of the power conversion device according to the present invention is the first mode, wherein the control circuit is based on a voltage command vector generation unit (16e) for specifying a voltage command vector and the voltage command vector. An on / off pattern generation unit (16g) for generating the on / off pattern (P), and a control signal generation unit (16h) for performing on / off operation of each switch element based on the on / off pattern generated by the on / off pattern generation unit And have.

  The on / off pattern generation unit is a series of the zero voltage vector (V0, V7) and the non-zero voltage vector (Vα, Vβ: α, β = 1 to 6) for expanding the voltage command vector by two-phase modulation. When the arrangement pattern is determined, and the pair of zero voltage vectors different from each other in the arrangement pattern continues without the non-zero voltage vector, the order of the pair of zero voltage vectors is later (V7), the first non-zero voltage vector (V6) immediately thereafter, the second non-zero voltage vector (V2; V4) immediately after the first non-zero voltage vector, and the second The third non-zero voltage vector (V6) immediately after the non-zero voltage vector is defined as the second non-zero voltage vector, the first non-zero voltage vector, and the third non-zero. Pressure vectors, and generates the on-off pattern (P) corresponding to the arrangement pattern from the replaced in the order of the zero-voltage vector of the one.

The 4th aspect of the power converter device concerning this invention is the 2nd aspect or the 3rd aspect, Comprising: The said on-off pattern production | generation part (16g) respond | corresponds to a carrier wave signal (H) and each said phase An on / off pattern is generated based on the magnitude relationship with the voltage command value signals (Vu ^* , Vv ^* , Vw ^* ). (i) The on / off pattern corresponding to the same zero voltage vector (Vz ^{n−2, n−1} , Vz ^{n−1, n} ) and a plurality of the non-zero voltage vectors sandwiched between the zero voltage vectors. Is generated by adopting a triangular wave as the carrier signal, and (ii) a pair of different zero voltage vectors (Vz ^{n−1, n} , Vz ^{n, n + 1} ) and the zero voltage vector The on / off pattern corresponding to a plurality of the non-zero voltage vectors is generated using a sawtooth wave as the carrier signal.

A fifth aspect of the power conversion device according to the present invention is any one of the first to fourth aspects, wherein the pair of zero voltage vectors (Vz ⁿ⁻² ) in the on / off pattern (P). ^{, n−1} , Vz ^{n, n + 1} ) through a plurality of non-zero voltage vectors, the zero voltage vector (Vz ^{n−1, n} ) adjacent thereto is at least one of the pair of zero voltage vectors. It is the same as either.

  According to the first aspect of the power conversion device of the present invention, even when the type of the zero voltage vector employed in the two-phase modulation pattern is switched, each switching element (SW1, SW1, and U) is switched simultaneously with each phase (U, V, W). To SW6) are prevented from being turned on and off, thereby preventing the noise generated by the on / off operation of each switch element from being matched.

  According to the second aspect or the third aspect of the power conversion device according to the present invention, the series of voltage vectors for expanding the voltage command vector is continuous without damaging the two-phase modulation and without passing through the non-zero voltage vector. The existence of a pair of zero voltage vectors can be eliminated.

  According to the 4th aspect of the power converter device concerning this invention, an on-off pattern can be produced | generated by a cheap structure.

  The fifth aspect of the power conversion device according to the present invention is desirable from the viewpoint of maintaining the advantage as the two-phase modulation.

1 is a schematic configuration diagram of a power conversion device 1 according to an embodiment of the present invention. It is the figure which showed the combination of the on-off state of each switch element SW1-SW6. It is a figure explaining space voltage vector diagram S. FIG. 4 is a diagram illustrating an example of a sequence pattern of a series of voltage vectors in one cycle of an on / off pattern P. It is a figure which shows an example of the arrangement pattern of the voltage vector which expand ^| deploys voltage command vector V ^* in two-phase modulation. It is a figure which illustrates the arrangement | sequence of the corrected voltage vector. It is a figure which illustrates the arrangement | sequence of the corrected voltage vector. It is a figure which illustrates the corrected arrangement pattern in case voltage command vector V ^* changes between different fields Sm. It is a figure which shows the other example of the arrangement pattern of the voltage vector which expand ^| deploys voltage command vector V ^* in two-phase modulation. It is a figure which illustrates the arrangement | sequence of the corrected voltage vector. It is a figure which illustrates the arrangement | sequence of the corrected voltage vector. It is a figure which illustrates the corrected arrangement | sequence pattern in case voltage command vector V ^* exists in the same area | region Sm. It is a figure explaining the method of producing | generating the on-off pattern P (Pn) using the triangular wave H1 and each voltage command value signal Vu ^* , Vv ^* , Vw ^* . It is a figure explaining the method of producing | generating the on-off pattern P (Pn) using the sawtooth wave H2 and each voltage command value signal Vu ^* , Vv ^* , Vw ^* . It is the figure which showed the selectable stationary phase in case voltage command vector V ^* exists in each area | region S1-S6. It is the figure which showed an example of selection of a stationary phase. It is the figure which showed the other example of selection of a stationary phase. It is the figure which showed the further another example of selection of a stationary phase. It is a figure which shows an example of the on-off pattern of three-phase modulation.

<Overall configuration>
The power conversion device 1 according to this embodiment includes a three-phase load 10, a DC power supply 12, an inverter circuit 14, and a control circuit 16 with reference to FIG. 1. The inverter circuit 14 converts the DC power of the DC power supply 12 into three-phase AC power and supplies it to each phase U, V, W of the three-phase load 10. The control circuit 16 controls the inverter circuit 14.

  The three-phase load 10 is, for example, a three-phase motor, and includes position detection sensors (for example, hall sensors) Hu, Hv, and Hw that detect the rotational position thereof. In this embodiment, the rotational position of the three-phase load 10 is detected using a position detection sensor, but the current or voltage of each phase U, V, W, etc., without using the position detection sensors Hu, Hv, Hw, etc. The rotational position of the three-phase load 10 may be detected based on the detected value.

  As shown in FIG. 1, the DC power source 12 includes, for example, an AC power source 12a and a converter 12b that converts AC power of the AC power source 12a into DC power.

  The converter 12b includes four diodes D1 to D4 that constitute a bridge rectifier circuit, a coil L, and a capacitor C. Each of the diodes D1 and D2 is connected in series between the anode line 12p and the cathode line 12n so that the energization direction of each diode is toward the anode line 12p. Each of the diodes D3 and D4 is connected in series between the anode line 12p and the cathode line 12n so that the energization direction of each diode is toward the anode line 12p. An AC power supply 12a is connected between the connection point of each diode D1, D2 and the connection point of each diode D3, D4. The coil L is connected to the subsequent stage of the bridge rectifier circuit in the anode wire 12p. The capacitor C is connected between the anode line 12p and the cathode line 12n in the subsequent stage of the coil L.

  The inverter circuit 14 includes a plurality (six in this case) of switch elements SW1 to SW6. The switch elements SW1 and SW2 are connected in series between the anode line 12p and the cathode line 12n, and the potential between the switch elements SW1 and SW2 is applied to the U-phase electrode 11u of the three-phase load 10. The switch elements SW3 and SW4 are connected in series between the anode line 12p and the cathode 12n, and the potential between the switch elements SW3 and SW4 is applied to the V-phase electrode 11v of the three-phase load 10. The switch elements SW5 and SW6 are connected in series between the anode line 12p and the cathode line 12n, and the potential between the switch elements SW5 and SW6 is applied to the W-phase electrode 11w of the three-phase load 10.

  The switch elements SW1, SW3, SW5 connected to the anode line 12p (that is, the anode side of the DC power supply 12) are called upper arm elements, and are connected to the cathode line 12n (that is, the cathode side of the DC power supply 12). The switch elements SW2, SW4, SW6 are called lower arm elements.

  Here, two switch elements are connected in series for each phase U, V, W, and the potential between the two switch elements is applied to the corresponding phase of the three-phase load 10. In general, a plurality of switch elements are connected in series, and any potential between the plurality of switch elements is applied to a corresponding phase of the three-phase load 10.

  Each of the switch elements SW1 to SW6 includes a transistor T and a diode D connected in a reverse direction between the main electrodes of the transistor T. The control electrodes G of the switch elements SW1 to SW6 are connected to the control circuit 16, respectively. As the switch elements SW1 to SW6, an IGBT or the like provided with a reflux diode can be used.

  In the inverter circuit 14, the control circuit 16 applies a control signal to the control electrodes G of the switch elements SW <b> 1 to SW <b> 6 to control the on / off state of the transistors T of the switch elements. At that time, the U-phase switch elements SW1 and SW2 are not both turned on. Similarly, neither the V-phase switch elements SW3, SW4 nor the W-phase switch elements SW5, SW6 are both turned on. In this way, the DC power of the DC power supply 12 is converted into three-phase AC power, and a voltage is applied to the electrodes 11u, 11v, 11w of the respective phases U, V, W of the three-phase load 10. Thereby, for example, when the three-phase load 10 is a motor, the motor is rotationally driven.

  Hereinafter, description will be continued by taking the case where the three-phase load 10 is a motor as an example. The control circuit 16 controls the inverter circuit 14 so that the three-phase load 10 is rotationally driven at a desired rotational angular velocity. Referring to FIG. 1, the control circuit 16 includes a rotation angular velocity detection unit 16a, a rotation angular velocity command value generation unit 16b, a current command value generation unit 16c, a voltage command vector generation unit 16e, and an on / off pattern generation unit 16g. And a control signal generator 16h.

  The rotational angular velocity detection unit 16a obtains the temporal change from the rotational position of the three-phase load 10 detected by each position detection sensor Hu, Hv, Hw, and detects the rotational angular velocity ω of the three-phase motor 10 based on the temporal change. Then, it is output to the current command value generation unit 16c.

The rotation angular velocity command value generation unit 16b generates a rotation angular velocity command value ω ^* for rotating the three-phase motor 10 at a desired rotation angular velocity, and outputs it to the current command value generation unit 16c.

The current command value generation unit 16c generates a current command value I ^{* such} that the rotation angular velocity ω from the rotation angular velocity detection unit 16a approaches the rotation angular velocity command value ω ^* from the rotation angular velocity command value generation unit 16b. Specifically, the current command value generation unit 16c generates a current command value I ^* by performing a proportional-integral-derivative calculation (PID calculation) on the deviation between the rotational angular velocity ω and the rotational angular velocity command value ω ^*, and outputs the current command value I ^*. It outputs to the vector production | generation part 16e.

The voltage command vector generator 16e generates a voltage command vector V ^* based on the current command value I ^* . The voltage command vector is a command value of a voltage vector that is the basis of the on / off pattern, and the voltage vector can be developed by the non-zero voltage vector and the zero voltage vector. Hereinafter, the development will be described in order.

  First, referring to FIG. 2, the combination of the on / off states of the switch elements SW1 to SW6 of each phase U, V, W is represented by eight voltage vectors. That is, voltage vectors V0 (0, 0, 0), V1 (0, 0, 1), V2 (0, 1, 0), V3 (0, 1, 1), V4 (1, 0, 0), V5 ( 1, 0, 1), V6 (1, 1, 0), V7 (1, 1, 1). Hereinafter, the voltage vectors V0 to V7 may be referred to as “on / off state” depending on the case.

  The leftmost “0” or “1” in each parenthesis of each vector V0 to V7 indicates the on / off state of each U-phase switch element SW1 or SW2, and “0” or “ “1” indicates the on / off state of each of the V-phase switch elements SW3 and SW4, and “0” or “1” on the rightmost in each parenthesis indicates the on / off state of each of the W-phase switch elements SW5 and SW6. “1” indicates a state where the upper arm element is turned on and the lower arm element is turned off, and “0” indicates a state where the lower arm element is turned on and the upper arm element is turned off.

  As shown in FIG. 3, the non-zero voltage vectors V1 to V6 are arranged with their start points coincident with the center point 0 and their end points radially outward, and the zero voltage vectors V0 and V7 are zero in magnitude. A regular hexagonal diagram formed by placing the center point 0 on the assumption that the vector is a spatial vector is referred to as a spatial voltage vector diagram S. Each non-zero voltage vector V1 to V6 is arranged so that the on / off state of each switch element SW1 to SW6 changes by one phase clockwise or counterclockwise. In the spatial voltage vector diagram S, two adjacent ones of the voltage vectors V1 to V6 and the voltage vectors V0 and V7 constitute an equilateral triangular region Sj (j = 1 to 6).

The on / off pattern generation unit 16g converts the voltage command vector V ^* defined on the spatial voltage vector diagram S into each voltage vector (that is, the voltage command) constituting the region including the voltage command vector V ^* in each of the regions S1 to S6. Development is performed using two non-zero voltage vectors Vα and Vβ (α ≠ β and α, β = 1 to 6) and two zero voltage vectors V0 and V7 sandwiching the vector V ^* .

When the two-phase modulation is employed, the on / off state of the upper arm element of one phase or the lower arm element of one phase is fixed, so that the voltage command vector V ^* exists as a non-zero voltage vector. Only two non-zero voltage vectors forming the boundary of the region Sj (j = 1-6) are employed. Therefore, the non-negative real numbers aα, aβ, a0, a7 are set so as to satisfy Equations 1 and 2.

V ^* = aα · Vα + aβ · Vβ + a0 · V0 + a7 · V7 ··· Equation 1
aα + aβ + a0 + a7 = 1 Equation 2
Each coefficient aα is grasped as a projection component of the voltage command vector V ^* onto the voltage vector Vα, and the coefficient aβ is grasped as a projection component onto the voltage vector Vβ of the voltage command vector V ^* .

Each coefficient a0, a7 can be freely selected as long as a0 + a7 = 1− (aα + aβ) is satisfied. This is because the zero voltage vectors V0 and V7 are common in that the magnitude is zero, and the use of any of the zero voltage vectors V0 and V7 does not affect the development of the voltage command vector V ^* .

When an on / off pattern employing two-phase modulation is generated by the carrier comparison method, the same zero voltage vector is sandwiched between non-zero voltage vectors in one carrier period as described above. Therefore, here, it is understood that one cycle of the on / off pattern is based on an array of a pair of zero voltage vectors and a non-zero voltage vector sandwiched between these zero voltage vectors regardless of whether or not they are generated by the carrier comparison method. To do. Hereinafter, in the on-off pattern Pk of the k-th one cycle T _k , the first zero voltage vector is represented as Vz ^k i and the last zero voltage vector is represented as Vz ^k f. In particular, when the order of one cycle of the on / off pattern is not considered, the first zero voltage vector of the cycle is represented as Vzi, and the last zero voltage vector is represented as Vzf.

The on / off pattern generation unit 16g generates on / off patterns corresponding to a series of voltage vectors Vzi, Vα, Vβ, Vα, and Vzf in one cycle. However, the zero voltage vectors Vzi and Vzf and the non-zero voltage vectors Vα and Vβ are selected so that the on / off operation does not occur simultaneously in a plurality of different phases in one cycle. Referring to FIG. 13, the voltage command vector V ^* is in the region S1, and Vzi = Vzf = V0, Vα = V4, Vβ = V6. When one cycle T is divided into sections K1 to K5, the zero voltage vector V0 is adopted in the sections K1 and K5, the non-zero voltage vector V4 is adopted in the sections K2 and K4, and the non-zero voltage vector V6 is adopted in the section K3. Is done. As is well known, such a series of voltage vector arrangements can be obtained by the carrier comparison method using the triangular wave H1 as the carrier H.

On the other hand, it is also well known that a series of voltage vectors such as Vzi = Vzf = V7, Vα = V6, Vβ = V4 can be adopted even when the voltage command vector V ^* is in the region S1.

FIG. 4 illustrates a specific example of an array pattern of a series of voltage vectors in one cycle of the on / off pattern P when the voltage command vector V ^* is in each of the regions S1 to S6. S1 to S6 in the left column of FIG. 4 indicate a region where the voltage command vector V ^* exists. From FIG. 4, when the voltage command vector V ^* is in the region S1, the order of the series of voltage vectors is V7 → V6 → V4 → V6 → V7 according to the zero voltage vector taken by Vzi = Vzf. There are two cases: the case where the u-phase upper arm element is fixed on and the case where V0 → V4 → V6 → V4 → V0 (that is, the case where the w-phase lower arm element is fixed on). is there.

The on / off pattern generation unit 16g thus determines an array pattern composed of a series of zero voltage vectors V0 and V7 and non-zero voltage vectors Vα and Vβ that expand the voltage command vector V ^* .

  When a pair of zero voltage vectors V0 and V7 that are different from each other in the arrangement pattern are continuous without passing through the non-zero voltage vectors Vα and Vβ, the arrangement pattern is corrected as described later at the relevant location and its vicinity. To generate an on / off pattern P corresponding to the array pattern.

  Based on the on / off pattern P generated as described above, the control signal generation unit 16h generates a control signal (for example, a PWM signal) for controlling the on / off operation of each of the switch elements SW1 to SW6, and each of the switch elements SW1. ~ Applied to the control electrode G of SW6. Accordingly, the switch elements SW1 to SW6 are turned on / off according to the on / off pattern P.

<Correction of voltage vector array pattern>
Hereinafter, a technique for correcting the arrangement pattern of the voltage vectors in the on / off pattern generation unit 16g will be exemplified. Of course, the desirable voltage vector arrangement pattern is not based on the correction, but may be generated sequentially. Here, only a technique of once generating a voltage vector array pattern and correcting it is illustrated.

FIG. 5 illustrates a series of voltage vector arrangements that develop the voltage command vector V ^* in two-phase modulation. However, each of the voltage vectors arranged here is realized by one of the on / off states of the switch element, and is either the above-described zero voltage vector or non-zero voltage vector. FIG. 5 shows the vicinity of the boundary where the voltage command vector V ^* transitions from the region S1 to the region S2. Specifically, the voltage command vector V ^* in the region S1 is developed in one cycle _Tn-2 and _Tn-1 , and the voltage command vector V ^* in the region S2 in one cycle _Tn and _{Tn + 1} ^. Is expanded. In this example, the zero voltage vectors employed in the regions S1 and S2 are different from each other.

  In this way, a series of voltage vectors subjected to two-phase modulation are arranged in the order of voltage vectors Vzi, Vα, Vβ, Vα, and Vzf when viewed in each cycle. In this case, the execution time tβ of the voltage vector Vβ is given by tβ = aβ · T when the symbol T is also used for the length of one cycle T. The execution time tα of the voltage vector Vα is given by tα = aα · T. Since Vα appears at the second and fourth places in the execution order in each cycle, the sum of the execution times at these two places is aα.・ Each execution time of these two places is set appropriately so that it becomes T. For example, each of the two implementation periods may be set to aα · T / 2.

  Further, the execution times tzi and tzf of the voltage vectors Vzi and Vzf are as follows. When the zero voltage vectors Vzi and Vzf are V0 (thus, when a0 ≠ 0 and a7 = 0), tzi + tzf = a0 · T = {1- ( aα + aβ)} · T is set appropriately. Similarly, when the zero voltage vectors Vzi and Vzf are V7 (therefore, when a0 = 0 and a7 ≠ 0), they are appropriately set so as to satisfy tzi + tzf = a7 · T = {1− (aα + aβ)} · T. The In any case, for example, the implementation periods tzi and tzf may be set to tzi = tzf = a0 · T / 2, respectively.

  However, in order to avoid the complexity of illustration, FIG. 5 and FIGS. 6, 7, 9, and 10 described later show only the order of the arrangement pattern, and the length of each implementation period is not shown.

In one cycle T _n−2 and T _n−1 , the lower arm element of the W phase is fixed to the on state, and V0 is adopted as the zero voltage vector. In one cycle T _n , T _{n + 1} , the V-phase upper arm element is fixed to the ON state, and V7 is adopted as the zero voltage vector.

In the case shown in FIG. 5, the zero voltage vector Vz ^n-1 f appearing at the end of one cycle T _n-1 is V0, and the zero voltage vector Vz ⁿ i appearing at the beginning of one cycle T _n is V7. Are adjacent. That is, the zero voltage vector is switched at the timing when the voltage command vector V ^* transitions from the region S1 to the region S2. This invites the switching elements SW1 to SW6 to be turned on and off simultaneously in the U, V, and W phases, and is not desirable in view of the generated noise.

As described above, when a pair of mutually different zero voltage vectors Vz ⁿ⁻¹ f = V 0 and Vz ⁿ i = V 7 in the arrangement pattern are continuous without passing through the non-zero voltage vectors Vα and Vβ, the following correction is performed. . The other arrangement pattern arrangements are not corrected.

(i) The zero voltage vector Vz ⁿ i whose order is later among the adjacent zero voltage vectors is changed to the zero voltage vector Vz ⁿ⁻¹ f whose order is earlier.

(ii) The order of the first non-zero voltage vector Vα immediately after the zero voltage vector Vz ⁿ i, which is later in order, and the second non-zero voltage vector Vβ immediately after the first non-zero voltage vector are switched.

FIG. 6 shows the arrangement pattern thus obtained. Due to the above (i), it is avoided that a pair of mutually different zero voltage vectors continue without passing through the non-zero voltage vectors Vα and Vβ. Here, symbols added to the upper right of the symbol Vz and separated by commas indicate at which boundary of the adjacent period the zero voltage vector exists. Specifically, there is a zero voltage vector Vz ^{n−2, n−1} = V0 at the boundary between one cycle T _n−2 and T _n−1 , and at the boundary between one cycle T _n−1 and T _n. the present zero-voltage vector ^{Vz n-1, n = V0} , the one period T _n, T _{n + 1} between boundary exists zero voltage vector ^{Vz n, n + 1 = V7} . Thus, in the arrangement pattern shown in FIG. 6, the zero voltage vector is switched after the voltage command vector V ^* transitions to the region S2. That is, unlike the arrangement pattern shown in FIG. 5, the zero voltage vector is not switched at the timing when the voltage command vector V ^* transitions from the region S1 to the region S2. Accordingly, the switch elements SW1 to SW6 are not simultaneously turned on / off in the U, V, and W phases.

Further, according to the above (ii), a plurality of continuous non-zero voltage vectors V2 and V6 sandwiched by a pair of different zero voltage vectors _Vzn ^{-1, n} = V0, Vzn ^{, n + 1} = V7 are Between the zero voltage vector Vz ^{n−1, n} = V0 and the zero voltage vector Vz ^{n, n + 1} = V7, one on / off operation is performed for each phase. Moreover, since the implementation period of the non-zero voltage vectors Vα and Vβ is maintained in one cycle T _n , there is no problem in the development of the voltage command vector V ^* .

  Alternatively, instead of (i) (ii), the following modifications may be made.

(iii) a zero voltage vector Vz ⁿ i that is later in order among adjacent zero voltage vectors, a first non-zero voltage vector Vα immediately after that, and a second non-zero immediately after the first non-zero voltage vector Vα. An arrangement pattern of a voltage vector Vβ and a non-zero voltage vector Vα immediately after the second non-zero voltage vector Vβ is represented by a second non-zero voltage vector Vβ, a first non-zero voltage vector Vα, and a third non-zero, respectively. The array pattern of the voltage vector Vα and the zero voltage vector Vz ⁿ i is changed and changed.

FIG. 7 shows the arrangement pattern thus obtained. Similar to the above (i) and (ii), it is avoided that a pair of different zero voltage vectors continue without passing through the non-zero voltage vectors Vα and Vβ, and a pair of different zero voltage vectors Vz ^{n− 1, n} = V0, Vzn ^{, n + 1} = A plurality of continuous non-zero voltage vectors V2 and V6 sandwiched by V7 are represented by zero voltage vector Vzn ^{-1, n} = V0 to zero voltage vector Vzn ^{, n. Between + 1} = V7, one on / off operation is performed for each phase. Moreover, since the implementation period of the non-zero voltage vectors Vα and Vβ is maintained in one cycle T _n , there is no problem in the development of the voltage command vector V ^* .

  6 and 7, the resulting voltage vector array pattern (on-off pattern is adopted because the array pattern employs a zero voltage vector or a non-zero voltage vector). It can be understood that the following features are satisfied.

(A) A plurality of continuous non-zero voltage vectors (V4, V6) sandwiched by the same zero voltage vector (Vzn ^{-2, n-1} , Vzn ^{-1, n} = V0) (V0) and a two-phase modulation pattern are formed,
(B) A plurality of consecutive non-zero voltage vectors (V2, V6) sandwiched between a pair of different zero voltage vectors (Vz ^{n-1, n} = V0, Vz ^{n, n + 1} = V7) The zero voltage vector is switched from one (Vz ^{n−1, n} = V0) to the other (Vz ^{n, n + 1} = V7) by one on / off operation for each phase.

With the arrangement pattern as described above, the zero voltage vector employed before and after the zero voltage vector Vz ^{n−1, n} is different, but each switch element is turned on / off while maintaining the two-phase modulation. It is prevented that the noise generated by the operation matches.

FIG. 8 shows a specific example of an array pattern when the voltage command vector V ^* in the region Sj transitions to the adjacent region Sm (m = 1 to 6). For example, S3 / S1 → S2 in the second row in the left column of FIG. 8 indicates a case where Sj = S3 (or Sj = S1) and Sm = 2. The middle column shows the case where the upper arm element is fixed in the on state in the region Sj and the lower arm element is fixed in the on state in the region Sm. The right column shows a case where the lower arm element is fixed in the on state in the region Sj and the upper arm element is fixed in the on state in the region Sm. For example, all of the arrangement patterns illustrated in FIGS. 6 and 7 correspond to V0 → V2 → V6 → V7 shown in the right column of the second row in FIG.

Now, even when the voltage command vector V ^* is within the same region Sj, there are cases where an on / off pattern for fixing the upper arm element and an on / off pattern for fixing the lower arm element are switched. As described above, one of the reasons for such switching is that either the upper arm element or the lower arm element shortens the lifetime.

FIG. 9 shows the vicinity of the boundary where the voltage command vector V ^* is in the region S1 and transitions from an on / off pattern for fixing the lower arm element of the W phase to an on / off pattern for fixing the upper arm element of the V phase. Yes. Even in such a case, the arrangement pattern can be corrected as shown in FIG. 10 by using the above-described methods (i) and (ii). Alternatively, the arrangement pattern can be corrected as shown in FIG. 11 using the method (iii) described above. The non-zero voltage vector Vβ in which the voltage vector V2 is employed in FIGS. 5 to 7 is different from the non-zero voltage vector Vβ in FIGS. 9 to 11 in that the voltage vector V2 is employed.

Therefore, although the modified arrangement pattern is different in the zero voltage vector adopted before the zero voltage vector Vz ^{n−1, n} and after that, while maintaining the two-phase modulation in each other, It is possible to prevent the noise generated by the on / off operation of the switch element from being matched. Moreover, since the implementation period of the non-zero voltage vectors Vα and Vβ is maintained in one cycle T _n , there is no problem in the development of the voltage command vector V ^* .

FIG. 12 shows a specific example of an arrangement pattern in which the arrangement pattern for fixing the upper arm element and the arrangement pattern for fixing the lower arm element are switched while the voltage command vector V ^* exists in the region Sj. For example, the first level in the left column of FIG. 12 shows a case where the voltage command vector V ^* is in the region S1. The middle column shows a case where the arrangement pattern transitions from the arrangement pattern in which the upper arm element is fixed to the on state in the region Sj to the arrangement pattern in which the lower arm element is fixed to the on state. The right column shows a case where the arrangement pattern transitions from the arrangement pattern in which the lower arm element is fixed to the on state in the region Sj to the arrangement pattern in which the upper arm element is fixed to the on state. For example, all of the arrangement patterns illustrated in FIGS. 10 and 11 correspond to V0 → V4 → V6 → V7 shown in the right column of the first row in FIG.

As can be seen by comparing FIGS. 8 and 12, if the same is an area Sm of the voltage command vector V ^* is present after the transition, the region in which the voltage command vector V ^* has existed before the transition in the region Sm Even if there is a region Sj adjacent thereto, the arrangement pattern is the same. In other words, the array pattern shown in FIG. 12 includes the array pattern shown in FIG. 8 if the region shown in the left column is regarded as a region where the voltage command vector V ^* exists after the transition. Can be grasped.

In order to maintain the advantage of the two-phase modulation, it is not desirable that the adjacent zero voltage vectors are alternately arranged across the non-zero voltage vector as in the three-phase modulation. That is, it is not desirable that the arrangement pattern formed by a plurality of continuous non-zero voltage vectors sandwiched between different zero voltage vectors is continuous (for example, V0 → V2 → V6 → V7 → V6 → V4 → V0). In other words, the zero voltage vector adjacent to them via a plurality of non-zero voltage vectors between a pair of zero voltage vector ^{(Vz n-2, n-} 1, Vz n, n + 1) (Vz n-1 ^{, n} ) are preferably the same as at least one of the pair of zero voltage vectors.

  In the above-described embodiment, the zero voltage vector employed may be arbitrarily set. Specifically, the zero voltage vector may be changed according to the voltage phase. Or you may change without depending on a voltage phase, such as changing with a fixed period or changing according to device temperature. Even when the zero voltage vector is arbitrarily set as described above, the present embodiment is effective if the above features (A) and (B) are satisfied.

  The arrangement pattern in the arrangement pattern modified as described above can be generated easily, for example, at a low cost by the carrier comparison method.

The on / off pattern generation unit 16g generates an on / off pattern based on the magnitude relationship between the carrier wave signal H and the voltage command value signals Vu ^* , Vv ^* , Vw ^* corresponding to each phase according to the arrangement pattern. Specifically, for example, the following processing is performed. Symbols in parentheses illustrate the symbols adopted in FIGS. 6 and 7.

When a pair of zero voltage vectors (Vz ^{n−2, n−1} , Vz ^{n−1, n} ) adopts the same zero voltage vector (V0), the zero voltage vector and a plurality of non-zero voltages sandwiched therebetween The on / off pattern corresponding to the vector (V4, V6) is generated by adopting the triangular wave H1 as the carrier wave signal H (see FIG. 13 described above). Here, since the lower arm element of the W-phase switch is fixed to the ON state, the value of the voltage command value signal Vw ^* is set to be equal to or greater than the maximum value of the triangular wave H1. In addition, since the zero voltage vector V0 is adopted, the values of the voltage command value signals Vu ^* and Vv ^* are set to be larger than the minimum value of the triangular wave H1 and less than the maximum value of the triangular wave H1.

On the other hand, when a pair of zero voltage vectors (Vz ^{n−1, n} , Vz ^{n, n + 1} ) employ different zero voltage vectors (V 0, V 7), the zero voltage vector and a plurality of the above-described zero voltage vectors The on / off pattern corresponding to the non-zero voltage vector (V2, V6) is generated by employing the sawtooth wave H2 as the carrier wave signal H (see FIG. 14). Here, since two zero voltage vectors V0 and V7 are adopted, the values of the voltage command value signals Vu ^* , Vv ^* , and Vw ^* are all larger than the minimum value of the sawtooth wave H2, and the maximum value of the sawtooth wave H2. Set to less than.

  When the on / off pattern generation unit 16g generates an on / off pattern corresponding to the array pattern modified as described above (that is, having the features (A) and (B)) using the carrier comparison method, the on / off pattern generation unit 16g generates the carrier wave signal H as a triangular wave H1. And the sawtooth wave H2. In addition, from the above description, in order to obtain an array pattern having the characteristics (A) and (B), in any of the methods (i) (ii) and (iii), the zero voltage vector is changed, and And / or a change in the order of the zero and non-zero voltage vectors. Therefore, it is unrelated to the period of the carrier signal H, and it is obvious that the present invention can be applied to two-phase modulation in which the period of the carrier signal H and its frequency are changed.

  Alternatively, the on / off pattern generation unit 16g stores a correspondence relationship between each of the zero voltage vector and the non-zero voltage vector and the on / off state of each switch element SW1 to SW6, and the on / off pattern corresponding to the array pattern is associated with the correspondence. It may be generated based on the relationship and the implementation period of each voltage vector.

  Here, the control circuit 16 can be configured to include a microcomputer and a storage device. The microcomputer executes each processing step (in other words, a procedure) described in the program. The storage device is composed of one or more of various storage devices such as a ROM (Read Only Memory), a RAM (Random Access Memory), a rewritable nonvolatile memory (EPROM (Erasable Programmable ROM), etc.), and a hard disk device, for example. Is possible. The storage device stores various information, data, and the like, stores a program executed by the microcomputer, and provides a work area for executing the program. It can be understood that the microcomputer functions as various means corresponding to each processing step described in the program, or can realize that various functions corresponding to each processing step are realized. Further, the control circuit 16 is not limited to this, and various procedures executed by the control circuit 16 or various means or various functions implemented may be realized by hardware.

<Specific example of two-phase modulation>
A specific example of the two-phase modulation employed in the power conversion device 1 will be described. The arrangement relationship between the non-zero voltage vectors V1 to V6 and the regions S1 to S6 is set as shown in FIG. FIG. 15 shows phases that can be selected as phases (fixed phases) in which the ON / OFF state of the upper arm element or the lower arm element is fixed during the two-phase modulation for each of the regions S1 to S6.

S1 to S6 in the upper part of FIG. 15 indicate regions where the voltage command vector V ^* exists. In the left column, indicated as U-phase, V-phase, and W-phase, “1” means that the upper arm element can be fixed in the ON state, and “0” indicates that the lower arm element is fixed in the ON state. A blank means that neither the upper arm element nor the lower arm element can be fixed in the ON state.

For example, paying attention to the S1 column, when the voltage command vector V ^* exists in the region S1, the U-phase upper arm element SW1 may be fixed to the ON state, or the W-phase lower arm element SW6 may be turned on. It can be fixed to.

  FIGS. 16 to 18 show examples of selecting a stationary phase by normal two-phase modulation based on FIG.

  In the example shown in FIG. 16, switching of the stationary phase is prohibited inside each of the regions S1 to S6, and switching of the stationary phase is performed between the adjacent regions S1 to S6. That is, this corresponds to the arrangement pattern shown in FIG.

  In the example shown in FIG. 17, the stationary phase is switched inside each of the regions S1 to S6, and the stationary phase is not switched between the adjacent regions S1 to S6. That is, this corresponds to the arrangement pattern shown in FIG.

  In the example shown in FIG. 18, the stationary phase is switched inside each of the regions S1 to S6, and the stationary phase is also switched between the adjacent regions S1 to S6. That is, this corresponds to an array pattern in which the array pattern shown in FIG. 5 and the array pattern shown in FIG. 9 are mixed.

  Accordingly, any of the stationary phase selections shown in FIGS. 16 to 18 has the features (A) and (B) using the above-described methods (i), (ii) and (iii), or directly. By obtaining the arrangement pattern, the above-described effects can be obtained.

DESCRIPTION OF SYMBOLS 1 Power converter 10 Three-phase load 12 DC power supply 14 Inverter circuit 16 Control circuit H Carrier wave signal H1 Triangular wave H2 Sawtooth wave P, Pn On-off pattern SW1-SW6 Switch element Vu ^* , Vv ^* , Vw ^* Voltage command value signal V ^* Voltage Command vector Vzn ^{-2, n-1} , Vzn ^{-1, n} , Vzn ^{, n + 1} Zero voltage vector Vα, Vβ Non-zero voltage vector

Claims (5)

A power converter for driving and controlling a three-phase load (10),
For each phase (U, V, W) of the three-phase load, a plurality of switch elements (SW1, SW2; SW3, SW4; SW5, SW6) connected in series to a predetermined DC power source (12) are provided. And an inverter circuit (14) for applying any one of the potentials between the switch elements for each phase to the three-phase load of each phase;
A control circuit (16) that generates an on / off pattern (P) and performs on / off operation of each switch element for each phase based on the on / off pattern;
With
Only the switch elements (SW2, SW4, SW6) connected to the cathode side of the DC power supply (12) or only the switch elements (SW1, SW3, SW5) connected to the anode side of the DC power supply. Each of the on-states (V0, V7) is set as a zero voltage vector, and the other combinations of the on-off operations (V1 to V6) are set as non-zero voltage vectors,
In the on-off pattern,
(A) A plurality of continuous non-zero voltage vectors sandwiched by the same zero voltage vector (Vz ^{n−2, n−1} , Vz ^{n−1, n} ) are two-phase modulation patterns together with the zero voltage vector. Form the
(B) A plurality of consecutive non-zero voltage vectors sandwiched by a pair of different zero voltage vectors (Vz ^{n−1, n} , Vz ^{n, n + 1} ) is ^{one of the} pair of zero voltage vectors. To the other of the pair of zero voltage vectors, the on / off operation is formed once for each phase. The control circuit includes:
A voltage command vector generation unit (16e) for specifying a voltage command vector;
An on / off pattern generator (16g) for generating the on / off pattern (P) based on the voltage command vector;
A control signal generation unit (16h) for performing on / off operation of each switch element based on the on / off pattern generated by the on / off pattern generation unit;
The on-off pattern generation unit
Determining a sequence pattern of a series of the zero voltage vector (V0, V7) and the non-zero voltage vector (Vα, Vβ: α, β = 1 to 6) that expands the voltage command vector in two-phase modulation;
When a pair of mutually different zero voltage vectors in the arrangement pattern continues without passing through the non-zero voltage vector, one of the pair of zero voltage vectors which is later in order (V7) is replaced with the pair of zero voltage vectors. Of the zero voltage vectors of the first non-zero voltage vector (V6) immediately after the one of the zero voltage vectors, and the first non-zero voltage vector. The order of the second non-zero voltage vector (V2) immediately after the zero voltage vector is changed to correct the array pattern, and then the on / off pattern (P) corresponding to the array pattern is generated. The power converter described. The control circuit includes:
A voltage command vector generation unit (16e) for specifying a voltage command vector;
An on / off pattern generator (16g) for generating the on / off pattern (P) based on the voltage command vector;
A control signal generation unit (16h) for performing on / off operation of each switch element based on the on / off pattern generated by the on / off pattern generation unit;
The on-off pattern generation unit
Determining a sequence pattern of a series of the zero voltage vector (V0, V7) and the non-zero voltage vector (Vα, Vβ: α, β = 1 to 6) that expands the voltage command vector in two-phase modulation;
When a pair of different zero voltage vectors in the array pattern continues without the non-zero voltage vector, the order of the pair of zero voltage vectors is later (V7), immediately thereafter Of the first non-zero voltage vector (V6), the second non-zero voltage vector (V2; V4) immediately after the first non-zero voltage vector, and the second non-zero voltage vector. The third non-zero voltage vector (V6) immediately after the second non-zero voltage vector (V2; V4), the first non-zero voltage vector (V6), and the third non-zero voltage vector. 2. The power variation according to claim 1, wherein the on / off pattern (P) corresponding to the arrangement pattern is generated after the order of (V6) and the one of the zero voltage vectors (V7) is changed. Apparatus. The on / off pattern generation unit (16g) generates an on / off pattern based on the magnitude relationship between the carrier wave signal (H) and the voltage command value signals (Vu ^* , Vv ^* , Vw ^* ) corresponding to the phases,
(i) The on / off pattern corresponding to the same zero voltage vector (Vz ^{n−2, n−1} , Vz ^{n−1, n} ) and a plurality of the non-zero voltage vectors sandwiched between the zero voltage vectors. Is generated by employing a triangular wave as the carrier signal,
(ii) The on / off pattern corresponding to a pair of different zero voltage vectors (Vz ^{n−1, n} , Vz ^{n, n + 1} ) and a plurality of the non-zero voltage vectors sandwiched between the zero voltage vectors. The power conversion device according to claim 2, wherein a sawtooth wave is adopted as the carrier signal. In the on / off pattern (P), a zero voltage vector adjacent to each other through a plurality of non-zero voltage vectors between a pair of the zero voltage vectors (Vz ^{n−2, n−1} , Vz ^{n, n + 1} ). 5. The power conversion device according to claim ^{1, wherein} (Vz ^{n−1, n} ) is the same as at least one of the pair of zero voltage vectors.

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