JP5606516B2 - NAF converter - Google Patents

Description

  The present invention relates to a NAF conversion device that converts an integer represented in binary to a redundant binary representation.

  The fact that multiplication can be made efficient by converting the multiplier into a redundant binary representation and already being known, for example, as the Booth method in the 1950s (see, for example, Non-Patent Document 1 and Non-Patent Document 2) ). Recently, NAF, which is a kind of redundant binary representation, is often used in the context of speeding up cryptographic processing (see, for example, Non-Patent Document 3 and Non-Patent Document 2).

  NAF is described on page 98 of Non-Patent Document 2, for example. NAF is a kind of redundant binary representation, and the integer k has only one corresponding NAF representation NAF (k). The number of non-zero digits in NAF (k) has proven to be the smallest among any redundant binary representations. The average number of non-zero digits is 1/3.

  In normal binary representation, two types of numbers, 0 or 1, appear in each digit, but in NAF, there is a difference that numbers of -1, 0, 1 appear.

  The NAF expression has a feature that at least one of the subsequent two digits is 0, which is also a reason for the low density. It is also the origin of the name Non-adjacent form.

  As an example, if the binary number 11011 (59 = 32 + 16 + 8 + 2 + 1 in decimal) is converted to NAF, 1000-10-1 (64-4-1 = 59) is obtained.

Table 1 shows an example in which a binary number of 4 bits or less is converted to NAF.

  A number of algorithms for converting an integer k into a NAF representation NAF (k) are known. For example, it is described in page 39 (Table 3.2) of Non-Patent Document 4, page 98 (Algorithm 3.30) of Non-Patent Document 3, and 151 (Algorithm 9.14) of Non-Patent Document 2. .

  There is w-NAF as an extension of NAF (see, for example, page 99 of Non-Patent Document 3).

  The difference between w-NAF and normal NAF is that w-NAF has more numbers available for each digit. If it is 3-NAF, five types of -3, -1, 0, 1, 3 can be used. The above NAF can be considered as 2-NAF.

  Tables 2 and 3 below show the characteristics of w-NAF.

Table 2 lists the numbers used in each NAF.

  However, “^” is a power (冪). For example, 2 ^ w means 2 to the power of w.

Table 3 lists the non-zero digit density of each NAF.

  The w-NAF is characterized in that at least one non-zero digit among the following w digits is at most. The lower the density, the fewer the number of digits to process, so the number of clocks decreases. However, there is a trade-off because more preparations are required.

  Regarding the conversion algorithm of w-NAF, there are Non-Patent Document 3 page 100 (Algorithm 3.35) and Non-Patent Document 2 page 153 (Algorithm 9.20).

  Consider the conventional NAF conversion algorithm.

  The algorithm 3.35 of Non-Patent Document 3 and the algorithm 9.20 of Non-Patent Document 2 are characterized by high scalability that can be applied to any w, but on the other hand, there are the following problems: is there.

・ K cannot be input sequentially. In other words, k must be read first. This is because k itself is changed.

Since the change to k is a multiple-length operation, the circuit scale increases, and the number of clocks required to obtain one digit increases.

  Regarding Table 3.2 of Non-Patent Document 4, there is no description that NAF conversion is in Non-Patent Document 4, but what is output as a result is NAF conversion. This algorithm does not have the disadvantages of the above two algorithms. That is, k can be processed sequentially and multiple length arithmetic is not necessary. However, since it can be applied only when w = 2, there is a problem that there is no scalability. The algorithm 9.14 of Non-Patent Document 2 has the same features and disadvantages.

A.D.Booth, "A signed binary multiplication technique", Quart. J. Mech. Appl. Math., 4, 2, 236-240, 1951. "Handbook of Elliptic and Hyperelliptic Curve Cryptography", CRC, 2006 "Guide to Elliptic Curve Cryptography", Springer, 2003 "VLSI algorithms for arithmetic operations" Corona, 2005

  As described above, the known NAF conversion algorithm has a problem that scalability and circuit scale are not compatible.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a scalable w-NAF conversion device with a small circuit scale.

  A NAF conversion device according to an aspect of the present invention is a NAF conversion device that converts a binary-represented integer into a redundant binary representation represented by w-NAF. Accepting means for receiving bit by bit, storage means for storing a value of a state expressed by 1 bit, a shift register for storing a value of a state expressed by w−1 bits, and a 1-bit received by the receiving means With reference to the value, the state value of the storage means, and the state value of the w-1 bit shift register, the state of the storage means and the state of the w-1 bit shift register at the next time Updating means for determining and determining w-bit parallel output at the current time.

  According to the present invention, a scalable w-NAF conversion device with a small circuit scale can be provided. In particular, since there is almost no different part for an arbitrary w (only the length of the shift register), it is possible to dynamically change w. In addition, the circuit scale is smaller than the known conversion algorithm dedicated to 2-NAF, and further smaller than the known w-NAF conversion algorithm.

Block diagram showing the functional configuration of the w-NAF converter Diagram showing 2-NAF converter Illustration of the selector description method A diagram showing a conversion example of a 2-NAF conversion device Diagram showing a 3-NAF converter The figure which shows the example of a conversion of 3-NAF converter Diagram showing a 4-NAF converter Diagram showing 2-4-NAF converter Figure showing the 2-NAF state transition table Figure showing a 2-NAF state transition diagram Figure showing the 3-NAF state transition table Diagram showing 3-NAF state transition diagram Figure showing the 4-NAF state transition table Figure showing the 5-NAF state transition table

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a functional configuration of a NAF conversion device according to an embodiment of the present invention. This apparatus receives a 1-bit serial input, an updating unit 2 connected to the receiving unit 1, an updating unit 2 connected to the updating unit 2, and outputs a w-bit value expressed in w-NAF in parallel. It has a 1-bit shift register 3 and a 1-bit storage means 4 connected to the update means 2. When the NAF conversion device is configured by hardware, the reception unit 1 does not need to be provided independently, and a connection portion where the signal line and the update unit are connected corresponds.

  The initial values of the 1-bit storage means 4 and the w-1 bit shift register 3 are 0.

  In the NAF conversion device according to the present embodiment, the reception unit 1 receives a binary representation of an integer to be converted into a w-NAF representation bit by bit in order from the lower bit in accordance with the clock. This accepted value is called 1-bit serial input. The contents of the 1-bit storage means 4 and the w-1 bit shift register 3 are replaced with new contents by the update means 2 every clock, that is, every time 1 bit is input.

  The updating unit 2 calculates the new contents of the 1-bit storage unit 4 and the w-1 bit shift register 3 according to the contents of the 1-bit storage unit 4 and the w-1 bit shift register 3 and the 1-bit serial input before the update. To do. The updating means 2 determines w-bit parallel output. That is, a w-bit conversion result is output for each clock. At this time, a valid output is output after w-1 clocks. The value “1” of the least significant bit output is given to the w−1 bit shift register 3 as a clear input of a trigger for clearing the w−1 bit shift register 3. When the value “1” of the least significant bit output is given to the w−1 bit shift register 2, the value of the w−1 bit shift register 2 is cleared.

  With reference to FIG. 2, a 2-NAF conversion device that further embodies the NAF conversion device of FIG. 1 will be described. As shown in FIG. 2, C included in the 2-NAF conversion device corresponds to the 1-bit storage unit 4 in the configuration of FIG. Similarly, S0 corresponds to 1-bit shift register 3 (w = 2 = 1 because w = 2). Y1 and Y0 correspond to 2-bit parallel output. + Is a 1-bit adder and corresponds to the element of the updating means 2 in FIG.

  Special symbols are illustrated in FIG. The selector is described as shown in FIG. That is, when the selection signal S is 1, the output is C = A, and when S is 0, the output is C = B.

  In FIG. 1, the configuration in which the least significant bit output is given as the clear input of the w-1 bit shift register corresponds to the configuration in which Y0, which is a part of the parallel output, is given as the selector selection signal S0 in FIG.

  The initial values of C and S0 are zero. When S0 is 1, the next value of C is the lower bit of the input + C, the next value of S0 is 0, Y1 is the lower bit of the input + C, and Y0 is S0, that is, 1. On the other hand, when S0 is 0, the next value of C is the upper bit of input + C, the next value of S0 is the lower bit of input + C, Y1 is the lower bit of input + C, and Y0 is S0, 0. Note that the value of Y1 is written to S0 at the timing of the next clock.

  Referring to FIG. 4, an actual conversion example of this 2-NAF conversion device will be shown. FIG. 4 is in a timing chart format, and various values are updated each time a clock is input. In FIG. 4, clk is a clock, start is a start signal, in is an input, c is a 1-bit storage means 4, s is a 1-bit shift register 3, and out is a 2-bit parallel output.

  An example in which a binary number 1111011 (59 = 32 + 16 + 8 + 2 + 1 in decimal) is input is shown. Looking at the in line, it can be seen that 111011 are inputted in order from the lower order for each clock. The output is delayed by one clock from the input.

  The way to read the output out is “0” when “00” or “10”, “1” when “01”, and “−1” when “11”.

  As described above, there are a plurality of outputs expressing 0, but when all are even numbers and the least significant bit is 0, it is only necessary to regard the output as 0. Note that when the output is other than 0, it is expressed in 2-bit 2's complement. In general, in the case of w-NAF, if the least significant bit of the output is 0, it is 0, and if it is 1, the w bit is represented in 2's complement. A clear 0 can also be output by ANDing the least significant bit with the least significant bit other than the least significant bit of the output. The result is also output from the lower order. According to FIG. 4, it can be seen that the output is −10−10000 from the lower order. This is 1000-10-1 when read from the top, and since 64-4-1 = 59, it can be seen that the same number as the original binary number is expressed. The original binary number of non-zero (1) bits is 5, but after NAF conversion, the number of non-zero digits is reduced to 3 after NAF conversion. In the NAF conversion, the number of output bits may be up to the original number of bits + 1, and this example is also the same.

  FIG. 5 shows a 3-NAF conversion device which is an embodiment of the NAF conversion device of FIG. As shown in FIG. 5, C included in the 3-NAF conversion device corresponds to the 1-bit storage unit 4 in the configuration of FIG. Similarly, S1 and S0 correspond to a 2-bit shift register 3 (w = 3, so w-1 = 2 bits). Y2, Y1, and Y0 correspond to 3-bit parallel output. + Is a 1-bit adder and corresponds to the element of the updating means 2 in FIG. In FIG. 1, the configuration in which the least significant bit output is given as the clear input of the w-1 bit shift register is the configuration in which Y0 which is a part of the parallel output is given as the selection signal S0 of each of the two selectors in FIG. Corresponding to

  Comparing the 2-NAF conversion device of FIG. 2 with the 3-NAF conversion device of FIG. 5, only Y2 and S1 are increased. The operation is the same as that of the 2-NAF converter.

  The initial values of C and S0 are zero. When S0 is 1, the next value of C is the lower bit of input + C, the next value of S1 and S0 is 0, Y2 is the lower bit of input + C, Y1 is S1, and Y0 is S0, that is, 1. On the other hand, when S1 is 0, the next value of C is the upper bit of input + C, the next value of S1 is the lower bit of input + C, the next value of S0 is S1, and Y2 is input + C Y1 is S1, and Y0 is S0, that is, 0.

  With reference to FIG. 6, an actual conversion example of the 3-NAF conversion device will be described. FIG. 6 is in a timing chart format, and various values are updated each time a clock is input. In FIG. 6, clk is a clock, start is a start signal, in is an input, c is a 1-bit storage means 4, s is a 2-bit shift register 3, and out is a 3-bit parallel output.

  An example in which a binary number 1111011 (59 = 32 + 16 + 8 + 2 + 1 in decimal) is input is shown. Looking at the in line, it can be seen that 111011 are inputted in order from the lower order for each clock. The output is 2 clocks behind the input. The way to read the output out is “0” when “000”, “010”, “100”, “110”, “1” when “001”, and “3” when “011”. Yes, "-3" when "101", "-1" when "111".

  As described above, there are a plurality of outputs expressing 0, but when all are even numbers and the least significant bit is 0, it is only necessary to regard the output as 0. Also, note that when the output is other than 0, it is expressed in 2's complement notation. The result is also output from the lower order. It can be seen that 300-1001 is output in order from the lower order. This is 100-1003 when read from the top, and 64-8 + 3 = 59, so it can be seen that the same number as the original binary number is expressed. In the NAF conversion, the number of output bits may be up to the original number of bits + 1, and this example is also the same.

  FIG. 7 shows a 4-NAF conversion device that is a further embodiment of the NAF conversion device of FIG. As shown in FIG. 7, C included in the 4-NAF converter corresponds to the 1-bit storage unit 4 in the configuration of FIG. Similarly, S2, S1, and S0 correspond to the 3-bit shift register 3 (w = 1 = 3 because w = 4). Y3, Y2, Y1, and Y0 correspond to 4-bit parallel output. + Is a 1-bit adder, which is an element of the updating means 2 in FIG.

  When comparing the 2-NAF conversion device of FIG. 2 or the 3-NAF conversion device of FIG. 5 with the 4-NAF conversion device of FIG. 7, it can be seen that the shift register 3 and the output have the same structure just by increasing the output. .

  Referring to FIG. 8, an example of a k-NAF conversion device that makes k variable is shown. In this example, 2, 3 and 4 can be selected as the value of k. In FIG. 8, C of the k-NAF conversion device corresponds to the 1-bit storage means 4 in the configuration shown in FIG. S2, S1, and S0 correspond to the 3-bit shift register 3 (w = 1 = 3 because w = 4) in the configuration of FIG. Y3, Y2, Y1, and Y0 correspond to 4-bit parallel output. + Is a 1-bit adder.

  S is the least significant bit depending on k. In order to operate k = 2, that is, to operate this apparatus as a 2-NAF conversion apparatus, it is sufficient to adopt S2 as the least significant bit S. Similarly, to operate as a 3-NAF conversion apparatus, as the least significant bit S, S1 may be adopted, and the least significant bit in the case of the 4-NAF conversion device may be S = S0. At this time, the output is Y3 and Y2 for 2-NAF, Y3, Y2, Y1 for 3-NAF, and Y4, Y3, Y2, Y1, Y0 for 4-NAF.

  In a situation where the memory is limited as in a portable device, the calculation itself is slowed down by reducing w, but the memory can be saved. In general, increasing w increases calculation speed but increases memory consumption. For example, the calculation can be speeded up by reducing w when the memory is low and increasing w when the memory is high. Further, power can be saved by reducing w and stopping power supply to unnecessary registers.

  With reference to FIG. 9, the above-described 2-NAF conversion device will be described from another viewpoint. That is, the 2-NAF conversion device according to this embodiment will be described in the form of a state transition table as shown in FIG. In FIG. 9, s is the current state (possible states are 3 states), in is a 1-bit input, s' is the next state, and out is an output. The initial state is s = 0. Each time the input in is input bit by bit, the state transitions to s' determined by s and in, and the output out is output.

  In the first state, when the input is 0, the state transitions to the first state and outputs 0, and when the input is 1, the state transitions to the second state and 0 is output. In the second state, when the input is 0, the state transitions to the first state and 1 is output, and when the input is 1, the state transitions to the third state and -1 is output. In the third state, when the input is 0, the state transitions to the second state and outputs 0, and when the input is 1, the state transitions to the third state and 0 is output. When the integer expressed in binary is input bit by bit from the lower order, a redundant binary expression expressed in 2-NAF is output bit by bit.

  The 2-NAF conversion device will be further described with reference to FIG. In FIG. 10, states are circled and correspond to s in the state transition table. There are three states. Number / number means that when the left number is in and the right number is out and the left number is input, the right number is output. FIG. 10 like this is a rewrite of the state transition table of FIG. 9 into a state transition diagram. The initial state is state 0.

  With reference to FIG. 11, the above-described 3-NAF conversion device will be described from another viewpoint. That is, the 3-NAF conversion device according to the present embodiment will be described along the format of the state transition table as shown in FIG. The value that can be taken as the state s has increased from 0 to 4 to 5 states, and since the output is 3-NAF, there are five types of -3, -1, 0, 1, and 3.

  In the first state, when the input is 0, the state transitions to the first state and outputs 0, and when the input is 1, the state transitions to the third state and 0 is output. In the second state, when the input is 0, the state transitions to the first state and outputs 1, and when the input is 1, the state transitions to the fifth state and -3 is output. In the third state, when the input is 0, the state transitions to the second state and outputs 0, and when the input is 1, the state transitions to the fourth state and 0 is output. In the fourth state, when the input is 0, the state transitions to the first state and 3 is output, and when the input is 1, the state transitions to the 5th state and −1 is output. In the fifth state, when the input is 0, the state transitions to the third state and outputs 0, and when the input is 1, the state transitions to the 5th state and outputs 0. Thus, when an integer expressed in binary is input bit by bit from the lower order, a redundant binary expression expressed in 3-NAF is output in units of 3 bits.

  FIG. 12 is a rewrite of the state transition table of FIG. 11 into a state transition diagram, and is the same as FIG.

  With reference to FIG. 13, the above-described 4-NAF conversion device will be described from another viewpoint. That is, the 4-NAF conversion device according to the present embodiment will be described according to the format of the state transition table as shown in FIG. The possible values for state s have increased from 0 to 9 states. Since the output is 4-NAF, there are nine outputs of -7, -5, -3, -1, 0, 1, 3, 5, and 7.

  In the first state, when the input is 0, the state transitions to the first state and outputs 0, and when the input is 1, the state transitions to the 5th state and 0 is output. In the second state, when the input is 0, the state transitions to the first state and outputs 1, and when the input is 1, the state transitions to the 9th state and outputs -7. In the third state, when the input is 0, the state transitions to the second state and outputs 0, and when the input is 1, the state transitions to the sixth state and 0 is output. In the fourth state, when the input is 0, the state transitions to the first state and 3 is output, and when the input is 1, the state transitions to the 9th state and −5 is output. In the fifth state, when the input is 0, the state transitions to the third state and outputs 0, and when the input is 1, the state transitions to the 7th state and outputs 0. In the sixth state, when the input is 0, the state transitions to the first state and 5 is output, and when the input is 1, the state transitions to the 9th state and -3 is output. In the seventh state, when the input is 0, the state transitions to the fourth state and outputs 0, and when the input is 1, the state transitions to the 8th state and outputs 0. In the eighth state, when the input is 0, the state transitions to the first state and 7 is output, and when the input is 1, the state transitions to the 9th state and -1 is output. In the ninth state, when the input is 0, the state transitions to the fifth state and outputs 0, and when the input is 1, the state transitions to the 9th state and outputs 0. When an integer expressed in binary is input bit by bit from the lower order, a redundant binary expression expressed in 4-NAF is output every 4 bits.

  FIG. 14 shows a 5-NAF converter. The state transition table is the same as that described in FIG. The value that can be taken as the state s has increased from 0 to 17 states. In general, in the case of w-NAF, 2 ^ (w-1) +1 state is taken.

  Although the above-described embodiment can be realized by a sequential circuit, it can be realized as a synchronous circuit or an asynchronous circuit.

  New cryptographic attack methods such as side channel attacks have appeared. According to the embodiment described above, it is possible to prevent a side channel attack by changing w during the scalar multiplication of elliptic curve cryptography. w can be changed when the shift register is zero. That is, it is when a value other than 0 is output immediately before.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 ... acceptance means;
2 ... Update means;
3 ... w-1 bit shift register;
4 ... 1 bit storage means

Claims (3)

1-bit serial input for inputting an integer expressed in binary one bit at a time starting from the least significant digit ;
A 2-bit parallel output that outputs a redundant binary representation in which the integer is represented by 2-NAF in an order of 2 bits from the least significant digit ;
Storage means for storing three states including a first state, a second state, and a third state ;
The initial state is the first state,
In the first state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the first state, and outputs a 2-bit represents 0,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to the second state, and outputs a 2-bit represents 0,
In the second state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the first state, and outputs a 2-bit representing a,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to said third state, and outputs a 2 bits representing -1,
In the third state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the second state, and outputs a 2-bit represents 0,
Wherein when 1 bit input by 1-bit serial input is 1, and updating means for the state changes to said third state, and outputs the two bits represents 0,
Comprising
The 2-bit parallel output is the 2-bit output by the updating means when a bit of the (i + 1) -th integer (i is an integer of 1 or more) is input by the 1-bit serial input. Output as the i-th smallest digit of the redundant binary representation,
2-NAF converter. 1-bit serial input for inputting an integer expressed in binary one bit at a time starting from the least significant digit ;
A 3-bit parallel output for outputting a redundant binary representation in which the integer is expressed in 3-NAF in an order of 3 bits from the least significant digit ;
Storage means for storing five states including a first state, a second state, a third state, a fourth state, and a fifth state ;
The initial state is the first state,
In the first state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the first state to output the three bits represents 0,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to said third state to output the three bits represents 0,
In the second state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the first state, and outputs a 3-bit representing a,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to the fifth state to output the three bits representing the -3,
In the third state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the second state, and outputs the three bits represents 0,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to the fourth state, and outputs the three bits represents 0,
In the fourth state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the first state to output the three bits representing the 3,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to the fifth state to output the 3 bits representing -1,
In the fifth state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to said third state to output the three bits represents 0,
Wherein when 1 bit input by 1-bit serial input is 1, and updating means for state transition to the fifth state, and outputs the three bits represents 0,
Comprising
The 3-bit parallel output is obtained by outputting the 3 bits output by the updating means when a bit of the integer (i + 2) th (i is an integer of 1 or more) is input by the 1-bit serial input. Output as the i-th smallest digit of the redundant binary representation,
3-NAF converter. 1-bit serial input for inputting an integer expressed in binary one bit at a time starting from the least significant digit ;
A 4-bit parallel output that outputs a redundant binary representation in which the integer is expressed in 4-NAF in order of 4 bits from the least significant digit ;
Nine states including a first state, a second state, a third state, a fourth state, a fifth state, a sixth state, a seventh state, an eighth state, and a ninth state Storage means for storing;
The initial state is the first state,
In the first state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the first state, and outputs a 4-bit represents 0,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to the fifth state, and outputs a 4-bit represents 0,
In the second state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the first state, and outputs a 4-bit representing a,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to the state of the ninth, and outputs a 4-bit representing the -7,
In the third state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the second state, and outputs a 4-bit represents 0,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to the state of the sixth, and outputs a 4-bit represents 0,
In the fourth state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the first state, and outputs a 4-bit representing a 3,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to the state of the ninth, and outputs a 4-bit representing a -5,
In the fifth state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to said third state, and outputs a 4-bit represents 0,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to the state of the seventh, and outputs a 4-bit represents 0,
In the sixth state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the first state, and outputs a 4-bit representing a 5,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to the state of the ninth, and outputs a 4-bit representing the -3,
In the seventh state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the fourth state, and outputs a 4-bit represents 0,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to the state of the eighth, and outputs a 4-bit represents 0,
In the eighth state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the first state, and outputs a 4-bit representing a 7,
Wherein when 1 bit input by 1-bit serial input is 1, the state changes to the state of the ninth, and outputs a 4-bit representing a -1,
In the ninth state,
Wherein when 1 bit input by 1-bit serial input is 0, the state changes to the fifth state, and outputs a 4-bit represents 0,
Wherein when 1 bit input by 1-bit serial input is 1, and updating means for the state changes to the state of the ninth, and outputs a 4-bit represents 0,
Comprising
The 4-bit parallel output is the 4-bit output by the updating means when the (i + 3) th bit (i is an integer of 1 or more) of the integer is input by the 1-bit serial input. Output as the i-th smallest digit of the redundant binary representation,
4-NAF converter.

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