JP5606380B2 - Hold circuit - Google Patents

Description

  The present invention relates to a hold circuit, and more particularly to a peak hold circuit that holds a peak value of an input signal and a bottom hold circuit that holds a bottom value of an input signal.

  For example, various sensors are mounted on an automobile. These sensors include those whose output signals (sensor signals) have temperature dependence. A hold circuit may be used to compensate for the temperature dependence of the sensor signal. In this case, the hold circuit holds the peak value (bottom value) of the sensor signal, and the sensor signal is corrected based on the peak value (bottom value). In order to compensate the temperature dependence of the sensor signal with high accuracy, it is desired that the hold circuit holds the peak value (bottom value) of the sensor signal with high accuracy.

  In addition, for example, the sensor may be mounted out of the intended mounting position. In that case, the magnitude (voltage amplitude) of the sensor signal may deviate from the initially assumed magnitude. Therefore, it is desired that the hold circuit accurately holds the peak value (bottom value) even when a large voltage (a large amplitude sensor signal) is input. In other words, the hold circuit is desired to expand the input voltage amplitude range.

  Furthermore, for example, when the hold circuit is used as an in-vehicle device, it is desired that the hold circuit operate accurately in various temperature environments (for example, in a high temperature environment).

  Patent Document 1 discloses a hold circuit. The hold circuit of Patent Document 1 includes an input terminal, a switch circuit, a switching circuit for switching on / off of the switch circuit, a capacitor, a reference voltage terminal, and a reset circuit for discharging electric charge stored in the capacitor. Have. Here, the input terminal, the switch circuit, the capacitor, and the reference voltage terminal are connected in series in this order.

  In the hold circuit of Patent Document 1, when the reset circuit discharges the electric charge stored in the capacitor, the switching circuit turns off the switch circuit. By doing so, it is prevented that a through current flows from the input terminal to the reference voltage terminal when discharging the electric charge. As a result, the hold circuit disclosed in Patent Document 1 can reduce power consumption.

  Patent Document 1 states that it is desirable to configure a switch circuit using an insulated gate transistor. In such a case, Patent Document 1 states that in order to improve the accuracy of the hold circuit, it is desirable to connect the well region of the insulated gate transistor to the output terminal.

  In an insulated gate transistor, the conductivity type is different between the well region and the contact region, so that a parasitic diode is formed between the contact region and the well region. Therefore, when a large potential difference is generated between the well region and the contact region, a current flows through the parasitic diode, the capacitor is charged and discharged, and the voltage applied to the capacitor may fluctuate.

  Therefore, in Patent Document 1, the contact region is connected to the capacitor and the well region is connected to the output terminal so as not to cause a potential difference between the contact region and the well region. With this configuration, improvement in detection accuracy of the hold circuit can be expected.

  However, in the configuration described above, the voltage in the well region of the insulated gate transistor, which is a switch circuit for appropriately leading the input signal to the capacitor, is equal to the voltage at the output terminal. For this reason, the threshold voltage increases due to the substrate bias effect, which causes a problem that the hold circuit cannot hold a peak value with a large voltage amplitude.

  In Patent Document 1, in order to solve this problem, the switch circuit includes a p-type insulated gate transistor including two p-type insulated gate transistors connected in series and two n-type connected in series. The n-type insulated gate transistor including the insulated gate transistor is used as a complementary switch circuit, thereby expanding the operating voltage range (voltage range that can be held).

JP 2010-028215 A

  However, in the above-described policy of expanding the operating voltage range of the hold circuit by configuring the switch circuit as a complementary switch circuit, the expanded voltage range is relatively small. Therefore, this measure cannot be said to be a measure that fundamentally solves the above problem.

  The insulated gate transistor has a property that the threshold voltage increases as the temperature increases. Therefore, the above-described configuration also has a problem that the operating voltage range of the hold circuit is further narrowed when the temperature of the insulated gate transistor rises.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a hold circuit that operates accurately over a wide operating voltage range.

  The hold circuit according to the present invention is an input terminal to which an input signal is input and an amplifier, an amplifier having an input terminal to which an input signal is input to the non-inverting input terminal, and an inverting amplifier, An inverting amplifier having an input terminal connected to the output terminal of the amplifier and a capacitor, having one end connected to the inverting input terminal of the amplifier and the other end connected to a reference potential, and a buffer circuit. A buffer circuit having one end of the capacitor connected to its input terminal, an output voltage output terminal connected to the output terminal of the buffer circuit, an output terminal of the amplifier connected to the gate terminal, and an output terminal of the buffer circuit to the source terminal Is connected, the voltage source is connected to the bulk, the output terminal of the inverting amplifier is connected to the gate terminal, the voltage to the source terminal and the bulk Are connected, the drain terminal is connected to the drain terminal of the first transistor, the gate terminal is connected to the output terminal of the inverting amplifier, and the source terminal and the bulk are connected to the drain terminal of the first transistor and the second transistor. Is a hold circuit having a third transistor connected to one end of the capacitor and an input terminal of the buffer circuit.

  In the hold circuit according to the present invention, the voltage applied to the source and bulk of the transistor (third transistor) connected to the capacitor that holds the voltage corresponding to the magnitude of the input signal is related to the level of the input signal voltage and the output voltage. By adjusting to an appropriate value accordingly, an increase in threshold voltage and an increase in leakage current of the transistor can be suppressed, and the transistor can operate with high accuracy in a wide operating voltage range.

A circuit diagram showing a configuration of a peak hold circuit according to the first embodiment. Circuit diagram showing configuration example of inverting amplifier Circuit diagram showing configuration example of buffer circuit Circuit diagram (a) and sectional view (b) of p-type transistor on p-type semiconductor substrate The figure of the time change of each voltage by operation of the peak hold circuit of Embodiment 1 A circuit diagram showing a configuration of a peak hold circuit according to a second embodiment. The figure of the time change of each voltage by operation of the peak hold circuit of Embodiment 2 Circuit diagram showing configuration of peak hold circuit according to embodiment 3 Circuit diagram showing configuration of peak hold circuit according to embodiment 4 Circuit diagram showing configuration of peak hold circuit according to embodiment 5 The circuit diagram which shows the structure of the bottom hold circuit by Embodiment 6 The figure of the time change of each voltage by operation of the bottom hold circuit of Embodiment 6.

  Hereinafter, embodiments of the present invention will be described in detail. Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component. The following circuit is an example of the circuit, and is not limited thereto.

  The hold circuit (peak hold circuit, bottom hold circuit) according to the embodiment of the present invention is a hold circuit having a relatively wide operating voltage range.

  In the peak hold circuit according to the embodiment of the present invention, when the output voltage is lower than the voltage of the input signal, the voltage of the source and bulk (well region) of the transistor connected to one electrode of the capacitor is set to the voltage of the voltage source. The transistor is operated close to it. By doing so, the substrate bias effect of the transistor can be reduced, and thus the operating voltage range of the input signal can be widened. When the output voltage is higher than the voltage of the input signal, the voltage of the source and bulk (well region) of the transistor connected to one electrode of the capacitor is brought close to the voltage of the output terminal to operate the transistor. By doing so, the potential difference applied to the parasitic diode formed between the drain and bulk (well region) of the transistor can be reduced, and thus the leakage current that increases as the temperature of the parasitic diode increases is reduced. It can be made extremely small. This improves the peak value detection accuracy of the peak hold circuit.

  In the bottom hold circuit according to the embodiment of the present invention, when the output voltage is higher than the voltage of the input signal, the voltage of the source and bulk (well region) of the transistor connected to one electrode of the capacitor is brought close to the reference potential. The transistor is operated. By doing so, the substrate bias effect of the transistor can be reduced, and thus the operating voltage range of the input signal can be widened. When the output voltage is lower than the voltage of the input signal, the transistor is operated by bringing the voltage of the source and bulk (well region) of the transistor connected to one electrode of the capacitor close to the voltage of the output terminal. By doing so, the potential difference applied to the parasitic diode formed between the drain and bulk (well region) of the transistor can be reduced, and thus the leakage current that increases as the temperature of the parasitic diode increases is reduced. It can be made extremely small. Thereby, the bottom value detection accuracy of the bottom hold circuit is improved.

Embodiment 1 FIG. (Peak hold circuit)
1-1. Configuration FIG. 1 is a circuit diagram showing a configuration of a peak hold circuit according to a first embodiment of the present invention. A peak hold circuit 100 according to Embodiment 1 shown in FIG. 1 is a circuit that detects and holds a peak value of an input signal (input voltage) Vin and outputs the peak value as an output voltage Vo.

  As shown in FIG. 1, the peak hold circuit 100 includes an input terminal 1, an output terminal 2, a capacitor 5, a first amplifier 6, a buffer circuit 7, an inverting amplifier 8, three transistors 9, 10, And 11 is comprised. The transistors 9, 10, and 11 may be field effect transistors (FETs). The field effect transistor may be an insulated gate transistor. For example, the transistors 9, 10, and 11 may be p-type MOS-FETs.

  The capacitor 5 has one end connected to the terminal (drain) of the transistor 11 and the other end connected to the reference potential 4.

  In the first amplifier 6, the input terminal 1 is connected to the non-inverting input terminal 6a, and one end of the capacitor 5 is connected to the inverting input terminal 6b. The first amplifier 6 of the present invention may be configured as a comparator circuit that binarizes the output voltage to high or low.

  In the buffer circuit 7, one end of the capacitor 5 and the inverting input terminal 6b of the first amplifier 6 are connected to the input terminal 7a, and the output terminal 2 of the peak hold circuit 100 is connected to the output terminal 7b.

  The inverting amplifier 8 has an input terminal 8a connected to the output terminal 6c of the first amplifier 6, and an output terminal 8b connected to the gate of the transistor 10 (second transistor) and the gate of the transistor 11 (third transistor). The

  In the transistor 9 (first transistor), the output terminal 6c of the first amplifier 6 is connected to the gate, the output terminal 2 is connected to the source, and the source and bulk (well region) of the third transistor 11 are connected to the drain. The voltage source 3 is connected to the bulk (well region).

  In the second transistor 10, the output terminal 8b of the inverting amplifier 8 and the gate of the third transistor 11 are connected to the gate, the voltage source 3 is connected to the source and bulk (well region), and the third is connected to the drain. The source and bulk (well region) of the transistor 11 and the drain of the first transistor 9 are connected.

  In the third transistor 11, the output terminal 8 b of the inverting amplifier 8 and the gate of the second transistor 10 are connected to the gate, and the drain of the first transistor 9 and the second transistor 10 are connected to the source and bulk (well region). And one end of the capacitor 5 and the input terminal 7a of the buffer circuit 7 are connected to the drain.

  FIG. 2 is a circuit diagram illustrating a configuration example of the inverting amplifier 8 according to the first embodiment. As shown in FIG. 2, the inverting amplifier 8 includes a second amplifier 16, resistors 18 and 19, and a reference voltage source 17.

  The resistor 18 (first resistor) is connected between the input terminal 8 a of the inverting amplifier 8 and the inverting input terminal 16 b of the second amplifier 16.

  The resistor 19 (second resistor) is connected between the inverting input terminal 16 b of the second amplifier 16 and the output terminal 16 c of the second amplifier 16.

  The reference voltage source 17 is connected to the non-inverting input terminal 16a of the second amplifier 16, the one end of the first resistor 18 and one end of the second resistor 19 are connected to the inverting input terminal 16b, and the output terminal 16c is connected to the output terminal 16c. The output terminal 8b of the inverting amplifier 8 is connected. The inverting amplifier 8 can be realized by an inverter that inverts and outputs an input voltage, and is not limited thereto.

  FIG. 3 is a circuit diagram showing a configuration example of the buffer circuit 7 in the first embodiment. As shown in FIG. 3, the buffer circuit 7 includes a third amplifier 20. The non-inverting input terminal 20a of the buffer circuit 7 is connected to the input terminal 7a of the buffer circuit 7, and the inverting input terminal 20b is connected to the output terminal 7b of the buffer circuit 7 and the output terminal 20c of the third amplifier 20, The output terminal 7b of the buffer circuit 7 is connected to the output terminal 20c. The buffer circuit 7 may be any circuit that converts the impedance of the input terminal 7a and the output terminal 7b, and is not limited to the above configuration.

  FIG. 4 is a circuit diagram and a cross-sectional view showing a configuration example (p-type transistor 21) of the transistors 9, 10, and 11. FIG. 4A is an equivalent circuit diagram of the p-type transistor 21, and FIG. 4B is a cross-sectional view of the p-type transistor 21. As shown in FIG. 4, the p-type transistor 21 is formed on a p-type semiconductor substrate (p-sub) and includes terminals (source 21b, drain 21c) which are p + diffusion layers. The bulk 21d of the p-type transistor 21 is an n + diffusion layer, and has the same potential as the well region (n-well). Parasitic diodes 22, 23, and 24 are formed in the well region (n-well) between the source 21b, the drain 21c, and the p-type semiconductor substrate (p-sub), respectively. The

1-2. Operation The operation of the peak hold circuit 100 will be described with reference to FIG. FIG. 5 is a plot showing the time change of each voltage due to the operation of the peak hold circuit 100.

  The operation of the peak hold circuit 100 will be described by taking as an example the case where the input voltage Vin changes as shown in FIG. That is, the input voltage Vin in this example increases monotonically from time zero to time t1, exhibits a peak value at time t1, and decreases monotonously after time t1.

  While the output voltage Vo is lower than the voltage of the input signal Vin, that is, while approaching time t1 from time zero, the voltage V12 of the output node 12 of the first amplifier 6 (voltage applied to the gate of the first transistor 9) gradually increases. The first transistor 9 is gradually turned on.

  Here, the voltage V13 of the output node 13 of the inverting amplifier 8 is a voltage obtained by inverting the voltage V12 of the output node 12 of the first amplifier 6, and from the time zero to the time t1, The voltage applied to each gate of the transistor 11 gradually increases, and the second transistor 10 and the third transistor 11 are gradually turned off from the on state.

  When the second transistor 10 and the third transistor 11 are in the ON state in the period from time zero to time t1, the voltage of the source of the third transistor 11 and the bulk (well region) (the voltage V14 of the node 14) is the voltage It becomes a voltage near the voltage of the source 3, and charges are accumulated (charged) in the capacitor 5.

  When the time approaches time t1, the second transistor 10 and the third transistor 11 gradually approach the off state, and conversely, the first transistor 9 gradually approaches the on state. As the first transistor 9 gradually approaches the ON state, the voltage of the source and bulk (well region) of the third transistor 11 (the voltage V14 of the node 14) gradually increases from the voltage near the voltage of the voltage source 3 to the output voltage. The voltage approaches the voltage in the vicinity of Vo, and at time t1, the voltage V14 becomes approximately the same as the output voltage Vo.

  As described above, while the output voltage Vo is lower than the voltage of the input signal Vin, the second transistor 10 is turned on and the first transistor 9 is turned off, whereby the source and bulk (well region) of the third transistor 11 are turned on. Can be made substantially equal to the voltage of the voltage source 3 (a voltage in the vicinity of the voltage of the voltage source 3). Thereby, while the electric charge is accumulated in the capacitor 5 according to the input signal Vin, an increase in the threshold voltage of the third transistor 11 is suppressed.

  By operating the first to third transistors 9, 10, 11 in this way, the substrate bias effect of the third transistor 11 can be reduced. Therefore, an increase in the threshold voltage of the third transistor 11 is well suppressed. Therefore, the peak hold circuit 100 can reduce the influence of the input signal Vin on the operating voltage range.

  Further, while the output voltage Vo is higher than the voltage of the input signal Vin, that is, after the time t1, the second transistor 10 is turned off, and the first transistor 9 is turned on, whereby the source of the third transistor 11 and The potential of the bulk (well region) can be a voltage near the output voltage Vo. That is, the potential difference between the source of the third transistor 11 and the bulk (well region) can be made substantially equal to zero. Thereby, the potential difference applied to the parasitic diode formed in the drain and bulk (well region) of the third transistor 11 can be extremely reduced, and the leakage current flowing through the parasitic diode can be reduced.

  In general, when a reverse bias voltage is applied to the parasitic diode formed in the drain and bulk (well region) of the third transistor 11, a leakage current flows. The leakage current increases with an exponential function as the temperature rises, and the amount of charge held in the capacitor 5 varies significantly.

  However, in the peak hold circuit 100, the leakage current flowing through the parasitic diode can be made extremely small, so that the amount of charge held in the capacitor 5 can be prevented from fluctuating. The output voltage Vo can be reliably held, and the peak value detection accuracy of the peak hold circuit 100 can be improved.

1-3. Conclusion In the peak hold circuit 100, when the output voltage Vo is lower than the voltage of the input signal Vin, the source and bulk (well region) of the third transistor 11 are brought close to the voltage of the voltage source 3 (substantially the voltage of the voltage source 3). The substrate bias effect of the third transistor 11 is reduced. Thereby, the operating voltage range of the input signal Vin can be kept wide.

  In the peak hold circuit 100, when the output voltage Vo is higher than the voltage of the input signal Vin, the first transistor 9 is turned on, so that the source and bulk (well region) voltage of the third transistor 11 is peak-held. The voltage of the output terminal 2 of the circuit 100 (output voltage Vo) can be brought close to. That is, the potential difference between the source of the third transistor 11 and the bulk (well region) can be made substantially equal to zero. As a result, the potential difference applied to the parasitic diode formed in the drain and bulk (well region) of the third transistor 11 is made extremely small, the leakage current of the parasitic diode that increases due to temperature rise is made extremely small, and is held in the capacitor 5. Therefore, the output voltage Vo can be reliably held, and the peak value detection accuracy of the peak hold circuit 100 can be improved.

Embodiment 2. FIG. (Peak hold circuit)
2-1. Configuration FIG. 6 is a circuit diagram showing a configuration of a peak hold circuit according to the second embodiment of the present invention. The peak hold circuit 200 is a circuit that detects and holds the peak value of the input signal (input voltage) Vin and outputs the peak value as the output voltage Vo. The peak hold circuit 200 is a circuit obtained by adding a configuration for resetting the charged charge to the peak hold circuit 100 of the first embodiment shown in FIG.

  As shown in FIG. 6, the peak hold circuit 200 includes an input terminal 1, an output terminal 2, an inverting input reset terminal 25, a non-inverting input reset terminal 32, a capacitor 5, a first amplifier 6, and a buffer circuit. 7, an inverting amplifier 8, and seven transistors 9, 10, 11, 26, 27, 28, 31. The transistors 9, 10, 11, 26, 27, 28, 31 may be field effect transistors (FETs). The field effect transistor may be an insulated gate transistor. For example, the transistors 9, 10, 11, 26, 27, and 28 may be p-type MOS-FETs, and the transistor 31 may be an n-type MOS-FET. In this embodiment, the input terminal 1, the output terminal 2, the capacitor 5, the first amplifier 6, the buffer circuit 7, the inverting amplifier 8, and the three transistors 9, 10, and 11 are the same as those in the first embodiment. The same component as the corresponding component of the peak hold circuit 100 may be used.

  The non-inverting input reset terminal 32 receives a voltage (first reset signal) RST that can take a binary value of high or low. A second reset signal RSTB having a value obtained by inverting the first reset signal RST is input to the inverting input reset terminal 25. The peak hold circuit 200 resets the charge accumulated in the capacitor 5 when the value of the first reset signal RST is high.

  The transistor 26 (fourth transistor) has a gate terminal connected to the inverting input reset terminal 25, a source terminal connected to the input terminal 1 and the non-inverting input terminal 6a of the first amplifier 6, and a bulk (well region). The voltage source 3 is connected to the drain terminal, and the drain terminal is connected to the source terminal of the transistor 27 (fifth transistor) and the drain terminal of the transistor 28 (sixth transistor).

  The transistor 31 (seventh transistor) has a non-inverting input reset terminal 32 connected to its gate terminal, a source terminal connected to the source terminal of the fourth transistor 26 and the input terminal 1, and a reference potential 4 connected to the bulk. The drain terminal of the fourth transistor 26 is connected to the drain terminal.

  The fourth transistor 26 and the seventh transistor 31 constitute a complementary switch. The complementary switch serves to reduce the on-resistance when resetting the electric charge charged in the capacitor 5 and widen the dischargeable voltage range.

  The fifth transistor 27 has its gate terminal connected to the inverting input reset terminal 25, its source terminal connected to the drain terminal of the fourth transistor 26 and the drain terminal of the sixth transistor 28, and the bulk (well region) connected to the second transistor. The drain terminal of one transistor 9 is connected, and one end of the capacitor 5 and the input terminal 7a of the buffer circuit 7 are connected to the drain terminal.

  The sixth transistor 28 has its gate terminal connected to the output terminal 6c of the first amplifier 6 and the gate terminal of the first transistor 9, the source terminal connected to the output terminal 2, and the drain terminal connected to the fourth transistor 26. Are connected to the drain terminal of the fifth transistor 27.

2-2. Operation The operation of the peak hold circuit 200 will be described with reference to FIG. FIG. 7A is a plot showing the time change of each voltage due to the operation of the peak hold circuit 200. FIG. 7B is a diagram illustrating temporal changes in the values of the first reset signal RST and the second reset signal RSTB.

  As shown in FIG. 7B, the first reset signal RST has a voltage value near the voltage of the voltage source 3 from time zero to time t1, and falls to a voltage value near the reference potential 0V at time t1. Shall. At this time, the second reset signal RSTB has a value obtained by inverting the value of the first reset signal RST as shown in FIG. 7B.

  Therefore, between time zero and time t1, the first reset signal RST having a high value is input to the gate terminal of the seventh transistor 31, and the gate terminals of the fourth transistor 26 and the fifth transistor 27 are also input. Receives a second reset signal RSTB having a low value.

  Therefore, the fourth transistor 26, the fifth transistor 27, and the seventh transistor 31 are turned on from time zero to time t1.

  As a result, the voltage at the node 29 connected to one end of the capacitor 5 is approximately the same as the input signal Vin.

  At this time, the voltage V12 at the node 12 connected to the output of the first amplifier 6 is a voltage in the vicinity of 0 V, as shown in FIG. Further, the voltage V13 at the node 13 connected to the output of the inverting amplifier 8 becomes a voltage near the voltage of the voltage source 3.

  Therefore, the first transistor 9 and the sixth transistor 28 are turned on. As a result, the voltage node 30 connected to the source terminal of the fifth transistor 27 and the voltage node 14 connected to the bulk (well region) have the same voltage as the input signal Vin.

  At time t1, the first reset signal RST falls to a voltage value near the reference potential 0V. Therefore, the fourth transistor 26, the fifth transistor 27, and the seventh transistor 31 are turned off at time t1.

  In this manner, in the peak hold circuit 200, the fourth transistor 26, the fifth transistor 27, and the seventh transistor 31 are turned on by the first reset signal RST and the second reset signal RSTB from time zero to time t1. The voltage node 29 connected to one end of the capacitor 5 can be set to a voltage comparable to the voltage of the input signal Vin. The timing for changing the values (potentials) of the first reset signal RST and the second reset signal RSTB (reset end timing, time t1 in FIG. 7) may be arbitrary, but the value of the input signal Vin becomes the highest. It is desirable that the timing does not match.

  From time t1 to time t2, which is the reset end timing, charge accumulation (charging) is performed on the capacitor 5. Hereinafter, accumulation (charging) of electric charge in the capacitor 5 will be described.

  The voltage V12 at the output node 12 of the first amplifier 6 rises from a voltage near 0 V at time t1, and then gradually approaches a voltage near 0 V, which is the reference potential, until time t2. Accordingly, the first transistor 9 and the sixth transistor 28 are gradually turned on from the off state.

  The voltage V13 at the output node 13 of the inverting amplifier 8 is a voltage obtained by inverting the voltage V12 at the output node 12 of the first amplifier 6. Therefore, the voltage V13 falls from the voltage of the voltage source 3 at time t1, and then gradually approaches the voltage near the voltage source 3 voltage until time t2. Thereby, the second transistor 10 and the third transistor 11 are gradually turned off from the on state.

  During the period from time t1 to time t2 and while the second transistor 10 and the third transistor 11 are on, the voltage of the source and bulk (well region) of the third transistor 11 (the voltage of the node 14) is The voltage becomes a voltage near the voltage of the voltage source 3, and the capacitor 5 accumulates charges (charges).

  As the time t2 approaches, the second transistor 10 and the third transistor 11 gradually approach the off state. Then, the first transistor 9 and the sixth transistor 28 gradually approach the on state.

  As the first transistor 9 gradually approaches the ON state, the voltage applied to the source and bulk (well region) of the third transistor 11 (the voltage at the node 14) gradually increases from the voltage near the voltage source 3 voltage to the output voltage Vo. The voltage at the node 14 becomes approximately the same as the output voltage Vo at time t2 when approaching a nearby voltage.

  Further, as the sixth transistor 28 gradually approaches the on state, the voltage at the source of the fifth transistor 27 (the voltage at the node 30) becomes the same level as the output voltage Vo as with the voltage change at the node 14. Become.

2-3. In this way, in the peak hold circuit 200, during the reset period, the fourth transistor 26, the fifth transistor 27, and the seventh transistor 31 are turned on using the first reset signal RST and the second reset signal RSTB, The voltage of the voltage node 29 connected to one end of the capacitor 5 is reset to a voltage comparable to the input signal Vin. As a result, the potential difference between the voltage of the voltage node 29 connected to one end of the capacitor 5 after the end of reset and the voltage of the input signal Vin can be reduced, and charging of the input signal Vin can be started immediately. .

  Further, after the reset is completed, charges corresponding to the peak value of the input signal Vin are accumulated (charged) in the capacitor 5. When the peak value of the input signal Vin is detected, the potential of the bulk (well region) of the third transistor 11 and the fifth transistor 27 connected to one end of the capacitor 5 is brought close to the output voltage Vo. By doing so, the voltage applied to the parasitic diode formed between the drain and the bulk (well) of each of the third transistor 11 and the fifth transistor 27 can be extremely reduced. The amount of electric charge held at 5 does not fluctuate, and the output voltage Vo is reliably held, thereby improving the peak value detection accuracy of the peak hold circuit.

Embodiment 3 FIG. (Peak hold circuit)
3-1. Configuration FIG. 8 is a circuit diagram showing a configuration of a peak hold circuit according to the third embodiment of the present invention. The peak hold circuit 300 according to the third embodiment shown in FIG. 8 is a circuit that detects and holds the peak value of the input signal (input voltage) Vin and outputs the peak value as the output voltage Vo. The peak hold circuit 300 changes the transistors (second and third transistors 10 and 11) for charging the capacitor 5 in the peak hold circuit 100 of the first embodiment shown in FIG. This is an improved circuit.

  As shown in FIG. 8, the peak hold circuit 300 includes an input terminal 1, an output terminal 2, a capacitor 5, a first amplifier 6, a buffer circuit 7, an inverting amplifier 8, and six transistors 9, 10, 11, 33, 34, and 35. The transistors 9, 10, 11, 33, 34, and 35 may be field effect transistors (FETs). The field effect transistor may be an insulated gate transistor. For example, the transistors 9, 10, 11, and 33 may be p-type MOS-FETs, and the transistors 34 and 35 may be n-type MOS-FETs. In this embodiment, the input terminal 1, the output terminal 2, the capacitor 5, the first amplifier 6, the buffer circuit 7, the inverting amplifier 8, and the three transistors 9, 10, and 11 are the same as those in the first embodiment. The same component as the corresponding component of the peak hold circuit 100 may be used.

  The transistor 33 (fourth transistor) has its gate terminal connected to the output terminal 6c of the first amplifier 6, its source terminal connected to the output terminal 2, and its drain terminal connected to the bulk (well) of the transistor 35 (sixth transistor). Region) and the drain terminal of the transistor 34 (fifth transistor) are connected, and the voltage source 3 is connected to the bulk (well region).

  The fifth transistor 34 has the gate terminal connected to the output terminal 6c of the first amplifier 6, the source and the bulk (well region) connected to the reference potential 4, the drain terminal connected to the drain terminal of the fourth transistor 33 and the second transistor 34. The bulk (well region) of the six transistors 35 is connected.

  The sixth transistor 35 has its gate terminal connected to the output terminal 6c of the first amplifier 6, its source terminal connected to the drain terminal of the first transistor 9, the drain terminal of the second transistor 10, the source terminal of the third transistor 11, and The bulk (well region) is connected, the drain terminal is connected to the drain terminal of the third transistor 11 and one end for charging the capacitor 5, and the bulk (well region) is connected to the drain terminal of the fourth transistor 33. The drain terminal of the fifth transistor 34 is connected.

  The output of the inverting amplifier 8 is input to the gate terminal of the third transistor 11, and the output of the first amplifier 6 is input to the gate terminal of the sixth transistor 35. Therefore, the input to the third transistor 11 and the input to the gate terminal of the sixth transistor 35 have opposite polarities. The source terminal of the third transistor 11 and the source terminal of the sixth transistor 35 are commonly connected. The source terminal of the third transistor 11 and the drain terminal of the sixth transistor 35 are also commonly connected.

3-2. Operation The third transistor 11 and the sixth transistor 35 serve as complementary switches that lower the on-resistance when the electric charge is accumulated (charged) in the capacitor 5. Therefore, in the peak hold circuit 300, the charge speed in the case where charges are accumulated (charged) in the capacitor 5 is improved in comparison with the peak hold circuit 100.

  When the voltage of the input signal Vin is lower than the output voltage Vo, the voltage of the bulk (well region) of the sixth transistor 35 becomes approximately the same as the reference potential 4 by turning on the fifth transistor 34.

  Therefore, similarly to the peak hold circuit 100 according to the first embodiment, the substrate bias effect of the sixth transistor 35 can be reduced, and the increase of the threshold voltage is suppressed, thereby reducing the operating voltage range of the input signal. The influence can be reduced.

  Further, when the voltage of the input signal Vin is higher than the output voltage Vo, the fourth transistor 33 is turned on, so that the voltage of the bulk (well region) of the sixth transistor 35 becomes approximately the same as the output voltage Vo. .

  Therefore, similar to the peak hold circuit 100 according to the first embodiment, the potential difference applied to the parasitic diode formed between the drain and the bulk (well region) of the sixth transistor 35 can be made extremely small. The leakage current flowing through the diode can be made extremely small.

3-3. Summary The peak hold circuit 300 according to the present embodiment has an effect equivalent to that of the peak hold circuit 100. Further, in comparison with the peak hold circuit 100, the charge speed in the case of accumulating (charging) the capacitor 5 is shown. Is improved.

Embodiment 4 FIG. (Peak hold circuit)
4-1. Configuration FIG. 9 is a circuit diagram showing a configuration of a peak hold circuit according to the fourth embodiment of the present invention. The peak hold circuit 400 according to the fourth embodiment shown in FIG. 9 is a circuit that detects and holds the peak value of the input signal (input voltage) Vin and outputs the peak value as the output voltage Vo. The peak hold circuit 400 is a circuit in which the capacitor 5 is changed to a circuit that can be charged with a constant current I1 with respect to the peak hold circuit 100 of the first embodiment shown in FIG. In the present embodiment, the operation speed can be changed by adjusting the magnitude of the constant current I1.

  As shown in FIG. 9, the peak hold circuit 400 includes an input terminal 1, an output terminal 2, a capacitor 5, a first amplifier 6, a buffer circuit 7, an inverting amplifier 8, a constant current source 40, 4 It comprises two transistors 36, 37, 38, 39. The transistors 36, 37, 38, 39 may be field effect transistors (FETs). The field effect transistor may be an insulated gate transistor. For example, the transistors 36, 37, 38, 39 may be p-type MOS-FETs. In the present embodiment, the input terminal 1, the output terminal 2, the capacitor 5, the first amplifier 6, the buffer circuit 7, and the inverting amplifier 8 are components corresponding to the peak hold circuit 100 according to the first embodiment. The same element can be used.

  The transistor 36 (first transistor) has its gate terminal connected to the output terminal 6c of the first amplifier 6, and its drain terminal connected to the drain terminal of the transistor 37 (second transistor) and the bulk of the transistor 38 (third transistor). Well region), the output terminal 2 is connected to the source terminal, and the voltage source 3 is connected to the bulk (well region).

  The second transistor 37 has its gate terminal connected to the output terminal 8b of the inverting amplifier 8 and the gate terminal of the third transistor, the voltage source 3 connected in common to the source terminal and the bulk (well region), and the drain terminal. The drain terminal of the first transistor 36 and the bulk (well region) of the third transistor 38 are connected to each other.

  The third transistor 38 has its gate terminal connected to the output terminal 8b of the inverting amplifier 8 and the gate terminal of the second transistor 37, and its source terminal connected to the constant current source 40 and the drain terminal of the transistor 39 (fourth transistor). Are connected to each other, one end of the capacitor 5 is connected to the drain terminal, and the drain terminal of the first transistor 36 and the drain terminal of the second transistor 37 are connected to the bulk (well region).

  The fourth transistor 39 has its gate terminal connected to the output terminal 6c of the first amplifier 6, its drain terminal connected to the constant current source 40 and the source terminal of the third transistor 38, and its output terminal 2 connected to the source terminal. The voltage source 3 is connected to the bulk (well region).

  The constant current source 40 has one end connected to the source terminal of the third transistor 38 and the fourth transistor drain terminal, and the other end connected to the voltage source 3.

4-2. When the operation output voltage Vo is lower than the voltage of the input signal Vin, the second transistor 37 and the third transistor 38 are turned on, and the first transistor 36 and the fourth transistor 39 are turned off. At this time, the current of the constant current source 40 flows through the node 15 connected to one end of the capacitor 5 and the capacitor 5 is charged.

  In the peak hold circuit 400 according to the fourth embodiment, the magnitude of the current I 1 that flows through the node 15 at one end of the capacitor 5 and contributes to the charging of the capacitor 5 is changed by changing the magnitude of the current of the constant current source 40. be able to. Therefore, by changing the magnitude of the current of the constant current source 40 in accordance with the frequency of the input signal Vin, the capacitor 5 can be charged at a charging speed without delay even with the input signal Vin that varies at a high frequency. . Further, overcharge of the capacitor 5 due to overcurrent can be suppressed, and the peak value detection accuracy of the peak hold circuit 400 can be improved.

  Further, when the output voltage Vo is lower than the voltage of the input signal Vin, the bulk (well region) of the third transistor 38 is close to the voltage source 3. Therefore, it is possible to reduce the substrate bias effect of the third transistor 38, and thus it is possible to suppress the increase in the threshold voltage and suppress the narrowing of the operating voltage range of the input signal Vin.

  Next, when the output voltage Vo is higher than the voltage of the input signal Vin, the second transistor 37 and the third transistor 38 are turned off, and the first transistor 36 and the fourth transistor 39 are turned on. . At this time, the voltage due to the electric charge accumulated in the capacitor 5 is held, and the output voltage Vo is output to the output terminal 2 via the buffer circuit 7.

  The voltage of the voltage node 42 in the bulk (well region) of the third transistor 38 is approximately the same as the output voltage Vo. Therefore, the potential difference applied to the parasitic diode formed between the drain terminal of the third transistor 38 and the bulk (well region) is extremely small, and the leakage current flowing through the parasitic diode can be extremely small.

4-3. Summary The peak hold circuit 400 according to the present embodiment has the same effect as the peak hold circuit 100. Further, the charge rate when the capacitor 5 is charged (charged) is set to, for example, the frequency of the input signal Vin. It is easy to adjust to a speed suitable for. The constant current source 40 may be capable of controlling the magnitude of the constant current based on the characteristics (for example, frequency) of the input signal Vin.

Embodiment 5 FIG. (Peak hold circuit)
5-1. Configuration FIG. 10 is a circuit diagram showing a configuration of a peak hold circuit according to the fifth embodiment of the present invention. The peak hold circuit 500 according to the fourth embodiment shown in FIG. 10 is a circuit that detects and holds the peak value of the input signal (input voltage) Vin and outputs the peak value as the output voltage Vo. The peak hold circuit 500 eliminates the inverting amplifier 8 in the circuit 100 by changing the first amplifier 6 in the peak hold circuit 100 of the first embodiment shown in FIG. I am trying.

  As shown in FIG. 10, the peak hold circuit 500 includes an input terminal 1, an output terminal 2, a capacitor 5, a differential amplifier 43, a buffer circuit 7, and three transistors 44, 45, and 46. Composed. The transistors 44, 45, 46 may be field effect transistors (FETs). The field effect transistor may be an insulated gate transistor. For example, the transistors 44, 45, and 46 may be p-type MOS-FETs. In the present embodiment, the input terminal 1, the output terminal 2, the capacitor 5, and the buffer circuit 7 may be the same elements as the corresponding components of the peak hold circuit 100 according to the first embodiment.

  In the differential amplifier 43, the input terminal 1 is connected to the non-inverting input terminal 43a, and one end for charging the capacitor 5 and the input terminal 7a of the buffer circuit 7 are connected to the inverting input terminal 43b. The gate terminal of the transistor 45 (second transistor) and the gate terminal of the transistor 46 (third transistor) are connected to 43c, and the gate terminal of the transistor 44 (first transistor) is connected to the non-inverting output terminal 43d.

  The first transistor 44 has a gate terminal connected to the non-inverting output terminal 43d of the differential amplifier 43, a source terminal connected to the output terminal 2, and a drain terminal connected to the drain terminal of the second transistor 45 and the third transistor 46. Are connected to the source terminal and the bulk (well region), and the voltage source 3 is connected to the bulk (well region).

  The second transistor 45 has a gate terminal connected to the inverting output terminal 43c of the differential amplifier 43 and the gate terminal of the third transistor 46, a voltage source 3 connected to the source terminal and the bulk (well region), and a drain. The drain terminal of the first transistor 44 and the source terminal and bulk (well region) of the third transistor 46 are connected to the terminal.

  The third transistor 46 has a gate terminal connected to the inverting output terminal 43c of the differential amplifier 43 and the gate terminal of the second transistor 45, and a source terminal and a bulk (well region) connected to the drain terminal of the first transistor 44. And the drain terminal of the second transistor 45 are connected to one end of the capacitor 5 and the inverting input terminal 43b of the differential amplifier 43 are connected to the drain terminal.

5-2. Operation The operation of the peak hold circuit according to the fifth embodiment of the present invention shown in FIG. 10 is the same as the operation of the peak hold circuit 100 of the first embodiment shown with reference to FIG. The time change of the voltage of the output node 48 of the non-inverting output terminal 43d of the differential amplifier 43 is the time change of the voltage V12 of the output node 12 of the output terminal 6c of the first amplifier 6 of the peak hold circuit 100 of the first embodiment. Equivalent to. Further, the time change of the voltage of the output node 47 of the inverting output terminal 43c of the differential amplifier 43 is the time change of the voltage V13 of the output node 13 of the output terminal 8b of the inverting amplifier 8 of the peak hold circuit 100 of the first embodiment. Equivalent to.

5-3. Conclusion The peak hold circuit 500 according to the present embodiment can reduce the substrate bias effect of the third transistor 46, similarly to the peak hold circuit 100 according to the first embodiment. As a result, an increase in the threshold voltage of the third transistor 46 can be suppressed, and thus the narrowing of the operating voltage range of the input signal Vin can be suppressed. In addition, after holding the peak value of the input signal Vin, the potential difference applied to the parasitic diode formed between the drain terminal of the third transistor 46 and the bulk (well region) can be made extremely small. Therefore, in the peak hold circuit 500, the leakage current flowing through the parasitic diode can be made extremely small, the fluctuation of the charge held in the capacitor 5 is prevented, and the output voltage Vo is reliably held, so that the peak hold circuit 500 Peak value detection accuracy can be improved. Furthermore, by changing the first amplifier 6 in the peak hold circuit 100 of the first embodiment to the differential amplifier 43, components corresponding to the inverting amplifier 8 of the circuit 100 can be eliminated. The current consumption can be reduced in comparison with the circuit 100.

Embodiment 6 FIG. (Bottom hold circuit)
6-1. Configuration FIG. 11 is a circuit diagram showing a configuration of a bottom hold circuit according to a sixth embodiment of the present invention. The bottom hold circuit 600 according to the sixth embodiment shown in FIG. 11 is a circuit that detects and holds the bottom value of the input signal (input voltage) Vin and outputs the bottom value as the output voltage Vo.

  As shown in FIG. 11, the bottom hold circuit 600 is realized by a circuit configuration similar to that of the peak hold circuit 100 of the first embodiment. The bottom hold circuit 600 is changed to have a polarity opposite to that of the peak hold circuit 100 in order to enable detection of the bottom value.

  The bottom hold circuit 600 includes an input terminal 1, an output terminal 2, a capacitor 5, a first amplifier 6, a buffer circuit 7, an inverting amplifier 8, and three transistors 49, 50, and 51. Configured. The transistors 49, 50, 51 may be field effect transistors (FETs). The field effect transistor may be an insulated gate transistor. For example, the transistors 49, 50, 51 may be n-type MOS-FETs. In the present embodiment, the input terminal 1, the output terminal 2, the capacitor 5, the first amplifier 6, the buffer circuit 7, and the inverting amplifier 8 are components corresponding to the peak hold circuit 100 according to the first embodiment. The same element can be used.

  The transistor 49 (first transistor) has the gate terminal connected to the output terminal 6c of the first amplifier 6, the drain terminal connected to the output terminal 2, the source terminal connected to the drain terminal of the transistor 51 (third transistor) and The bulk (well region) is connected, and the reference potential 4 is connected to the bulk (well region).

  The transistor 50 (second transistor) has a gate terminal connected to the output terminal 8b of the inverting amplifier 8 and the gate terminal of the third transistor 51, a reference potential 4 connected to the source terminal and the bulk (well region), The source terminal of the first transistor 49, the source terminal of the third transistor 51, and the bulk (well region) are connected to the drain terminal.

  The third transistor 51 has a gate terminal connected to the output terminal 8b of the inverting amplifier 8 and a gate terminal of the second transistor 50, and a source terminal and a bulk (well region) connected to the source terminal of the first transistor 49 and the second transistor 50. The drain terminal of the two transistors 50 is connected, and one end for charging the capacitor 5 and the input terminal 7 a of the buffer circuit 7 are connected to the drain terminal.

6-2. Operation The operation of the bottom hold circuit 600 will be described with reference to FIG. FIG. 12 is a plot showing the time change of each voltage due to the operation of the bottom hold circuit 600.

  The operation of the bottom hold circuit 600 will be described by taking as an example the case where the input voltage Vin changes as shown in FIG. That is, the input voltage Vin in this example decreases monotonously from time zero to time t1, shows a bottom value at time t1, and increases monotonously after time t1. At time zero, the capacitor 5 is charged with a voltage not less than the maximum voltage of the input signal by a power source (not shown).

  While the output voltage Vo is higher than the voltage of the input signal Vin, that is, while approaching time t1 from time zero, the voltage V12 of the output node 12 of the first amplifier 6 (voltage applied to the gate of the first transistor 49) gradually increases. The first transistor 49 is gradually turned on.

  Here, the voltage V13 of the output node 13 of the inverting amplifier 8 is a voltage obtained by inverting the voltage V12 of the output node 12 of the first amplifier 6, and from the time zero to the time t1, the gate of the second transistor 50 and the third The voltage applied to each gate of the transistor 51 gradually decreases, and the second transistor 50 and the third transistor 51 are gradually turned off from the on state.

  When the second transistor 50 and the third transistor 51 are on in the period from time zero to time t1, the voltage of the source and bulk (well region) of the third transistor 51 (the voltage V52 of the node 52) is 0V. As a result, the voltage of the capacitor 5 is discharged.

  When the time approaches time t1, the second transistor 50 and the third transistor 51 gradually approach the off state, and conversely, the first transistor 49 gradually approaches the on state. As the first transistor 49 gradually approaches the ON state, the voltage of the source and bulk (well region) of the third transistor 51 (the voltage V52 of the node 52) gradually increases from the voltage in the vicinity of the reference potential 4 which is 0V. At time t1, the voltage V52 becomes the same level as the output voltage Vo.

  As described above, while the output voltage Vo is higher than the voltage of the input signal Vin, the second transistor 50 is turned on and the first transistor 49 is turned off, whereby the source and bulk (well region) of the third transistor 51 are turned on. Can be set to a voltage in the vicinity of the voltage of the reference potential 4 which is 0V. Thereby, while the electric charge of the capacitor 5 is discharged according to the input signal Vin, the increase in the threshold voltage of the third transistor 51 is suppressed.

  Thus, by operating the first to third transistors 49, 50, 51, the substrate bias effect of the third transistor 51 can be reduced. Therefore, an increase in the threshold voltage of the third transistor 51 is well suppressed. Therefore, the bottom hold circuit 600 can reduce the influence of the input signal Vin on the operating voltage range.

  In addition, while the output voltage Vo is lower than the voltage of the input signal Vin, that is, after time t1, the second transistor 50 is turned off and the first transistor 49 is turned on, whereby the source of the third transistor 51 and The potential of the bulk (well region) can be a voltage near the output voltage Vo. Thereby, the potential difference applied to the parasitic diode formed in the drain and bulk (well region) of the third transistor 51 can be extremely reduced, and the leakage current flowing through the parasitic diode can be reduced.

  In general, when a reverse bias voltage is applied to the parasitic diode formed in the drain and bulk (well region) of the third transistor 51, a leakage current flows. The leakage current increases with an exponential function as the temperature rises, and the amount of charge held in the capacitor 5 varies significantly.

  However, in the bottom hold circuit 600, the leakage current flowing through the parasitic diode can be made extremely small, so that the amount of charge held in the capacitor 5 can be prevented from fluctuating. The output voltage Vo can be reliably held, and the bottom value detection accuracy of the bottom hold circuit 600 can be improved.

6-3. Conclusion In the bottom hold circuit 600, when the output voltage Vo is higher than the voltage of the input signal Vin, the source and bulk (well region) of the third transistor 51 are brought close to the voltage of the reference potential 4 which is 0V, thereby the third transistor The substrate bias effect of 51 is reduced. Thereby, the operating voltage range of the input signal Vin can be kept wide.

  In the bottom hold circuit 600, when the output voltage Vo is lower than the voltage of the input signal Vin, the first transistor 49 is turned on, so that the source and bulk (well region) voltages of the third transistor 51 are bottom-held. The voltage of the output terminal 2 of the circuit 600 (output voltage Vo) can be approached. As a result, the potential difference applied to the parasitic diode formed in the drain and bulk (well region) of the third transistor 51 is made extremely small, the leakage current of the parasitic diode that increases due to temperature rise is made extremely small, and is held in the capacitor 5. Therefore, the output voltage Vo can be reliably held, and the bottom value detection accuracy of the bottom hold circuit 600 can be improved.

  Although the bottom hold circuit 600 of the present embodiment is configured by reversing the polarity of the peak hold circuit 100 of the first embodiment, similarly, the peak hold circuit 200 of the second to fifth embodiments, A person skilled in the art can easily configure a bottom hold circuit having a configuration corresponding to the configuration of any of the peak hold circuits 200, 300, 400, and 500 by reversing the polarities of 300, 400, and 500. .

  The present invention is useful as a hold circuit such as a peak hold circuit or a bottom hold circuit.

1: input terminal 2: output terminal 3: voltage source 4: reference potential 5: capacitor 6: first amplifier 7: buffer circuit 8: inverting amplifier 9: first transistor 10: second transistor 11: third transistor 16: first 2 amplifier 17: reference voltage source 18: resistor 19: resistor 20: third amplifier 21: p-type transistor 22: parasitic diode 23: parasitic diode 24: parasitic diode 25: inverting input reset terminal 26: fourth transistor 27: fifth Transistor 28: Sixth transistor 31: Seventh transistor 32: Non-inverting input reset terminal 33: Fourth transistor 34: Fifth transistor 35: Sixth transistor 36: First transistor 37: Second transistor 38: Third transistor 39: Fourth transistor 40: constant current source 43: differential amplification 44: The first transistor 45: second transistor 46: third transistor 49: first transistor 50: second transistor 51: third transistor 100: peak hold circuit (Embodiment 1)
200: Peak hold circuit (Embodiment 2)
300: Peak hold circuit (Embodiment 3)
400: Peak hold circuit (Embodiment 4)
500: Peak hold circuit (Embodiment 5)
600: Bottom hold circuit (Embodiment 6)
RST: first reset signal RSTB: second reset signal V3: voltage V12 of voltage source 3: voltage V13 of node 12: voltage V14 of node 13: voltage V52 of node 14: voltage Vin of node 52: input signal (input voltage) )
Vo: Output voltage

Claims (14)

An input terminal to which an input signal is input;
An amplifier having an input terminal to which the input signal is input to a non-inverting input terminal; and
An inverting amplifier having an input terminal connected to the output terminal of the amplifier;
A capacitor having one end connected to the inverting input terminal of the amplifier and the other end connected to a reference potential;
A buffer circuit in which the one end of the capacitor is connected to an input terminal;
An output voltage output terminal connected to the output terminal of the buffer circuit;
A first transistor having a gate terminal connected to the output terminal of the amplifier, a source terminal connected to the output terminal of the buffer circuit, and a voltage source connected to the bulk;
A second transistor having a gate terminal connected to the output terminal of the inverting amplifier, a source terminal connected to the bulk voltage source, and a drain terminal connected to the drain terminal of the first transistor;
The output terminal of the inverting amplifier is connected to the gate terminal, the drain terminal of the first transistor and the drain terminal of the second transistor are connected to the source terminal and the bulk, and the one end of the capacitor and the drain terminal are connected to the drain terminal. A third transistor connected to the input terminal of the buffer circuit;
A hold circuit. The first transistor, the second transistor, and the third transistor are all p-type MOS-FETs,
Holding a voltage equal to the peak value of the input signal, and outputting a voltage equal to the peak value as an output voltage from the output terminal of the buffer circuit;
The hold circuit according to claim 1. When the output voltage is lower than the voltage of the input signal, the first transistor is turned off and the second transistor is turned on;
The hold circuit according to claim 2. When the output voltage is higher than the voltage of the input signal, the first transistor is turned on and the second transistor is turned off;
The hold circuit according to claim 2. further,
A non-inverting reset terminal to which a reset signal is input;
An inverted reset terminal to which an inverted reset signal, which is a signal whose value is inverted with respect to the reset signal, is input;
A fourth transistor having a gate terminal connected to the inverting reset terminal, a source terminal connected to an input terminal to which the input signal is input and a non-inverting input terminal of the amplifier, and a voltage transistor connected to the bulk; ,
The inverted reset terminal is connected to the gate terminal, the drain terminal of the fourth transistor is connected to the source terminal, the drain terminal of the first transistor is connected to the bulk, the one end of the capacitor and the buffer are connected to the drain terminal A fifth transistor connected to the input terminal of the circuit;
The output terminal of the amplifier and the gate terminal of the first transistor are connected to the gate terminal, the output terminal of the buffer circuit and the source terminal of the first transistor are connected to the source terminal, and the drain terminal A sixth transistor in which a drain terminal of the fourth transistor and a source terminal of the fifth transistor are connected, and the voltage source is connected in bulk;
The non-inverting reset terminal is connected to the gate terminal, the source terminal of the fourth transistor and the input terminal to which the input signal is input are connected to the source terminal, and the drain terminal of the fourth transistor is connected to the drain terminal. A seventh transistor in which a source terminal of the fifth transistor and a drain terminal of the sixth transistor are connected, and the reference potential is connected in bulk;
The hold circuit according to claim 2. The fourth transistor, the fifth transistor, and the sixth transistor are all p-type MOS-FETs,
The seventh transistor is an n-type MOS-FET.
The hold circuit according to claim 5. further,
A fourth transistor having a gate terminal connected to the output terminal of the amplifier, a source terminal connected to the output terminal of the buffer circuit and the source terminal of the first transistor, and the voltage source connected in bulk;
A fifth transistor in which the output terminal of the amplifier is connected to the gate terminal, the reference potential is connected to the source terminal and the bulk, and the drain terminal of the fourth transistor is connected to the drain terminal;
The output terminal of the amplifier is connected to the gate terminal, the drain terminal of the first transistor, the drain terminal of the second transistor, the source terminal of the third transistor, and the bulk are connected to the source terminal, A drain terminal of the third transistor, the one end of the capacitor, and an input terminal of the buffer circuit are connected, and a drain terminal of the fourth transistor and a drain terminal of the fifth transistor are connected in bulk. A transistor,
The hold circuit according to claim 2. The fourth transistor is a p-type MOS-FET,
The fifth transistor and the sixth transistor are all n-type MOS-FETs.
The hold circuit according to claim 7. An input terminal to which an input signal is input;
An amplifier having an input terminal to which the input signal is input to a non-inverting input terminal; and
An inverting amplifier having an input terminal connected to the output terminal of the amplifier;
A capacitor having one end connected to the inverting input terminal of the amplifier and the other end connected to a reference potential;
A buffer circuit in which the one end of the capacitor is connected to an input terminal;
An output voltage output terminal connected to the output terminal of the buffer circuit;
A first transistor having a gate terminal connected to the output terminal of the amplifier, a source terminal connected to the output terminal of the buffer circuit, and a voltage source connected to the bulk;
A second transistor having a gate terminal connected to the output terminal of the inverting amplifier, a source terminal connected to the bulk voltage source, and a drain terminal connected to the drain terminal of the first transistor;
The output terminal of the inverting amplifier is connected to the gate terminal, the constant current source is connected to the source terminal, the one end of the capacitor and the input terminal of the buffer circuit are connected to the drain terminal, A third transistor in which a drain terminal of one transistor and a drain terminal of the second transistor are connected;
The output terminal of the amplifier is connected to the gate terminal, the output terminal of the buffer circuit is connected to the source terminal, the constant current source and the source terminal of the third transistor are connected to the drain terminal, and the voltage is connected in bulk. A fourth transistor with a source connected;
A hold circuit. The first transistor, the second transistor, the third transistor, and the fourth transistor are all p-type MOS-FETs,
Holding a voltage equal to the peak value of the input signal, and outputting a voltage equal to the peak value as an output voltage from the output terminal of the buffer circuit;
The hold circuit according to claim 9. An input terminal to which an input signal is input;
A capacitor having one end connected to the inverting input terminal of the amplifier and the other end connected to a reference potential;
A differential amplifier in which an input terminal to which the input signal is input is connected to a non-inverting input terminal, and the one end of the capacitor is connected to an inverting input terminal;
A buffer circuit in which the one end of the capacitor is connected to an input terminal;
An output voltage output terminal connected to the output terminal of the buffer circuit;
A first transistor having a gate terminal connected to the non-inverting output terminal of the differential amplifier, a source terminal connected to the output terminal of the buffer circuit, and a voltage source connected to the bulk;
A second transistor having a gate terminal connected to the inverting output terminal of the differential amplifier, a source terminal connected to the voltage source in bulk, and a drain terminal connected to the drain terminal of the first transistor;
The gate terminal is connected to the inverting output terminal of the differential amplifier, the source terminal and the bulk are connected to the drain terminal of the first transistor and the drain terminal of the second transistor, and the drain terminal is connected to the one end of the capacitor. A third transistor connected to the input terminal of the buffer circuit;
A hold circuit. The first transistor, the second transistor, and the third transistor are all p-type MOS-FETs,
Holding a voltage equal to the peak value of the input signal, and outputting a voltage equal to the peak value as an output voltage from the output terminal of the buffer circuit;
The hold circuit according to claim 11. An input terminal to which an input signal is input;
An amplifier having an input terminal to which the input signal is input to a non-inverting input terminal; and
An inverting amplifier having an input terminal connected to the output terminal of the amplifier;
A capacitor having one end connected to the inverting input terminal of the amplifier and the other end connected to a reference potential;
A buffer circuit in which the one end of the capacitor is connected to an input terminal;
An output voltage output terminal connected to the output terminal of the buffer circuit;
A first transistor having a gate terminal connected to the output terminal of the amplifier, a source terminal connected to the output terminal of the buffer circuit, and a reference potential connected in bulk;
A second transistor having a gate terminal connected to the output terminal of the inverting amplifier, a source terminal connected to the reference potential in bulk, and a drain terminal connected to the drain terminal of the first transistor;
The output terminal of the inverting amplifier is connected to the gate terminal, the drain terminal of the first transistor and the drain terminal of the second transistor are connected to the source terminal and the bulk, and the one end of the capacitor and the buffer are connected to the drain terminal. A third transistor connected to the input terminal of the circuit;
A hold circuit. The first transistor, the second transistor, and the third transistor are all n-type MOS-FETs,
Holding a voltage equal to the bottom value of the input signal, and outputting a voltage equal to the bottom value as an output voltage from the output terminal of the buffer circuit;
The hold circuit according to claim 13.

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