JP5595644B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having fine wiring and a manufacturing method thereof.

  In recent years, with the miniaturization and high integration of semiconductor devices, a multilayer wiring structure is required. For the wiring, a Cu (copper) wiring having a low resistance and high electromigration resistance is used. However, Cu has a property that it is difficult to process by etching. For this reason, the damascene method is used as a formation method of Cu wiring.

Further, Cu has a property that it is easily oxidized. For this reason, an oxide film is easily formed on the surface of the Cu wiring. This oxide film may cause a decrease in wiring reliability, such as an increase in resistance of the Cu wiring. Such a technique for suppressing the oxidation of the surface of the Cu wiring is disclosed in Patent Documents 1 to 3. For example, in Patent Document 1 and Patent Document 2, it is possible to prevent the surface of the Cu wiring from being oxidized by covering the surface of the Cu wiring with a nitride film or forming a Cu silicide layer on the surface of the Cu wiring. Technology is disclosed. For example, in Patent Document 3, Si (silicon) is introduced into a Cu film before the polishing step in the damascene method, Si is diffused into the Cu film together with Cu grain growth by annealing treatment, and the entire Cu wiring is CuSi. The technique which suppresses that the surface of Cu wiring is oxidized by using an alloy is disclosed.
JP 2000-150517 A Japanese Patent Laid-Open No. 11-204523 JP 2004-342977 A

  However, in the method of covering the surface of the Cu wiring with the nitride film, a void may be generated in the Cu wiring near the boundary with the nitride film. Here, an example of a manufacturing method in the case where the surface of the Cu wiring is covered with a nitride film and voids generated in the Cu wiring will be described with reference to FIGS. First, as shown in FIG. 1A, a first oxide film 52a is formed on a semiconductor substrate 50 on which a semiconductor element (not shown) or the like is formed, and the first oxide film is etched using a photolithography technique and an etching technique. A first groove 54a is formed in 52a.

  In FIG. 1B, a barrier layer 56 for preventing diffusion of Cu and a Cu seed layer 58 for facilitating plating growth are sequentially formed. Thereafter, a Cu film 60 is formed by electrolytic plating.

  In FIG. 1C, the CMP film (chemical mechanical polishing) method is used to remove and planarize the Cu film 60 and the like on the first oxide film 52a, and the first wiring layer 62a made of Cu is formed in the first groove portion 54a. Form. Thereafter, plasma processing is performed on the surface of the first wiring layer 62a to remove an oxide film (not shown) and the like formed on the surface of the first wiring layer 62a. Next, a first nitride film 64a is formed on the first wiring layer 62a and the first oxide film 52a.

  Next, in FIG. 2A, a second oxide film 52b is formed on the first nitride film 64a, and vias are formed in the second oxide film 52b and the first nitride film 64a using a photolithographic technique and an etching technique. Hole 68 is formed.

  In FIG. 2B, a barrier layer 56 and a Cu seed layer 58 are sequentially formed, and then a Cu film (not shown) is formed. Then, the Cu film and the like on the second oxide film 52 b are removed and planarized, and a via 66 made of Cu is formed in the via hole 68. Plasma treatment is performed on the surface of the via 66 to remove an oxide film (not shown) and the like formed on the surface of the via 66. Next, a second nitride film 64b is formed on the via 66 and the second oxide film 52b.

  In FIG. 2C, a third oxide film 52c is formed on the second nitride film 64b, and a second groove portion 54b is formed in the third oxide film 52c and the second nitride film 64b so as to reach the via 66. To do. Thereafter, after sequentially forming the barrier layer 56 and the Cu seed layer 58, a Cu film (not shown) is formed. Then, the Cu film and the like on the third oxide film 52c are removed and planarized, and a second wiring layer 62b made of Cu is formed in the second groove portion 54b. Plasma treatment is performed on the surface of the second wiring layer 62b, and an oxide film (not shown) formed on the surface of the second wiring layer 62b is removed. Next, a third nitride film 64c is formed on the second wiring layer 62b and the third oxide film 52c. Thereby, a multilayer wiring structure using Cu wiring is formed.

  When such a manufacturing method is used, as shown in FIG. 2C, a void 70 may occur in the first wiring layer 62a in the vicinity of the boundary with the first nitride film 64a. The void 70 is considered to be generated by electromigration of Cu atoms in the first wiring layer 62a to the first nitride film 64a. When the void 70 is formed in the first wiring layer 62a, there arises a problem that the resistance of the first wiring layer 62a increases.

  Further, according to the method of forming a Cu silicide layer on the surface of the Cu wiring in Patent Document 1, a Cu silicide layer having a thickness of about 5 to 50 nm is formed on the surface of the Cu wiring. When the Cu wiring becomes fine, an increase in resistance of the Cu wiring due to a Cu silicide layer having a thickness of about 5 to 50 nm may be a problem. Moreover, according to the method of using CuSi alloy for the entire Cu wiring of Patent Document 3, there is a problem that the resistance of the Cu wiring increases.

  The present invention has been made in view of the above problems, and provides a semiconductor device capable of suppressing electromigration of a wiring material from a wiring layer and suppressing an increase in wiring resistance, and a method for manufacturing the same. The purpose is to do.

  The present invention includes a step of forming a groove in an insulating film formed on a semiconductor substrate, a step of forming a metal film on the insulating film so as to be embedded in the groove, and a step formed on the insulating film. Flattening the metal film, forming a wiring layer made of the metal film in the groove, and performing plasma treatment on the surface of the wiring layer in order to remove the oxide film formed on the surface of the wiring layer And a step of performing a heat treatment in a gas atmosphere containing a silane-based gas without exposing the semiconductor substrate to the atmosphere after the step of performing the plasma treatment. It is a manufacturing method. According to the present invention, since the silicide layer is formed on the surface of the wiring layer, electromigration of the wiring material in the wiring layer can be suppressed. Thereby, generation | occurrence | production of a void in a wiring layer can be suppressed and the increase in resistance of a wiring layer can be suppressed. Further, since the silicide layer is formed on the surface of the wiring layer without interposing an oxide film, the increase in resistance of the wiring layer can also be suppressed by this.

  In the above-described configuration, the step of performing the plasma treatment includes exposing the semiconductor substrate to any one of an ammonia gas atmosphere, a hydrogen gas atmosphere, and a hydrazine gas atmosphere to perform the plasma treatment on the surface of the wiring layer. It can be set as the structure which is a process to perform. According to this configuration, the oxide film on the surface of the wiring layer can be removed.

  In the above structure, the step of performing the heat treatment may be a step of performing a heat treatment on the semiconductor substrate in a gas atmosphere containing monosilane gas or disilane gas.

  In the above configuration, the step of performing the plasma treatment is a step of exposing the semiconductor substrate to an ammonia gas atmosphere and performing a plasma treatment on the surface of the wiring layer, and the step of performing the heat treatment is performed in the ammonia gas atmosphere. The monosilane gas is introduced into the semiconductor substrate, and the semiconductor substrate is heat-treated in a mixed gas atmosphere of the ammonia gas and the monosilane gas. According to this configuration, it is possible to improve manufacturing efficiency.

  In the above structure, the step of performing the heat treatment may be a step of performing the heat treatment for 0.5 second to 2 seconds on the semiconductor substrate. According to this configuration, an increase in resistance of the wiring layer can be minimized.

  In the above structure, in order to improve the crystallinity of the metal film, there is a step of annealing the metal film, and the step of annealing the metal film is performed before the step of performing the heat treatment. be able to. According to this configuration, an increase in resistance of the wiring layer can be suppressed.

  In the above configuration, the step of performing the heat treatment may be a step of performing the heat treatment in a state where the surface of the wiring layer is activated. Moreover, the said structure WHEREIN: The said wiring layer can be set as the structure which is a copper wiring.

  The present invention comprises an insulating film having a groove provided on a semiconductor substrate, a wiring layer provided so as to be embedded in the groove, and a silicide layer formed on a surface of the wiring layer, The semiconductor device is characterized in that no oxide film is interposed between the wiring layer and the silicide layer. According to the present invention, since the silicide layer is formed on the surface of the wiring layer, the electromigration of the wiring material in the wiring layer can be suppressed. Thereby, generation | occurrence | production of a void in a wiring layer can be suppressed and the increase in resistance of a wiring layer can be suppressed. Further, since the silicide layer is formed on the surface of the wiring layer without interposing an oxide film, this can also suppress an increase in resistance of the wiring layer.

  The said structure WHEREIN: The said wiring layer can be set as the structure which is a copper wiring.

  According to the present invention, since the silicide layer is formed on the surface of the wiring layer, electromigration of the wiring material in the wiring layer can be suppressed. Thereby, generation | occurrence | production of a void in a wiring layer can be suppressed and the increase in resistance of a wiring layer can be suppressed. Further, since the silicide layer is formed on the surface of the wiring layer without interposing an oxide film, the increase in resistance of the wiring layer can also be suppressed by this.

  Embodiments according to the present invention will be described below with reference to the drawings.

  A method for manufacturing a semiconductor device according to the first embodiment will be described with reference to FIGS. The first embodiment will be described by taking a nonvolatile semiconductor device having a SONOS type structure as an example. In FIG. 3A, an ONO film 14 made of an oxide film, a nitride film, and an oxide film is formed on a semiconductor substrate 10 which is a P-type Si (silicon) substrate, for example. For example, As (arsenic) is ion-implanted into the semiconductor substrate 10 using a mask layer (not shown) formed on the ONO film 14 as a mask. Thereby, the bit line 12 which is an N-type diffusion region is formed so as to extend in the semiconductor substrate 10.

  In FIG. 3B, a word line (not shown) extending in the direction intersecting the extending direction of the bit line 12 is formed on the ONO film 14. For example, a BPSG (Boron-doped Phospho Silicate Glass) film 16 is formed on the ONO film 14 so as to cover the word lines. A cap layer 18 made of, for example, a nitride film is formed on the BPSG film 16.

  In FIG. 3C, a mask layer 20 made of, for example, a resist is formed on the cap layer 18 and patterned.

  4A, using the mask layer 20 as a mask, the cap layer 18, the BPSG film 16 and the ONO film 14 are etched using, for example, RIE (reactive ion etching). As a result, a contact hole 22 that penetrates the cap layer 18, the BPSG film 16, and the ONO film 14 and exposes the surface of the bit line 12 is formed.

  In FIG. 4B, a Ta (tantalum) film is deposited along the inner surface of the contact hole 22 by using, for example, a CVD method. Next, a W (tungsten) film is deposited using, for example, a CVD method so as to be embedded in the contact hole 22. Thereafter, the Ta film and the W film formed on the cap layer 18 are removed and planarized by using, for example, a CMP (Chemical Mechanical Polishing) method. Thus, a barrier layer 24 made of a Ta film is formed along the inner surface of the contact hole 22, and a contact plug 26 made of a W film is formed on the surface of the barrier layer 24 so as to be embedded in the contact hole 22. Is done. Here, the barrier layer 24 is formed to prevent W atoms from diffusing into the BPSG film 16. The contact plug 26 is used to electrically connect the bit line 12 and a Cu wiring described later.

  In FIG. 4C, a nitride film 28 is formed on the contact plug 26 and the cap layer 18 by using, for example, a CVD method. A first insulating film 30 made of an oxide film is formed on the nitride film 28 by using, for example, a CVD method. Using the mask layer (not shown) formed on the first insulating film 30 as a mask, the first insulating film 30 and the nitride film 28 are etched using, for example, the RIE method. As a result, a groove 32 is formed in the first insulating film 30 and the nitride film 28. Further, the surface of the contact plug 26 is exposed on the bottom surface of the groove portion 32.

  In FIG. 5A, a Ta film is deposited along the inner surface of the groove 32 by using, for example, a CVD method. Thereby, a barrier layer 34 made of a Ta film is formed along the inner surface of the groove 32. Next, a Cu film is deposited along the surface of the barrier layer 34 using, for example, a CVD method. Thereby, the Cu seed layer 36 is formed along the surface of the barrier layer 34. Thereafter, a Cu film 38 is formed on the first insulating film 30 so as to be embedded in the groove 32 using, for example, an electrolytic plating method. Here, the barrier layer 34 is formed in order to prevent Cu atoms from diffusing into the first insulating film 30. The Cu seed layer 36 is formed to facilitate Cu plating growth.

In FIG. 5B, in order to improve the crystallinity of the Cu film 38, for example, after annealing the Cu film 38 in an N ₂ (nitrogen) gas atmosphere, the first insulating film is formed using, for example, a CMP method. The Cu film 38 and the like on 30 are removed and flattened, and a Cu wiring 40 made of Cu is formed in the groove 32. Here, after forming the Cu wiring 40 using the CMP method, the surface of the Cu wiring 40 is exposed to the atmosphere. For this reason, an oxide film 42 is formed on the surface of the Cu wiring 40.

Next, the manufacturing steps from STEP 1 to STEP 4 shown in Table 1 are sequentially performed. Here, STEP 1 to STEP 4 shown in Table 1 are executed continuously in the same chamber without exposing the semiconductor substrate 10 to the atmosphere.

In Table 1 and FIG. 5C, first, the semiconductor substrate 10 is set in a chamber. Thereafter, for example, NH ₃ (ammonia) gas and N ₂ (nitrogen) gas are introduced into the chamber and heated until the temperature of the semiconductor substrate 10 reaches 400 ° C. (STEP 1 in Table 1). Thereafter, the RF power is turned on (STEP 2 in Table 1). Thereby, plasma processing is performed on the surface of the Cu wiring 40. By this plasma treatment, the oxide film 42 and other impurities formed on the surface of the Cu wiring 40 are removed.

In Table 1 and FIG. 6A, after turning off the RF power, for example, SiH ₄ (monosilane) gas is introduced into the chamber (STEP 3 in Table 1). The time for introducing SiH ₄ gas in STEP 3 is, for example, 1 second. Here, the surface of the Cu wiring 40 is activated by the plasma treatment in STEP2. For this reason, as in STEP 3, by introducing SiH ₄ gas for a very short time of 1 second with the RF power OFF, that is, in a mixed gas atmosphere of NH ₃ gas and SiH ₄ gas, the semiconductor By subjecting the substrate 10 to heat treatment at 400 ° C. for 1 second, a very thin Cu silicide layer 44 of several nm can be formed on the surface of the Cu wiring 40.

In Table 1 and FIG. 6B, the RF power is turned on with the NH ₃ gas, SiH ₄ gas and N ₂ gas introduced into the chamber (STEP 4 in Table 1). As a result, a second insulating film 46 made of, for example, a nitride film is formed on the Cu wiring 40 and the first insulating film 30.

According to the manufacturing method of the first embodiment, as shown in FIG. 4C, after the groove portion 32 is formed in the first insulating film 30 and the nitride film 28 formed on the semiconductor substrate 10, FIG. ), A Cu film 38 is formed on the first insulating film 30 so as to be embedded in the groove 32. Thereafter, as shown in FIG. 5B, the Cu film 38 on the first insulating film 30 is removed and planarized by a CMP method or the like, and the Cu wiring 40 is formed in the groove 32. Then, as shown in FIG. 5C, plasma treatment is performed on the Cu wiring 40 in an NH ₃ gas atmosphere, and the oxide film 42 and impurities formed on the surface of the Cu wiring 40 are removed. As shown in FIG. 6A, the SiH ₄ gas is introduced into the NH ₃ gas atmosphere, and the semiconductor substrate 10 is exposed in the mixed gas atmosphere of NH ₃ gas and SiH ₄ gas without exposing the semiconductor substrate 10 to the atmosphere. Then, heat treatment is performed for 1 second to form a Cu silicide layer 44 on the surface of the Cu wiring 40.

  By such a manufacturing method, as shown in FIG. 6B, the Cu silicide layer 44 can be formed on the Cu wiring 40 without interposing an oxide film. The Cu silicide layer 44 is formed on the surface of the Cu wiring 40, and the second insulating film 46 is formed on the Cu silicide layer 44, so that the second insulating film 46 is directly formed on the surface of the Cu wiring 40. Compared to the case, electromigration of Cu atoms in the Cu wiring 40 to the second insulating film 46 can be suppressed.

  For this reason, as shown in FIG. 2C, the first wiring layer 62a (in the first embodiment, Cu in the first embodiment) near the boundary with the first nitride film 64a (in the first embodiment, corresponding to the second insulating film 46). It is possible to suppress the formation of the void 70 in the wiring 40). That is, an increase in resistance of the Cu wiring 40 due to the generation of the void 70 can be suppressed.

  Further, when Example 1 has a multilayer wiring structure as shown in FIG. 2C, the oxide film is not interposed between the Cu wiring 40 and the Cu silicide layer 44. An increase in contact resistance between the Cu wiring 40 and the underlying Cu wiring 40 can be suppressed. Further, since the Cu silicide layer 44 is formed on the surface of the Cu wiring 40, even when the via hole 68 as shown in FIG. 2A is formed, it is not necessary to expose the surface of the Cu wiring 40 to the atmosphere. . For this reason, it becomes difficult to form an oxide film on the surface of the Cu wiring 40, and an increase in contact resistance between the upper Cu wiring 40 and the lower Cu wiring 40 can be suppressed.

Further, after annealing for improving the crystallinity of the Cu film 38 as shown in FIG. 5B, in a mixed gas atmosphere of NH ₃ gas and SiH ₄ gas as shown in FIG. 6A. Then, the semiconductor substrate 10 is heat-treated, and a Cu silicide layer 44 is formed on the surface of the Cu wiring 40. If the Cu film is annealed after introducing Si into the Cu film as in Patent Document 3, Si diffuses throughout the Cu film and the resistance of the Cu film (Cu wiring) increases. However, according to the first embodiment, since the Cu silicide layer 44 is formed after annealing the Cu film 38, the Cu silicide layer 44 can be formed only on the surface of the Cu wiring 40. Therefore, an increase in resistance of the Cu wiring 40 can be suppressed as compared with Patent Document 3.

Furthermore, as shown in STEP 3 in Table 3, the temperature of the heat treatment performed in a mixed gas atmosphere of NH ₃ gas and SiH ₄ gas is as low as 400 ° C., and the heat treatment time is as short as 1 second. The thickness of the Cu silicide layer 44 to be formed can be made very thin as several nm. As described above, according to the first embodiment, the thickness of the Cu silicide layer 44 can be made very thin, so that an increase in resistance of the Cu wiring 40 can be suppressed to a minimum.

In the first embodiment, as shown in STEP 3 of Table 1, the case where the SiH ₄ gas is introduced for 1 second in the state where the RF power is turned off is shown as an example, but the present invention is not limited to this. In other words, in the mixed gas atmosphere of NH ₃ gas and SiH ₄ gas, the time for performing the heat treatment on the semiconductor substrate 10 is shown as an example, but the present invention is not limited thereto. As long as the thickness of the Cu silicide layer 44 formed on the surface of the Cu wiring 40 is sufficiently small and the resistance increase of the Cu wiring 40 can be sufficiently suppressed, the heat treatment time may be other than 1 second.

Here, FIG. 7 shows the time of heat treatment (STEP 3 in Table 1) performed on the semiconductor substrate 10 in a mixed gas atmosphere of NH ₃ gas and SiH ₄ gas under conditions of 0 second, 1 second, and 2 seconds, respectively. An example of the resistance value of the Cu wiring 40 in the semiconductor device manufactured in (1) is shown. Note that a semiconductor device manufactured with a heat treatment time of 0 seconds is taken as experimental example 1, a semiconductor device manufactured with a heat treatment time of 1 second is taken as experimental example 2, and a semiconductor device manufactured with a heat treatment time of 2 seconds is taken as experimental example. 3. For reference, plasma treatment on the surface of the Cu wiring 40 (STEP 2 in Table 1), heat treatment to the semiconductor substrate 10 in a mixed gas atmosphere of NH ₃ gas and SiH ₄ gas (STEP 3 in Table 1), A semiconductor device (Comparative Example 1) manufactured without performing the process is also illustrated. That is, in the semiconductor device according to Comparative Example 1, the Cu silicide layer 44 is not formed on the surface of the Cu wiring 40 in FIG. 6C, and an oxide film 42 is formed instead. Moreover, the measurement results in FIG. 7 show the results for a plurality of measurement points in the wafer.

  According to FIG. 7, the resistance value of the Cu wiring 40 is lower in the experimental example 1 in which the plasma treatment is performed and the heat treatment time is 0 second as compared with the comparative example 1 in which the plasma treatment and the heat treatment are not performed. I understand that. This is considered to be because the oxide film 42 and impurities formed on the surface of the Cu wiring 40 were removed by performing the plasma treatment on the Cu wiring 40. Further, as in Experimental Example 1, Experimental Example 2, and Experimental Example 3, it can be seen that the resistance value of the Cu wiring 40 increases as the heat treatment time increases. This is considered to be because the thickness of the Cu silicide layer 44 formed on the surface of the Cu wiring 40 is increased.

  Here, FIG. 8 shows an average value of resistance values measured at a plurality of measurement points in the wafer for each of Experimental Examples 1 to 3. The horizontal axis in FIG. 8 indicates the heat treatment time (seconds), and the vertical axis indicates the resistance value normalized by the resistance value of Experimental Example 1. Further, the solid line in FIG. 8 indicates an approximate curve. According to FIG. 8, compared with the resistance value of the Cu wiring 40 of Experimental Example 1, the resistance value of Experimental Example 2 is about 1.1 times, and the resistance value of Experimental Example 3 is about 1.5 times. . When the heat treatment time exceeds 2 seconds, the resistance value is about 1.5 times or more the resistance value of Experimental Example 1, and when the heat treatment time is 3 seconds, the resistance value of Experimental Example 1 is twice or more. It becomes.

Thus, the resistance value of the Cu wiring 40 increases as the time of the heat treatment performed on the semiconductor substrate 10 in the mixed gas atmosphere of NH ₃ gas and SiH ₄ gas increases. In particular, it can be seen that when the heat treatment time exceeds 2 seconds, the resistance value of the Cu wiring 40 rapidly increases. Therefore, in consideration of an increase in the resistance value of the Cu wiring 40, the heat treatment time performed in a mixed gas atmosphere of NH ₃ gas and SiH ₄ gas in order to keep the resistance value of the Cu wiring 40 within a practical range is: The case is preferably 2 seconds or less, and more preferably 1 second or less. In other words, the heat treatment time is preferably such that the resistance value of the Cu wiring 40 is not more than 1.5 times the resistance value of the Cu wiring 40 when the heat treatment time is 0 second. The heat treatment time is preferably such that the resistance value of 40 is 1.1 times or less. In other words, the specific resistance of the Cu wiring 40 when the heat treatment time is 0 second is substantially equal to the specific resistance of bulk Cu, and the Cu wiring when the heat treatment time is 2 seconds. The specific resistance of 40 is about 1.5 times the specific resistance of bulk Cu. Further, when the heat treatment time is 1 second, the specific resistance of the Cu wiring 40 is about 1.1 times the specific resistance of bulk Cu. That is, the heat treatment time is preferably such that the specific resistance of the Cu wiring 40 is 1.5 times or less of the specific resistance of bulk Cu, and further, 1.1 times or less of the specific resistance of bulk Cu. The heat treatment time is more preferable. By setting the time for the heat treatment performed on the semiconductor substrate 10 to such a time, an increase in the resistance value of the Cu wiring 40 can be minimized.

  If the Cu silicide layer 44 is not formed on the surface of the Cu wiring 40, voids due to electromigration occur as shown in FIG. 2C, and the resistance value of the Cu wiring 40 increases. Therefore, considering that the Cu silicide layer 44 is reliably formed on the surface of the Cu wiring 40, the heat treatment time is preferably 0.5 seconds or more.

Further, in Example 1, carried out in a mixed gas atmosphere of NH ₃ gas and the SiH ₄ gas, the temperature of the heat treatment to the semiconductor substrate 10, a case is 400 ° C. Examples, but not limited to . The heat treatment may be performed at a temperature at which the thickness of the Cu silicide layer 44 is sufficiently small and the increase in resistance of the Cu wiring 40 is sufficiently small. For example, it is preferable to perform heat treatment at a low temperature such as 100 ° C. to 500 ° C. Moreover, it is preferable to change the time of heat processing according to the temperature of heat processing.

In Example 1, the case where the oxide film 42 formed on the surface of the Cu wiring 40 is removed by performing plasma treatment in an NH ₃ gas atmosphere as shown in FIG. It is not limited to this. For example, even when the plasma treatment is performed in an H ₂ (hydrogen) gas atmosphere or an N ₂ H ₄ (hydrazine) gas atmosphere, the oxide film 42 formed on the surface of the Cu wiring 40 can be removed.

Further, as shown in FIG. 6A, an example in which a heat treatment is performed on the semiconductor substrate 10 in a mixed gas atmosphere of SiH ₄ gas and NH ₃ gas to form a Cu silicide layer 44 on the surface of the Cu wiring 40. However, the present invention is not limited to this. By performing heat treatment in a gas (silane-based gas) atmosphere containing a compound of Si (silicon) and H (hydrogen), such as SiH ₄ gas or Si ₂ H ₆ (disilane) gas, Cu is formed on the surface of the Cu wiring 40. A silicide layer 44 can be formed.

However, as in the manufacturing method of the first embodiment, plasma treatment is performed on the surface of the Cu wiring 40 in an NH ₃ gas atmosphere, thereby removing the oxide film 42 and the like formed on the surface of the Cu wiring 40, and the NH ₃ gas. It is preferable to form the Cu silicide layer 44 on the surface of the Cu wiring 40 by performing a heat treatment on the semiconductor substrate 10 in a mixed gas atmosphere of SiH ₄ gas and SiH ₄ gas. According to this manufacturing method, as shown in Table 1, plasma processing is performed on the semiconductor substrate 10 (STEP 2 in Table 1) in a chamber filled with NH ₃ gas, and the oxide film 42 on the surface of the Cu wiring 40, etc. Then, the Si silicide layer 44 can be formed on the surface of the Cu wiring 40 by introducing SiH ₄ gas into the chamber (STEP 3 in Table 1) and heat-treating the semiconductor substrate 10. That is, the removal of the oxide film 42 and the like formed on the surface of the Cu wiring 40 and the formation of the Cu silicide layer 44 on the surface of the Cu wiring 40 can be performed continuously in the same chamber. Therefore, it is possible to efficiently form the Cu silicide layer 44 on the surface of the Cu wiring 40 without interposing an oxide film. Furthermore, as shown in STEP 4 of Table 1 and FIG. 6B, the second insulating film 46 formed on the Cu silicide layer 44 and the first insulating film 30 can also be formed continuously in the same chamber. . Therefore, the manufacturing efficiency can be improved also in this respect.

  In the first embodiment, the case of a nonvolatile semiconductor device having a SONOS structure has been described as an example, but the present invention is not limited to this. Even in the case of other semiconductor devices, electromigration can be suppressed and the resistance of the Cu wiring can be increased by using the method for manufacturing the Cu wiring 40 shown in FIGS. 4C to 6B. It can be minimized. However, in the case of the non-volatile semiconductor device having the SONOS type structure as shown in the first embodiment, the Cu wiring 40 formed on the contact plug 26 has a very narrow pitch and is fine. For this reason, the effect of the present invention of minimizing the increase in resistance of the Cu wiring 40 becomes greater. In addition, although the case where the wiring layer formed so as to be embedded in the groove portion 32 is the Cu wiring 40 has been described as an example, the wiring layer is not limited thereto, and may be formed of other materials.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

FIG. 1A to FIG. 1C are cross-sectional views (part 1) showing the manufacturing method in the case where the surface of the wiring layer is covered with a nitride film. FIG. 2A to FIG. 2C are cross-sectional views (part 2) showing the manufacturing method when the surface of the wiring layer is covered with a nitride film. FIG. 3A to FIG. 3C are cross-sectional views (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 4A to 4C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 6A and 6B are cross-sectional views (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 7 is a diagram (part 1) showing a correlation between the time of heat treatment performed on the semiconductor substrate and the resistance of the wiring layer. FIG. 8 is a diagram (part 2) illustrating the correlation between the time of heat treatment performed on the semiconductor substrate and the resistance of the wiring layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 Bit line 14 ONO film 16 BPSG film 18 Cap layer 20 Mask layer 22 Contact hole 24 Barrier layer 26 Contact plug 28 Nitride film 30 1st insulating film 32 Groove part 34 Barrier layer 36 Cu seed layer 38 Cu film 40 Cu wiring 42 oxide film 44 Cu silicide layer 46 second insulating film 50 semiconductor substrate 52a first oxide film 52b second oxide film 52c third oxide film 54a first groove part 54b second groove part 56 barrier layer 58 Cu seed layer 60 Cu film 62a first 1 wiring layer 62b 2nd wiring layer 64a 1st nitride film 64b 2nd nitride film 64c 3rd nitride film 66 Via 68 Via hole 70 Void

Claims (8)

Forming a groove in an insulating film formed on the semiconductor substrate;
Forming a metal film on the insulating film so as to be embedded in the groove,
Flattening the metal film formed on the insulating film and forming a wiring layer made of the metal film in the groove;
Performing plasma treatment on the surface of the wiring layer in order to remove the oxide film formed on the surface of the wiring layer;
A step of heat-treating the semiconductor substrate in a gas atmosphere containing a silane-based gas without exposing the semiconductor substrate to the air after the step of performing the plasma treatment in order to form a silicide layer on the surface of the wiring layer; When,
After the step of performing the heat treatment, forming a nitride film on the surface of the silicide layer,
The wiring layer is Ri copper wiring der,
The method for manufacturing a semiconductor device, wherein the heat treatment is performed in a mixed gas atmosphere in which the silane-based gas is introduced into a gas atmosphere of the plasma treatment .   The step of performing the plasma treatment is a step of performing plasma treatment on the surface of the wiring layer by exposing the semiconductor substrate to any one of an ammonia gas atmosphere, a hydrogen gas atmosphere, and a hydrazine gas atmosphere. A method for manufacturing a semiconductor device according to claim 1.   The method for manufacturing a semiconductor device according to claim 1, wherein the step of performing the heat treatment is a step of performing a heat treatment on the semiconductor substrate in a gas atmosphere containing a monosilane gas or a disilane gas. The step of performing the plasma treatment is a step of exposing the semiconductor substrate to an ammonia gas atmosphere and performing a plasma treatment on the surface of the wiring layer,
The semiconductor device according to claim 1, wherein the step of performing the heat treatment is a step of introducing a monosilane gas into the ammonia gas atmosphere and performing a heat treatment on the semiconductor substrate in a mixed gas atmosphere of the ammonia gas and the monosilane gas. Manufacturing method.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the step of performing the heat treatment is a step of performing the heat treatment on the semiconductor substrate for 0.5 second to 2 seconds. In order to improve the crystallinity of the metal film, the method includes annealing the metal film,
The method for manufacturing a semiconductor device according to claim 1, wherein the step of annealing the metal film is performed before the step of performing the heat treatment.   The method of manufacturing a semiconductor device according to claim 1, wherein the step of performing the heat treatment is a step of performing the heat treatment in a state in which a surface of the wiring layer is activated.   Forming a contact prada on the semiconductor substrate;
  The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed on the contact ladder.

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