JP5549219B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Flash memories and ferroelectric memories are known as nonvolatile memories that can store information even when the power is turned off.

  Among these, the flash memory has a floating gate embedded in a gate insulating film of an insulated gate field effect transistor, and stores information by accumulating charges representing stored information in the floating gate. However, such a flash memory has a drawback that a tunnel current needs to flow through the gate insulating film when writing or erasing information, and a relatively high voltage is required.

  On the other hand, the ferroelectric memory is also called FeRAM (Ferroelectric Random Access Memory), and stores information using the hysteresis characteristic of a capacitor dielectric film made of a ferroelectric material. The capacitor dielectric film is polarized in accordance with the voltage applied between the upper electrode and the lower electrode of the capacitor, and the spontaneous polarization remains even if the voltage is removed. When the polarity of the applied voltage is reversed, this spontaneous polarization is also reversed, and information is written to the capacitor dielectric film by making the direction of the spontaneous polarization correspond to “1” and “0”. FeRAM has the advantage that the voltage required for the writing is lower than that in the flash memory and that writing can be performed at a higher speed than the flash memory.

JP 2006-5152 A JP-A-10-247724 JP-A-9-260614

  An object of the manufacturing method of a semiconductor device is to suppress damage to a capacitor dielectric film of a ferroelectric capacitor.

According to one aspect of the disclosure below, a step of forming an insulating film over a semiconductor substrate, and a first conductive film, a ferroelectric film, and a second conductive film are formed in this order on the insulating film. forming a step of the upper electrode of the ferroelectric capacitor of the previous SL second conductive film is etched by patterning the previous SL ferroelectric film to the capacitor dielectric film of the ferroelectric capacitor And a step of etching the first conductive film to form a lower electrode of the ferroelectric capacitor. The step of etching the second conductive film includes a first etching gas containing a halogen gas. The first step of etching the second conductive film to a halfway depth by the second step, and after the first step, using the second etching gas containing oxygen gas and not containing halogen, Etching the rest of the conductive film And a second step that, in the step of etching the second conductive film, when the ferroelectric film next to the upper electrode is exposed, the etching atmosphere, an and halogen containing oxygen gas Provided is a method for manufacturing a semiconductor device which does not include an atmosphere. According to another aspect of the disclosure below, a step of forming an insulating film above a semiconductor substrate, and a first conductive film, a ferroelectric film, and a second conductive film on the insulating film Are formed in this order, the second conductive film is etched to form an upper electrode of a ferroelectric capacitor, and the ferroelectric film is patterned to form a capacitor dielectric film of the ferroelectric capacitor. And a step of etching the first conductive film to form a lower electrode of the ferroelectric capacitor, and the step of etching the second conductive film contains oxygen gas and contains halogen A first step of etching the second conductive film to an intermediate depth with a non-etching gas, and after the first step, the flow rate ratio of the oxygen gas in the etching gas is set to the oxygen in the first step. Ga And a second step of etching the remaining portion of the second conductive film, and in the step of etching the second conductive film, the ferroelectric material beside the upper electrode. Provided is a method for manufacturing a semiconductor device in which an etching atmosphere is an atmosphere containing oxygen gas and not containing halogen when the film is exposed.

  According to the following disclosure, when the ferroelectric film is exposed beside the upper electrode, the ferroelectric film is not exposed to the halogen, so that the deterioration of the capacitor dielectric film due to the halogen can be suppressed. It becomes possible.

FIG. 1 is a plan view of the FeRAM used for the investigation. 2A to 2C are cross-sectional views (part 1) in the middle of manufacturing the FeRAM used for the investigation. FIG. 3 is a cross-sectional view (part 2) in the middle of manufacturing the FeRAM used for the investigation. FIG. 4 is a cross-sectional view (part 1) of the semiconductor device according to the present embodiment during manufacturing. FIG. 5 is a cross-sectional view (part 2) of the semiconductor device according to the present embodiment during manufacture. FIG. 6 is a cross-sectional view (part 3) of the semiconductor device according to the present embodiment during manufacture. FIG. 7 is a cross-sectional view (part 4) of the semiconductor device according to the present embodiment during manufacture. FIG. 8 is a cross-sectional view (part 5) of the semiconductor device according to the present embodiment during manufacture. FIG. 9 is a cross-sectional view (No. 6) of the semiconductor device according to the present embodiment in the middle of manufacture. FIG. 10 is a cross-sectional view (No. 7) of the semiconductor device according to the present embodiment during manufacturing. FIG. 11 is a cross-sectional view (No. 8) in the middle of manufacturing the semiconductor device according to the present embodiment. FIG. 12 is a sectional view (No. 9) in the middle of manufacturing the semiconductor device according to this embodiment. FIG. 13 is a cross-sectional view (part 10) of the semiconductor device according to the present embodiment in the middle of manufacture. FIG. 14 is a cross-sectional view (No. 11) in the middle of manufacturing the semiconductor device according to the present embodiment. FIG. 15 is a cross-sectional view (No. 12) of the semiconductor device according to the present embodiment during manufacturing. FIG. 16 is a cross-sectional view (No. 13) of the semiconductor device according to the present embodiment during manufacturing. FIG. 17 is a cross-sectional view (No. 14) of the semiconductor device according to the present embodiment during manufacturing. FIG. 18 is a cross-sectional view (No. 15) of the semiconductor device according to the present embodiment during manufacturing. FIG. 19 is a plan view (part 1) of the semiconductor device according to the present embodiment in the middle of manufacture. FIG. 20 is a plan view (part 2) of the semiconductor device according to the present embodiment during manufacture. FIG. 21 is a plan view (part 3) of the semiconductor device according to the present embodiment during manufacturing. FIG. 22 is a plan view (part 4) of the semiconductor device according to the present embodiment during manufacture. FIG. 23 is a plan view (part 5) of the semiconductor device according to this embodiment in the middle of manufacture. FIG. 24 is a plan view (part 6) of the semiconductor device according to the present embodiment during manufacturing. FIG. 25 is a plan view (No. 7) of the semiconductor device according to the present embodiment during manufacturing. FIG. 26 is a plan view (No. 8) of the semiconductor device according to the present embodiment during manufacturing.

  Prior to the description of the present embodiment, an investigation conducted by the present inventor will be described.

  FIG. 1 is a plan view of the FeRAM used in this investigation.

  This FeRAM has a silicon substrate 100 and a striped lower electrode 101a, a ferroelectric film 102a, and an upper electrode 103a formed thereabove.

  Among these, the upper electrode 103a has an island-like planar shape, and a plurality of upper electrodes 103a are formed on the striped capacitor dielectric film 102a. Each ferroelectric capacitor Q is formed corresponding to the upper electrode 103a, and the lower electrode 101a is shared by each capacitor Q. The FeRAM having such a structure is also called a planar type FeRAM.

  2 to 3 are cross-sectional views in the course of manufacturing a planar type FeRAM and correspond to a cross-sectional view taken along the line AA in FIG.

  To manufacture this FeRAM, first, as shown in FIG. 2A, a first conductive film 101 such as a platinum film, a ferroelectric film 102 such as a PZT film, A second conductive film 103 such as iridium oxide is formed in this order.

  Next, as shown in FIG. 2B, a titanium nitride film is formed as the hard mask 104, and a resist pattern 105 is formed thereon.

  Among these, the hard mask 104 can be formed by forming a titanium nitride film on the entire surface of the second conductive film 103 by sputtering and then dry etching the resist pattern 105 as a mask.

  Next, as shown in FIG. 2C, the second conductive film 103 is dry-etched by RIE (Reactive Ion Etching) using the hard mask 104 and the resist pattern 105 as a mask to form the upper electrode 103a.

  In this study, a mixed gas of chlorine gas and argon gas was used as the etching gas for this etching.

  Due to the sputtering action of the etching gas or the like, the resist pattern 105 is reduced during the etching, and the resist pattern 105 substantially disappears when the etching is completed.

  At the end of etching, the ferroelectric film 102 is exposed between the adjacent upper electrodes 103a, and the ferroelectric film 102 is exposed to an etching atmosphere containing chlorine. The damaged layer 102x is formed on the ferroelectric film 102 in the portion exposed to the etching atmosphere by the action of chlorine.

  Further, in this step, overetching of about several tens of percent of the film thickness of the second conductive film 103 is performed so as not to leave an etching residue of the second conductive film 103, but the damage layer 102x is also affected by this overetching. Is formed.

  After this etching is completed, the hard mask 104 is removed by wet etching.

  Thereafter, as shown in FIG. 3, the ferroelectric film 102 and the first conductive film 101 are individually patterned to form a capacitor dielectric film 102a and a lower electrode 101a.

  Thus, the basic structure of this FeRAM is completed.

  In such a FeRAM manufacturing method, as shown in FIG. 2C, the capacitor dielectric between the adjacent upper electrodes 103a is caused by chlorine gas or over-etching when the second conductive film 103 is etched. A damage layer 102x is formed on the body film 102a.

  The damaged layer 102x reduces the ferroelectric characteristics of the capacitor dielectric film 102a, such as the residual polarization charge amount, and increases the leakage current of the capacitor dielectric film 102a. This hinders the provision of Q.

  Here, in order to prevent formation of the damaged layer 102x due to overetching, the flow rate ratio of chlorine gas in the etching gas is increased in the step of FIG. 2C, and the ferroelectric film 102 and the second conductive film 103 are separated. It is also conceivable to increase the etching selectivity.

  However, when the flow rate ratio of chlorine gas is increased in this way, the etching rate of the hard mask 104 is increased, so that the outer shape of the hard mask 104 becomes unstable during the etching, and the processing accuracy of the upper electrode 103a is lowered. .

  In order to prevent the formation of the damaged layer 102x by chlorine gas, it is also conceivable to use a fluorine compound gas in place of the chlorine gas in the process of FIG.

  However, with an etching gas containing a fluorine compound gas, the etching selectivity between the second conductive film 103 and the ferroelectric film 102 is lowered, so that it is difficult to automatically stop the etching on the upper surface of the ferroelectric film 102. . Therefore, overetching must be performed so as not to leave an etching residue of the second conductive film 103 on the ferroelectric film 102, and the damage layer 102x is also formed by this overetching.

  As described above, the inventors' investigation reveals that the ferroelectric characteristics of the capacitor dielectric film 102a are deteriorated when halogen such as chlorine or fluorine compound is added to the etching gas for the second conductive film 103. became. Based on such investigation results, the inventor of the present application has arrived at the present embodiment as described below.

(This embodiment)
4 to 18 are cross-sectional views of the semiconductor device according to the present embodiment during manufacture, and FIGS. 19 to 26 are plan views thereof.

  The first cross section in FIGS. 4 to 18 corresponds to a cross section taken along line I-I in FIGS. Moreover, the 2nd cross section in FIGS. 4-18 corresponds to the cross section which follows the II-II line in FIGS.

  This semiconductor device is a so-called planar type FeRAM and is manufactured as follows.

  First, as shown in FIGS. 4 and 19, a trench for element isolation is formed in a silicon (semiconductor) substrate 1, and a silicon oxide film is buried in the trench as an element isolation insulating film 2 that defines an active region. Such an element isolation structure is called STI (Shallow Trench Isolation). Alternatively, element isolation may be performed by LOCOS (Local Oxidation of Silicon).

  Next, p-type impurities are ion-implanted into the active region to form a p-well 3.

  Further, the silicon substrate 1 in the active region is thermally oxidized to form a thermal oxide film to be the gate insulating film 4 with a thickness of 6 nm to 7 nm.

  Then, an amorphous silicon film having a thickness of about 50 nm and a tungsten silicide film having a thickness of about 150 nm are formed in this order on the thermal oxide film by CVD, and the gate electrode 5 is formed by patterning these films. To do.

  Two gate electrodes 5 are formed on the p-well 3, each of which constitutes a part of a word line.

  Subsequently, n-type impurities are ion-implanted into the silicon substrate 1 using the gate electrode 5 as a mask to form low-concentration first and second n-type source / drain extensions 6a and 6b.

  Next, an insulating film is formed on the entire upper surface of the silicon substrate 1, and the insulating film is etched back to form an insulating sidewall 9 next to the gate electrode 5. As the insulating film, for example, a silicon oxide film is formed to a thickness of about 45 nm by a CVD method.

  Then, by using this insulating sidewall 9 and the gate electrode 5 as a mask, n-type impurities are ion-implanted into the silicon substrate 1 to thereby form the first and second n-type source / drain regions 7a and 7b having a high concentration. Form.

  Thus, the MOS transistor TR including the gate electrode 5, the gate insulating film 4, the n-type source / drain regions 7a and 7b, and the like is formed.

  Thereafter, a cobalt layer is formed on the entire upper surface of the silicon substrate 1 by sputtering, and heated to react with silicon to form a refractory metal silicide layer 8 such as a cobalt silicide layer.

  Next, the cover insulating film 10 and the first insulating film 11 are formed in this order on the entire upper surface of the silicon substrate 1 by the CVD method. Among these, as the cover insulating film 10, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed. As the first insulating film 11, a silicon oxide film is formed to a thickness of about 600 nm by a plasma CVD method using TEOS gas.

  Thereafter, the upper surface of the first insulating film 11 is polished and planarized by a thickness of about 200 nm by a CMP (Chemical Mechanical Polishing) method.

  Next, as shown in FIG. 5, a silicon oxide film is formed as a cap insulating film 13 on the first insulating film 11 to a thickness of about 100 nm, and the surface of the first insulating film 11 is subjected to the CMP. The fine scratches attached to are buried with the cap insulating film 13.

  The cap insulating film 13 is formed by, for example, a plasma CVD method using TEOS gas.

  Then, in order to dehydrate moisture contained in the cap insulating film 13, the cap insulating film 13 is annealed in a nitrogen atmosphere under conditions of a substrate temperature of about 650 ° C. and a processing time of about 30 minutes.

Further, an alumina (Al ₂ O ₃ ) film is formed on the cap insulating film 13 as an adhesion layer 14 to a thickness of about 20 nm by sputtering.

  Annealing may be performed in an oxygen atmosphere after the formation of the adhesion layer 14. The annealing is performed, for example, under conditions of a substrate temperature of about 650 ° C. and a processing time of about 60 minutes in an RTA apparatus.

  Next, steps required until a structure shown in FIGS.

  First, a platinum film having a thickness of about 155 nm is formed on the adhesion layer 14 by sputtering, and the platinum film is used as the first conductive film 20. Note that an iridium film may be formed as the first conductive film 20 instead of the platinum film.

  Subsequently, a PZT film is formed on the first conductive film 20 to a thickness of 150 nm to 200 nm by sputtering, and the PZT film is used as the ferroelectric film 21. If necessary, calcium or strontium may be added to the PZT film.

  Thus, the ferroelectric film 21 formed by the sputtering method is in an amorphous state and has poor ferroelectric characteristics.

  Therefore, in a mixed atmosphere of oxygen and argon, RTA (Rapid Thermal Annealing) is performed on the ferroelectric film 21 under conditions of a substrate temperature of about 585 ° C. and a processing time of 90 seconds to crystallize the ferroelectric film 21. To be oriented in the (111) direction. The flow rate of oxygen at this time is, for example, 0.025 liter / min. Such annealing is also called crystallization annealing.

The ferroelectric film 21 is not limited to the PZT film. Instead of PZT, any ferroelectric material of PLZT, SrBi ₂ Ta ₂ O ₉ , Bi ₄ Ti ₃ O ₉ , Bi _0.25 La _0.75 Ti ₃ O ₁₂ , and BaBi ₂ Ta ₂ O ₉ is used as a ferroelectric film. 21 materials may be used.

  Further, the method of forming the ferroelectric film 21 is not limited to the sputtering method, and the ferroelectric film 21 may be formed by metal organic chemical vapor deposition (MOCVD) or sol-gel method. .

Subsequently, an iridium oxide (IrO ₂ ) film is formed as a _second conductive film 22 on the ferroelectric film 21 by a sputtering method.

  The second conductive film 22 is formed in two steps. In the first step, a first iridium oxide film is formed to a thickness of about 50 nm by sputtering. Then, the first iridium oxide film is annealed under the conditions of an oxygen flow rate of about 0.025 l / min, a substrate temperature of about 725 ° C., and a processing time of 20 seconds. Thereafter, a second iridium oxide film is formed on the first iridium oxide film by sputtering to a thickness of about 200 nm.

Note that any one of platinum, ruthenium, rhodium, rhenium, osmium, palladium, and SrRuO ₃ may be used as the material of the second conductive film 22 instead of iridium oxide.

  Thereafter, as shown in FIG. 7, a titanium nitride (TiN) film is formed as a mask material film 23 on the second conductive film 22 by a sputtering method to a thickness of about 20 nm to 40 nm.

  Then, as shown in FIG. 8, a photoresist is applied on the mask material film 23, and it is exposed and developed to form a first resist pattern 25.

  Subsequently, as shown in FIGS. 9 and 21, by using the first resist pattern 25 as a mask, the mask material film 23 is dry-etched by RIE, thereby forming a plurality of hard masks 23a having planar island shapes. To do.

  Although the etching gas in this etching is not particularly limited, in this embodiment, chlorine gas is used as the etching gas.

  As will be described later, the first resist pattern 25 may be formed directly on the second conductive film 22 without forming the hard mask 23a.

  Next, as shown in FIG. 10, the second conductive film 22 is dry-etched by RIE using the hard mask 23a and the first resist pattern 25 as a mask.

  The dry etching is performed in two steps in an ICP (Inductive Coupled Plasma) type etching chamber, and in the first first step, the second conductive film 22 is etched to an intermediate depth as shown in FIG.

  Although the etching gas in this 1st step is not specifically limited, For example, the gas which consists of oxygen gas and an inert gas can be used as etching gas. Of these, the flow rate of the oxygen gas is, for example, 0 sccm to 10 sccm. As the inert gas, argon gas having a flow rate of 40 sccm to 50 sccm can be used.

  The etching gas is turned into plasma by supplying high-frequency power to a coil provided in the chamber. The high-frequency power has, for example, a power of 1400 W and a frequency of 13.56 MHz.

  In addition, high-frequency power having a power of 800 W and a frequency of 400 kHz is applied to the stage on which the silicon substrate 1 is placed in the chamber, whereby plasmaized etching gas is drawn into the silicon substrate 1 side.

  The pressure in the chamber during etching is about 0.5 Pa to 1.0 Pa, and the substrate temperature is about 20 ° C.

  Next, as shown in FIGS. 11 and 22, the ICP type etching chamber used in the first step is continuously used, and a gas composed of oxygen gas and argon gas is used as an etching gas while the second conductive film is used. A second step of dry etching for 22 is performed.

  In this step, the flow rate ratio of oxygen in the etching gas is higher than in the first step, and the remainder of the second conductive film 22 that is not covered with the hard mask 23a is etched by RIE, so that the plurality of upper electrodes 22a is formed at intervals.

  The flow rate of the etching gas is not particularly limited, but in this embodiment, the flow rate of oxygen gas is 25 sccm to 40 sccm, and the flow rate of argon gas is 10 sccm to 25 sccm.

  Note that halogen such as chlorine and fluorine is not added to the etching gas.

  The other etching conditions are the same as those in the first step.

  Thus, by increasing the flow rate ratio of oxygen in the etching gas as compared with the first step, the etching rate of the ferroelectric film 21 is slower than that of the second conductive film 22 in this step. As a result, the etching is automatically stopped on the ferroelectric film 21, and it is possible to suppress the formation of a damaged layer on the ferroelectric film 21 due to over-etching.

  Furthermore, since oxygen in the etching gas is taken into the hard mask 23a, the etching resistance of the hard mask 23a is improved, and the outer shape of the hard mask 23a is not easily broken during the etching, and the processing accuracy of the upper electrode 22a is improved. .

  In addition, since the etching gas contains no halogen, a damage layer caused by halogen is not formed on the ferroelectric film 21 exposed beside the adjacent upper electrode 22a.

  Note that the first resist pattern 25 is thinned by the sputtering action of the etching gas or the like, and substantially disappears when this step is completed.

  Here, in order to suppress damage to the ferroelectric film 21 as described above, it is sufficient that halogen is excluded from the etching gas in the second step in which the ferroelectric film 21 is exposed after etching. In the step, halogen may be added to the etching gas.

  For example, in the first step, a mixed gas of chlorine gas having a flow rate of about 10 sccm and argon gas having a flow rate of 40 sccm to 50 sccm may be used as the etching gas. In this case, in the second step, the etching gas is switched to a gas composed of oxygen gas and argon gas. The flow rate of oxygen gas after such switching is, for example, 25 sccm to 40 sccm, and the flow rate of argon gas is, for example, 10 sccm to 25 sccm.

  When chlorine gas is used in the first step as described above, the second conductive film 22 is etched by a chemical reaction with chlorine gas in addition to the sputtering action of the etching gas. Therefore, compared with the case where chlorine gas is not used in the first step, the sputtering effect of the etching gas can be relatively reduced, and the first resist pattern 25 can be prevented from being reduced by the sputtering effect. Therefore, in this case, the hard mask 23 a is omitted and the first resist pattern 25 is directly formed on the second conductive film 22, and the second conductive film 22 is patterned only by the first resist pattern 25. It becomes possible to do.

  Note that the second conductive film 22 may be etched in a lump without dividing into the first step and the second step. Also in this case, it is possible to prevent the ferroelectric film 21 from being damaged due to the halogen by using a gas containing oxygen gas and argon gas and not containing halogen as the etching gas.

Thereafter, the hard mask 23a is removed by wet etching or the like. In the wet etching, for example, an etching solution made of a mixed solution of a hydrogen peroxide solution (H ₂ O ₂ ) having a concentration of 30 w% and an ammonium hydroxide (NH ₄ OH) solution having a concentration of 30 w% is used.

  After the hard mask 23a is removed, the ferroelectric film 21 is annealed in a vertical furnace in an oxygen atmosphere in order to recover the damage received by the ferroelectric film 21 in the steps so far. May be performed.

  The annealing is called recovery annealing and is performed, for example, under conditions of a substrate temperature of about 650 ° C., an oxygen flow rate of about 20 liters / hour, and a processing time of about 60 minutes.

  Next, as shown in FIGS. 12 and 23, a stripe-shaped second resist pattern 27 is formed on the ferroelectric film 21 so as to cover each of the plurality of upper electrodes 22a.

  Then, while using the first resist pattern 27 as a mask, the ferroelectric film 21 is etched by RIE to form a capacitor dielectric film 21a having a stripe shape in plan view.

  After the etching is finished, the second resist pattern 27 is removed.

  Thereafter, as the recovery annealing for the capacitor dielectric film 21a, annealing is performed in a vertical furnace under conditions of an oxygen flow rate of about 20 liters / minute, a substrate temperature of about 350 ° C., and a processing time of about 60 minutes.

  After the recovery annealing, an alumina film for protecting the capacitor dielectric film 21a from a reducing substance such as hydrogen may be formed on the entire upper surface of the silicon substrate 1.

  Subsequently, as shown in FIGS. 13 and 24, a photoresist is applied to the entire upper surface of the silicon substrate 1, and exposed and developed to form a third resist pattern 28 having a striped planar shape. To do.

  Further, using the third resist pattern 28 as a mask, the first conductive film 20 is dry-etched by RIE to form a lower electrode 20a having a stripe shape in plan view.

  In this etching, the portion of the adhesion layer 14 not covered with the third resist pattern 28 is also etched away.

  Thereafter, the third resist pattern 28 is removed.

  Then, in order to recover the damage received by the capacitor dielectric film 21a due to etching or the like, recovery annealing is performed in a vertical furnace having an oxygen-containing atmosphere. The conditions for the recovery annealing are not particularly limited, but in this embodiment, the oxygen flow rate is about 20 liters / minute, the substrate temperature is about 650 ° C., and the processing time is about 60 minutes.

  Through the steps so far, the ferroelectric capacitor Q is formed by laminating the lower electrode 20a, the capacitor dielectric film 21a, and the upper electrode 22a in this order.

  A plurality of ferroelectric capacitors Q are formed for each upper electrode 22a with the lower electrode 20a and the capacitor dielectric film 21a in common.

  Next, steps required until a sectional structure shown in FIG.

  First, an alumina film having a thickness of about 20 nm is formed on the capacitor Q and the cap insulating film 13 as an insulating hydrogen barrier film 31 by sputtering.

  After the formation of the insulating oxygen barrier film 31, recovery annealing may be performed on the capacitor Q in a vertical furnace. The conditions for the recovery annealing are, for example, an oxygen flow rate of about 20 liters / minute, a substrate temperature of about 550 ° C., and a processing time of 60 minutes.

  Next, a silicon oxide film having a thickness of about 1500 nm is formed on the insulating hydrogen barrier film 31 by a CVD method using oxygen and TEOS gas as a reaction gas. The silicon oxide film is formed with the second insulating film 32. To do.

  Although the TEOS gas contains hydrogen, the insulative hydrogen barrier film 31 prevents hydrogen from entering the capacitor Q, and the capacitor dielectric film 21a is reduced by hydrogen and its ferroelectric characteristics deteriorate. Can be suppressed.

  Thereafter, the upper surface of the second insulating film 32 is polished and planarized by the CMP method.

After this CMP, in order to prevent dehydration and moisture re-adsorption of the second insulating film 32, the second insulating film 32 substrate temperature of about 350 ° C. relative to, N ₂ O under the condition of 2 minutes process time Plasma treatment is performed to nitride the surface of the second insulating film 32. Such N ₂ O plasma treatment can be performed using, for example, a CVD apparatus.

  Subsequently, as shown in FIG. 15, a photoresist is applied on the second insulating film 32, and it is exposed and developed to form a fourth resist pattern 33.

  Next, the insulating films 10, 11, 13, 14, and 32 on the first and second n-type source / drain regions 7 a and 7 b are dry-etched through the window 33 a of the fourth resist pattern 33. First and second contact holes 32a and 32b are formed in the insulating film.

  Thereafter, the fourth resist pattern 33 is removed.

  Next, steps required until a structure shown in FIGS.

  First, a titanium (Ti) film having a thickness of about 20 nm and a titanium nitride (TiN) film having a thickness of about 50 nm are formed as barrier metal films on the upper surface of the second insulating film 32 and the inner surfaces of the contact holes 32a and 32b. Are formed in this order by sputtering. Then, a tungsten film is formed to a thickness of about 500 nm on the barrier metal film by a CVD method, and the contact holes 32a and 32b are completely filled with the tungsten film. Thereafter, the excess tungsten film and the barrier metal film on the second insulating film 32 are polished and removed by the CMP method, and these films are left as the conductive plugs 35 only in the contact holes 32a and 32b.

  Since the conductive plug 35 formed in this manner contains tungsten that is easily oxidized, it easily oxidizes in an oxygen-containing atmosphere and easily causes contact failure.

  Therefore, in order to prevent oxidation of the conductive plug 35, a silicon oxynitride film having a thickness of about 100 nm is formed on each of the conductive plug 35 and the second insulating film 32 by the CVD method. The silicon film is used as an oxidation preventing insulating film 36.

Before forming the oxidation-preventing insulating film 36, N ₂ O plasma treatment is performed on the second insulating film 32 in the CVD apparatus in order to prevent dehydration of the second insulating film 32 and re-adsorption of moisture. May be performed. The N ₂ O plasma treatment is performed, for example, under conditions of a substrate temperature of about 350 ° C. and a treatment time of 2 minutes.

  Next, as shown in FIG. 17, a photoresist is applied on the antioxidant insulating film 36, and is exposed and developed to form a fifth resist pattern 40.

  Then, by dry-etching the insulating films 14, 32, and 36 through the window 40a of the fifth resist pattern 40, the first holes 32c are formed in these insulating films on the upper electrode 22a and on the lower electrode 20a. A second hole 32d is formed in these insulating films.

  After this etching is finished, the fifth resist pattern 40 and the antioxidant insulating film 36 are removed.

  Then, recovery annealing is performed on the capacitor dielectric film 21a in an oxygen-containing atmosphere in order to reduce damage to the capacitor dielectric film 27a due to this etching. This recovery annealing is performed, for example, under conditions of a substrate temperature of 500 ° C. to 600 ° C. and a processing time of 60 minutes.

  Next, as shown in FIGS. 18 and 26, a metal laminated film is formed on the second insulating film 32 and in the holes 32c and 32d by sputtering, and then patterned to form a metal wiring 41. . The metal laminated film is, in order from the bottom, a titanium nitride film having a thickness of about 150 nm, a copper-containing aluminum film having a thickness of about 550 nm, a titanium film having a thickness of about 5 nm, and a titanium nitride film having a thickness of about 150 nm.

  Of the metal wiring 41, a portion formed in the first hole 32c is electrically connected to the upper electrode 22a, and a portion formed in the second hole 32d is electrically connected to the lower electrode 20a. The

  Thus, the basic structure of the semiconductor device according to this embodiment is completed.

  According to the manufacturing method of the semiconductor device described above, when the upper electrode 22a is formed in the step of FIG. 11, the ferroelectric film 21 is exposed beside the upper electrode 22a and contains oxygen gas and does not contain halogen. The etching gas for the second conductive film 22 was switched to the gas.

  By using an etching gas containing no halogen in this way, it is possible to prevent a damage layer caused by halogen from being formed in the ferroelectric film 21 exposed between the adjacent upper electrodes 22a.

  Therefore, the ferroelectric characteristics of the capacitor dielectric film 21a formed by patterning the ferroelectric film 21 can be maintained in a high state, and the leakage current of the capacitor dielectric film 21a can be suppressed, so that high-grade ferroelectrics can be obtained. A semiconductor device including the body capacitor Q can be provided.

  In addition, the oxygen contained in the etching gas has a function of increasing the etching selectivity between the ferroelectric film 21 and the second conductive film 22, so that the etching of the second conductive film 22 is performed in the ferroelectric film. 21 can be automatically stopped. As a result, the ferroelectric film 21 can be prevented from being overetched, and the possibility that a damage layer is formed on the ferroelectric film 21 due to overetching can be reduced.

  The following additional notes are disclosed for each embodiment described above.

(Additional remark 1) The process of forming an insulating film above a semiconductor substrate,
Forming a first conductive film, a ferroelectric film, and a second conductive film in this order on the insulating film;
Forming a mask pattern on the second conductive film;
Etching the second conductive film into the upper electrode of the ferroelectric capacitor while using the mask pattern as a mask;
Removing the mask pattern;
Patterning the ferroelectric film to form a capacitor dielectric film of the ferroelectric capacitor;
Etching the first conductive film to form a lower electrode of the ferroelectric capacitor;
In the step of etching the second conductive film, when the ferroelectric film is exposed beside the upper electrode, the etching atmosphere is an atmosphere containing oxygen gas and not containing halogen. A method for manufacturing a semiconductor device.

(Supplementary Note 2) The step of etching the second conductive film includes:
A first step of etching the second conductive film to a halfway depth with a first etching gas containing a halogen gas;
And a second step of etching the remainder of the second conductive film using a second etching gas containing oxygen gas and not containing halogen after the first step. 2. A method for manufacturing a semiconductor device according to 1.

  (Supplementary note 3) The method for manufacturing a semiconductor device according to supplementary note 2, wherein a resist pattern is directly formed on the second conductive film as the mask pattern.

  (Additional remark 4) Chlorine gas is used as said halogen gas, The manufacturing method of the semiconductor device of Additional remark 2 or Additional remark 3 characterized by the above-mentioned.

(Supplementary Note 5) The step of etching the second conductive film includes:
A first step of etching the second conductive film to an intermediate depth with an etching gas containing oxygen gas and not containing halogen;
After the first step, there is provided a second step of etching the remainder of the second conductive film by increasing the flow rate ratio of the oxygen gas in the etching gas as compared with that in the first step. The manufacturing method of the semiconductor device according to appendix 1, which is characterized in that.

  (Additional remark 6) The said etching gas consists of inert gas and oxygen gas, The manufacturing method of the semiconductor device of Additional remark 5 characterized by the above-mentioned.

  (Supplementary Note 7) The step of etching the second conductive film is performed by collectively etching the second conductive film with an etching gas containing oxygen gas and not containing halogen. A method for manufacturing a semiconductor device according to attachment 1.

  (Additional remark 8) The manufacturing method of the semiconductor device of Additional remark 1 characterized by forming a hard mask as said mask pattern.

  (Additional remark 9) The said hard mask contains titanium nitride, The manufacturing method of the semiconductor device of Additional remark 8 characterized by the above-mentioned.

(Supplementary Note 10) In the step of etching the second conductive film, a plurality of the upper electrodes are formed at intervals,
10. The semiconductor device according to any one of appendices 1 to 9, wherein, in the step of etching the ferroelectric film, the capacitor dielectric film is formed in a stripe shape common to each of the plurality of upper electrodes. Manufacturing method.

DESCRIPTION OF SYMBOLS 1,100 ... Silicon substrate, 2 ... Element isolation insulating film, 3 ... p well, 4 ... gate insulating film, 5 ... gate electrode, 6a, 6b ... 1st and 2nd n-type source / drain extension, 7a, 7b 1st and 2nd n-type source / drain regions, 8 ... refractory metal silicide layer, 9 ... insulating sidewall, 10 ... cover insulating film, 11 ... first insulating film, 13 ... cap insulating film, 14 ... Adhesion layer, 20, 101 ... First conductive film, 20a, 103a ... Lower electrode, 21, 102 ... Ferroelectric film, 21a, 102a ... Capacitor dielectric film, 22, 103 ... Second conductive film, 22a 103a ... upper electrode, 23 ... mask material film, 23a, 104 ... mask pattern, 25 ... first resist pattern, 27 ... second resist pattern, 28 ... third resist pattern, 31 ... insulating property Elementary barrier film, 32 ... second insulating film, 32a, 32b ... first and second contact holes, 32c, 32d ... first and second holes, 33 ... fourth resist pattern, 33a ... window, 35 DESCRIPTION OF SYMBOLS ... Conductive plug, 36 ... Antioxidation insulating film, 40 ... 5th resist pattern, 40a ... Window, 41 ... Metal wiring, 105 ... Resist pattern, Q ... Ferroelectric capacitor.

Claims (3)

Forming an insulating film above the semiconductor substrate;
Forming a first conductive film, a ferroelectric film, and a second conductive film in this order on the insulating film;
Etching the second conductive film to form an upper electrode of a ferroelectric capacitor;
Patterning the ferroelectric film to form a capacitor dielectric film of the ferroelectric capacitor;
Etching the first conductive film to form a lower electrode of the ferroelectric capacitor;
The step of etching the second conductive film includes:
A first step of etching halfway depth the second conductive film by a first etching gas containing a halogen gas,
After the first step, using a second etching gas not containing and halogen-containing oxygen gas, the remainder of the second conductive film have a second step of etching,
In the step of etching the second conductive film, when the ferroelectric film is exposed beside the upper electrode, the etching atmosphere is an atmosphere containing oxygen gas and not containing halogen. method of manufacturing a semi-conductor device shall be the. Forming an insulating film above the semiconductor substrate;
Forming a first conductive film, a ferroelectric film, and a second conductive film in this order on the insulating film;
Etching the second conductive film to form an upper electrode of a ferroelectric capacitor;
Patterning the ferroelectric film to form a capacitor dielectric film of the ferroelectric capacitor;
Etching the first conductive film to form a lower electrode of the ferroelectric capacitor;
The step of etching the second conductive film includes:
A first step of etching the second conductive film to an intermediate depth with an etching gas containing oxygen gas and not containing halogen;
After the first step , a flow rate ratio of the oxygen gas in the etching gas is set higher than a flow rate ratio of the oxygen gas in the first step , and a second portion of the second conductive film is etched. It possesses a step,
In the step of etching the second conductive film, when the ferroelectric film is exposed beside the upper electrode, the etching atmosphere is an atmosphere containing oxygen gas and not containing halogen. method of manufacturing a semi-conductor device shall be the. In the step of etching the second conductive film, a plurality of the upper electrodes are formed at intervals,
3. The method of manufacturing a semiconductor device according to claim 1 , wherein in the step of etching the ferroelectric film, the capacitor dielectric film is formed in a stripe shape common to each of the plurality of upper electrodes. Method.

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