JP5541350B2 - Semiconductor module - Google Patents

Description

  The present invention relates to a semiconductor module formed with high accuracy and high reliability. The semiconductor module of the present invention is used for a high-frequency front end portion of an ultra-small communication function module that integrates information communication functions and storage functions of information communication equipment, particularly personal computers, cellular phones, video equipment, audio equipment, etc. Is preferred.

In recent years, with the digitization of data such as music, sound, and images, it has become possible to easily handle data on personal computers and mobile computers.
In addition, a band is compressed by a data codec such as an image or sound, and an environment in which such data can be easily distributed by digital communication or digital broadcasting has been established.
In communication of data of these contents, not only outdoor transmission / reception by a mobile phone or a mobile terminal has become possible, but also various wireless networks have been constructed in the home.

Using the wireless network as described above, it is possible to seamlessly exchange various data, access the Internet, and transmit / receive data on the Internet at home and outdoors.
On the other hand, with the spread of digital television, an environment in which terrestrial digital broadcasting can be easily received by a portable terminal or the like not only at home but also outdoors is being prepared. In order to realize the miniaturization of a portable terminal that receives such terrestrial digital broadcasts, one key technology is how to realize the communication function as described above in a small, cheap and simple manner. Yes.

  In addition, the configuration of a high frequency front end for communication includes large functional parts such as a frequency filter, a local oscillator (VCO), and a SAW filter, and is an inductor unique to a high frequency analog circuit such as a matching circuit and a bias circuit. Since the number of passive components such as L, capacitor C, and resistor R is very large, there is a problem in miniaturization.

Conventionally, the communication functions described above have been reduced in size, cost, and power consumption due to higher integration.
In recent years, with the miniaturization of design rules, the scale of systems that can be integrated on a chip has become very large.
Therefore, in order to achieve higher integration, there is a demand for simultaneously integrating a plurality of different functional circuits such as digital signal processing circuits and high-speed analog circuits such as RF.
A large-scale single chip called SOC (system on chip) is being promoted.

However, if the above-described plurality of different functional circuits are made into one chip, the wafer manufacturing process becomes very complicated, and it becomes difficult to optimize the manufacturing process for each function such as logic / analog. .
Therefore, it is considered that systems that require SOC are limited to systems that pursue very high performance and can be mass-produced.

In order to satisfy the above-described conditions, a technique called SIP (system in package) in which a plurality of semiconductor integrated circuit chips or different kinds of chips are accommodated in one package has been spreading. With this method, it is possible to increase the number of functions by mixing with chips made by other companies, mixing with chips of different types, and the like.
Specifically, for example, a technique of performing rewiring such as connecting chips after embedding a plurality of chips in a wafer has been proposed (see, for example, Patent Document 1).

Japanese Patent No. 3802936

However, in the technique described in Patent Document 1, since the wafer is formed by a mold sealing material made of a resin material after the chips are arranged, the dimensional shrinkage of the wafer due to the curing shrinkage of the resin when the wafer is formed. Is likely to occur.
Therefore, when forming the rewiring, there is a possibility that a dimensional deviation occurs in the peripheral portion of the wafer or the like.

In addition, the module described in Patent Document 1 has a configuration in which a multilayer wiring layer is formed on a sealing material that seals a chip. Therefore, from the mismatch of curing shrinkage and thermal expansion coefficient when forming a resin material. The warpage of the completed wafer is expected to increase.
When the warpage of the wafer increases in this way, the module remains warped.

  In order to solve the above-described problems, in the present invention, a plurality of different devices can be integrated, passive components such as inductors and capacitors can be incorporated, and a semiconductor module that can be reduced in size and thickness. The present invention provides a highly reliable semiconductor module that can be manufactured with high yield.

The semiconductor module of the present invention includes a multilayer wiring layer formed by forming a plurality of wiring layers in an insulating layer, a semiconductor chip provided on at least one main surface of the multilayer wiring layer, and a seal that covers the semiconductor chip. In the sealing material on the at least one main surface side of the multilayer wiring layer, the sealing material made of the same material is provided on both main surfaces of the multilayer wiring layer and the side surfaces of the multilayer wiring layer. A sealing material is formed on both main surfaces of the multilayer wiring layer, wherein a conductor layer is formed through the sealing material to electrically connect the wiring layer of the multilayer wiring layer and the outside of the sealing material. In addition, a protective film is formed on each surface of the semiconductor chip and the chip member .

  According to the configuration of the semiconductor module of the present invention described above, since the sealing material is provided on both the main surface and the side surface of the multilayer wiring layer, the sealing material that covers the chip member with the multilayer wiring layer interposed therebetween is mainly used. Since it is formed on the surface and the side surface, it is possible to reduce the warpage caused by the difference in thermal expansion coefficient between the multilayer wiring layer and the sealing material.

According to the present invention described above, the warpage of the semiconductor module can be reduced, so that a plurality of different types of devices can be integrated, passive components such as inductors and capacitors can be incorporated, and the size and thickness can be reduced. Therefore, it is possible to manufacture a semiconductor module capable of achieving high yield.
Therefore, according to the present invention, a highly reliable semiconductor module can be realized.

It is a schematic block diagram (sectional drawing) of the high frequency module of one embodiment of this invention. It is a schematic sectional drawing of the form which deform | transformed the high frequency module of FIG. It is a schematic block diagram (sectional drawing) of the high frequency module of other embodiment of this invention. FIGS. 4A and 4B are manufacturing process diagrams illustrating a method for manufacturing the high-frequency module of FIG. 3. FIGS. C, D It is a manufacturing-process figure which shows the manufacturing method of the high frequency module of FIG. E, F It is a manufacturing-process figure which shows the manufacturing method of the high frequency module of FIG. G and H are manufacturing process diagrams showing a manufacturing method of the high-frequency module of FIG. I and J are manufacturing process diagrams showing a method of manufacturing the high-frequency module of FIG. K and L are manufacturing process diagrams showing a method of manufacturing the high-frequency module of FIG. M and N are manufacturing process diagrams showing a method of manufacturing the high-frequency module of FIG. O and P are manufacturing process diagrams showing a manufacturing method of the high-frequency module of FIG. 3. It is a manufacturing process figure which shows the manufacturing method of the high frequency module of FIG. It is a schematic sectional drawing of the three-dimensional module using the structure of the high frequency module of FIG. It is a manufacturing process figure which shows the manufacturing method of the three-dimensional module of FIG.

As an embodiment of the semiconductor module of the present invention, a schematic configuration diagram (cross-sectional view) of a high-frequency module is shown in FIG.
The semiconductor module 10 basically includes chip sealing layers 24 and 25 made of a sealing material 15 on both sides with a multilayer wiring layer 23 interposed therebetween.

The multilayer wiring layer 23 includes a plurality of wiring layers 13 and an insulating layer 14 that fills the interlayer.
The wiring layer 13 is made of, for example, Cu having good conductivity.
The insulating layer 14 is made of, for example, a resin material such as polyimide resin or epoxy resin.
The wiring layers 13 of the multilayer wiring layer 23 are electrically connected by a conductor layer embedded in the insulating layer 14. Here, the conductor layer is a layer made of the same conductive material as the wiring layer 13. The semiconductor chip 11 and the wiring layer 13 are also electrically connected by a similar conductor layer.

  Here, the lower chip sealing layer 24 side is defined as A surface, and the upper chip sealing layer 25 side is defined as B surface.

The A-side chip sealing layer 24 has a configuration in which the semiconductor chip 11 and the magnetic body 12 </ b> A are embedded in the sealing material 15, and the protective film 18 is formed on the surface of the sealing material 15.
The chip sealing layer 25 on the B surface has a configuration in which the magnetic body 12 </ b> B is embedded in the sealing material 15, and the protective film 18 is formed on the surface of the sealing material 15.
The semiconductor chip 11 is connected to the multilayer wiring layer 23.
The two magnetic bodies 12A and 12B are arranged so as to sandwich the multilayer wiring layer 23 therebetween.

  In order to operate at a high frequency, for example, a semiconductor chip for RF (Radio Frequency) manufactured by CMOS technology is used as the semiconductor chip 11.

The sealing material 15 is preferably a material that can be cured from a liquid material in order to seal the semiconductor chip 11. For example, a material such as a resin containing filler particles can be used. In order to secure the strength of the completed module, a resin whose strength is improved by the inclusion of filler particles in this way is desirable.
Alternatively, an inorganic material such as a ceramic material can be used for the sealing material 15.

  Examples of magnetic materials used for the magnetic bodies 12A and 12B include magnetic materials such as Ni—Zn-based materials and Ni—Zn—Cu-based materials.

A spiral inductor 21A is formed by the two wiring layers 13 in the multilayer wiring layer 23 where the two magnetic bodies 12A and 12B are disposed.
Further, on the left side of the figure, a spiral inductor 21B is formed by a single wiring layer 13.

Further, on the right side of the figure, a high dielectric film 17 is sandwiched between two wiring layers 13 to form an MIM type capacitor 22.
It is also possible to form a wiring interlayer type capacitor using a dielectric film between wirings instead of the high dielectric film 17.

A conductive post 16 made of a conductor layer is formed on the sealing material 15 on the B surface, and the conductive post 16 penetrates the sealing material 15 and is connected to the wiring layer 13 of the multilayer wiring layer 23.
Module bumps 19 that are terminals of the high-frequency module 10 are formed on the conductive posts 16. That is, the conductive post 16 electrically connects the wiring layer 13 of the multilayer wiring layer 23 and the module bump 19.
With this module bump 19, the high-frequency module 10 can be mounted on a printed circuit board or the like.
The semiconductor chip 11 can be electrically connected to the outside of the high-frequency module 10 via the wiring layer 13 of the multilayer wiring layer 23, the conductive post 16, and the module bump 19.

The conductive post 16 is formed of a conductive material such as a Cu material, for example. Moreover, you may form the conduction | electrical_connection post 16 from the electrically conductive paste containing a metal particle and resin.
For the module bump 19, for example, a metal material that can be mounted on a mother substrate, such as a solder bump or an Au bump, can be used.

The protective film 18 has a purpose of preventing the surface of the semiconductor chip 11 from being exposed to the outside of the high-frequency module 10 and has a role of improving the reliability of the high-frequency module 10.
Further, the B-side module bump 19 side also has a role of protection in solder mounting when the high-frequency module 10 is mounted on the substrate by using a material such as solder resist for the protective film 18, for example.

  It is also possible to omit the protective film 18 and form the chip sealing layer only with the sealing material 15.

  According to the configuration of the high-frequency module 10 of the above-described embodiment, the chip sealing layers 24 and 25 made of the sealing material 15 are provided on both main surfaces of the multilayer wiring layer 23, respectively. Even if there is a difference in thermal expansion coefficient between the 25 sealing materials 15 and the multilayer wiring layer 23, the warpage of the module 10 can be suppressed.

Further, there is no member (silicon substrate or the like) that becomes a rigid substrate, and it is possible to use a relatively soft material by using a resin material for the sealing material 15 or the insulating layer 14 between the multilayer wiring layers 23. is there.
Therefore, for example, when the high frequency module 10 is mounted on a printed circuit board, since the printed circuit board and the high frequency module 10 are organic materials and are similar materials, there is not much difference in thermal expansion coefficient. Thereby, for example, the mounting reliability is remarkably improved as compared with the case of mounting a silicon chip or the like.

Further, the semiconductor chip 11 and the wiring layer 13 of the multilayer wiring layer 23 are electrically connected by a conductor layer embedded in the insulating layer 14. Thereby, it is not necessary to solder the terminals of the semiconductor chip 11.
Since the high-frequency module 10 is electrically connected to the outside by the module bump 19, it is not necessary to solder this connecting portion, and a highly reliable connection can be performed.

Further, in the high frequency module 10 of the above-described embodiment, the spiral inductor 21A is formed in the multilayer wiring layer 23, and the chip 21 is sandwiched between the chip sealing layers 24 and 25 on both sides of the multilayer wiring layer 23. Chips of magnetic bodies 12A and 12B are arranged. Thereby, the inductance of the inductor 21A can be increased by the closed magnetic circuit effect of the magnetic bodies 12A and 12B.
Therefore, it is possible to increase the inductance with the same size as the conventional one, and to realize the same inductance as the conventional one with a smaller inductor.

The A-side chip sealing layer 24 and the B-side chip sealing layer 25 are configured to have substantially the same thickness, and it is desirable that the sealing materials 15 of the respective sealing layers 24 and 25 are made of the same material. .
Thus, by making the sealing material 15 of both surfaces into the same thickness and the same material, the high frequency module 10 makes the expansion-contraction by a thermal expansion coefficient difference equal up and down, and the curvature at the time of manufacture and use is as much as possible. The configuration is reduced.

In the high-frequency module 10 shown in FIG. 1, the semiconductor chip 11 is disposed only on the A surface, but it is possible to dispose the semiconductor chip also on the B surface, whereby a plurality of semiconductor chips are three-dimensionally arranged. It is also possible to configure the arranged module.
Further, in the high-frequency module 10 shown in FIG. 1, the magnetic bodies 12A and 12B are arranged on the A plane and the B plane, but a configuration in which the magnetic bodies are arranged only on either side is also possible.

In the high-frequency module 10 shown in FIG. 1, the semiconductor chip 11 and the magnetic bodies 12A and 12B are formed on the same surface as the surface of the sealing material 15, and the back surfaces of these chips 11, 12A and 12B are ground. ing.
On the other hand, you may form a sealing material so that the whole chip | tip of a semiconductor chip and a magnetic body may be covered.

Further, the high frequency module 10 shown in FIG. 1 is modified, and as shown in FIG. 2, a conductive post 16 is provided also on the chip sealing layer 24 on the A side, and both the A side and B side chip seals are provided. It is also possible to form the conductive posts 16 on the stop layers 24 and 25.
This makes it possible to form a three-dimensional module in which other modules are stacked in the thickness direction and electrically connected to the other modules.
For example, a digital processing circuit unit such as a baseband processing circuit can be manufactured as a separate module, and this separate module can be stacked with the high frequency module shown in FIG. 2 to form a three-dimensional module. It is.

  In this configuration, since the wiring layer 13 of the multilayer wiring layer 23 and the outside of the high-frequency module 10 are connected by the conductive post 16 penetrating the sealing material 15, for example, a rigid substrate such as a glass substrate or a quartz substrate is used. It can be easily laminated with another module without opening a through hole.

FIG. 3 shows a schematic configuration diagram (cross-sectional view) of a high-frequency module as another embodiment of the semiconductor module of the present invention.
The basic structure of the high-frequency module 20 is the same as that of the high-frequency module 10 of the previous embodiment shown in FIG.

However, the configuration described below is different from the high-frequency module 10 of the previous embodiment.
In the semiconductor module 20 of the present embodiment, an inductor 21A sandwiched between two magnetic bodies 12A and 12B is formed by three wiring layers 13.
Further, the number of wiring layers 13 of the multilayer wiring layer 23 is larger than that of the high-frequency module 10 of FIG.
The insulating layer 14 of the multilayer wiring layer 23 is formed thick on the lower side except for the semiconductor chip 11 and the magnetic body 12A. In other words, the insulating layer 24 is recessed in the semiconductor chip 11 and the magnetic body 12A.
The MIM type capacitor shown in FIG. 1 is not formed in the multilayer wiring layer 23.
The upper magnetic body 12B is bonded to the multilayer wiring layer 23 with an adhesive 26.

  Other configurations are the same as those of the high-frequency module 10 of FIG.

  According to the configuration of the high-frequency module 20 of the above-described embodiment, the chip sealing layer 24 made of the sealing material 15 on each of the main surfaces of the multilayer wiring layer 23, as in the high-frequency module 10 of the previous embodiment. , 25 can suppress warping of the high-frequency module 20 even if there is a difference in thermal expansion coefficient between the chip sealing layers 24, 25 and the multilayer wiring layer 23.

Further, in the high-frequency module 20 of the above-described embodiment, the spiral inductor 21A is formed in the multilayer wiring layer 23, and the chip 21 is sandwiched between the chip sealing layers 24 and 25 on both sides of the multilayer wiring layer 23. Chips of magnetic bodies 12A and 12B are arranged. Thereby, the inductance of the inductor 21A can be increased by the closed magnetic circuit effect of the magnetic bodies 12A and 12B.
Therefore, it is possible to increase the inductance with the same size as the conventional one, and to realize the same inductance as the conventional one with a smaller inductor.

Next, the manufacturing method of the high frequency module 20 of FIG. 3 is demonstrated with reference to drawings.
First, the first support substrate 31 shown in FIG. 4A is prepared, and each component is formed on the first support substrate 31. A release layer 32 for peeling the first support substrate 31 later is formed on the surface of the first support substrate 31.

The peeling layer 32 is formed of an appropriate material in accordance with a peeling method when peeling the first support substrate 31 later.
As a method for peeling the support substrate 31 later, for example, a peeling method by light irradiation, a peeling method using a metal film for the peeling layer and dissolving the peeling layer using an acid solution or an alkaline solution, and a resin material for the peeling layer The peeling method etc. which melt | dissolve a peeling layer with an organic solvent etc. using are used.

Hereinafter, a manufacturing process will be described by employing a peeling method by light irradiation.
In this case, the first support substrate 31 is made of a material that transmits light to be irradiated, such as glass or quartz material.
In addition, if the release layer 32 is irradiated with, for example, ultraviolet light, almost all resins such as an epoxy resin and a polyimide resin can be used.

Next, as shown in FIG. 4B, a guide layer 33 for guiding a semiconductor chip to be mounted is patterned.
The material of the guide layer 33 is not particularly limited. For example, the same material as that of the insulating layer 14 of the multilayer wiring layer 23 can be used.

The guide layer 33 is not particularly required, and the chip may be mounted using another alignment method.
For example, when the alignment marker is formed on the support substrate and the chip member is mounted, a method of arranging and fixing the chip member on the alignment marker can be considered.

  Next, as shown in FIG. 5C, the semiconductor chip 11 and the magnetic body 12A are fixed on the first support substrate 31, and these chip members 11 and 12A are mounted. The semiconductor chip 11 is mounted by bonding with an adhesive 34 with the surface (front surface) on which terminals and the like are formed facing down.

  Instead of adhering with the adhesive 34 formed on the surface of the semiconductor chip 11, an ultraviolet curable resin or wax may be applied and then cured by irradiating with ultraviolet rays from the first support substrate 31 side. In this case, after curing, the uncured excess resin / wax is removed.

  Next, as shown in FIG. 5D, the semiconductor chip 11 and the magnetic body 12A are covered, the sealing material 15 is formed on the entire first support substrate 31, and the semiconductor chip 11 and the magnetic body 12A are sealed.

Further, if necessary, the sealing material 15 may be ground and thinned together with the semiconductor chip 11 and the magnetic body 12A as shown in FIG. 6E.
By this grinding step, the A-side chip sealing layer 24 can be thinned to control the thickness.

Next, as shown in FIG. 6F, the protective film 18 is formed on the upper surface of the sealing material 15, and then the second support substrate 35 is bonded. At this time, a release layer 36 for peeling the second support substrate 35 later is formed on the second support substrate 35.
In addition, the 2nd support substrate 35 is bonded together by giving the protective film 18 the adhesive effect. For example, an adhesive made of a resin material is used for the protective film 18.

Next, as shown in FIG. 7G, the first support substrate 31 serving as the base is peeled off by the peeling method described above. When the peeling method by light irradiation is adopted, for example, ultraviolet light is irradiated through the first support substrate 31 from the lower side in the figure.
And if the peeling layer 32 has adhered, the peeling layer 32 will be removed and the adhesive agent which adhered to the surface of chip members, such as the semiconductor chip 11 and the magnetic body 12A, will be removed. Thereby, the substrate on which the surfaces of the semiconductor chip 11 and the magnetic body 12A are exposed is completed.

Next, as shown in FIG. 7H, a wiring process is performed in which an interlayer insulating layer 14 and a wiring layer 13 are formed above the semiconductor chip 11 and the magnetic body 12 </ b> A whose surfaces are exposed by turning upside down. FIG. 7H shows a state in which the first wiring layer 13 and the surrounding insulating layer 14 are formed. The pads of the semiconductor chip 11 are connected to the first wiring layer 13 by a conductor layer embedded in the insulating layer 14.
Hereinafter, the guide layer 33 is included in the insulating layer 14 for display.

  Subsequently, the wiring process is similarly repeated to sequentially form the wiring layer 13 and the insulating layer 14 of each layer, and as shown in FIG. 8I, the multilayer wiring layer 23 is formed. Note that the magnetic body 12A and the wiring layer 13 are separated via an interlayer insulating layer 14 to avoid resistance loss due to eddy current.

  The conductor layer connecting the wiring layers 13 of the multilayer wiring layer 23 (that is, between the upper and lower wiring layers 13) may be formed separately from the wiring layer 13, or the conductor layer. And the upper wiring layer 13 may be formed simultaneously. Examples of the method of forming simultaneously include a method of forming a conductor layer by opening a connection hole (opening) in the insulating layer and then covering the insulating layer so as to fill the inside of the hole.

Next, as illustrated in FIG. 8J, the conductive posts 16 are formed on the multilayer wiring layer 23 so as to be connected to the uppermost wiring layer 13 of the multilayer wiring layer 23.
The conductive post 16 may be formed by a method such as Cu plating, or may be formed using a conductive paste or the like.
Then, on the upper side (B surface) of the multilayer wiring layer 23, a chip component such as the magnetic body 12B is mounted as another chip member. The chip of the magnetic body 12 </ b> B is bonded to the multilayer wiring layer 23 with the adhesive 26.

  If necessary, in addition to the magnetic body 12B, a semiconductor chip may be mounted face-down while ensuring connection with the multilayer wiring layer 23 using a flip chip mounting method or the like.

Next, as shown in FIG. 9K, a half cut is made from the multilayer wiring layer 23 to the middle of the lower sealing material 15 by a method similar to dicing. In the figure, 39 indicates a cutting material for dicing.
By performing this step, the side surface of the multilayer wiring layer 23 can be protected later by covering with the sealing material 15, and the high-frequency module 20 itself completed by full-cut dicing is sealed without exposing the wiring layer 13. Since it is protected by the material 15, the reliability is improved.
This step may be omitted if not necessary.

Next, as shown in FIG. 9L, a sealing material 15 is formed so as to cover the entire surface, and the entire B surface is sealed so as to cover the chip member on the B surface such as the magnetic body 12 </ b> B and the conduction posts 16.
As a result, the side and top surfaces of the multilayer wiring layer 23, the B-side chip member such as the magnetic body 12 </ b> B, and the conductive posts 16 are covered with the sealing material 15.

Then, by grinding the sealing material 15 on the surface of the B surface, the surface of the conduction post 16 is exposed so that a module terminal can be formed. Thereby, the chip sealing layer 24 on the B surface can be thinned to control the thickness.
Further, after the protective film 18 is formed, the protective film 18 is patterned so as to open the surface of the conductive post 16 as shown in FIG. 10M.

Next, as shown in FIG. 10N, module bumps 19 are formed on the conductive posts 16.
Then, as shown in FIG. 11O, the second support substrate 35 that has been supported in the steps so far is peeled by the same method as in the peeling step of the first support substrate 31 described above.

Subsequently, as shown in FIG. 11P, the second support substrate 35 is removed, and the wafer is separated into pieces by a dicing process.
Thus, the high frequency module 20 is completed as shown in FIG.

  Since the high-frequency module 20 according to the present embodiment manufactured by these steps is formed with a substantially symmetric structure in the thickness direction, the curing shrinkage and thermal expansion coefficient of each material of the sealing material 15 and the insulating layer 14 are as follows. The influence of the warp due to the difference between them can be considerably reduced, and a good module state can be secured.

  In addition, the thickness of the module can be sufficiently reduced by grinding the sealing material 15 together with the chip members 11, 12A, and 12B on both the A surface and the B surface. Further, by controlling the thicknesses of the chip sealing layers 24 and 25 on the A and B surfaces, it is possible to reduce the warpage of the module as much as possible.

  In each of the above-described embodiments, the configuration in which only the semiconductor chip 11 and the magnetic bodies 12A and 12B are sealed with the sealing material 15 is shown. However, if necessary, a commercially available chip component such as a passive element may be mounted. Is also possible. At this time, various chip components are mounted on the substrate using an adhesive or the like. Any adhesive may be used as long as it can fix the chip member.

  Further, for example, by using a magnetic powder-containing resin as the material of the sealing material, an effect equivalent to that of the magnetic body can be exhibited. Thereby, it is also possible to omit the magnetic body and cause the sealing material itself to play the role of the magnetic body.

By the way, as shown in a schematic cross-sectional view in FIG. 13, by using the configuration of the high-frequency module 10 shown in FIG. It is also possible to form a three-dimensional module 40 that is three-dimensionally integrated while ensuring upper and lower connections.
The three-dimensional module 40 shown in FIG. 13 has a configuration in which the protective film 18 and the module bumps 19 are removed from the high-frequency module 10 shown in FIG. 1, and another wiring layer 55 and the semiconductor chip 41 are sealed with a sealing material 42. In this configuration, module wafers made of the chip sealing layer 45 are stacked.
The chip sealing layer 45 is formed by sealing a semiconductor chip 41 and a wiring layer 43 with a sealing material 42. Further, conductive posts 44 penetrating the chip sealing layer 45 are formed in the vicinity of the left and right ends of the chip sealing layer 45 in the drawing.
Module bumps 46 are formed on the conductive posts 44 of the chip sealing layer 45.
The other wiring layer 55 includes an insulating layer 51, one wiring layer 53, and an adhesive layer 52 for bonding to the chip sealing layer 25 of the high-frequency module 10. Also, a conductor layer 54 for electrically connecting the wiring layer 53 to the conductive post 16 of the high-frequency module 10 and a wiring layer 53 for electrically connecting the wiring layer 43 of the chip sealing layer 45 and the semiconductor chip 41. The conductor layer is formed.

As shown in FIG. 14, the three-dimensional module 40 shown in FIG. 13 includes a module wafer in which each component of the high-frequency module 10 is formed on a support substrate 61, and a chip sealing layer 45 and other wiring layers on the support substrate 62. The module wafer formed with 55 can be used.
From the state shown in FIG. 14, after bonding two module wafers with the adhesive layer 52, the support substrates 61 and 62 are peeled off, and a module bump 46 is formed on the conductive post 44 of the chip sealing layer 45. Thus, the three-dimensional module 40 shown in FIG. 13 can be manufactured.

  The three-dimensional module 40 shown in FIG. 13 is obtained by laminating two module wafers, but it is also easy to multistage by laminating another wafer.

  By laminating a plurality of module wafers in this way, a plurality of different types of chip members can be arranged three-dimensionally to form a three-dimensional module, and an emergency component with built-in passive components such as inductors and capacitors A compact and thin module can be configured.

  In each of the above-described embodiments, the side surface of the multilayer wiring layer 23 is sealed with the sealing material 15, but in the present invention, a configuration in which the side surface of the multilayer wiring layer is not sealed with the sealing material is also possible. In that case, the process illustrated in FIG. 9K may be omitted and the other processes may be performed in the same manner.

In addition, if a terminal is formed on the side surface of the multilayer wiring layer and this terminal is made conductive to the wiring layer in the multilayer wiring layer, a conductive post (conductor layer) penetrating the upper or lower sealing material is not formed. It is possible to electrically connect the semiconductor module and the outside.
That is, in the semiconductor module of the present invention, the conductive post is not essential.
The configuration in which the conductive posts are formed in the sealing material and connected to the outside has the advantages of better stability and higher connection reliability.

In each of the above-described embodiments, the chip members (semiconductor chip 11 and magnetic bodies 12A and 12B) are provided in the upper and lower sealing materials 15 of the multilayer wiring layer 23. However, in the present invention, one of the upper and lower ones is provided. It is also possible to provide a configuration in which a chip member is provided only in the sealing material and no chip member is provided in the other sealing material. Even with this configuration, the effect of preventing warpage can be obtained.
However, if the chip member is not provided in the sealing material, the volume of the module is larger than the volume of the chip member as compared with the conventional configuration in which the sealing material is provided only on one side. It is preferable to provide chip members on both the upper and lower sealing materials.

  In each of the above-described embodiments, the thickness of the upper and lower sealing materials 15 of the multilayer wiring layer 23 is substantially the same. However, in the present invention, the thickness of the upper and lower sealing materials may be different to some extent. It is. Thus, even in a configuration in which the thickness of the upper and lower sealing materials differs to some extent, the effect of reducing warpage can be reduced compared to the conventional configuration in which the sealing material is provided only on one main surface of the multilayer wiring layer. can get.

  As the passive element provided in the multilayer wiring layer, a resistor (resistive element) made of a material having a sufficiently higher resistance than the wiring layer can be considered in addition to the inductor and the capacitor shown in FIG.

  The present invention is not limited to the case where the high-frequency module is configured as in each of the above-described embodiments, and the semiconductor chip is not limited to RF, and a semiconductor chip using an arbitrary configuration is used. Modules can be configured.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

10, 20 High-frequency module, 11, 41 Semiconductor chip, 12A, 12B Magnetic body, 13, 43, 53 Wiring layer, 14, 51 Insulating layer, 15, 42 Sealing material, 16, 44 Conducting post, 17 High dielectric film , 18 Protective film, 19, 46 Module bump, 21A, 21B Inductor, 22 Capacitor, 23 Multilayer wiring layer, 24, 25, 45 Chip sealing layer, 26, 34 Adhesive, 31 First support substrate, 32, 36 Release layer, 33 guide layer, 35 second support substrate, 40 three-dimensional module, 52 adhesive layer, 55 other wiring layers, 61, 62 support substrate

Claims (6)

A multilayer wiring layer formed by forming a plurality of wiring layers in an insulating layer;
A semiconductor chip provided on at least one main surface of the multilayer wiring layer;
Having a sealing material covering the semiconductor chip,
The sealing material of the same material is provided on both main surfaces of the multilayer wiring layer and the side surfaces of the multilayer wiring layer ,
An inductor is built in the multilayer wiring layer, a chip member made of a magnetic material is provided in the sealing material on both main surface sides of the multilayer wiring layer with the inductor interposed therebetween,
In the sealing material on at least one main surface side of the multilayer wiring layer, a conductor that penetrates the sealing material and electrically connects the wiring layer of the multilayer wiring layer and the outside of the sealing material A layer is formed,
The semiconductor module in which the protective film is formed in each surface of the said sealing material, the said semiconductor chip, and the said chip member which are in the both main surface sides of the said multilayer wiring layer . The semiconductor module according to claim 1, wherein the sealing material is a resin material or a ceramic material. The semiconductor module according to claim 1, wherein the sealing material is a resin material containing filler particles. The semiconductor module according to claim 1, wherein the sealing material is a resin material containing magnetic powder.   5. The semiconductor module according to claim 1, wherein in the multilayer wiring layer, the wiring layer is made of Cu wiring, and the insulating layer is made of a resin material. The semiconductor module according to claim 5 , wherein the insulating layer is a polyimide resin or an epoxy resin.

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