JP5532324B2 - Transmission device, reception device, transmission method, reception method, and program - Google Patents

Description

  The present invention relates to a transmission device, a reception device, a transmission method, a reception method, and a program.

  In recent years, the development of wireless communication technology such as mobile phones has been remarkable, and the demand for high-quality and large-capacity communication is increasing. In general, when communication is performed using radio, the communication quality varies greatly depending on the environment in which the terminal is used, such as fading and interference from other systems. As a technique for improving communication quality in such an environment, a system using a nested code that incorporates the concept of network coding has been proposed (see Non-Patent Document 1).

  Here, network coding is a technique for superimposing a certain information bit sequence and another information bit sequence by exclusive OR (XOR) and transmitting the superimposed bit sequence. In the described technology, the transmission device performs the same convolution coding after performing different convolutional coding on the sequence previously transmitted to the reception device and the sequence newly transmitted to the reception device, thereby transmitting the same sequence. Send multiple times. That is, a certain information bit sequence is encoded by the convolutional encoder 1, and the information bit sequence previously transmitted to the same receiving apparatus is encoded by the convolutional encoder 2 having a configuration different from that of the convolutional encoder 1, and these are encoded. Superimposed and transmitted by exclusive OR operation. Then, the receiving device that has received the signal transmitted from the transmitting device correctly obtains the information bit sequence from the received signal by performing decoding considering that the same sequence is transmitted a plurality of times. Thereby, the communication system can reduce errors due to the temporal diversity effect.

Takashi Hayashi, Koji Ishii, Shigeaki Ikugo, Kohei Hirata, Shinpei Fuji, Satoshi Kubota, “Characteristic Evaluation of Transmit Diversity Using Nested Codes”, IEICE Technical Report, RCS 2009-170, Dec. 2009.

  However, the technique described in Non-Patent Document 1 is designed using a convolutional code as an error correction code, and has a configuration in which one information bit sequence is encoded by one convolutional encoder. Therefore, it is not possible to obtain a gain by iterative decoding like a turbo code. On the other hand, when a turbo code in which element encoders are connected in parallel is applied to a communication system using network coding such as the nested code, there is a problem that the decoding process becomes complicated and the system becomes unrealistic. It was.

  The present invention has been made in view of the above points, and an object of the present invention is to apply a transmitter capable of iterative decoding in a communication system using network coding to obtain a gain by iterative decoding and reception. An apparatus, a transmission method, a reception method, and a program are provided.

(1) The present invention has been made to solve the above-described problems, and the transmission apparatus of the present invention encodes different information bit sequences using different codes, and converts the encoded bit sequences into different encoded bit sequences. A plurality of encoding units to be generated, an exclusive OR operation unit that superimposes encoded bit sequences generated by the plurality of encoding units by exclusive OR, and the superimposed encoded bit sequence is modulated. And transmitting at least one of the plurality of encoding units is encoded by a first stage encoder unit that encodes the information bit sequence and the first stage encoding unit And an interleaver for interleaving the bit sequence and a second-stage encoder unit for encoding the interleaved bit sequence.

(2) Moreover, the transmitting apparatus of this invention is the above-mentioned transmitting apparatus, Comprising: The encoding rates of these encoding parts are mutually equal, It is characterized by the above-mentioned.

(3) Moreover, the transmitting apparatus of this invention is the above-mentioned transmitting apparatus, Comprising: The sum total of the encoding rate in the encoding of each last stage of these encoding parts is 1 or less, It is characterized by the above-mentioned. .

(4) In addition, the transmission device of the present invention is any one of the above-described transmission devices, and at least one of the different information bit sequences can be decoded on the reception side independently of the transmission. It is transmitted to.

(5) Further, the transmission device of the present invention is the above-described transmission device, wherein the at least one information bit sequence is transmitted with the transmission by transmitting the at least one information bit sequence before the transmission. Is independently transmitted so that it can be decoded on the receiving side.

(6) Moreover, the transmitting apparatus of this invention is the above-mentioned transmitting apparatus, Comprising: The said 1st stage encoding part and a 2nd stage encoding part encode using a convolutional code, It is characterized by the above-mentioned.

(7) Moreover, the transmitting apparatus of this invention is the above-mentioned transmitting apparatus, Comprising: The said 2nd stage encoding part encodes using a recursive convolutional code, It is characterized by the above-mentioned.

(8) Moreover, the transmission device of the present invention is the above-described transmission device, and the plurality of encoding units include:
A first-stage encoder for encoding the information bit sequence; an interleaver for interleaving the bit sequence encoded by the first-stage encoder; and a second-stage code for encoding the interleaved bit sequence The first stage encoder unit included in the plurality of encoding units performs encoding using the same code, and the interleaver included in the plurality of encoding units is the same The second-stage encoder unit that interleaves with an interleave pattern and includes the plurality of encoding units performs encoding using different codes.

(9) In addition, the receiving device of the present invention is a transmitting device that encodes different information bit sequences using different codes, superimposes the encoded bit sequences by exclusive OR, and transmits the information bit sequences. And at least one of the different codes is a receiving apparatus that receives a signal transmitted by a transmitting apparatus in which first-stage encoding, interleaving, and second-stage encoding are connected, and Demodulating a signal received from a transmission device to generate a reception sequence, and based on a result of decoding in advance for at least one information bit sequence of information bit sequences superimposed in the transmission device, An inverting unit for inverting the sign of the received sequence, and a decoding unit for decoding the received sequence inverted by the inverting unit are provided.

(10) In addition, the receiving device of the present invention is a transmitting device that encodes different information bit sequences using different codes, superimposes the encoded bit sequences by exclusive OR, and transmits the information bit sequences. And at least one of the different codes is a receiving apparatus that receives a signal transmitted by a transmitting apparatus in which first-stage encoding, interleaving, and second-stage encoding are connected, and A demodulator that demodulates a signal received from the transmission device to generate a reception sequence, and a third decoding unit that performs decoding corresponding to the combination of encoding of the final stage of each of the different codes with respect to the reception sequence And a deinterleaver that performs deinterleaving corresponding to the interleaving on a decoding result corresponding to the second-stage encoding among the decoding results by the third decoding unit, and the deinterleaving A first decoding unit that performs decoding corresponding to the first-stage encoding on a decoding result deinterleaved by a receiver, and a decoding result obtained by the first decoding unit, similar to the interleaving. An interleaver that performs interleaving, and performs an iterative decoding process by the third decoding unit, the deinterleaver, the first decoding unit, and the interleaver.

(11) In addition, in the transmission method of the present invention, a first step of encoding a first information bit sequence to generate an encoded bit sequence, and a second information bit sequence of the first step A second step of generating a coded bit sequence by encoding using a code different from the above and an exclusive OR of the coded bit sequence generated in the first step and the second step. A third step of superimposing and a fourth step of modulating and transmitting the superimposed encoded bit sequence, and encoding by the first step and encoding by the second step At least one of the encodings includes a first stage encoding step for encoding the information bit sequence and an interleaving step for interleaving the bit sequence encoded by the first stage encoding step. And flop, characterized in that it comprises a step of the second stage encoding for encoding the interleaved bit sequence is determined in step interleaving.

(12) Further, the reception method of the present invention is a transmission apparatus that encodes different information bit sequences using different codes, superimposes the encoded bit sequences by exclusive OR, and transmits the information bit sequences. In this case, at least one of the different codes is a receiving method in a receiving apparatus that receives a signal transmitted from a transmitting apparatus in which first-stage encoding, interleaving, and second-stage encoding are connected. Then, a first step of demodulating a signal received from the transmission device to generate a reception sequence, and at least one information bit sequence of the information bit sequence superimposed in the transmission device is decoded in advance A second step of inverting the sign of the received sequence based on a result; and a third step of decoding the received sequence inverted by the second step. It is characterized in.

(13) Further, the reception method of the present invention is a transmission apparatus that encodes different information bit sequences using different codes, superimposes the encoded bit sequences by exclusive OR, and transmits the information bit sequences. In this case, at least one of the different codes is a receiving method in a receiving apparatus that receives a signal transmitted from a transmitting apparatus in which first-stage encoding, interleaving, and second-stage encoding are connected. Then, the first step of demodulating the signal received from the transmission device to generate a reception sequence and the decoding corresponding to the combination of the encoding of the final stage of each of the different codes are performed on the reception sequence A second step and a third step of performing deinterleaving corresponding to the interleaving on a decoding result corresponding to the second-stage encoding among the decoding results of the second step. And a decoding step deinterleaved by the third step, a fourth step for decoding corresponding to the first stage encoding, and a decoding result by the fourth step, A fifth step of performing interleaving similar to the interleaving, and performing iterative decoding processing by the second step, the third step, the fourth step, and the fifth step. .

(14) Further, the program of the present invention causes the computer to encode the first information bit sequence to generate an encoded bit sequence, and to add the second information bit sequence to the first information bit sequence. A second step of generating an encoded bit sequence by encoding using a code different from that of the step, and an exclusive OR of the encoded bit sequence generated in the first step and the second step And a fourth step of modulating and transmitting the superimposed encoded bit sequence, and encoding by the first step; At least one of the encodings in the second step was encoded by a first-stage encoding step for encoding the information bit sequence and the first-stage encoding step. A interleaving step of interleaving the Tsu preparative sequence, the steps of the second stage encoding for encoding the interleaved bit sequence is determined in step interleaving.

(15) Further, the program of the present invention is a transmitting apparatus that encodes different information bit sequences using different codes, superimposes the encoded bit sequences by exclusive OR, and transmits the encoded bit sequences. Then, at least one of the different codes is transmitted to the computer of the receiving apparatus that receives the signal transmitted by the transmitting apparatus in which the first stage encoding, interleaving, and second stage encoding are connected. A first step of demodulating a signal received from the device to generate a reception sequence, and based on a result of decoding in advance for at least one information bit sequence of the information bit sequence superimposed in the transmission device, Executing a second step of inverting the sign of the received sequence and a third step of decoding the received sequence inverted by the second step

(16) Further, the program of the present invention is a transmitting apparatus that encodes different information bit sequences using different codes, superimposes the encoded bit sequences by exclusive OR, and transmits the encoded bit sequences. Then, at least one of the different codes is transmitted to the computer of the receiving apparatus that receives the signal transmitted by the transmitting apparatus in which the first stage encoding, interleaving, and second stage encoding are connected. A first step of demodulating a signal received from the apparatus to generate a reception sequence; and a second step of performing decoding corresponding to a combination of encoding of the final stage of each of the different codes on the reception sequence And a third step of performing deinterleaving corresponding to the interleaving on the decoding result corresponding to the second-stage encoding among the decoding results of the second step. A fourth step of performing decoding corresponding to the first stage encoding on the decoding result deinterleaved in the third step, and the interleaving on the decoding result in the fourth step. And a fifth step for performing interleaving similar to the above, wherein the iterative decoding process according to the second step, the third step, the fourth step, and the fifth step is performed. Let it run.

  According to the present invention, a gain by iterative decoding can be obtained in a communication system using network coding.

1 is a conceptual diagram of a communication system 10 according to a first embodiment of the present invention. It is a schematic block diagram which shows the structure of the transmitter a1 which concerns on the same embodiment. It is a schematic block diagram which shows the structure of the 1st encoding part c111 which concerns on the same embodiment. It is a schematic block diagram which shows the structure of the 2nd encoding part c112 which concerns on the same embodiment. It is a figure showing an example of circuit composition of the 1st encoder c121 concerning the embodiment. It is a figure which shows an example of the circuit structure of the 2nd encoder c123 which concerns on the same embodiment. It is a figure which shows an example of the circuit structure of the 3rd encoder c126 which concerns on the same embodiment. It is a schematic block diagram which shows the structure of the transmitter a2 which concerns on the same embodiment. It is the schematic which shows an example of the superimposition bit sequence which concerns on the same embodiment. It is a schematic block diagram which shows the structure of the receiver b1 which concerns on the same embodiment. It is a schematic block diagram which shows the structure of the decoding part F1 which concerns on the same embodiment. It is a schematic block diagram which shows the structure of the 1st encoding part c111a which concerns on 2nd Embodiment of this invention. It is a schematic block diagram which shows the structure of the 2nd encoding part c112a which concerns on the same embodiment. It is a schematic block diagram which shows another structural example of the 1st encoding part c111a which concerns on the same embodiment. It is a schematic block diagram which shows another structural example of the 2nd encoding part c112a which concerns on the same embodiment. It is a schematic block diagram which shows the structure of the decoding part F2 which concerns on the same embodiment. It is a schematic block diagram which shows the structure of another decoding part F2-1 which concerns on the same embodiment. It is a schematic block diagram which shows the structure of the transmitter a3 which concerns on 3rd Embodiment of this invention. It is a schematic block diagram which shows the structure of the 1st encoding part c311 which concerns on the same embodiment. It is a schematic block diagram which shows the structure of the 2nd encoding part c312 which concerns on the embodiment. It is a schematic block diagram which shows the structure of the 3rd encoding part c313 which concerns on the same embodiment. It is the schematic which shows an example of the superimposition bit sequence which concerns on the same embodiment. It is a schematic block diagram which shows the structure of the decoding part F3 which concerns on the same embodiment.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a conceptual diagram of a communication system 10 according to the first embodiment of the present invention. The communication system 10 includes a transmission device a1 and a reception device b1. This figure shows that the transmission device a1 (base station device) transmits a signal and the reception device b1 (mobile station device) receives the signal. Here, the transmitting device a1 performs different encoding on a plurality of information bit sequences addressed to one receiving device b1, superimposes a plurality of encoded bit strings by applying network coding, and superimposes bits. A plurality of information bit sequences are transmitted simultaneously by transmitting the sequences. A bit sequence is a sequence of information represented by 0 and 1, and is also called a bit string. An information bit sequence is a sequence of information desired to be transmitted to a receiving device.

  Here, the information bit sequence transmitted simultaneously is a sequence previously transmitted to the receiving device b1 and a sequence newly transmitted to the receiving device b1. In addition, the receiving device b1 switches the decoding process of the sequence to be received next based on the decoding result of the previously transmitted information bit sequence. However, although FIG. 1 illustrates downlink transmission in which the transmission device a1 is a base station device and the reception device b1 is a mobile station device, the present invention is not limited to this, and the present invention refers to a mobile station device as a transmission device a1. The present invention is also applicable to uplink transmission using the receiving device b1 as a base station device. Further, the present invention can also be applied to a system such as an ad hoc mode of a wireless LAN system without distinction such as a base station device or a mobile station device.

<About the transmitter a1>
FIG. 2 is a schematic block diagram illustrating a configuration of the transmission device a1 according to the present embodiment. In this figure, the transmission device a1 includes a CRC (Cyclic Redundancy Check) unit a101, an information holding unit a102, a superposed bit generation unit E1, a modulation unit a103, a radio unit a104, and a transmission antenna a105. Is done. The superposition bit generation unit E1 includes a first encoding unit c111, a second encoding unit c112, and an exclusive OR operation unit c113.

The CRC unit a101 adds a CRC code for performing error detection to the input information bit sequence T, and outputs it to the first encoding unit c111 and the information holding unit a102. Hereinafter, a bit string obtained by adding a CRC code to the information bit sequence by the CRC unit a101 is referred to as an information bit string _dt . Here, t represents the time of transmission timing when the unit time for performing one transmission process (referred to as transmission unit time) is 1. That is, the information bit string _dt is an information bit string transmitted by one transmission process, and at least one CRC code is added by the CRC unit a101. Here, the CRC unit a101 outputs two identical signals to the first encoding unit c111 and the information holding unit a102, but the output from the CRC unit a101 is a single signal, and the CRC unit An information series duplicating unit that duplicates the output of a101 may be provided.

The information holding unit a102 holds the information bit sequence _dt input from the CRC unit a101, and outputs it to the second encoding unit c112 at the next transmission timing. That is, when the information bit sequence _{d t} at time t in the first encoding unit c111 is input, the information bit sequence _{d t-1} at time t-1 is input to the second encoding unit c112. In the present embodiment and each of the following embodiments, the information bit strings d _t and d _t−1 are not interleaved. However, after the information bit strings are interleaved, the first encoding unit c111, You may input into the encoding part c112.

The first encoding unit c111 and the second encoding unit c112 in the superimposition bit generation unit E1 respectively encode the information bit sequences input from the CRC unit a101 and the information holding unit a102, and code the encoded bit sequences. Is output to the exclusive logic operation unit c113. Here, when the output of the first encoding unit c111 is C _{1, t} , and the output of the second encoding unit c112 is C _{2, t−1} , the exclusive OR operation unit c113 calculates the following formula ( performs an exclusive OR operation such as 1), calculates the overlapped bit sequence S _t that is transmitted to the transmission unit time of the time t.

By such superposition processing by exclusive OR operation, the information bit sequence _dt-1 that has already been transmitted to the receiving device b1 and the information bit sequence _dt to be newly transmitted are superposed. The circuit configurations of the first encoding unit c111 and the second encoding unit c112 will be described later.

Modulation section a103 generates a modulated signal by modulating the superimposed bit sequence S _t that is input from the exclusive operation unit c113, and outputs it to the radio section a104.
The radio unit a104 performs D / A (Digital to Analog) conversion on the modulated signal input from the modulation unit a103, and then up-converts the modulated signal to a radio frequency and transmits the radio signal to the reception device b1 via the transmission antenna a105.
As described above, the transmission device a1 encodes the information bit sequence to be newly transmitted and the information bit sequence transmitted in advance one transmission unit time, and superimposes them by exclusive OR operation. Then send. In this embodiment, the information bit sequence one transmission unit time before is held and superimposed in advance, but the information bit sequence to be superimposed may be a past information bit sequence and is not limited to one transmission unit time before. .

<About the encoding unit>
Here, the configuration of the first encoding unit c111 and the second encoding unit c112 will be described. FIG. 3 is a schematic block diagram showing the configuration of the first encoding unit c111 according to this embodiment. In this figure, the first encoder c111 includes a first encoder c121 (first stage encoder), an interleaver c122, and a second encoder c123 (second stage encoder). FIG. 4 is a schematic block diagram showing the configuration of the second encoding unit c112 according to this embodiment. In this figure, the second encoding unit c112 includes a first encoder c124, an interleaver c125, and a third encoder c126. Each of the two encoding units in the present embodiment has a configuration in which two encoders are connected via an interleaver.

  In the present embodiment, as an example of these encoders, the second encoder c123 and the third encoder c126 are RSC (RSC; Recursive Systematic Convolutional) encoders, and the first encoder c121 and c124 are configured as convolutional encoders. In addition, although c123 and c126 in this embodiment are recursive systematic convolutional codes, they may be recursive encoders and may be non-systematic codes. Moreover, although c121 and 124 in this embodiment are convolutional encoders, they may be any encoder that can perform soft decision, and are not limited thereto. Then, the first encoders c121 and c124 that perform encoding as outer codes and the second and third encoders c123 and c126 that perform encoding as inner codes are connected by interleavers c122 and c125, respectively. An encoding unit having a configuration of a serially connected turbo encoder is used. In the present embodiment, the same first encoder and interleaver are used between the two encoding units, but the second encoder c123 and the third encoder c126 are configured by different encoders. The first encoder and the interleaver may be different between the two encoding units.

In the first encoding unit c111, first, the first encoder c121 performs convolutional encoding on the information bit string _dt and outputs the result. The interleaver c122 rearranges the code bit string convolutionally encoded by the first encoder c121 with a predetermined interleave pattern, and outputs the result to the second encoder c123. The second encoder c123 RSC-codes the code bit string output from the interleaver c122 and outputs a code bit string C1 _{, t} .
In the second encoding unit c112, first, the first encoder c124 performs convolutional encoding on the information bit string _dt-1 , and outputs the result. The interleaver c125 rearranges the code bit string convolutionally encoded by the first encoder c124 in a predetermined pattern and outputs the rearranged code bit string to the third encoder c126. The third encoder c126 performs RSC encoding on the code bit string output from the interleaver c122, and outputs a code bit string C2 _{, t-1} .

  FIG. 5 is a diagram illustrating an example of a circuit configuration of the first encoder c121 in FIG. The first encoder c124 has a circuit configuration similar to that of the first encoder c121, and thus description thereof is omitted. The first encoder c121 includes three shift registers D1, D2, D3, two adders c131, c132, a puncture unit c134, and a P / S (Parallel / Serial) converter c135. Consists of. However, the shift register is an element having a function of outputting 1 bit input before a temporary point every time 1 bit is newly input. An adder is an element that arithmetically adds all input bits and outputs the least significant bit (LSB) of the result. The input to the first encoder c121 is input to the shift register D1 and the adders c131 and c132. The output of the shift register D1 is input to the shift register D2 and the adder c132. The output of the shift register D2 is input to the shift register D3 and adders c131 and c132. The output of the shift register D3 is input to adders c131 and c132.

In the first encoder c121, when the generation polynomial of the input to the puncturing unit 134 is expressed in octal, it is expressed as [15 17] ₈ . As shown in FIG. 5, this is a notation in the case where the input / output of the encoder is represented by the numbers shown beside the shift register. That is, the adder c131 is represented by the bit input to the first encoder c121 represented by “1”, the bit output by the shift register D2 represented by “4”, and “8”. The bit output from the register D3 is added and the addition result is output. Further, the adder c132 is represented by a bit input to the first encoder c121 represented by “1”, a bit output by the shift register D2 represented by “2”, and “4”. The bit output from the shift register D2 is added to the bit output from the register D3 represented by “8”, and the addition result is output. For such outputs of the two adders, the puncturing unit c134 performs bit puncturing using a puncture pattern shown in Expression (2).

  However, in the expression (2), the first row shows a puncture pattern applied to the output of the adder c131, the second row shows a puncture pattern applied to the output of the adder c132, and the bit from the adder Is output (each time a bit is input to the first encoder c121), the column to be applied is changed. It also means that the bit corresponding to zero in the puncture pattern is punctured. That is, since the first column is “1, 1”, it indicates that the outputs of the adders c131 and c132 are output as they are. Since the next second column is “1, 0”, only the output of the adder c131 is output, and the output of the adder c132 is punctured (not output). Since the next third column is “0, 1”, it indicates that the output of the adder c131 is punctured and only the output of the adder c132 is output.

  Further, the P / S conversion unit c135 performs parallel-serial conversion on the bit string after puncturing output from the puncturing unit 134, and outputs the result to the interleaver c122 (interleaver c125 in the case of the first encoder c124). By such processing, the coding rate in the first encoders c121 and c124 becomes 3/4, that is, when 3 information bits are input, 4 code bits are output.

FIG. 6 is a diagram illustrating an example of a circuit configuration of the second encoder c123 in FIG. The second encoder c123 includes two shift registers D4 and D5, two adders c141 and c142, and a P / S conversion unit c143. The output of the interleaver c122, that is, the input to the second encoder c123 is input to the adder c141 and the P / S conversion unit c143. At this time, the bits output from the interleaver c122 are duplicated and input to the P / S conversion unit c143 as bits C13 _{, t} and bits C14 _{, t} . The output of the adder c141 is input to the shift register D4 and the adder c142. The output of the shift register D4 is input to the shift register D5 and the adder c141.

The output of the shift register D5 is input to the adder c141 and the adder c142. The output of the adder c142 is input to the P / S converter c143. The bits output from the adder c142 are duplicated and input to the P / S conversion unit c143 as bits C11 _{, t} and bits C12 _{, t} . P / S conversion unit c143 the bit _{C 11,} t is inputted in _{parallel, C 12, t,} in parallel-serial conversion to _{C 13, t, C 14,} t, the output as a sequence of code bits _{C 1, t} To do. Here, the second encoder c123 has a coding rate of 1/4 and a constraint length of 3. When a 1-bit information bit is input, the second encoder c123 outputs a 4-bit code bit. The second encoder c123 outputs both systematic bits and parity bits.

FIG. 7 is a diagram illustrating an example of a circuit configuration of the third encoder c126 in FIG. The third encoder c126 includes two shift registers D6 and D7, three adders c151, c152 and c153, and a P / S converter c154. The output of the interleaver c125, that is, the input to the third encoder c126 is input to the adder c151. The output of the adder c151 is input to the shift register D6 and the adder c152. The output of the shift register D6 is input to the shift register D7, the adder c151, the adder c152, and the adder c153. The output of the shift register D7 is input to the adder c151, the adder c153, and the P / S conversion unit c154. At this time, the output of the shift register D7 is input to the P / S conversion unit c143 as bits C23 _{, t-1} . The bits output from the adder c152 are duplicated and input to the P / S conversion unit c143 as bits C22 _{, t-1} and bits C24 _{, t-1} . The output of the adder c153 is input to the P / S conversion unit c143 as bits C21 _{, t-1} . The P / S conversion unit c154 converts the bits C _{21, t−1} , C _{22, t−1} , C _{23, t−1} , C _{24, and t−1} input in parallel into a serial bit and generates a sign bit. Output as C _{2, t} sequence. Here, the third encoder c126 has a coding rate of 1/4 and a constraint length of 3. When a 1-bit information bit is input, the third encoder c126 outputs a 4-bit code bit. However, the third encoder c126 outputs only parity bits. As described above, the second encoder c123 and the third encoder c126 in the present embodiment are configured to output the same bits redundantly (specifically, the bits C ₁₁ ,. _t and C _{12, t} , C _{13, t} and C _{14, t} , and bits C _{22, t-1} and C _{24, t-1 of} the third encoder c126 are overlapped). It is also possible to have an encoder configuration that does not overlap. The third encoder c126 is configured to output only parity bits, but may be configured to output systematic bits.

Here, similarly to the first encoder, the second and third encoders c123 and c126 are represented by [5/7 5/7 1 1] ₈ , [3 / a 7 6/7 1/7 _{6/7] 8.} However, the fractional denominator represents a recursive bit. As described above, the second encoder c123 and the third encoder c126 have the same encoding rate but perform encoding with different encoder configurations.

  The encoding rates in the first encoding unit c111 and the second encoding unit c112 including two encoders as described above are determined by considering the first encoder c111, Both of the second encoding units c112 are 3/16. Also, as shown in FIGS. 2 and 3, an exclusive OR operation unit c113 performs an exclusive OR operation on the output bit sequences of the second encoder c123 and the third encoder c126, Superimpose. In the present embodiment, two encoders that are directly before the exclusive OR operation unit c113 and directly generate a code bit sequence to be superimposed, that is, the final stage encoder (second encoder c123, second encoder c123, The sum of the coding rates of the third encoder c 126) is 2/4, which is 1 or less. This is because if the sum of the coding rates of the two encoders that directly generate the superimposed code bit sequence is greater than 1, the decoding result is not uniquely determined on the receiving side, and decoding may not be performed. is there.

  In this way, when serially connected turbo coding that enables iterative decoding is applied to a nested code that superimposes a plurality of different encoded bit sequences by exclusive OR, two serially connected turbo code units (first Two encoders (second encoder c123, third code) that directly generate a code bit sequence to be superimposed with the same coding rate of the first encoding unit c111 and the second encoding unit c112) It is important to design the sum of the coding rates of the unit c126) to be 1 or less. Here, by making the two coding rates of the serially connected turbo coding unit the same, the output from each coding unit has the same number of bits, so the two coded bit sequences are superimposed by exclusive OR. It becomes possible. Note that the configuration of each encoder is not limited to the configurations of FIGS. 5 to 7 as long as the coding rate limitation described here is satisfied, and other encoder configurations may be used.

The code bit C _{1, t} output from the second encoder c123 is composed of bits C _{11, t} , C _{12, t} , C _{13, t} , C _{14, t} , and the code output from the third encoder c126. Bits C _{2 and t−1} are made up of bits C _{21 and t−1} , C _{22 and t−1} , C _{23 and t−1} , and C _{24 and t−1} . Therefore, the exclusive OR operation unit c113 performs the exclusive OR operation of the bits C11 _{, t} and C21 _{, t-1} , and the exclusive OR operation of the bits C12 _{, t} and C22 _{, t-1} , respectively. , Bits C _{13, t} and C _{23, t-1} exclusive OR operation, bits C _{14, t} and C _{24, t-1} exclusive OR operation, and outputs these results. Then, the exclusive OR operation unit c113 performs parallel-serial conversion on the result of the exclusive OR operation and outputs the result. That is, as described above, this is expressed by the equation (1) when the output of the first encoding unit c111 is C _{1, t} and the output of the second encoding unit c112 is C _{2, t-1.} In other words, the superimposition bit generation unit E1 superimposes the bit string whose sequence in the original information bit sequence is around.

  With the configuration of the transmission apparatus as described above, it is possible to apply serially concatenated turbo coding that enables iterative decoding to a nested code, and a plurality of code bits each encoded by a single convolutional encoder. Compared with the conventional apparatus for superimposing, stronger encoding can be performed. In the present embodiment, the configuration of the transmission device is the configuration of the transmission device a1 illustrated in FIGS. 2 to 4, but may be the configuration of the transmission device a2 illustrated in FIG. 8 includes a CRC unit a101, a first encoding unit c121, an interleaver c122, a second encoding unit c123, an information holding unit a102, a third encoder c126, an exclusive OR operation unit c113, A modulation unit a103, a radio unit a104, and a transmission antenna a105 are included.

  As described above, the first encoder c121 and interleaver c122 in the first encoder c111 of the transmission device a1 and the first encoder c124 and interleaver c125 in the second encoder c112 have the same configuration. Therefore, the information holding unit a102 can be inserted after the first encoder 121, and the first encoder c124 and the interleaver c125 can be deleted. That is, in transmission apparatus a2 shown in FIG. 8, information bit sequence dt at time t is input to CRC unit a101, and the output of CRC unit a101 is input to first encoder c121. The interleaver c122 rearranges the bit sequence of the output of the first encoder c121. The interleaver c122 outputs the rearranged bit sequence to the second encoder c123 and the information holding unit a102.

  The information holding unit a102 holds the information bit sequence input from the interleaver c122, and outputs it to the third encoder c126 at the next transmission timing. That is, when the sequence after interleaving at time t is input to the second encoder c123, the sequence after interleaving at time t-1 is input to the third encoder c126. As described above, the first encoder c121 and interleaver c122 in the first encoder c111 in FIG. 2 and the first encoder c124 and interleaver c125 in the second encoder c112 are shared. It is good also as a structure.

FIG. 9 is a schematic diagram illustrating an example of a superimposed bit string according to the present embodiment. In this figure, the horizontal axis indicates time t. As shown in FIG. 9, in the present embodiment, a sequence to be newly transmitted and a sequence transmitted before one transmission unit time (for example, C _1,2 and C _2,1 ) are superimposed and transmitted. Is done. However, when the same information bit sequence is transmitted for the first time and when it is transmitted after one transmission unit time, encoding is performed by different encoders (for example, C _1,2 and C _2,2 ). In the first transmission unit (time t = 1), since there is no bit sequence transmitted before one transmission unit time, only C _1,1 (C _{1, t = 1} ) is transmitted.

<Receiver b1>
FIG. 10 is a schematic block diagram illustrating the configuration of the receiving device b1 according to the present embodiment. The reception device b1 includes a reception antenna b101, a radio unit b102, a demodulation LLR calculation unit b103, and a decoding unit F1. The reception antenna b101 receives a transmission signal from the transmission device a1. The radio unit b102 down-converts the signal received by the reception antenna b101 into a baseband band and performs A / D (Analog to Digital) conversion. The radio unit b102 outputs the A / D converted signal S ′ _t to a demodulation LLR (Log Likelihood Ratio) calculation unit b103.

The demodulation LLR calculation unit b103 demodulates the reception signal S ′ _t input from the radio unit b102, decomposes it into bits, and calculates an LLR indicating reliability for each bit based on the reception signal. Specifically, the demodulation LLR calculation unit b103 calculates the log likelihood ratio LLR of each bit by calculating the Euclidean distance between the received signal S ′ _t and 0, 1 (each modulation symbol). The LLR of the received signal S ′ _t (n) subjected to bit decomposition is expressed by the following equation (3).

Here, n represents the number of coded bits in one transmission unit (1 ≦ n ≦ N, N is the number of coded bits), and P (x) represents the probability of x. The demodulated LLR calculation unit b103 outputs the calculated LLR to the decoding unit F1.
The decoding unit F1 decodes the information bit sequence using the LLR of the received signal input from the demodulation LLR calculation unit b103, and outputs a decoded bit sequence T ′.

<About Decoding Unit F1>
Next, FIG. 11 is a schematic block diagram illustrating a configuration of the decoding unit F1 according to the present embodiment. The decoding unit F1 includes a first switching unit f101, an LLR inversion unit f102, a second MAP decoding unit f103, a deinterleaver f104, a first MAP decoding unit f105, an interleaver f106, a CRC detection unit f107, and a third MAP decoding. Unit f108, deinterleaver f109, first MAP decoding unit f110, interleaver f111, deinterleaver f109a, first MAP decoding unit f110a, interleaver f111a, second switching unit f112, second encoding unit f113, second The information holding unit f114.

  Based on the CRC detection result input from the first information holding unit f116, the first switching unit f101 converts the LLR input from the demodulation LLR calculation unit b103 into the LLR inversion unit f102 or a third MAP (Maximum A Postoriori). output to the decryption unit f108. Here, MAP decoding is a decoding method that estimates a sequence that maximizes the posterior probability of each transmission bit as a transmitted sequence when a received sequence is given. The CRC detection result input from the first information holding unit 1 is the CRC detection result of the signal received one reception unit time before (the reception unit time is a time synchronized with the transmission unit time) (hereinafter, the previous time). CRC result).

Specifically, the first switching unit f101 outputs the LLR to the LLR inversion unit f102 when the previous CRC detection result indicates that there is no error in the signal received one reception unit time before. Further, the first switching unit f101 outputs the LLR to the third MAP decoding unit f108 when the previous CRC detection result indicates that the signal received before one reception unit time has an error. Note that the first receiving unit (t = 1) of the LLR (LLR received signal _{S 1} corresponding to the _{S 1} that bit resolution '(n)), the first switching section f101 is output to the LLR inversion section f102 To do.

The LLR inversion unit f102 inverts the positive / negative sign of the LLR input from the first switching unit f101 using the code bit string input from the second encoding unit f113. Here, the code bit string input from the second encoding unit f113 correctly decodes the signal one reception unit time ago, and the decoded information bits are processed by the same processing as the second encoding unit c112 of the transmission device a1. This is the generated sign bit. Specifically, it is a bit string corresponding to the bits C _{21, t-1} , C _{22, t-1} , C _{23, t-1} , C _{24, t-1} (sign bit string C _{2, t-1} ).

Specifically, the LLR inversion unit f102 sets the LLR corresponding to the bit that is 0 in the code bit string C2 _{, t−1} as the value L (S _t ′ (n)) as it is. On the other hand, the LLR inversion unit f102 sets the LLR corresponding to the bit that is 1 in the code bit string C2 _{, t−1} to −L (S _t ′ (n)) obtained by inverting the sign of the LLR. This is a signal in which C1 _{, t} and C2 _{, t-1} are superimposed by exclusive OR, and when C2 _{, t-1} has already been correctly decoded, This is because the components of C _{2 and t−1} can be removed from the LLR based on the received signal in consideration of the property of the exclusive OR operation. That is, the LLR corresponding to the code bit string C1 _{, t} is extracted by this calculation.

In the first transmission (t = 1), since only one bit string is transmitted instead of two bit strings being superimposed, the LLR is left as it is. As described above, the LLR inversion unit f102 obtains the LLR for the code bit string C _{1, t} superimposed on the code bit string based on the decoding result of the code bit string received and correctly decoded one reception unit time before. And output to the second MAP decoding unit f103.

  The second MAP decoding unit f103 uses the prior probability input from the interleaver f106 for the LLR input from the LLR inversion unit f102, and performs MAP corresponding to encoding by the second encoder c123 of the transmission device a1. Decrypt. As described above, this is based on the likelihood and prior probability of the bit string obtained from the received signal, and the bit with the maximum posterior probability of each transmission bit under the condition given the received bit string is transmitted bit. And decoding is performed. However, in the first process, since there is no output of the interleaver f106, the prior probability is not considered. In this way, the deinterleaver f104 corresponding to the interleaver c122 returns the arrangement to the LLR obtained by the second MAP decoding unit f103, and outputs it to the first MAP decoding unit f105.

  The first MAP decoding unit f105 performs MAP decoding corresponding to the encoding by the first encoder c121 on the LLR output from the deinterleaver f104. The LLR decoded by the first MAP decoding unit f105 and improved in reliability is rearranged by the interleaver f106 that performs the same rearrangement as the interleaver c122. The interleaver f106 outputs the rearranged LLR to the second MAP decoding unit f103 as a prior probability. As described above, the second MAP decoding unit f103 uses the prior probability input from the interleaver f106 with respect to the LLR input from the LLR inversion unit f102, and performs encoding by the second encoder c123 of the transmission device a1. MAP decoding corresponding to conversion is performed again.

These processes by the second MAP decoding unit f103, the deinterleaver f104, the first MAP decoding unit f105, and the interleaver f106 are repeated any number of times, and finally the posterior probability calculated by the first MAP decoding unit f105 is calculated. By hard-deciding the maximum LLR, an information bit sequence d _t ″ corresponding to the transmission information bit sequence dt is obtained. The arbitrary number of times may be a predetermined value determined by the receiving device b1 or the system. Then, the repetition may be terminated when it can be determined that the error has disappeared, such as when the absolute value of the LLR becomes equal to or greater than a predetermined value, and the first MAP decoding unit f105 performs the decoding process in this way. The bit sequence d _t ″ and the LLR are output to the CRC detection unit f107.

For MAP decoding, algorithms such as BCJR (Bahl, Cocke, Jelinek, Raviv) and Max-log MAP may be used, and the calculation method is not limited to this as long as the calculation method realizes MAP estimation. The reason why the decoding unit F1 uses MAP decoding is that, as will be described later, there is an error in the decoding result of the information bit sequence d _t-1 ″ (or d _t-1 ′ described later) at time _t−1 . In this case, since the decoding result is used as prior information at the next time t, it is preferable to output the LLR, but since the prior probability is not input to the MAP decoding unit f105, the MAP decoding unit f105 It is not restricted to what performs MAP decoding, You may decode using maximum likelihood sequence (ML: Maximum Likelihood) estimation using SOVA (Soft Output Viterbi Algorithm).

The third MAP decoding unit f108 transmits the transmission device a1 to the LLR input from the first switching unit f101 when the previous CRC detection result indicates that the signal received one reception unit time ago has an error. MAP decoding in consideration of both the second encoder c123 and the third encoder c126 in FIG. This is because the sequence decoded by the third MAP decoding unit f108 includes the encoded bit sequence C _{1, t} encoded by the second encoder c123 and the code encoded by the third encoder c126. This is because the two different bit sequences of the digitized bit systems C _{2 and t−1} are superposed bit sequences superposed by exclusive OR on the transmission side. That is, the third MAP decoding unit f108 performs a process of MAP decoding two bit strings at the same time in consideration of these two encoders and exclusive OR operation.

Specifically, this process considers both the second encoder c123 and the third encoder c126, both of which have a coding rate of ¼. Decoding is performed. That is, the number of states is 16, and the transition (path) from one state to the next state takes into account four state transitions. In addition, when performing decoding in consideration of such state transition, the third MAP decoding unit f108 receives from the interleaver f111 the prior probability regarding the information bit sequence _dt transmitted for the first time in the transmission unit of time t. Prior probabilities related to the information bit sequence _dt-1 transmitted for the first time in the transmission unit of _t-1 are input from the interleaver f111a, and these prior probabilities are used.

For example, P (S _t ′ (n) | [d _t−1 (n), d _t (n)]) is information bits (first encoding unit c111 and second encoding unit) encoded in the transmission device a1. The probability that S _t ′ (n) is received when the input bits to the encoding unit c112) are d _t−1 (n) and d _t (n), that is, the reliability obtained from the received signal And the prior probability is P (d (n) = x). Then, the value regarding the reliability in consideration of the received signal and the prior probability is P (d _t−1 ′ (n) = 0) × P (d _t ′ (n) = 0) × P (S _t ′ (n) | [0,0]), P (d _t-1 ′ (n) = 1) × P (d _t ′ (n) = 0) × P (S _t ′ (n) | [1, 0]), P (d _t−1 ′ (n) = 0) × P (d _t ′ (n) = 1) × P (S _t ′ (n) | [0, 1]), P (d _t−1 ′ ( n) = 1) × P (d _t ′ (n) = 1) × P (S _t ′ (n) | [1, 1])), and decoding is performed based on these values. Is called.

However, here, P (S _t ′ (n) | [0, 0]) = P (S _t ′ (n) | [1, 1]), P (S _t ′) due to the exclusive OR property. (N) | [1, 0]) = P (S _t ′ (n) | [0, 1]). D _t ′ (n) indicates a decoding result corresponding to the n-th bit of the information bit sequence transmitted in the transmission unit time at time t. In addition, since there is no prior probability to be considered at the first decoding, the third MAP decoding unit f108 performs decoding without considering the prior probability.

The third MAP decoding unit f108 outputs the LLR relating to d _t−1 ′ to the deinterleaver f109a and outputs the LLR relating to d _t ′ to the deinterleaver f109 among the LLRs obtained by such decoding processing. The deinterleaver f109 restores the input LLR sequence by rearranging according to the interleaver c122, and outputs it to the first MAP decoding unit f110. Further, the deinterleaver f109a restores the original order by rearrangement according to the interleaver c125, and outputs the original order to the first MAP decoding unit f110a. The first MAP decoding unit f110 performs MAP decoding corresponding to the encoding by the first encoder c121 on the LLR output from the interleaver f109. The first MAP decoding unit f110a performs MAP decoding corresponding to the encoding by the first encoder c124 on the LLR output from the interleaver f109a.

However, the first MAP decoding unit f110a has the prior probability (LLR) obtained from the decoding result corresponding to the information bit d _t−1 of the signal received from the information holding unit f114 before one reception unit time. 2 is input from the information holding unit f114, and the first MAP decoding unit f110a performs MAP decoding using the prior probability. This prior probability is the LLR before the hard decision of the decoding result corresponding to the information bit d _t−1 , and is the LLR calculated by the first MAP decoding unit f105 or the first MAP decoding unit f110. Further, the first MAP decoding units f110 and f110a also perform depuncturing corresponding to puncturing in the first encoders c121 and c124 of the transmission device a1 prior to MAP decoding.

The interleavers f111 and f11a, which are the same interleavers as the interleavers c122 and c125, replace the arrangement with respect to the LLRs that have been decoded by the first MAP decoding units f110 and f110a and have improved reliability through the processes as described above. , And input to the third MAP decoding unit f108 as a prior probability. Then, as described above, the third MAP decoding unit f108 uses the prior probabilities input from the interleavers f111 and f111a and the LLR of the received signal input from the demodulated LLR calculation unit b103, as described above. MAP decoding is performed in consideration of both the second encoder c123 and the third encoder c126. These processes are repeated an arbitrary number of times (for example, a preset number, until the absolute values of all LLRs exceed a predetermined value), and finally, the first MAP decoding unit f110 performs the decoded information bit sequence to obtain d _t 'hard decision information bit sequence _{d t} the LLR of' outputs a and its LLR information bit sequence _{d t} 'to the CRC detection unit F107. Similarly, the first MAP decoding unit F110a, to give 'a LLR hard decision information bit sequence _{d t-1} in the' decoded information bit sequence _{d t-1,} the information bit sequence _{d t-1} 'and its LLR Is output to the CRC detection unit f107. By performing such decoding, a sequence in which a previously decoded sequence and a newly transmitted sequence are superimposed, and partial reliability information of the previously decoded sequence are obtained in advance. It becomes possible to decode by using it as a probability.

Next, the CRC detection unit f107 receives the information bit sequence d _t ″ input from the first MAP decoding unit f105 or the information bit sequence d _t ′, d _t− input from the first MAP decoding units f110 and f110a. _A CRC code is extracted from ₁ ′ and error detection is performed. If no error is detected as a result of this error detection, the information bit sequence d _t ′ is transmitted via the second switching unit f112. The information is output to the second encoding unit f113, and the information bit sequence d _t ′ or the information bit sequences d _t−1 ′ and d _t ′ is output to an upper layer (not shown). The encoding unit f113 encodes the information bit sequence d _t ′ again and outputs it to the LLR inversion unit f102 as described above.

On the other hand, if an error is detected as a result of the error detection by the CRC detection unit f107, the second switching unit f112 switches the output destination and holds the LLR of the information bit sequence d _t ′ as the second information. To the part f114. The second information holding unit f114 performs the LLR of the information bit sequence d _t ′ (handled as the LLR of d _t−1 ′ after one reception unit time) until the decoding process of the reception signal after one reception unit time is performed. Are held, and the held LLR is output to the first MAP decoding unit f110a as a prior probability during the decoding process.

  As described above, according to the present embodiment, the transmission apparatus a1 superimposes and transmits the series that was previously transmitted to the reception apparatus b1 and the series that is newly transmitted to the reception apparatus b1. Turbo coding can be applied to the diversity technique to be transmitted. Therefore, it is possible to obtain both a diversity gain obtained by transmitting the same sequence a plurality of times and a gain obtained by iterative decoding by repeatedly exchanging soft outputs between the two decoders.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings. In this embodiment, a communication system having a configuration different from that of the first embodiment will be described for two encoding units in the transmission device and a decoding unit in the reception device. The schematic block configuration of the transmission apparatus in the present embodiment is the same as that in the first embodiment (FIG. 2), but includes a first encoding unit c111a instead of the first encoding unit c111. The second encoding unit c112 is different from the second encoding unit c112 in that a second encoding unit c112a is provided. The schematic block configuration of the receiving apparatus in the present embodiment is the same as that in the first embodiment (FIG. 10), except that a decoding unit F2 is provided instead of the decoding unit F1.

<About the encoding unit>
FIG. 12 is a schematic block diagram showing the configuration of the first encoding unit c111a according to this embodiment. In this figure, the first encoding unit c111a includes a first encoder c221, an interleaver c222, and a second encoder c223. Here, the first encoder c221 in the first encoder c111a is a convolutional encoder with a coding rate of 1/2 as an outer code, and the second encoder c223 has a coding rate as an inner code. A 2/4 RSC encoder is used. By connecting these encoders by an interleaver c222, the first encoding unit c111a is configured as a serially connected turbo encoder.

FIG. 13 is a schematic block diagram showing the configuration of the second encoding unit c112a according to this embodiment. In this figure, the second encoding unit c112a is configured to include a third encoder c224. The second encoding unit c112a (third encoder c224) is a convolutional encoder with a coding rate of 1/4. That is, the encoding unit in this embodiment, (coding unit for encoding the information bit sequence d _t at time t) a first encoding unit c111a, the encoding rate 1/4 (the first code This is a configuration of a serially concatenated turbo code of a product of a coding rate 1/2 of the encoder and a coding rate 2/4 of the second encoder. On the other hand, the second encoding unit C 112a (time t-1 of the information bit sequence _{d t-1} encoding unit for encoding the) is constituted by a convolutional encoder with a coding rate of 1/4. As in the first embodiment, the encoding unit in this embodiment has the same encoding rate of the two encoding units (in this example, 1/4), and the second encoder The sum of the coding rates of the third encoder (in this example, 2/4 + 1/4 = 3/4) may be 1 or less, and the configuration of each encoder is not limited to this.

In this way, the two encoding units are configured differently because the first encoding unit c111a is an encoding for transmitting the information bit sequence for the first time, and thus gain by iterative decoding is obtained. Since the second encoding unit c112a is an encoding for retransmitting the information bit sequence one transmission unit time before stored in the information holding unit a102, the serial encoding turbo encoder is configured. This is because a simple encoder is considered sufficient. As in this embodiment, by the information bit sequence d _t at time t serially concatenated turbo encoder, and configure the information bit sequence d _t-1 at time t-1 in a convolutional encoder, a first embodiment It is possible to apply turbo coding to diversity by superimposing a plurality of code bit sequences with a simpler configuration than the transmission device configuration in FIG. 1, and to obtain gain by iterative decoding.

Also, as shown in FIGS. 14 and 15, the configurations of the first encoding unit c111a and the second encoding unit c112a of this embodiment are reversed (that is, the information bit sequence dt at time _t is shown in FIG. 13 is encoded by a simple encoder (third encoder c224), and the information bit sequence d _t-1 at time t-1 is converted into a serially concatenated turbo encoder (first encoder c221, interleaver c222, The second encoder c223) can also be encoded). With this configuration, it is possible to reduce the amount of calculation for decoding compared to the present embodiment. As described above, whichever encoder configuration is used, turbo encoding can be applied to diversity in which a plurality of code bit sequences are superimposed with a configuration simpler than the configuration in the first embodiment. .

<About decryption unit>
FIG. 16 is a schematic block diagram showing the configuration of the decoding unit F2 according to the present embodiment. As shown in FIG. 16, the decoding unit F2 in the present embodiment is obtained by changing the following three points from the decoding unit F1 in the first embodiment. The first point is that the deinterleaver f109a, the first MAP decoding unit f110a, and the interleaver f111a are deleted. The second point is that the second MAP decoding unit f103 is replaced with a second MAP decoding unit f103b, the deinterleaver f104 is replaced with a deinterleaver f104b, and the first MAP decoding unit f105 is replaced with the first MAP decoding unit f105. A MAP decoder f105b, an interleaver f106 instead of the interleaver f106, a third MAP decoder f108b instead of the third MAP decoder f108b, a deinterleaver f109b instead of the deinterleaver f109, The first MAP decoding unit f110b is provided instead of the first MAP decoding unit f110, and the interleaver f111b is provided instead of the interleaver f111. The third point is that the prior probability output from the second information holding unit f114 is input to the third MAP decoding unit f108b.

The second MAP decoding unit f103b performs MAP decoding corresponding to the encoding by the second encoder c223. The deinterleavers f104b and f109b restore the rearrangement by the interleaver c222. The first MAP decoding units f105b and f110b perform MAP decoding corresponding to the encoding by the first encoder c221. The interleavers f106b and f111b perform the same rearrangement as the interleaver c222. The third MAP decoding unit f108b performs decoding in consideration of state transition based on both the second encoder c223 and the third encoder c224 using the input prior probability. This is because d _t−1 is encoded only by the third encoder c 224, and the iterative decoding by the two decoding units as shown in the first embodiment is d Only done for _t '.

  FIG. 17 is a schematic block diagram illustrating a configuration of a decoding unit F2-1 that is a decoding unit of the receiving device when the configuration of the encoding unit is set to FIGS. 14 and 15 in the present embodiment. As illustrated in FIG. 17, the decoding unit F2-1 in the present embodiment has a configuration in which the deinterleaver f104b, the first MAP decoding unit f105b, and the interleaver f106b are deleted from the decoding unit F2 in the present embodiment. Further, the second MAP decoding unit f103b in FIG. 16 is configured to perform iterative decoding for the decoding process of the serially concatenated turbo code. However, in the second MAP decoding unit f103b-1 in FIG. Therefore, iterative decoding is not performed. Therefore, by setting the configuration of the encoding unit to FIGS. 14 and 15, it is possible to reduce the amount of calculation required for decoding compared to the cases of FIGS. 12 and 13.

(Third embodiment)
Hereinafter, the third embodiment of the present invention will be described in detail with reference to the drawings. In the first and second embodiments, the number of code bit sequences to be superimposed is set to 2, but in this embodiment,
A configuration when the number of code bit sequences to be superimposed is 3 will be described.
<About the transmitter a3>
FIG. 18 is a schematic block diagram showing the configuration of the transmission device a3 according to this embodiment. The transmission device a3 includes a CRC unit a101, an information holding unit a302, a superposed bit generation unit E3, a modulation unit a103, a radio unit a104, and a transmission antenna a105. In the figure, the same reference numerals (a101, a103 to a105) are assigned to portions corresponding to the respective portions in FIG. 2, and the description thereof is omitted.

In the first and second embodiments, the superposition bit generation unit E1 includes two encoding units (a first encoding unit c111 and a second encoding unit c112) and an exclusive OR operation for superimposing them. The superimposition bit generation unit E3 in this embodiment is configured with three encoding units (a first encoding unit c311, a second encoding unit c312, and a third encoding unit c313). And an exclusive OR operation unit c314 for superimposing them. The information holding unit a302 holds the information bit string _dt input from the CRC unit a101, outputs the information bit sequence _dt to the second encoding unit c312 at the next transmission timing, and further outputs the third code at the next transmission timing. To the conversion unit c313. That is, the information holding unit a302 holds the information bit string _dt for two transmission unit times.

<About the encoding unit>
FIG. 19 is a schematic block diagram showing the configuration of the first encoding unit c311 according to this embodiment. In this figure, the first encoding unit c311 includes a first encoder c321, an interleaver c322, and a second encoder c323. Here, the first encoder c321 in the first encoder c311 is a convolutional encoder with a coding rate of 1/2 as an outer code, and the second encoder c223 has a coding rate as an inner code. A 2/4 RSC encoder is used. By connecting these encoders by an interleaver c322, the first encoding unit c311 is configured as a serially connected turbo encoder.

FIG. 20 is a schematic block diagram showing the configuration of the second encoding unit c312 according to this embodiment. In this figure, the second encoding unit c312 includes a third encoder c324, and is a convolutional encoder with a coding rate of 1/4.
FIG. 21 is a schematic block diagram showing the configuration of the third encoding unit c313 according to the present embodiment. The third encoding unit c313 has a configuration similar to that of the second encoding unit c312 and is a convolutional encoder with a coding rate of 1/4.

That is, the encoding unit in this embodiment, (coding unit for encoding the information bit sequence d _t at time t) a first encoding unit c311 is coding rate 1/4 (the first code This is a configuration of a serially concatenated turbo code of a product of a coding rate 1/2 of the encoder and a coding rate 2/4 of the second encoder. On the other hand, the second encoding unit C 312 (encoding unit for encoding the information bit sequence _{d t-1} at time t-1) and the third encoding unit c313 (time t-2 of the information bit sequence d The encoding unit for encoding _t-2 is configured by a convolutional encoder with a coding rate of 1/4. As in the first embodiment, the encoding unit in the present embodiment has the same encoding rate of the three encoding units (c311, c312 and c313) (in this example, 1/4), In addition, the sum of the coding rates of the second encoder c323, the third encoder c324, and the fourth encoder c325 (in this example, 2/4 + 1/4 + 1/4 = 1) may be 1 or less, The coding rate of each encoder and the type of encoder are not limited to this.

FIG. 22 is a schematic diagram illustrating an example of a superimposed bit string according to the present embodiment. In this figure, the horizontal axis indicates time t. As shown in FIG. 22, in this embodiment, a sequence to be newly transmitted, a sequence transmitted before one transmission unit time, and a sequence transmitted two time before transmission unit time are superimposed and transmitted (for example, , C _1,3 and C _2,2 and C _3,1 , C _1,4 and C _2,3 and C _3,2 etc.). Further, in the transmission unit for the first time (time t = 1), since there is no bit sequence transmitted in the past, only sends C _{1, 1,} at time t = 2, and C _{1, 2} as shown in FIG. to send the exclusive oR of the C _2,1, and transmits only the _{C 2,1.}

<About decryption unit>
The schematic block configuration of the receiving apparatus in this embodiment is the same as that of the first embodiment (FIG. 10), except that a decoding unit F3 is provided instead of the decoding unit F1. FIG. 23 is a schematic block diagram showing a configuration of the decoding unit F3 according to the present embodiment. In the decoding unit F2 in the second embodiment, since the number of code bit sequences superimposed is 2, the first switching unit f101 determines that the number of CRCs of the information bit sequence one reception unit time before is 2 The decoding process is switched in one case (when the CRC result is correct or when the CRC result is incorrect). On the other hand, in the decoding unit F3 in the present embodiment, the number of superimposed code bit sequences is 3, so the first switching unit f101c is one reception unit time before input from the first information holding unit f116c. According to the CRC detection result of the information bit sequence two reception unit times ago, it is divided into three cases (when both CRC results are correct, only one CRC result is correct, or both CRC results are incorrect). Switch the decryption process.

When both CRC detection results are correct, the first switching unit f101c outputs the LLR input from the demodulation LLR calculation unit b103 to the first LLR inversion unit f102c. The first LLR inversion unit f102c is input from the first switching unit f101c using the code bit sequence input from the second encoding unit f113c and the code bit sequence input from the third encoding unit f117c. Inverts the sign of LLR. Specifically, the first LLR inversion unit f102c calculates the exclusive OR of each bit of the code bit string C2 _{, t-1} and C3 _{, t-2} , and calculates the LLR corresponding to the bit that is 0. The value L (S _t ′ (n)) is used as it is, and the LLR corresponding to the bit which is 1 is −L (S _t ′ (n)) obtained by inverting the sign of the LLR. By this calculation, the LLR corresponding to the code bit string C1 _{, t} is extracted.

  The second MAP decoding unit f103c performs MAP decoding corresponding to the encoding by the second encoder c323 on the output of the first LLR inversion unit f102c. The deinterleaver f104c restores the rearrangement by the interleaver c222 to the output of the second MAP decoding unit f103c. The first MAP decoding unit f105c performs MAP decoding corresponding to the encoding by the first encoder c321 on the output of the deinterleaver f104c. The interleaver f106c performs the same rearrangement on the output of the first MAP decoding unit f105c as the interleaver c322.

If only one CRC detection result is correct, the first switching unit f101c outputs the LLR input from the demodulation LLR calculation unit b103 to the second LLR inversion unit f118c. The second LLR inversion unit f118c uses the code bit string input from the second encoding unit f113c or the third encoding unit f117c to change the sign of the LLR input from the first switching unit f101c. Invert. Specifically, the second encoding unit f113c or the third encoding unit f117c outputs the code bit sequence that has been correctly decoded out of the code bit sequences C2 _{, t-1} and C3 _{, t-2} to the second. The LLR corresponding to the bit that is 0 in the input code bit string is set to the value L (S _t ′ (n)) as it is, and the LLR corresponding to the bit that is 1 is It is assumed that −L (S _t ′ (n)) is obtained by inverting the sign of the LLR. By this operation, the code bit string C1 _{, t} and the LLR relating to the code bit string in which the CRC detection result is incorrect are extracted.

  The deinterleaver f109c restores the rearrangement by the interleaver c222 to the output of the third MAP decoding unit f108c. The first MAP decoding unit f110c performs MAP decoding corresponding to the encoding by the first encoder c321 on the output of the deinterleaver f109c. The interleaver f111c performs rearrangement similar to the interleaver c322 on the output of the first MAP decoding unit f110c.

  The second information holding unit f114 inputs, to the third MAP decoding unit f108c, the prior probability based on the information bit sequence in which the CRC detection result is incorrect, and the third MAP decoding unit f108c receives the input prior probability. The two state transitions of the second encoder c323 and the encoder with the wrong CRC detection result (the one with the wrong CRC detection result among the third encoder c324 or the fourth encoder c325) are used. Decode taking into account.

  When both of the CRC detection results are incorrect, the first switching unit f101c outputs the LLR input from the demodulation LLR calculation unit b103 to the fourth MAP decoding unit f119c. The fourth MAP decoding unit f119c uses the prior probability input from the second information holding unit f114c, and performs state transition based on the second encoder c323, the third encoder c324, and the fourth encoder c325. Decode taking into account.

The deinterleaver f120c restores the rearrangement by the interleaver c222 to the output of the fourth MAP decoding unit f119c. The first MAP decoding unit f121c performs MAP decoding corresponding to the encoding by the first encoder c321 on the output of the deinterleaver f114c. The interleaver f122c performs rearrangement similar to that of the interleaver c322 on the output of the first MAP decoding unit f121c.
The CRC detection unit f107c performs error detection by extracting a CRC code from the information bit sequence input from the first MAP decoding units f105c, f110c, and f121c. The CRC detection unit f107c extracts the CRC code from the information bit sequence input from the third MAP decoding unit f108c and the fourth MAP decoding unit f119c, and performs error detection.

The second switching unit f112c outputs the LLR of the information bit sequence in which an error is detected to the second information holding unit f114c. The second switching unit f112c outputs the information bit sequence in which no error is detected to the encoding unit corresponding to the encoding applied on the transmission side in the next transmission unit time. That is, when no error is detected in the information bit sequence d _t ′, the error is output to the second encoding unit f113c. When no error is detected in the information bit sequence d _t−1 ′, the third bit is output. The data is output to the encoding unit f117c. The second encoding unit f113c performs the same encoding as the second encoding unit c312. The third encoding unit f117c performs the same encoding as the third encoding unit c313.

  As described above, according to the present embodiment, the transmitter transmits the same sequence a plurality of times by superimposing the sequence previously transmitted to the receiver and the sequence newly transmitted to the receiver. In a system in which turbo coding is applied to the technology, it can be realized even when the number of superimposed sequences is 3 or more.

  Moreover, you may make it implement | achieve a part of transmission apparatus and receiving apparatus in each embodiment mentioned above with a computer. In that case, the program for realizing the control function may be recorded on a computer-readable recording medium, and the program recorded on the recording medium may be read by a computer system and executed. Here, the “computer system” is a computer system built in the transmission device and the reception device, and includes hardware such as an OS and peripheral devices. The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Furthermore, the “computer-readable recording medium” is a medium that dynamically holds a program for a short time, such as a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line, In such a case, a volatile memory inside a computer system serving as a server or a client may be included and a program that holds a program for a certain period of time. The program may be a program for realizing a part of the functions described above, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system.

Moreover, you may implement | achieve part or all of the transmission apparatus in each embodiment mentioned above, and a receiver as integrated circuits, such as LSI (Large Scale Integration). Each functional block of the transmission device and the reception device may be individually made into a processor, or a part or all of them may be integrated into a processor. Further, the method of circuit integration is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. Further, in the case where an integrated circuit technology that replaces LSI appears due to progress in semiconductor technology, an integrated circuit based on the technology may be used.
As described above, the embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to the above, and various design changes and the like can be made without departing from the scope of the present invention. It is possible to

DESCRIPTION OF SYMBOLS 10 ... Communication system a1, a3 ... Transmission apparatus b1 ... Reception apparatus a101 ... CRC part a102, a302 ... Information holding part a103 ... Modulation part a104 ... Radio | wireless part a105 ... Transmission antenna b101 ... Reception antenna b102 ... Radio | wireless part b103 ... Demodulation LLR calculation Unit c111, c111a, c311 ... first encoding unit c112, c112a, c312 ... second encoding unit c313 ... third encoding unit c113, c314 ... exclusive OR operation unit c121, c124, c221, c321 ... first encoder c122, c125, c222, c322 ... interleaver c123, c223, c323 ... second encoder c126, c224, c324 ... third encoder c325 ... fourth encoder c131, c132, c133, c141, c142, c151, c152, c 53 ... adder c134 ... puncture unit c135, c143, c154 ... P / S conversion unit f101, f101c ... first switching unit f102 ... LLR inversion unit f102c ... first LLR inversion unit f103, f103b, f103b-1 , F103c ... second MAP decoding unit f104, f109, f109a, f104b, f109b, f104c, f109c, f120c ... deinterleaver f105, f110, f110a, f105b, f110b, f105c, f110c, f121c ... first MAP decoding unit f106 , F111, f111a, f106b, f111b, f106c, f111c, f122c ... interleaver f107, f107c ... CRC detection unit f108, f108b, f108c ... third MAP decoding unit f112, f11 c ... second switching unit f113, f113c ... second encoding unit f114, f114c ... second information holding unit f116, f116c ... first information holding unit f117c ... third encoding unit f118c ... second LLR inversion unit f119c ... Fourth MAP decoding unit D1, D2, D3, D4, D5, D6, D7 ... Shift register E1, E3 ... Superimposition bit generation unit F1, F2, F2-1, F3 ... Decoding unit

Claims (16)

A plurality of encoding units that encode different information bit sequences using different codes to generate an encoded bit sequence;
An exclusive OR operation unit that superimposes encoded bit sequences generated by the plurality of encoding units by exclusive OR,
A transmitter that modulates and transmits the superimposed encoded bit sequence;
At least one of the plurality of encoding units is:
A first stage encoder for encoding the information bit sequence;
An interleaver for interleaving the bit sequence encoded by the first stage encoder unit ;
A second stage encoder unit for encoding the interleaved bit sequence ;
The information bit sequences different from each other are an information bit sequence to be newly transmitted and an information bit sequence which has already been transmitted at least once toward the receiving side .   The transmission apparatus according to claim 1, wherein coding rates of the plurality of coding units are equal to each other.   The transmission apparatus according to claim 2, wherein the sum of coding rates in the last stage of coding of each of the plurality of coding units is 1 or less.   The at least one of the different information bit sequences is transmitted so that it can be decoded on the receiving side independently of the transmission. Transmitter.   The at least one information bit sequence is transmitted before the transmission, so that the at least one information bit sequence is transmitted so that it can be decoded on the receiving side independently of the transmission. Item 5. The transmission device according to Item 4. The first stage encoder unit and a second-stage encoder unit, transmitting apparatus according to claim 1, wherein the encoded using a convolutional code. The second stage encoder unit, transmitting apparatus according to claim 6, characterized in that the encoded using a convolutional recursive code. The plurality of encoding units are:
A first stage encoder for encoding the information bit sequence;
An interleaver for interleaving the bit sequence encoded by the first stage encoder unit ;
A second stage encoder unit for encoding the interleaved bit sequence;
The first stage encoder unit included in the plurality of encoding units performs encoding using the same code,
The interleavers included in the plurality of encoding units interleave with the same interleave pattern,
The transmitting apparatus according to claim 1, wherein the second-stage encoder units included in the plurality of encoding units perform encoding using different codes. A transmission apparatus that encodes different information bit sequences using different codes and superimposes the encoded bit sequences by exclusive OR, and transmits at least one of the different codes. Is a receiver that receives a signal transmitted by a transmitter in which first-stage encoding, interleaving, and second-stage encoding are connected,
A demodulator that demodulates a signal received from the transmitter and generates a received sequence;
An inverting unit for inverting the sign of the received sequence based on a result of decoding in advance for at least one information bit sequence out of the information bit sequence superimposed in the transmission device;
A decoding unit that performs decoding on the reception sequence inverted by the inversion unit ,
The information bit sequence which is different from each other is an information bit sequence to be newly transmitted and an information bit sequence which has already been transmitted to the receiving side at least once . A transmission apparatus that encodes different information bit sequences using different codes and superimposes the encoded bit sequences by exclusive OR, and transmits at least one of the different codes. Is a receiver that receives a signal transmitted by a transmitter in which first-stage encoding, interleaving, and second-stage encoding are connected,
A demodulator that demodulates a signal received from the transmitter and generates a received sequence;
A third decoding unit that performs decoding corresponding to the combination of encoding of the final stage of each of the different codes, with respect to the received sequence;
A deinterleaver that performs deinterleaving corresponding to the interleaving on the decoding result corresponding to the second stage encoding among the decoding results by the third decoding unit;
A first decoding unit that performs decoding corresponding to the first stage encoding on the decoding result deinterleaved by the deinterleaver;
An interleaver that performs interleaving similar to the interleaving on the decoding result by the first decoding unit;
With
It said third decoder, the deinterleaver, the first decoding unit, have rows iterative decoding process by the interleaver,
The information bit sequence which is different from each other is an information bit sequence to be newly transmitted and an information bit sequence which has already been transmitted to the receiving side at least once . A first step of encoding a first information bit sequence that is a newly transmitted information bit sequence to generate an encoded bit sequence;
A second information bit sequence, which is an information bit sequence that has already been transmitted at least once toward the receiving side, is encoded using a code different from the first step to generate an encoded bit sequence; And the steps
A third step of performing an exclusive OR operation on the encoded bit sequences generated in the first step and the second step and superimposing the bit sequence;
A fourth step of modulating and transmitting the superimposed encoded bit sequence, and
At least one of the encoding by the first step and the encoding by the second step is:
A first stage encoding step of encoding the information bit sequence;
An interleaving step of interleaving the bit sequence encoded by the first stage encoding step;
And a second-stage encoding step of encoding the bit sequence interleaved in the interleaving step. A transmission apparatus that encodes different information bit sequences using different codes and superimposes the encoded bit sequences by exclusive OR, and transmits at least one of the different codes. Is a receiving method in a receiving apparatus for receiving a signal transmitted by a transmitting apparatus in which first-stage encoding, interleaving, and second-stage encoding are connected,
A first step of demodulating a signal received from the transmitter to generate a received sequence;
A second step of inverting the sign of the received sequence based on a result of decoding in advance for at least one information bit sequence out of the information bit sequence superimposed in the transmission device;
And a third step of performing decoding on the reception sequence inverted by the second step ,
The information bit sequence different from each other is an information bit sequence to be newly transmitted and an information bit sequence which has already been transmitted at least once toward the receiving side . A transmission apparatus that encodes different information bit sequences using different codes and superimposes the encoded bit sequences by exclusive OR, and transmits at least one of the different codes. Is a receiving method in a receiving apparatus for receiving a signal transmitted by a transmitting apparatus in which first-stage encoding, interleaving, and second-stage encoding are connected,
A first step of demodulating a signal received from the transmitter to generate a received sequence;
A second step of performing decoding on the received sequence corresponding to a combination of encoding of the final stage of each of the different codes;
A third step of performing deinterleaving corresponding to the interleaving on the decoding result corresponding to the second-stage encoding among the decoding results of the second step;
A fourth step of performing decoding corresponding to the first stage encoding on the decoding result deinterleaved by the third step;
A fifth step of performing interleaving similar to the interleaving on the decoding result of the fourth step;
With
The second step, the third step, the fourth step, have rows iterative decoding process by the fifth step,
The information bit sequence different from each other is an information bit sequence to be newly transmitted and an information bit sequence which has already been transmitted at least once toward the receiving side . On the computer,
A first step of encoding a first information bit sequence that is a newly transmitted information bit sequence to generate an encoded bit sequence;
A second information bit sequence, which is an information bit sequence that has already been transmitted at least once toward the receiving side, is encoded using a code different from the first step to generate an encoded bit sequence; And the steps
A third step of superimposing the encoded bit sequences generated in the first step and the second step by exclusive OR,
A program for performing the fourth step of modulating and transmitting the superimposed encoded bit sequence,
At least one of the encoding by the first step and the encoding by the second step is:
A first stage encoding step of encoding the information bit sequence;
An interleaving step of interleaving the bit sequence encoded by the first stage encoding step;
And a second stage encoding step for encoding the bit sequence interleaved in the interleaving step. A transmission apparatus that encodes different information bit sequences using different codes and superimposes the encoded bit sequences by exclusive OR, and transmits at least one of the different codes. Is a computer of a receiving apparatus that receives a signal transmitted by a transmitting apparatus in which first-stage encoding, interleaving, and second-stage encoding are connected,
A first step of demodulating a signal received from the transmitter to generate a received sequence;
A second step of inverting the sign of the received sequence based on a result of decoding in advance for at least one information bit sequence out of the information bit sequence superimposed in the transmission device;
And a third step of performing decoding on the reception sequence inverted in the second step ,
The information bit sequences different from each other are an information bit sequence to be newly transmitted and an information bit sequence which has already been transmitted at least once toward the receiving side.
A program characterized by A transmission apparatus that encodes different information bit sequences using different codes and superimposes the encoded bit sequences by exclusive OR, and transmits at least one of the different codes. Is a computer of a receiving apparatus that receives a signal transmitted by a transmitting apparatus in which first-stage encoding, interleaving, and second-stage encoding are connected,
A first step of demodulating a signal received from the transmitter to generate a received sequence;
A second step of performing decoding on the received sequence corresponding to a combination of encoding of the final stage of each of the different codes;
A third step of performing deinterleaving corresponding to the interleaving on the decoding result corresponding to the second-stage encoding among the decoding results of the second step;
A fourth step of performing decoding corresponding to the first stage encoding on the decoding result deinterleaved by the third step;
A fifth step of performing interleaving similar to the interleaving on the decoding result of the fourth step;
Order to the execution, and,
A program for executing an iterative decoding process according to the second step, the third step, the fourth step, and the fifth step ,
The information bit sequences different from each other are an information bit sequence to be newly transmitted and an information bit sequence which has already been transmitted at least once toward the receiving side.
A program characterized by

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