JP5528852B2 - Multi-thread processing device - Google Patents

Description

  The present invention relates to a multi-thread processing apparatus in which a plurality of threads perform processing while partially sharing hardware.

  2. Description of the Related Art Conventionally, a multi-thread device is known that has a source program, a register file, and the like for each of a plurality of threads, and performs parallel processing by sharing an arithmetic circuit and the like between threads. Thus, the function of the multi-thread device in which the components for each thread exist is called hardware multi-threading.

  An invention of a multi-thread processor that performs hardware multi-threading is disclosed (for example, see Patent Document 1). In this multi-thread processor, a register window capable of storing data used for instruction processing by an arithmetic unit is provided for each thread, and data can be transferred between a plurality of register windows and between one or more arithmetic units. A work register and a multi-thread control unit for controlling data transfer are provided.

  On the other hand, there is known a microcomputer that includes a plurality of processing means including an arithmetic unit and the like, distributes each processing of a program to a plurality of processing means as necessary, and performs parallel processing. As described above, the operation for distributing the processing to a plurality of processing means is called a superscalar (or superscaler) operation. By performing the superscalar operation, the processing time can be shortened and the processing efficiency can be improved.

  An invention of a superscalar processor that performs a superscalar operation is disclosed (for example, see Patent Document 2). This processor issues and executes instructions that can be executed simultaneously to a plurality of execution units in parallel, and the operation mode for specifying the operation power supply voltage and the operation clock signal for each of the execution units is controlled by software control for each execution unit. The command issue destination is changed according to the operating power supply voltage and the operating state of the operating clock signal.

JP 2006-039815 A JP 2002-366351 A

  By the way, if the multi-thread processing device as described above performs a superscalar operation (in other words, if a microcomputer capable of superscalar operation is provided with a hardware multithreading function), the real-time property of processing performed by the thread is reduced. There is a problem of being damaged. Specifically, when there is a situation where a specific process is desired to be executed after a predetermined clock time has elapsed from a certain reference time, the processing time is shortened by the superscalar operation, and the original scheduled time (scheduled clock elapsed number) is exceeded. Certain treatments may be terminated before. Such a problem becomes particularly serious when applied to an in-vehicle control device that performs vehicle control. This is because in the in-vehicle control device, the control timing may be important depending on the control target, and it may be necessary to ensure real-time processing.

  The present invention is intended to solve such problems, and it is a main object of the present invention to provide a multi-thread processing device capable of performing efficient processing by superscalar operation and ensuring real-time processing. To do.

In order to achieve the above object, one embodiment of the present invention provides:
Having a plurality of processing means,
A multi-thread processing device that performs hardware multi-threading using any of the plurality of processing means,
Permits superscalar operation using two or more processing means of the plurality of processing means for each of the threads that execute processing for in-vehicle device control among the plurality of threads related to the hardware multithreading Or disallowance ,
The permission or non-permission of superscalar operation for at least some of the plurality of threads is dynamically changed according to a vehicle state of a vehicle on which the multi-thread processing device is mounted .
A multi-thread processing device.

  According to this aspect of the present invention, permission or non-permission of superscalar operation is defined for each of a plurality of threads related to hardware multithreading. Real-time property can be secured.

In one embodiment of the present invention,
The permission or non-permission of the superscalar operation regarding the plurality of threads is defined by, for example, a data table stored in a predetermined storage device.

In one embodiment of the present invention ,
It said vehicle condition includes the shift position,
The permission or refusal of superscalar operation for at least some of the plurality of threads, may be used as the ones characterized in that it is dynamically changed according to the shift position,
It said vehicle condition includes an engine speed,
Permission or non-permission of superscalar operation for at least a portion of the plurality of threads may be those characterized by being dynamically changed depending on the engine speed.

  According to the present invention, it is possible to provide a multi-thread processing apparatus capable of performing efficient processing by superscalar operation and ensuring real-time processing.

1 is a system configuration example of a multithread processing apparatus 1 according to an embodiment of the present invention. FIG. 2 is a partial configuration example of the multi-thread processing apparatus 1 and is a diagram mainly showing the internal configurations of an instruction issuing unit 12 and a thread schedule control unit 24 in more detail. It is explanatory drawing for demonstrating a mode that processing efficiency improves by superscalar operation | movement. When the number of threads of the multi-thread processing device is 2 (assumed to be # 0 and # 1), FIG. It is a figure which shows a mode that real-time property is ensured when integrating several ECU and it is set as one multithread processing apparatus. It is a figure which shows notionally the system configuration | structure of the vehicle-mounted control apparatus to which the multithread processing apparatus 1 of a present Example was applied.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings.

<Basic example>
[Basic configuration]
A multi-thread processing apparatus 1 according to an embodiment of the present invention will be described below with reference to the drawings. The multi-thread processing device 1 is preferably applied to a control device that is mounted on a vehicle, for example, and each thread executes various in-vehicle device control commands.

  Examples of in-vehicle device control include engine control, brake control, steering control for controlling power steering, body control for controlling door locks, vehicles such as VSC (Vehicle Stability Control) and VDIM (Vehicle Dynamics Integrated Management). Stabilization control, driving support control such as ACC (Adaptive Cruise Control), navigation control, and the like can be given.

  FIG. 1 is a system configuration example of a multithread processing apparatus 1 according to an embodiment of the present invention. The multi-thread processing device 1 includes, as main components, an instruction buffer 10 # 0 to 10 # 3, an instruction issuing unit 12, instruction decoders 14A and 14B, register acquisition units 16A and 16B, and arithmetic units 18A and 18B. , Register group 20 # 0-20 # 3, pipeline control unit 22, and thread schedule control unit 24.

  The instruction buffers 10 # 0 to 10 # 3 and the register groups 20 # 0 to 20 # 3 are provided for each of a plurality of threads (# 0 to # 3). Here, the thread refers to a virtual processing entity that performs processing while partially sharing hardware. In this embodiment, the instruction buffer 10 # 0 to 10 # 3 and the register group 20 # 0 to 20 # 0 are registered. 20 # 3 is prepared for each thread, but the other instruction issuing unit 12, instruction decoders 14A and 14B, register acquisition units 16A and 16B, and arithmetic units 18A and 18B are shared between threads. In this embodiment, four threads are set, and these are referred to as threads # 0 to # 3.

  Two systems of processing means (instruction decoder 14A, register acquisition unit 16A, arithmetic unit 18A (these are referred to as system A), instruction decoder 14B, register acquisition unit 16B, arithmetic unit 18B (these are referred to as system B) For example, when superscalar operation is not performed, processing is performed using only the system A, and when superscalar operation is performed, processing is performed using the systems A and B. Used in the embodiment.

  The instruction buffers 10 # 0 to 10 # 3 store a program (instruction sequence) acquired from a program memory such as a ROM (Read Only Memory) and an EEPROM (Electrically Erasable and Programmable Read Only Memory) (not shown) for each thread.

  The instruction issuing unit 12 issues an instruction for each thread according to the setting state of multithreading or superscalar. Details will be described later.

  The instruction decoders 14A and 14B decode (decode) the instruction supplied from the instruction issuing unit 12 and output the decoded instruction to the register acquisition units 16A and 16B. The decoding results by the instruction decoders 14A and 14B are, for example, the type of operation, the source operand, the storage location of the result, and the like.

  The register acquisition units 16A and 16B acquire operation target values and the like from the register groups 20 # 0 to 20 # 3 according to the instructions input from the instruction decoders 14A and 14B.

  The calculators 18A and 18B perform calculations on the calculation target values stored in the register groups 20 # 0 to 20 # 3 and acquired by the register acquisition units 16A and 16B according to the type of calculation. The contents of the operation are store, load, addition, multiplication, division, branch, and the like. For example, in the case of a store instruction, the arithmetic units 18A and 18B specify the calculated address and read data from the RAM or the like via a data bus or the like.

  The register groups 20 # 0 to 20 # 3 store calculation results, statuses, and the like by the calculators 18A and 18B.

  The pipeline control unit 22 controls each stage of the pipeline control as described above. Specifically, for example, the address of the program counter set corresponding to the threads # 0 to # 3 is output to the program memory according to the internal clock, and the read instruction is sent to the instruction buffers 10 # 0 to 10 #. 3 is controlled.

  The thread schedule control unit 24 sequentially operates the threads # 0 to # 3 according to the internal clock. In addition, the thread schedule control unit 24 is given an operation ratio (time distribution) of threads # 0 to # 3 from an OS or the like (not shown). This operating rate is referred to as a band. If the bandwidth is given by, for example, # 0: # 1: # 2: # 3 = 2: 2: 1: 1, the thread schedule control unit 24 operates the thread # 0 for two clocks, Thread # 1 is then activated for 2 clocks, then thread # 2 is activated for 1 clock, and then thread # 3 is activated for 1 clock. And it repeats a process in this order.

[Super scalar operation]
FIG. 2 is a partial configuration example of the multi-thread processing device 1 and is a diagram showing in more detail the internal configurations of the instruction issuing unit 12 and the thread schedule control unit 24 mainly.

  The instruction issuing unit 12 includes a simultaneous execution determination unit 12a and selectors 12b and 12c. The simultaneous execution determination unit 12a determines whether or not two instructions to be issued next among the instructions input from the instruction buffers 10 # 0 to 10 # 3 can be issued simultaneously.

  Whether or not simultaneous issue is possible is determined by other methods such as an operand check (such as checking whether a subsequent instruction uses an operation result of a previous instruction). Further, as described later, the permission or non-permission of the superscalar operation set for each thread is taken into consideration. The simultaneous execution determination unit 12a may include a buffer that stores a plurality of instructions input from the instruction buffers 10 # 0 to 10 # 3.

  The thread schedule control unit 24 includes a thread schedule setting register 24a and a superscalar permission setting register 24b. These registers store, for example, 8-bit data.

  The thread schedule setting register 24a defines a band that is an operation ratio of a plurality of threads. As described above, the thread schedule control unit 24 switches threads according to the internal clock so as to realize the set bandwidth. More specifically, a select signal is sent to the selectors 12b and 12c in synchronization with the internal clock, and control is performed so that the instruction of the thread to be operated is output to the decoders 14A and 14B. It is assumed that the simultaneous execution determination unit 12a determines in advance whether or not simultaneous issuance is possible for each thread and holds the result therein.

  When the simultaneous execution determination unit 12a performs simultaneous issuance, two consecutive instructions of the thread are output to the selectors 12b and 12c, respectively. As a result, two instructions are issued simultaneously to the instruction decoders 14A and 14B, and a superscalar operation is performed.

  FIG. 3 is an explanatory diagram for explaining how the processing efficiency is improved by the superscalar operation. In the figure, the processing flow on the left schematically shows how a single thread microcomputer performs processing using a single scalar (not performing superscalar operation). In this figure, an instruction A3 and an instruction A4 are instructions that require two clocks for reasons such as including a memory access with a large latency (a pipeline installation occurs for one clock).

  On the other hand, the flow of processing on the right side in FIG. 3 schematically shows how the single thread microcomputer performs processing by performing a superscalar operation. In this figure, instruction A1 and instruction A2, and instruction A4 and instruction A5 are instructions that cannot be executed simultaneously. For such an instruction set, instructions are not issued simultaneously and a superscalar operation is not performed. On the other hand, the instruction A2 and the instruction A3, and the instruction A5 and the instruction A6 are instructions that can be executed simultaneously. For such an instruction set, instructions are issued simultaneously and a superscalar operation is performed. As a result, it can be seen that the processing efficiency is improved as compared with the processing flow on the left side.

[Allow / disallow superscalar operation]
The superscalar permission setting register 24b defines whether or not superscalar operation is permitted for each thread. The contents of the superscalar permission setting register 24b may be rewritable from the outside depending on the security of the processing contents of the multi-thread processing device 1, or may be protected so as not to be rewritable at the user level. .

  The simultaneous execution determination unit 12a refers to the superscalar permission signal output based on the contents of the superscalar permission setting register 24b when determining whether simultaneous issuance is possible. Accordingly, simultaneous issuing is not performed for threads for which superscalar operation is not permitted in the superscalar permission setting register 24b.

  FIG. 4 is a diagram showing the flow of processing when the superscalar operation is performed only for thread # 0 when the number of threads of the multi-thread processing apparatus 1 is 2 (assumed to be # 0 and # 1). In the figure, the uppermost number indicates the number of elapsed internal clocks.

  As shown in the drawing, at the first clock, the thread # 0 executes IF (instruction fetch; output from the instruction buffer to the instruction issuing unit 12). Here, the instruction issuing unit 12 determines that the instruction of the thread # 0 is a superscalable instruction, and issues the instructions simultaneously.

  At the second clock, thread # 0 executes ID (instruction decoding; decoding processing by instruction decoders 14A and 14B) in two systems by superscalar operation, and thread # 1 executes IF.

  At the third clock, thread # 0 executes EXE (processing such as computation) in two systems by superscalar operation, and executes an IF that can be processed in parallel with this, and thread # 1 executes ID.

  At the 4th clock, thread # 0 executes MEM (memory access) in two systems by superscalar operation, and executes IDs that can be processed in parallel with two systems by superscalar operation, and thread # 1 executes EXE. Run.

  At the 5th clock, thread # 0 executes WB (write back) by two systems by superscalar operation, and EXE that can be processed in parallel with this by two systems by superscalar operation, and thread # 1 executes MEM. Run.

  As described above, the processing efficiency can be improved by performing the superscalar operation on the instruction sequence capable of performing the superscalar operation while sequentially executing the instructions by the pipeline control.

  In addition, real time processing can be ensured by not simultaneously issuing threads that are not permitted to perform superscalar operations in the superscalar permission setting register 24b.

  As described above, in many cases, it is not known in advance whether or not the instructions executed by the multithread processing apparatus 1 can be issued simultaneously. In particular, the frequency of occurrence of superscalar operations tends to be unpredictable, such as after a branch instruction is executed. Therefore, when the superscalar operation is permitted, the reliability (the real-time property of the process) that a specific process is performed at a specific timing is lowered.

  Ensuring real-time processing is often important when integrating the functions of multiple microcomputers into a single multi-thread processing device, especially when applied to an in-vehicle controller that integrates multiple functions. .

  FIG. 5 shows real time when a plurality of ECUs (Electronic Control Units) are integrated into a single multi-thread processing device in which a CPU, a RAM, a ROM, an I / O port, and the like are connected via a bus. It is a figure which shows a mode that property is ensured.

  Here, ECU #A to ECU #D operating at 50 [MHz] are integrated, and the functions are integrated into a multi-thread processing device operating at 200 [MHz]. The processes performed by ECU #A to ECU #D are executed by threads # 0 to # 3, respectively. As a premise, the processing performed by ECU #A to ECU #C has a low importance of real-time property, and it is desirable to end the processing quickly. However, the processing performed by ECU #D has the importance of real-time property. High.

  In this case, superscalar operation is permitted for threads # 0 to # 2 that execute the functions of ECU # A to ECU # C, but superscalar operation is not permitted for thread # 3 that executes the functions of ECU # D. Set as follows.

  As a result, as shown in FIG. 5, the processing performed by the ECUs #A to ECU # C in the related art is shortened by the superscalar operation, and ends early. Specifically, instruction A5 is processed in parallel with instruction A4, instruction B5 is processed in parallel with instruction B4, and instruction C5 is processed in parallel with instruction C4. On the other hand, since the super-scalar operation is not performed for the processing conventionally performed by the ECU #D, the instruction execution timing with respect to the number of elapsed internal clocks does not vary. Therefore, the processing can be executed at the same timing as the processing timing that the ECU #D has conventionally performed.

  According to the multithread processing apparatus 1 of the present embodiment described above, it is possible to perform the efficiency process by the superscalar operation and to secure the real time property of the process.

<Application example>
Hereinafter, the case where the multithread processing device 1 of the present embodiment is applied to an in-vehicle control device that performs in-vehicle device control will be described.

  FIG. 6 is a diagram conceptually showing the system configuration of the in-vehicle control device to which the multi-thread processing device 1 of this embodiment is applied. This in-vehicle control device is configured as the above-described ECU, and integrates four functions of ECU management, system #A, system #B, and system #C. The software is constructed so that these four functions are executed by the threads # 0 to # 3, respectively.

  Of these functions, ECU management and system #B are less important for real-time processing, and always allow superscalar operation. Since system #A is highly important for real-time processing, superscalar operation is not permitted. In the system #C, since real-time processing varies depending on the vehicle state, permission / non-permission of superscalar operation varies (superscalar dynamic control). In this case, the contents of the superscalar permission setting register 24b are rewritten by an instruction from the OS (not shown).

  Here, two patterns of superscalar dynamic control when applied to an in-vehicle control device are illustrated.

  (1) When the multi-thread processing device 1 is applied to a driving support system, for example, permission / non-permission of superscalar operation varies with a shift position as a trigger. The shift position is grasped by a signal input from a shift position sensor attached to the shift lever.

  In this case, when the shift position is D (drive), a specific thread in the in-vehicle control device performs processing for auto-cruise control or a collision safety system, and when the shift position is R (reverse). A back monitor that displays the rear of the vehicle in the passenger compartment and a process for parking support control are performed.

  Auto-cruise control and collision safety systems do not allow superscalar operation because real-time processing is required. Specifically, it is necessary to keep the sampling period of the sensor output value (for example, the vehicle speed) substantially constant.

  On the other hand, super-scalar operation is permitted because back-monitoring and parking support control do not require real-time processing. Therefore, when the shift position is D, the thread of the vehicle-mounted control device disallows the superscalar operation, and permits the superscalar operation when the shift position is R.

  (2) When the multi-thread processing device 1 is applied to an engine control system, for example, permission / non-permission of superscalar operation varies depending on the engine speed. The engine speed can be calculated based on a value input from a crank angle sensor attached to the crankshaft of the engine.

  When the engine speed is low, particularly during idling, it is necessary to accurately control the engine speed in order to improve fuel consumption, and therefore the importance of real-time processing is increased. Therefore, superscalar operation is not permitted.

  On the other hand, when the engine speed is high, a calculation process that is faster than the processing timing is desired, and the real-time property of the process is less important. Therefore, superscalar operation is permitted.

  The thread of the vehicle-mounted control device permits the superscalar operation when the engine speed is equal to or higher than the reference value, and disallows the superscalar operation when it is less than the reference value.

  Thus, by dynamically changing the permission / non-permission of the superscalar operation, it is possible to execute the instruction in a manner that matches the characteristics of the process requested by the controlled object.

  The best mode for carrying out the present invention has been described above with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. And substitutions can be added.

DESCRIPTION OF SYMBOLS 1 Multithread processing apparatus 10 # 0-10 # 3 Instruction buffer 12 Instruction issuing part 12a Simultaneous execution determination part 12b, 12c Selector 14A, 14B Instruction decoder 16A, 16B Register acquisition part 18A, 18B Calculator 20 # 0-20 # 3 Register group 22 Pipeline control unit 24 Thread schedule control unit 24a Thread schedule setting register 24b Super scalar permission setting register

Claims (4)

Having a plurality of processing means,
A multi-thread processing device that performs hardware multi-threading using any of the plurality of processing means,
Permits superscalar operation using two or more processing means of the plurality of processing means for each of the threads that execute processing for in-vehicle device control among the plurality of threads related to the hardware multithreading Or disallowance ,
The permission or non-permission of superscalar operation for at least some of the plurality of threads is dynamically changed according to a vehicle state of a vehicle on which the multi-thread processing device is mounted .
Multi-thread processing unit. The multi-thread processing apparatus according to claim 1,
The permission or disapproval of the superscalar operation for the plurality of threads is defined by a data table stored in a predetermined storage device,
Multi-thread processing unit. The multi-thread processing apparatus according to claim 1 or 2 ,
It said vehicle condition includes the shift position,
Permission or non-permission of superscalar operation for at least a portion of the plurality of threads, characterized in that it is dynamically changed according to the shift position,
Multi-thread processing unit. The multi-thread processing apparatus according to claim 1 or 2 ,
It said vehicle condition includes an engine speed,
Permission or non-permission of superscalar operation for at least a portion of the plurality of threads, characterized in that it is dynamically changed according to the engine rotational speed,
Multi-thread processing unit.

Images