JP5528301B2 - Touch panel and display device including the same - Google Patents

Description

  The present invention relates to a touch panel and a display device including the touch panel.

  The touch panel is a device that detects a touch with a finger or the like and specifies position coordinates of a touched position. The touch panel is attracting attention as one of excellent user interface means. Various types of touch panels such as a resistive film type and a capacitance type have been commercialized.

  As one of capacitive touch panels, there is a projected capacitive touch panel (see, for example, Patent Document 1). The projected capacitive touch panel can detect a touch even when the front surface of a touch screen with a built-in touch sensor is covered with a protective plate such as a glass plate having a thickness of about several millimeters. This type of touch panel has advantages such as the fact that the protective plate can be placed on the front surface, so it is excellent in robustness, can detect touch even when wearing gloves, and has a long life because there is no moving part. Yes.

  The touch screen constituting the touch panel described in Patent Document 1 includes a first series conductor element formed on a thin dielectric film as a detection wiring for detecting capacitance, and a first series conductor element. And a second series of conductor elements formed with an insulating film therebetween. There is no electrical contact between the conductor elements, and a plurality of intersections are formed. By detecting a capacitance formed between an indicator such as a finger and a conductor element that is a detection wiring with a detection circuit, the position coordinates of the position touched by the indicator are specified.

JP-T 9-51186 (page 7, line 19 to page 8, line 4, page 8, line 23 to page 9, line 6, page 13, line 4 to line 12, page 13, line 23 to page 14) Page 10 line, FIG. 1, FIG. 2, FIG. 6, FIG. 8)

  The detection sensitivity of the capacitance in the touch panel is greatly influenced by the parasitic capacitance of the detection wiring and the detection circuit of the touch screen. If the parasitic capacitance is extremely large compared to the capacitance formed between the indicator such as a finger and the detection wiring (hereinafter sometimes referred to as “touch capacitance”), the desired detection sensitivity for the touch capacitance Cannot be obtained, or the detection time increases in order to obtain a desired detection sensitivity.

  An object of the present invention is to provide a touch panel capable of obtaining a desired detection sensitivity with respect to a touch capacitance and a display device including the same in a detection time as short as possible.

The touch panel of the present invention, have a plurality of test Dehai lines arranged in the row and column directions, the plurality of detection wires, the plurality of detection wires constituted by the detection wiring in the number of predetermined a touch screen that is divided into sets, wherein each provided corresponding to multiple detection wire assembly, a plurality of selection switches for selecting the test Dehai lines included in the corresponding detection wiring sets sequentially, the plurality one on the detection wire pairs respectively provided corresponding has a detection node that said analyzing Dehai line selected by the selection switch circuit corresponding to the corresponding detection wire pair are electrically connected sequentially is the operating state, and a plurality of capacitance detection circuits for detecting an electrostatic capacitance of the connected said analyzing Dehai line to the detection node are sequentially detected by the capacitance detection circuit of the multiple obtained from the capacitance, the electrostatic capacitance Based on the values given as the detection result, and a touch coordinate calculation circuit for calculating the touch coordinates representing the position of the indicator in the touch screen, the plurality of detection wires, a plurality of which extends in the row direction And a plurality of column detection wirings that intersect with each of the row detection wirings and extend in the column direction, and the plurality of detection wiring groups are configured by a predetermined number of the row detection wirings. A plurality of row detection wiring sets, and a plurality of column detection wiring sets configured by a predetermined number of the column detection wirings, and the plurality of selection switch circuits respectively correspond to the plurality of row detection wiring sets. A plurality of row selection switch circuits for sequentially selecting the row detection wirings included in the corresponding row detection wiring group, and corresponding column detection wirings provided corresponding to the plurality of column detection wiring groups, respectively. Characterized in that it comprises a plurality of column selection switch circuit for sequentially selecting the column sensing lines contained.

  Moreover, the display device of the present invention includes the touch panel and a display panel attached to the touch screen of the touch panel.

According to the touch panel of the present invention, a touch panel includes a touch screen, a plurality of selection switch circuits, a plurality of capacitance detection circuits, and a touch coordinate calculation circuit . The touch screen has a plurality of detection wirings arranged in the row direction and the column direction. A plurality of test Dehai line is divided into a plurality of detection wires set consists of detection wires in the number specified in advance. The plurality of selection switch circuits provided corresponding to the plurality of detection wiring groups sequentially select the detection wirings included in the corresponding detection wiring group, and one corresponding to each of the plurality of detection wiring groups is provided. is Ru is electrically connected to the detection node of the plurality of capacitance detection circuits. The plurality of capacitance detection circuits are sequentially activated, and the capacitance of the detection wiring connected to the detection node is detected. Obtained from the capacitance that will be sequentially detected at a plurality of capacitance detection circuits based on the value given as the detection result of the capacitance, the touch coordinate calculation circuit, touch representing the position of the pointer on the touch screen Coordinates are calculated. The plurality of detection wirings include a plurality of row detection wirings extending in the row direction, and a plurality of column detection wirings that intersect each row detection wiring and extend in the column direction. The plurality of detection wiring groups include a plurality of row detection wiring groups configured by a predetermined number of row detection wirings and a plurality of column detection wiring groups configured by a predetermined number of column detection wirings. The plurality of selection switch circuits are provided corresponding to the plurality of row detection wiring groups, respectively, and a plurality of row selection switch circuits for sequentially selecting the row detection wirings included in the corresponding row detection wiring group, and a plurality of column detection wirings And a plurality of column selection switch circuits that are provided corresponding to the groups and sequentially select the column detection wirings included in the corresponding column detection wiring group.

  As a result, the detection node of the capacitance detection circuit is used as a reference compared to the case where a plurality of detection wirings are selected by the same selection switch circuit and connected to the detection node of the same capacitance detection circuit. Thus, the parasitic capacitance of the selection switch circuit can be reduced. Therefore, it is possible to improve the detection sensitivity of the capacitance (hereinafter sometimes referred to as “touch capacitance”) formed between the indicator and the detection wiring in the detection time that is restricted from the desired response time. . Specifically, the detection value of the capacitance with respect to the touch capacitance can be increased. Moreover, the calculation accuracy of touch coordinates can be improved. Further, it is possible to shorten the detection time required for obtaining the detection sensitivity of the touch capacitance required from the desired touch coordinate accuracy, specifically, the magnitude of the detection value of the capacitance with respect to the touch capacitance. From the above, it is possible to realize a touch panel that can obtain a desired detection sensitivity for the touch capacitance in as short a detection time as possible.

  According to the display device of the present invention, the display device is configured by including the above-described touch panel and display panel of the present invention. Therefore, it is possible to realize a display device having a touch panel function capable of obtaining a desired detection sensitivity for the touch capacitance in a detection time as short as possible.

It is a top view which shows the structure of the touch screen 1 in the touchscreen which is the 1st Embodiment of this invention. FIG. 2 is a perspective sectional view showing a configuration of a part of the touch screen 1 shown in FIG. 1. It is a figure which shows typically the whole structure of the touch panel 100 which is the 1st Embodiment of this invention. FIG. 2 is a block diagram showing a configuration of a touch screen 1 and a detection processing circuit 19 in the first embodiment of the present invention. FIG. 5 is a block diagram showing a configuration of a first column selection switch circuit X (1) 20a shown in FIG. 2 is a diagram showing a configuration of a capacitance detection circuit 21. FIG. It is a timing chart which shows the sequence of the touch detection operation | movement in the 1st Embodiment of this invention. It is a timing chart which shows the sequence of the touch detection operation | movement in the 1st Embodiment of this invention. It is a figure which shows the structure of the part which applies the buffering voltage of a detection voltage to the non-selection detection wiring in the 1st Embodiment of this invention. It is a figure which shows the structure of the part which applies the buffering voltage of a detection voltage to the non-selection detection wiring in a comparative example. It is a block diagram which shows the structure of the touch screen 1 and the detection processing circuit 19A in the 2nd Embodiment of this invention. It is a timing chart which shows the sequence of the touch detection operation | movement in the 2nd Embodiment of this invention. It is a timing chart which shows the sequence of the touch detection operation | movement in the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the liquid crystal display device which is the 3rd Embodiment of this invention. It is a characteristic view which shows an example of the relationship between the electrostatic capacitance connected to the relaxation oscillation circuit used for the touch panel of the premise technique of this invention, and an oscillation period. It is a figure which shows the relationship between an oscillation period and detection time.

<Prerequisite technology>
FIG. 15 is a characteristic diagram showing an example of the relationship between the capacitance connected to the relaxation oscillation circuit used in the touch panel of the base technology of the present invention and the oscillation period. FIG. 16 is a diagram illustrating the relationship between the oscillation period and the detection time.

  The touch panel includes a touch screen in which detection wirings are arranged in a matrix, and a detection circuit that detects contact of an indicator with the touch screen, that is, a touch. The detection wiring is connected to a capacitance control oscillator, which is a detection circuit, via an output line and a multiplexer circuit.

  As the capacity control oscillator, for example, a relaxation oscillation circuit can be used. The oscillation period of the relaxation oscillation circuit is determined according to, for example, a time constant due to charging / discharging of the resistance element and the capacitance element. The relaxation oscillation circuit detects a change ΔC in capacitance (hereinafter referred to as “touch capacitance”) formed between an indicator such as a finger and the detection wiring of the touch screen as a change Δt in the oscillation period.

  The relationship between the capacitance connected to the relaxation oscillation circuit and the oscillation cycle is linear, that is, linear, as shown in FIG. A detection value for the touch capacitance can be obtained by integrating the oscillation cycle deviation when the touch capacitance is generated for a predetermined oscillation cycle, that is, for a predetermined number N. The oscillation period deviation when the touch capacitance Ct occurs is constant regardless of the values of other capacitances, for example, the parasitic capacitance of the detection circuit and the detection wiring.

  However, as shown in FIG. 15, the oscillation period increases as the capacitance connected to the detection end of the relaxation oscillation circuit increases. For example, when the capacitance connected to the detection end of the relaxation oscillation circuit changes from the first capacitance Cp1 to the second capacitance Cp2 (Cp2> Cp1) that is larger than that, the oscillation cycle is The second oscillation period Tc2 (Tc2> Tc1) is larger than the first oscillation period Tc1, which is the oscillation period when the capacitance Cp1 is 1.

  As described above, the detection value for the touch capacitance is obtained by integrating the oscillation period for a predetermined oscillation period, that is, for a predetermined number N. Therefore, as the electrostatic capacitance as the parasitic capacitance increases, the time required for integrating the oscillation period is increased accordingly, and the detection time required to obtain a desired detection value for the touch capacitance is also shown in FIG. It will grow as shown. This increases the response time from when the touch screen is touched by the user's finger or the like until the touch coordinate data is output from the touch panel, and the responsiveness to the touch is reduced.

  Further, when the number of times of oscillation cycle integration is reduced in order to satisfy a desired detection time, the detection value for the touch capacitance is reduced. Thereby, the detection sensitivity with respect to the touch capacitance is lowered, and the accuracy of the position coordinate data of the touch position calculated based on the detection value is lowered.

  As described above, the detection sensitivity and response time for a touch on the touch panel greatly depend on the parasitic capacitance at the detection end of the detection circuit. This applies similarly even when a detection method other than the relaxation oscillation method is used.

  The capacitance that is the parasitic capacitance at the detection end of a detection circuit such as a relaxation oscillation circuit is the capacitance of the cross section (hereinafter referred to as “cross section capacitance”) that is the intersection of the detection wirings provided in the row and column directions. And a parasitic capacitance of a multiplexer circuit for switching the connection between the detection wiring and the detection circuit. In particular, the parasitic capacitance of the multiplexer circuit is dominant in the parasitic capacitance of the detection circuit. The parasitic capacitance of the multiplexer circuit that switches the connection between the detection wiring of the touch screen and the detection circuit depends on the number of the detection wirings that switch the connection. As an example, when the number of detection wirings is 32, the parasitic capacitance of the multiplexer circuit reaches about 150 pF.

  However, the touch capacitance is formed only about several pF at most. In particular, when a glass plate or the like is provided on the front surface of the touch screen to ensure robustness, the touch capacity further decreases. Accordingly, the response time increases as the detection time for obtaining a desired detection value increases. Alternatively, the detection value decreases to satisfy a desired response time. And the precision of the touch coordinate data calculated based on this detection value falls.

  The parasitic capacitance of the detection circuit, such as the parasitic capacitance of the multiplexer circuit that switches the connection between the detection wiring and the detection end of the detection circuit, is detected when the number of detection wirings increases as the touch screen increases in size. It increases as the number of wires increases. Furthermore, in order to reduce the noise from the display device used in combination on the back side of the touch screen, if it is configured to provide an electrostatic shield surface on the back side of the touch screen detection wiring, The parasitic capacitance of the wiring also increases. In particular, when the touch screen is increased in size, the parasitic capacitance of the detection wiring increases as the wiring length of the detection wiring increases.

  As described above, the parasitic capacitance of the detection circuit and the detection wiring affects the touch detection time and detection sensitivity on the touch screen, and thus affects the response and coordinate accuracy of the touch panel. Since this influence becomes more prominent as the touch screen becomes larger, it becomes a problem for the enlargement of the touch screen. Therefore, in the present invention, the configurations of the following embodiments are employed.

<First Embodiment>
FIG. 1 is a plan view showing a configuration of a touch screen 1 in a touch panel according to a first embodiment of the present invention. The touch screen 1 includes a plurality of detection column wirings 2 and a plurality of detection row wirings 3. The plurality of detection column wirings 2 extend in the column direction, in the vertical direction toward the paper surface in FIG. 1, and are arranged in parallel in the row direction at a predetermined pitch and in the horizontal direction in FIG. . The plurality of detection row wirings 3 extend in the row direction and are arranged in parallel in the column direction at a predetermined pitch.

  In the present embodiment, a plurality of, for example, a predetermined number of detection column wirings 2 are electrically connected in common by the column connection wirings 4 at one end and the other end, respectively, at the upper end and the lower end in FIG. Thus, a bundle of detection column wiring groups 6 is configured. Similarly, a plurality of, for example, a predetermined number of detection row wires 3 are electrically connected in common by the row connection wires 5 at one end and the other end, respectively, at the left end and the right end in FIG. A bundle detection row wiring group 7 is formed. Therefore, a slit-shaped opening is formed between the detection column wirings 2 of each detection column wiring group 6. Similarly, a slit-shaped opening is formed between the detection row wirings 3 of each detection row wiring group 7.

  In FIG. 1, a bundle of detection column wiring groups 6 includes five detection column wirings 2, and a bundle of detection row wiring groups 7 includes five detection row wirings 3. Configured.

  In the touch screen 1, a row direction in which the detection row wiring group 7 extends is defined as “x-axis direction”, and a column direction in which the detection column wiring group 6 extends is defined as “y-axis direction”. Is defined. The detection row wiring group 7 and the detection column wiring group 6 are orthogonal to each other, and the x-axis direction and the y-axis direction are orthogonal to each other. In the following description, the row direction may be referred to as “row direction x” and the column direction may be referred to as “column direction y”.

  In the present embodiment, a plurality of, for example, a predetermined number of detection column wiring groups 6 are arranged in parallel in the row direction x at intervals. Similarly, a plurality of, for example, a predetermined number of detection row wiring groups 7 are arranged in parallel at intervals in the column direction y. In FIG. 1, one of the detection column wiring group 6 and the detection row wiring group 7 (hereinafter, the detection column wiring group 6 and the detection row wiring group 7 may be collectively referred to as “detection wiring group”). The illustration of the part is omitted.

  As will be described later, in the present embodiment, the predetermined number of the detection column wiring group 6 which is the detection wiring group in the column direction y is 2m (m is a positive integer), and the detection wiring in the row direction x. The predetermined number of detection row wiring groups 7 as a group is 2n (n is a positive integer). Hereinafter, each of the detection wiring groups 6 and 7 may be referred to as a system, and the predetermined number of the detection wiring groups 6 and 7 may be referred to as a system number. In the present embodiment, the detection column wiring group 6 which is a detection wiring group in the column direction y is a 2m system, and the detection row wiring group 7 which is a detection wiring group in the row direction x is a 2n system.

  The detection wiring groups 6 and 7 are connected to the terminal 10 by lead wirings 8 and 9. In the present embodiment, when the indicator touches the touch screen 1, the detection column wiring 2 and the detection row wiring 3 (hereinafter referred to as the detection column wiring 2 and the detection wiring) constituting the detection wiring groups 6 and 7. A touch capacitor is formed between the indicator and the row wiring 3 as a generic term “detection wiring”. The number and the wiring pitch of the detection wiring groups 6 and 7 and the number, the wiring width and the wiring pitch of the detection wirings 2 and 3 constituting the detection wiring groups 6 and 7 are determined by the touch position of the indicator on the touch panel. Specifically, the touch position is appropriately selected from the required resolution of the coordinate value on the touch screen 1 (hereinafter sometimes referred to as “touch coordinate value”).

  Here, instead of each of the detection wiring groups 6 and 7 constituted by a plurality of detection wirings 2 and 3, if a wiring constituted by a so-called solid wiring having no opening in the wiring is provided, the touch Large capacity can be secured. However, when a touch panel is used in front of the display panel, the solid wiring is a factor that prevents transmission of light used for display on the display panel (hereinafter sometimes referred to as “display light”). As a result, the transmittance of display light is reduced.

  Therefore, in the present embodiment, the detection wiring groups 6 and 7 are configured by the plurality of detection wirings 2 and 3 as described above, and the area of the slit-shaped opening between the detection wirings 2 and 3 is determined. Is set to a large value to suppress a decrease in the transmittance of the display light. As the detection wirings 2 and 3, for example, thin conductive wires having a diameter of 10 μm to 20 μm can be used.

  However, a modification in which a single wiring, which is a so-called solid wiring, is provided instead of the detection wiring groups 6 and 7 may be applied in view of the problem of a decrease in the transmittance of display light. . As the detection wirings 2 and 3 in the case where such a modification is applied, for example, a light-transmitting conductive material (hereinafter referred to as “translucent conductive”) such as indium tin oxide (abbreviation: ITO). Material)). When visibility of the detection wirings 2 and 3 becomes a problem on display, it is preferable to use a light-transmitting conductive material such as ITO. By using a light-transmitting conductive material such as ITO, the visibility of the detection wirings 2 and 3 can be lowered, so that a decrease in the transmittance of display light can be suppressed.

  FIG. 2 is a perspective sectional view showing a configuration of a part of the touch screen 1 shown in FIG. 2 corresponds to a perspective view of the touch screen 1 shown in FIG. 1 as viewed obliquely from the front side of the drawing in FIG. 1, and shows a layer structure in the thickness direction of the touch screen 1.

  The touch screen 1 includes a translucent transparent substrate (hereinafter referred to as “base substrate”) 12, an interlayer insulating film 13, and a protective film 14. The base substrate 12 is a layer constituting a surface on one side in the thickness direction of the touch screen 1. More specifically, the base substrate 12 has translucency and insulation, and is made of an insulating material having translucency such as transparent glass and transparent resin. In the present embodiment, the base substrate 12 is made of transparent glass.

  On the surface on the other side in the thickness direction of the base substrate 12, the plurality of detection column wirings 2 are formed, and the detection column wiring group 6 is configured by the detection column wirings 2. The detection column wiring 2 is composed of a conductive film made of a conductive material. Examples of the conductive material include metal wiring materials such as copper (Cu) and aluminum (Al), and light-transmitting conductive materials (hereinafter sometimes referred to as “transparent wiring material”) such as ITO. In the present embodiment, a transparent wiring material is used as the conductive material, and the detection column wiring 2 is realized by a transparent wiring made of a transparent wiring material.

  A transparent interlayer insulating film 13 is formed on the other side in the thickness direction of the base substrate 12, and below the base substrate 12 in FIG. The interlayer insulating film 13 has a light-transmitting property and an insulating property and is made of a light-transmitting insulating material such as silicon nitride (SiN). The plurality of detection row wirings 3 described above are formed on the surface of the interlayer insulating film 13 on the other side in the thickness direction, and the detection row wiring group 7 is configured by these detection row wirings 3. The detection row wiring 3 is made of the same conductive film as the detection column wiring 2. In the present embodiment, the detection row wiring 3 is realized by a transparent wiring in the same manner as the detection column wiring 2.

  Although different from the present embodiment, the arrangement positions of the detection column wirings 2 and the detection row wirings 3 in the thickness direction of the base substrate 12 are reversed, and the detection rows are formed on the surface of the base substrate 12 on the other side in the thickness direction. The wiring 3 may be formed, and the detection column wiring 2 may be formed on the surface of the interlayer insulating film 13 on the other side in the thickness direction. The detection wirings 2 and 3 may be realized not by a transparent wiring using a transparent wiring material such as ITO but by a metal wiring using a metal wiring material such as aluminum. In this case, as described above, the detection wiring groups 6 and 7 are constituted by the plurality of detection wirings 2 and 3, and the area of the slit opening between the detection wirings 2 and 3 is increased. By setting, the transmittance for display light can be secured.

  A transparent protective film 14 is formed on the other side in the thickness direction of the interlayer insulating film 13, that is, below the interlayer insulating film 13 in FIG. The protective film 14 has a light-transmitting property and an insulating property, and is made of a light-transmitting insulating material such as SiN, like the interlayer insulating film 13.

  FIG. 3 is a diagram schematically showing the overall configuration of the touch panel 100 according to the first embodiment of the present invention. The touch panel 100 includes the touch screen 1 shown in FIGS. 1 and 2, a flexible printed circuit (abbreviated as FPC) 17, and a controller substrate 18.

  A terminal provided at one end of the FPC 17 is mounted on the terminal 10 shown in FIG. 1 of the touch screen 1 by using an anisotropic conductive film (abbreviation: ACF) or the like. The terminals 10 of the touch screen 1 are not shown in FIG. A terminal provided at the other end of the FPC 17 is mounted on the controller board 18. Through the FPC 17, the ends of the detection wiring groups 6 and 7 of the touch screen 1 and the controller board 18 are electrically connected. As a result, the panel shown in FIG. 3 functions as the touch panel 100.

  The controller board 18 performs detection processing for calculating the touch position of the indicator, more specifically, the coordinates of the touch position on the touch screen 1 (hereinafter referred to as “touch coordinates”) based on the detection result of the touch capacitance. A circuit 19 is mounted. The touch coordinate value calculated by the detection processing circuit 19, that is, the touch coordinate value is output as detected coordinate data to an external computer (not shown).

  FIG. 4 is a block diagram showing configurations of the touch screen 1 and the detection processing circuit 19 in the first embodiment of the present invention. In the present embodiment, for convenience of explanation, the number of the detection column wiring groups 6 and the detection row wiring groups 7 of the touch screen 1 is assumed to be an even number. Specifically, a case where the number of the detection column wiring groups 6 of the touch screen 1 is 2 m (m is a positive integer) and the number of the detection row wiring groups 7 is 2n (n is a positive integer) will be described. To do. The number of the detection column wiring group 6 and the detection row wiring group 7 is not limited to an even number, and may be an odd number. Even if the number of the detection column wiring groups 6 and the detection row wiring groups 7 is an odd number, it can be implemented in the same manner as in the case of an even number.

  In the following description, the detection column wiring group 6 may be simply referred to as “column detection wiring”, and the detection row wiring group 7 may be simply referred to as “row detection wiring”. The column detection wiring 6 and the row detection wiring 7 may be collectively referred to as “detection wiring”.

  In the present embodiment, 2m column detection wirings 6 are divided into two column detection wiring groups. The two column detection wiring sets include a first column detection wiring set X (1) and a second column detection wiring set X (2).

  The first column detection wiring set X (1) includes m column detection wirings 6 from the first to the m-th among the 2m column detection wirings 6. Hereinafter, the first to m-th column detection wirings 6 are referred to as “first to m-th column detection wirings Wx (1) to Wx (m)” or “first to m-th detection column wiring groups Wx (1). ) To Wx (m) ".

  The second column detection wiring set X (2) includes m column detection wirings 6 from the (m + 1) th to the 2mth among the 2m column detection wirings 6. Hereinafter, the (m + 1) th to 2mth column detection wirings 6 are referred to as “m + 1 to 2m column detection wirings Wx (m + 1) to Wx (2m)” or “m + 1 to 2m detection column wiring groups Wx (m + 1)”. ) To Wx (2 m) ".

  In this embodiment, 2n row detection wirings 7 are divided into two row detection wiring groups. The two row detection wiring sets include a first row detection wiring set Y (1) and a second row detection wiring set Y (2).

  The first row detection wiring set Y (1) includes the first to nth row detection wirings 7 from the 2n row detection wirings 7. Hereinafter, the first to nth row detection wirings 7 are referred to as “first to nth row detection wirings Wy (1) to Wy (n)” or “first to nth detection row wiring groups Wy (1). ) To Wy (n) ".

  The second row detection wiring set Y (2) includes n row detection wirings 7 from the (n + 1) th to the 2nth among the 2n row detection wirings 7. Hereinafter, the (n + 1) th to 2nth row detection wirings 7 are referred to as “n + 1 to 2nth row detection wirings Wy (n + 1) to Wy (2n)” or “n + 1st to 2nth detection row wiring groups Wy (n + 1)”. ) To Wy (2n) ".

  The detection processing circuit 19 includes selection switch circuits 20a to 20d, capacitance detection circuits 21a to 21d, buffer circuits 22a to 22d, subsequent switch circuits 23a to 23d, a selector circuit 24, a first counting circuit 25, and a second counting circuit 26. The touch coordinate calculation circuit 27 and the detection control circuit 28 are included. The detection control circuit 28 includes hardware resources including selection switch circuits 20a to 20d, capacitance detection circuits 21a to 21d, rear-stage switch circuits 23a to 23d, a selector circuit 24, a first counting circuit 25, and a second counting circuit 26. Control all over.

  The first counting circuit 25 corresponds to a first counting circuit. The second counting circuit 26 corresponds to a second counting circuit. The selection switch circuits 20a to 20d also function as a common node voltage application unit. The selection switch circuits 20a to 20d, the buffer circuits 22a to 22d, and the post-stage switch circuits 23a to 23d as common node voltage application means constitute detection voltage application means.

  The selection switch circuits 20a to 20d include a first column selection switch circuit X (1) 20a, a second column selection switch circuit X (2) 20b, a first row selection switch circuit Y (1) 20c, and a second row selection switch circuit. Y (2) 20d is included. The capacitance detection circuits 21a to 21d include a first column capacitance detection circuit X (1) 21a, a second column capacitance detection circuit X (2) 21b, and a first row capacitance detection circuit Y (1). 21c and second row capacitance detection circuit Y (2) 21d.

  The buffer circuits 22a to 22d include a first column buffer circuit 22a, a second column buffer circuit 22b, a first row buffer circuit 22c, and a second row buffer circuit 22d. The post-stage switch circuits 23a to 23d include a first column post-stage switch circuit 23a, a second column post-stage switch circuit 23b, a first row post-stage switch circuit 23c, and a second row post-stage switch circuit 23d. The plurality of rear switch circuits 23a to 23d are provided in the subsequent stage of the buffer circuits 22a to 22d.

  Hereinafter, when an unspecified selection switch circuit, an unspecified capacitance detection circuit, an unspecified buffer circuit, and an unspecified back-stage switch circuit are shown, “selection switch circuit 20”, “capacitance detection circuit 21”. ”,“ Buffer circuit 22 ”, and“ second-stage switch circuit 23 ”, the suffixes“ a ”to“ d ”of reference numerals may be omitted.

  The two column detection wiring groups X (1) and X (2) are distributed and connected to the first column selection switch circuit X (1) 20a and the second column selection switch circuit X (2) 20b, respectively. Similarly, the two row detection wiring groups Y (1) and Y (2) are distributed and connected to the first row selection switch circuit Y (1) 20c and the second row selection switch circuit Y (2) 20d, respectively. .

  Specifically, the first column detection wiring set X (1) is connected to the first column selection switch circuit X (1) 20a, and the second column detection wiring set X (2) is connected to the second column selection switch circuit X (1) 20a. Connected to the switch circuit X (2) 20b. The first row detection wiring set Y (1) is connected to the first row selection switch circuit Y (1) 20c, and the second row detection wiring set Y (2) is connected to the second row selection switch circuit Y (2). 2) Connected to 20d.

  The first column selection switch circuit X (1) 20a is based on the control signal given from the detection control circuit 28, and the first column detection wiring set X (1) and the first column capacitance detection circuit X (1). The connection state with 21a is switched. The second column selection switch circuit X (2) 20b is based on the control signal supplied from the detection control circuit 28, and the second column detection wiring set X (2) and the second column capacitance detection circuit X (2). The connection state with 21b is switched.

  Similarly, the first row selection switch circuit Y (1) 20c is connected to the first row detection wiring set Y (1) and the first row capacitance detection circuit Y based on a control signal supplied from the detection control circuit 28. (1) The connection state with 21c is switched. The second row selection switch circuit Y (2) 20d is connected to the second row detection wiring set Y (2) and the second row capacitance detection circuit Y (2) based on the control signal supplied from the detection control circuit 28. The connection state with 21d is switched.

  In FIG. 4, a first column capacitance detection circuit X (1) 21a, a second column capacitance detection circuit X (2) 21b, a first row capacitance detection circuit Y (1) 21c, and a second row static. The detection nodes of the capacitance detection circuit Y (2) 21d are described as Nx (1), Nx (2), Ny (1), and Ny (2), respectively. Each electrostatic capacitance detection circuit 21a-21d detects the electrostatic capacitance connected to the detection node of an own circuit.

  When the relaxation oscillation circuit described in the base technology is used as the capacitance detection circuits 21a to 21d, the charge / discharge resistance elements connected to the detection nodes of the capacitance detection circuits 21a to 21d, The parasitic capacitances of the selection switch circuits 20a to 20d connected to the capacitance detection circuits 21a to 21d, the parasitic capacitances of the column detection wiring 6 and the row detection wiring 7 of the touch screen 1, and the like of each capacitance detection circuit 21a to 21d. This is a parasitic capacitance connected to the detection node.

  In the present embodiment, the column detection wiring 6 and the row detection wiring 7 are divided into two groups, and in each group, connection to the detection nodes of the capacitance detection circuits 21a to 21d provided corresponding to each group is performed. These are configured to be switched by selection switch circuits 20a to 20d provided corresponding to each set.

  On the other hand, in the detection processing circuit of the prior art, there is one capacitance detection circuit, and the capacitance detection circuit has one detection node. In the detection processing circuit 19 according to the present embodiment, the detection node of the capacitance detection circuit, which has conventionally been one (one node), is divided into a plurality, specifically four (four nodes), as described above. doing.

  The parasitic capacitance of the detection processing circuit is mainly occupied by the parasitic capacitance of the selection switch circuit that switches the connection between the detection wiring and the capacitance detection circuit. As described above, in the detection processing circuit 19 of the present embodiment, a plurality of capacitance detection circuits 20a to 20d are provided and the detection node is divided into a plurality of detection nodes. In comparison, the parasitic capacitance of the selection switch circuit that occupies mainly the parasitic capacitance of the detection processing circuit can be reduced. Specifically, in the present embodiment, four capacitance detection circuits 20a to 20d are provided and the detection node is divided into four, so that the parasitic capacitance of the selection switch circuit is approximately 4 minutes. It can be reduced to 1 (1/4).

  The capacitance detection circuits 21a to 21d are connected to the buffer circuits 22a to 22d through the post-stage switch circuits 23a to 23d. The first column capacitance detection circuit 21a is connected to the first column buffer circuit 22a via the first column post-stage switch circuit 23a. The second column capacitance detection circuit 21b is connected to the second column buffer circuit 22b via the second column post-stage switch circuit 23b. The first row capacitance detection circuit 21c is connected to the first row buffer circuit 22c via the first row post-stage switch circuit 23c. The second row capacitance detection circuit 21d is connected to the second row buffer circuit 22d via the second row latter stage switch circuit 23d. Each buffer circuit 22a-22d buffers and outputs the voltage of the detection node of corresponding electrostatic capacitance detection circuit 21a-21d.

  One ends of the post-stage switch circuits 23a to 23d are connected to the outputs of the corresponding buffer circuits 22a to 22d. The other ends of the post-stage switch circuits 23a to 23d are connected in common. This commonly connected node (hereinafter sometimes referred to as “common connection node”) is referred to as “Na” in FIG. The post-stage switch circuits 23a to 23d switch between a state in which the voltage output from the corresponding buffer circuits 22a to 22d is output to the common node Na and a state in which the output of the voltage to the common node Na is blocked.

  When capacitance is detected by each of the capacitance detection circuits 21a to 21d, voltages appearing at the detection nodes (hereinafter referred to as “detection voltages”) are buffered by the corresponding buffer circuits 22a to 22d, and subsequent stages of the buffer circuits 22a to 22d. Are input to the subsequent-stage switch circuits 23a to 23d.

  FIG. 5 is a block diagram showing a configuration of the first column selection switch circuit X (1) 20a shown in FIG. As shown in FIG. 5, the first column selection switch circuit X (1) 20a includes a switch selector circuit 30.

  In the present embodiment, the column detection wiring 6 is divided into two groups of m pieces, and the row detection wiring 7 is divided into two groups of n pieces, and the selection switches corresponding to the detection wirings 6 and 7 of each group. Circuits 20a to 20d are provided. Therefore, each of the first column selection switch circuit X (1) 20a and the second column selection switch circuit X (2) 20b includes m switch selector circuits 30. Each of the first row selection switch circuit Y (1) 20c and the second row selection switch circuit Y (2) 20d includes n switch selector circuits 30. In the present embodiment, the switch selector circuit 30 is a switch circuit that switches the connection two-to-one.

  In the first column selection switch circuit X (1) 20a, the switch selector circuit 30 includes the column detection wirings 6 included in the first column detection wiring set X (1), that is, the first to m-th column detection wirings Wx ( The connection destination of 1) to Wx (m) is switched to the first terminal a or the second terminal b for each column detection wiring 6. The first terminal a is connected to the first column capacitance detection circuit X (1) 21a. The second terminal b is connected to the first column post-stage switch circuit 23a.

  Each switch selector circuit 30 switches the connection destination of the column detection wiring 6 to the first terminal a or the second terminal b based on a control signal given from the detection control circuit 28. In other words, each switch selector circuit 30 uses the detection control circuit 28 to connect the column detection wiring 6 to the first terminal a or connect the column detection wiring 6 to the second terminal b. Switch to connected state.

  The second column selection switch circuit X (2) 20b, the first row selection switch circuit Y (1) 20c, and the second row selection switch circuit Y (2) 20d are the first column selection switch circuit X (1 ) Since the configuration is the same as 20a, the illustration is omitted. The second column selection switch circuit X (2) 20b, the first row selection switch circuit Y (1) 20c, and the second row selection switch circuit Y (2) 20d are the same as the first column selection switch circuit X (1) 20a. Each of them includes a switch selector circuit 30.

  In the second column selection switch circuit X (2) 20b, the first terminal a of the switch selector circuit 30 is connected to the second column capacitance detection circuit X (2) 21b, and the second terminal b is connected to the second terminal b. It is connected to the rear row switch circuit 23b. In the first row selection switch circuit Y (1) 20c, the first terminal a of the switch selector circuit 30 is connected to the first row capacitance detection circuit Y (1) 21c, and the second terminal b is the first It is connected to the post-stage post switch circuit 23c. In the second row selection switch circuit Y (2) 20d, the first terminal a of the switch selector circuit 30 is connected to the second row capacitance detection circuit Y (2) 21d, and the second terminal b is connected to the second terminal b. This is connected to the post-stage switch circuit 23d.

  Hereinafter, in the switch selector circuit 30, a connection state in which the connection destination of the detection wirings 6 and 7 is the first terminal a, that is, a state in which the detection wirings 6 and 7 and the first terminal a are connected is referred to as “first This is called “terminal connection state”. A connection state in which the connection destination of the detection wirings 6 and 7 is the second terminal b, that is, a state in which the detection wirings 6 and 7 and the second terminal b are connected is referred to as a “second terminal connection state”.

  When the switch selector circuit 30 is switched to the first terminal connection state, the detection wirings 6 and 7 connected to the switch selector circuit 30 have capacitances corresponding to the detection wiring group to which the detection wirings 6 and 7 belong. Connected to detection nodes of detection circuits 21a to 21d. For example, in the first column selection switch circuit X (1) 20a shown in FIG. 5, the switch selector circuit to which any one of the first to m-th column detection wirings Wx (1) to Wx (m) is connected. When 30 is switched to the first terminal connection state, the detection wiring connected to the switch selector circuit 30 is connected to the detection node Nx (1) of the first column capacitance detection circuit 21a.

  When the detection wirings 6 and 7 are connected to the detection node in this way, the rear-stage switch circuit 23 corresponding to the detection wiring group to which the detection wirings 6 and 7 connected to the detection node belong, and other post-stage switches are connected. It is controlled by the detection control circuit 28 so that the circuit 23 is cut off and becomes non-conductive. At this time, the voltage obtained by buffering the detection voltage of the detection node by the buffer circuit 22 is applied to the common node Na of the post-stage switch circuit 23.

  Therefore, when the switch selector circuit 30 is switched to the second terminal connection state, the buffered voltage appearing at the common node Na is applied to the detection wirings 6 and 7 corresponding to the switch selector circuit 30. It will be.

  The parasitic capacitances of the detection wirings 6 and 7 to be detected include the cross capacitance Cc formed between the detection wirings 6 and 7 that intersect with the detection wirings 6 and 7, that is, the detection wiring to be detected. 6 and 7 and the adjacent capacitance Ca formed between the adjacent detection wirings 6 and 7 are included.

  In the present embodiment, the film thickness and dielectric constant of the interlayer insulating film 13 between the column detection wiring 6 and the row detection wiring 7, and the detection column wiring 2 that constitutes the column detection wiring 6 and the row detection wiring 7 and The cross capacitance is determined by the number, width and shape of the detection row wiring 3. The number of the detection column wirings 2 and the detection row wirings 3 affects the size of the touch capacitance that is an electrostatic capacitance formed between the finger and other indicators. Therefore, in order to secure a large touch capacitance, the number of the detection column wirings 2 and the detection row wirings 3 cannot be reduced so much.

  Further, when the touch screen 1 is manufactured by, for example, a TFT (Thin Film Transistor) process apparatus, the thickness of the interlayer insulating film 13 made of silicon nitride (SiN) or the like is increased mainly due to a problem of manufacturing throughput. Is difficult, and it is necessary to suppress it to about 1 μm at most. Therefore, there is a restriction in suppressing the cross capacitance Cc which is a parasitic capacitance of the detection wirings 6 and 7 to be small.

  In such a case, the detection wirings 6 and 7 (hereinafter referred to as “non-selection detection wirings”) other than the detection wirings 6 and 7 (hereinafter referred to as “selection detection wirings”) selected as capacitance detection targets may be used. ) Is preferably applied with a detection voltage. By applying the detection voltage to the non-selected detection wiring, the cross capacitance Cc can be apparently canceled, so that the detection sensitivity can be improved. Also, the detection time can be shortened.

  In the present embodiment, the detection control circuit 28 performs the following control in order to apply the detection voltage to the non-selected detection wiring. The detection control circuit 28 switches the switch selector circuit 30 corresponding to the selection detection wirings 6 and 7 to the first terminal connection state. The detection control circuit 28 switches the switch selector circuit 30 corresponding to the non-selected detection wiring to the second terminal connection state. In addition, the detection control circuit 28 turns on the subsequent-stage switch circuit 23 in the subsequent stage of the buffer circuit 22 corresponding to the set to which the selected detection wiring belongs, and sets the other subsequent-stage switch circuits 23 in the non-conductive state.

  As a result, the selection detection wiring is connected to the capacitance detection circuit 21 corresponding to the group to which the selection detection wiring belongs, and when the capacitance is detected, the selection detection wiring becomes a detection node of the capacitance detection circuit 21. The appearing voltage can be buffered and applied to the non-selected detection wiring as a detection voltage. Therefore, as described above, the cross capacitance Cc can be apparently canceled, so that the detection sensitivity can be improved. Also, the detection time can be shortened.

  FIG. 6 is a diagram showing the configuration of the capacitance detection circuit 21. In the present embodiment, the capacitance detection circuit 21 is configured using a relaxation oscillation circuit in which an oscillation cycle is determined by a time constant between the resistance element Rx and the detection capacitor Cx. The detection capacitor Cx includes the parasitic capacitance of the detection circuit or the detection wiring, or the touch capacitance when there is a touch. The capacitance detection circuit 21 includes a resistance element Rx, a first comparator circuit 40, a second comparator circuit 41, an RS flip-flop circuit 42, an output terminal 43, and an external reset input terminal 44. The

  The first comparator circuit 40 compares the first reference voltage Vref (L) with the detection potential at the detection node N. The output terminal of the first comparator circuit 40 is connected to the set input terminal S of the RS flip-flop circuit 42. When the potential of the set input terminal S is high (H) level, the output terminal Q of the RS flip-flop circuit 42 becomes H level and is output to the output terminal 43 of the capacitance detection circuit 21.

  The second comparator circuit 41 compares the second reference voltage Vref (H) with the detection potential at the detection node N. The output terminal of the second comparator circuit 41 is connected to the reset input terminal R of the RS flip-flop circuit 42. When the potential of the reset input terminal R is low (L) level, the output terminal Q of the RS flip-flop circuit 42 becomes L level and is output to the output terminal 43 of the capacitance detection circuit 21.

  The output terminal Q of the RS flip-flop circuit 42 is connected to the minus (−) input terminal of the first comparator circuit 40 via the resistance element Rx and to the plus (+) input terminal of the second comparator circuit 41. Is done. The first reference voltage Vref (L) is applied to the plus (+) input terminal of the first comparator circuit 40. The second reference voltage Vref (H) is applied to the minus (−) input terminal of the second comparator circuit 41. The first reference voltage Vref (L) and the second reference voltage Vref (H) are set so as to satisfy the relationship represented by the following expression (1).

L level <Vref (L) <Vref (H) <H level (1)
Specifically, the first reference voltage Vref (L) is set to the extent indicated by the following formula (2). Further, the second reference voltage Vref (H) is set to the extent indicated by the following equation (3).

Vref (L) = (1/3) · Vd (2)
Vref (H) = (2/3) · Vd (3)
However, Vd = (H level-L level)
A reset control signal is input from the detection control circuit 28 to the external reset input terminal 44. When the reset control signal input from the detection control circuit 28 to the external reset input terminal 44 becomes L level, the potential of the output terminal Q of the RS flip-flop circuit 42 is forcibly reset to L level, and the capacitance detection circuit Oscillation of a certain relaxation oscillation circuit 21 is stopped. This state is hereinafter referred to as “oscillation stopped state”. Further, forcibly resetting the potential of the output terminal Q of the RS flip-flop circuit 42 to L level by setting the reset control signal to L level is hereinafter referred to as “external reset”.

  In the oscillation stop state, the potential of the detection node N is L level, and the output of the first comparator circuit 40, that is, the set input terminal S of the RS flip-flop circuit 42 is H level. The output of the second comparator circuit 41, that is, the reset input terminal R of the RS flip-flop circuit 42 is at L level.

  When the external reset is released, the RS flip-flop circuit 42 is set and the output terminal Q becomes H level. At this time, the detection capacitor Cx is charged through the resistance element Rx, and the potential of the detection node N gradually increases.

  When the potential of the detection node N becomes higher than the second reference voltage Vref (H), the output of the second comparator circuit 41, that is, the reset input terminal R of the RS flip-flop circuit 42 becomes H level. As a result, the RS flip-flop circuit 42 is reset, and the output terminal Q becomes L level. At this time, the detection capacitor Cx is discharged through the resistance element Rx, and the potential of the detection node N gradually decreases.

  When the potential of the detection node N becomes smaller than the first reference voltage Vref (L), the RS flip-flop circuit 42 is set and the output terminal Q becomes H level. As described above, the relaxation oscillation circuit 21 which is a capacitance detection circuit oscillates at an oscillation period corresponding to the time constant due to charging / discharging of the resistance element Rx and the detection capacitor Cx.

  Returning to FIG. 4, the selector circuit 24 includes first to fourth input terminals a to d. The output terminal of the first column capacitance detection circuit X (1) 21a is connected to the first input terminal a. The output terminal of the second column capacitance detection circuit X (2) 21b is connected to the second input terminal b. The output terminal of the first row capacitance detection circuit Y (1) 21c is connected to the third input terminal c. The output terminal of the second row capacitance detection circuit Y (2) is connected to the fourth input terminal d.

  The selector circuit 24 selects one of the first to fourth input terminals a to d based on the control signal given from the detection control circuit 28. The selector circuit 24 selects one of the first to fourth input terminals a to d to select a signal output from the selected input terminal, and outputs the selected signal to the first counter circuit 25 in the subsequent stage. To do.

  Specifically, the selector circuit 24 includes a first column capacitance detection circuit X (1) 21a, a second column capacitance detection circuit X (2) 21b, and a first row capacitance detection circuit Y (1). 21c and the second row capacitance detection circuit Y (2) 21d, the detection signal output from the capacitance detection circuit 21 in which the capacitance is detected is selected, and the first count in the subsequent stage is selected. Output to the circuit 25. When a relaxation oscillation circuit is used as the capacitance detection circuit 21 as in the present embodiment, the selector circuit 24 is output as a detection signal from the capacitance detection circuit 21 in which the capacitance is detected. The oscillation output signal is selected and output to the first counting circuit 25 in the subsequent stage.

  The first counting circuit 25 counts the detection signal given from the capacitance detection circuit 21 via the selector circuit 24 until it reaches a predetermined count value (hereinafter sometimes referred to as “predetermined count value”) Cp, The counting result is output to the second counting circuit 26. In the present embodiment, the first counting circuit 25 counts the oscillation output signal from the capacitance detection circuit 21 until it reaches a predetermined count value Cp, and outputs the counting result to the second counting circuit 26. As a result, the first counting circuit 25 outputs, as a counting result, a signal indicating a period in which the period of the oscillation output signal is accumulated by a predetermined count value Cp to the second counting circuit 26 in the subsequent stage.

  The second counting circuit 26 counts a period required from when the first counting circuit 25 starts the counting operation until the predetermined counting value Cp is reached, and the counting result is used as a capacitance detection result (hereinafter referred to as “capacitance”). Output to the touch coordinate calculation circuit 27). In the present embodiment, the second counting circuit 26 counts the counting result output from the first counting circuit 25 in the previous stage using a predetermined clock signal Clk provided from a clock generation circuit (not shown).

  Specifically, the second counting circuit 26 outputs, from the clock generation circuit, a signal indicating the period in which the period of the oscillation output signal is accumulated by a predetermined count value Cp, which is output from the first counting circuit 25 as a counting result. Is counted by a predetermined clock signal Clk. The second counting circuit 26 outputs the counting result to the touch coordinate calculation circuit 27 as a capacitance detection value. The detection control circuit 28 controls the start and end of counting when the second counting circuit 26 counts the output of the first counting circuit 25.

  Since the detection processing circuit 19 is configured as described above, the external noise and the random noise are asynchronous with the relaxation oscillation circuit that configures the capacitance detection circuit 21. Therefore, by integrating the oscillation period, the influence of external noise or the like can be averaged and reduced, so that the detection accuracy of the capacitance detection value can be improved.

  The touch coordinate calculation circuit 27 is a touch coordinate that is a coordinate value of a touch position on the touch screen 1 of the indicator based on the capacitance detection value that is a detection result of the capacitance obtained by the second counting circuit 26. Calculate the value. The touch coordinate value calculated by the touch coordinate calculation circuit 27 is output as detection coordinate data to a computer outside the detection processing circuit 19 or the like.

  The touch coordinate calculation circuit 27 calculates a touch coordinate value as follows, for example. The detection values of the detection wirings 6 and 7 when there is no touch are calculated and held in advance as reference values (hereinafter sometimes referred to as “base values”). A difference value (hereinafter also referred to as “difference detection value”) from a reference value corresponding to the detection wiring 6, 7 is obtained from the detection value of each detection wiring 6, 7.

  Then, based on the difference detection value, it is determined whether or not there is a touch with an indicator such as a finger. For example, when there are detection wirings 6 and 7 whose difference detection value exceeds a predetermined threshold, it is determined that the detection wirings 6 and 7 are touched by an indicator such as a finger. Then, using the difference detection value of the detection wirings 6 and 7 determined to be touched and the difference detection value of the detection wirings 6 and 7 adjacent to the detection wirings 6 and 7, Interpolate the coordinates between them to find the touch coordinate value.

  7 and 8 are timing charts showing the sequence of the touch detection operation in the first embodiment of the present invention. FIG. 7 is a timing chart showing a sequence of column detection wiring scanning and detection operation, and FIG. 8 is a timing chart showing a sequence of row detection wiring scanning and detection operation and touch coordinate calculation processing operation. In the timing charts shown in FIGS. 7 and 8, time advances from the left side to the right side as viewed in the drawing.

  In the detection processing circuit 19 of the present embodiment, the first column selection switch circuit X (1) 20a, the second column selection switch circuit X (2) 20b, and the first row selection switch circuit Y are instructed by the detection control circuit 28. (1) The connection state of the switch selector circuit 30 of 20c and the second row selection switch circuit Y (2) 20d is sequentially switched. As a result, the first column detection wiring set X (1), the second column detection wiring set X (2), and the first row are set as the wiring set to be detected (hereinafter referred to as “detection target wiring set”). The detection wiring set Y (1) and the second row detection wiring set Y (2) are sequentially selected, and the capacitance is detected. The detection wirings 6 and 7 constituting each set are sequentially selected or scanned as detection target wirings one by one, and the capacitance is detected.

  Each detection wiring 6, 7 is selected as a detection target wiring by switching the connection state of the corresponding switch selector circuit 30 to the first terminal a side and connecting to the corresponding capacitance detection circuit 21. The Detection wirings that are not selected as detection target wirings, that is, the above-mentioned non-selection detection wirings 6 and 7 are connected to the corresponding subsequent switch circuit 23 by switching the connection state of the corresponding switch selector circuit 30 to the second terminal b side. Is done.

  Specifically, the detection processing circuit 19 first, as shown in FIG. 7, first column detection wiring Wx (1),..., M-th column detection wiring Wx (m), m + 1-th column detection wiring Wx ( m + 1),..., the second m column detection wiring Wx (2m), the column detection wirings 6 are sequentially selected or scanned as detection target wirings one by one to detect the capacitance. After that, as shown in FIG. 8, the detection processing circuit 19 includes the first row detection wiring Wy (1),..., The nth row detection wiring Wy (n), the n + 1th row detection wiring Wy (n + 1),. .., And the second n-row detection wiring Wy (2n) are sequentially selected, ie, scanned as the detection target wiring, one by one, and the capacitance is detected.

  As described above, the detection processing circuit 19 acquires the capacitances of all the detection wirings 6 and 7 as detection values. Thereafter, the detection processing circuit 19 performs coordinate calculation processing including touch determination and calculation of touch coordinate values based on the detection values of all the detection wirings 6 and 7 by the touch coordinate calculation circuit 27.

  Specifically, the touch coordinate calculation circuit 27 determines whether or not there is a touch (hereinafter sometimes referred to as “touch determination”) based on the detection values of all the detection wirings 6 and 7. In the touch determination, when it is determined that there is a touch, the touch coordinate calculation circuit 27 calculates a touch coordinate value and outputs it to the outside as detected coordinate data. The detection processing circuit 19 repeats a series of operations including selection of the detection wiring, detection of capacitance, acquisition of detection values, and coordinate calculation processing.

  More specifically, first, the first column detection wiring set X (1) is selected as the detection target wiring set, and each column detection wiring Wx ( 1),..., Wx (m) scan and capacitance detection.

  At this time, the detection processing circuit 19 selects the switch selector of the first column selection switch circuit X (1) 20a corresponding to the detection target wiring among the column detection wirings constituting the first column detection wiring set X (1). The circuit 30 is sequentially switched to the first terminal a shown in FIG. As a result, the detection processing circuit 19 sequentially selects the column detection wirings constituting the first column detection wiring set X (1) one by one as the detection target wiring, and detects the first column detection that is the detection target wiring set. Connected to the detection node Nx (1) of the first column capacitance detection circuit X (1) 21a corresponding to the wiring set X (1).

  In addition, the first column rear-stage switch circuit 23a in the subsequent stage of the first column buffer circuit 22a corresponding to the first column detection wiring set X (1) is turned on, and the second second in the subsequent stage of the other buffer circuits 22b to 22d. The column post-stage switch circuit 23b, the first row post-stage switch circuit 23c, and the second row post-stage switch circuit 23d are cut off. As a result, the detection voltage appearing at the detection node Nx (1), in the present embodiment, the voltage obtained by buffering the charge / discharge voltage of the relaxation oscillation circuit by the first column buffer circuit 22a becomes the first column post-stage switch circuit 23a. Are output to the common connection node Na of the second column post-stage switch circuit 23b, the first row post-stage switch circuit 23c, and the second row post-stage switch circuit 23d.

  In addition, the first column selection switch circuit X (1) 20a, the second column selection switch circuit X (2) 20b, the first row selection switch circuit Y ( 1) All the switch selector circuits 30 of 20c and the second row selection switch circuit Y (2) 20d are switched to the second terminal b side in FIG. As a result, the buffering voltage of the detection voltage of the detection node Nx (1) is applied to the non-selected detection wiring.

  In this way, the first column capacitance detection circuit X (1) 21a is brought into an operating state. Other capacitance detection circuit 21, that is, second column capacitance detection circuit X (2) 21b, first row capacitance detection circuit Y (1) 21c, and second row capacitance detection circuit Y (2) 21d is in a stopped state.

  The selector circuit 24 selects the first input terminal a shown in FIG. 4 based on the control signal given from the detection control circuit 28. As described above, the output terminal of the first column capacitance detection circuit X (1) 21a is connected to the first input terminal a. When the selector circuit 24 selects the first input terminal a, the detection signal output from the first column capacitance detection circuit X (1) 21a is input to the first counting circuit 25.

  As described above, the count value of the first count circuit 25 is given to the second count circuit 26, and the count value of the second count circuit 26 is given to the touch coordinate calculation circuit 27 as the detection value of the detection target wiring. . In this way, the touch coordinate calculation circuit 27 sets each column detection wiring Wx (1),..., Wx (m) constituting the first column detection wiring set X (1) that is the detection target wiring set. The detection values are acquired sequentially.

  Next, the detection processing circuit 19 selects the second column detection wiring set X (2) as the detection target wiring set, and performs the second column detection in the same manner as the first column detection wiring set X (1). Scan and detection of each column detection wiring Wx (m + 1),..., Wx (2m) constituting the column detection wiring set X (2) is performed.

  At this time, the detection processing circuit 19 selects the switch selector of the second column selection switch circuit X (2) 20b corresponding to the detection target wiring among the column detection wirings constituting the second column detection wiring set X (2). The circuit 30 is sequentially switched to the first terminal a shown in FIG. As a result, the detection processing circuit 19 sequentially selects the column detection wirings constituting the second column detection wiring set X (2) one by one as the detection target wiring, and the second column capacitance detection circuit X (2 ) Connect to the detection node Nx (2) of 21b and detect the capacitance.

  In addition, the second column rear-stage switch circuit 23b, which is the rear stage of the second column buffer circuit 22b corresponding to the second column detection wiring set X (2), is brought into a conductive state. As a result, a voltage obtained by buffering the detection voltage of the detection node Nx (2) of the second column capacitance detection circuit X (2) 21b by the second column buffer circuit 22b is output to the common connection node Na.

  At this time, the other post-stage switch circuits 23, that is, the first column post-stage switch circuit 23a, the first row post-stage switch circuit 23c, and the second row post-stage switch circuit 23d are cut off. In this way, the second column capacitance detection circuit X (2) 21b is in an operating state. Capacitance detection circuits 21 other than the second column capacitance detection circuit X (2) 21b, that is, the first column capacitance detection circuit X (1) 21a, the first row capacitance detection circuit Y (1) 21c. And 2nd row electrostatic capacitance detection circuit Y (2) 21d is made into a halt condition.

  The selector circuit 24 selects the second input terminal b shown in FIG. 4 based on the control signal given from the detection control circuit 28. As described above, the output terminal of the second column capacitance detection circuit X (2) 21b is connected to the second input terminal b. When the selector circuit 24 selects the second input terminal b, the detection signal output from the second column capacitance detection circuit X (2) is input to the first counting circuit 25 in the subsequent stage. In the present embodiment, the oscillation output signal of the relaxation oscillation circuit, which is a detection signal output from the second column capacitance detection circuit 21b, is applied to the first counting circuit 25 in the subsequent stage.

  Hereinafter, the touch is performed in the same manner as the scanning and detection of each column detection wiring Wx (1),..., Wx (m) constituting the first column detection wiring set X (1) which is the detection target wiring set. The coordinate calculation circuit 27 acquires detection values of the column detection wirings Wx (m + 1),..., Wx (2m) constituting the second column detection wiring set X (2) as the detection target wiring set. .

  Similarly, scanning and detection processing of each row detection wiring Wy (1),..., Wy (n) constituting the first row detection wiring set Y (1) as the detection target wiring set is performed. Further, scanning and detection processing of each row detection wiring Wy (n + 1),..., Wy (n) constituting the second row detection wiring set Y (2) as the detection target wiring set is performed, and scanning of all detection wirings is performed. And the detection process ends. At this point, the touch coordinate calculation circuit 27 has acquired the detection values of all the detection wirings, and a coordinate calculation process including touch determination and calculation of touch coordinate values is performed.

  The touch coordinate calculation circuit 27 performs, for example, the following process as the touch coordinate value calculation process. The touch coordinate calculation circuit 27 first detects the difference detection value of the detection wiring (hereinafter sometimes referred to as “peak detection wiring”) having the maximum difference detection value for each of the column detection wiring and the row detection wiring, and both of them. A difference detection value of an adjacent wiring (hereinafter sometimes referred to as “adjacent detection wiring”) is obtained.

  Next, the touch coordinate calculation circuit 27 uses the obtained difference detection value of the peak detection wiring and the difference detection value of the adjacent detection wirings on both sides to touch coordinates between the center of the peak detection wiring and the center of the adjacent detection wiring. Are obtained by interpolation calculation for each of the columns and rows. As an interpolation calculation method, various methods can be adopted depending on the shape of the detection wirings 6 and 7 and the like, but detailed description is omitted here.

  At the time of scanning and detection of each detection wiring 6, 7, the capacitance detection circuit 21 corresponding to the detection wiring group other than the detection target wiring group to which the detection wiring belongs is oscillated by the reset control signal from the detection control circuit 28. Stopped. As a result, the detection voltage of the capacitance detection circuit 21, the detection AC voltage of the capacitance detection circuit 21 corresponding to the other detection wiring set, and in this embodiment, the oscillation output voltage of the relaxation oscillation circuit are the power supply and Interference via a wiring pattern such as a ground can be prevented from being mixed as detection noise. Therefore, it is possible to prevent the deterioration of the detection S / N ratio (Signal to Noise ratio) caused by the detection noise.

  Further, the capacitance detection circuit 21 corresponding to the detection wiring group other than the detection target wiring group that is the detection wiring group to which the detection wiring to be detected belongs belongs to a stopped state. Thereby, power consumption can be reduced.

  Further, as shown in FIG. 8, in a period such as coordinate calculation processing in which detection wiring is not scanned and detected, a switch for selecting a detection target wiring and applying a buffering voltage of a detection voltage to a non-selection target wiring All the connection states of the circuit 20 are switched to the second terminal b side shown in FIG. Specifically, the detection processing circuit 19 includes a first column selection switch circuit X (1) 20a, a second column selection switch circuit X (2) 20b, a first row selection switch circuit Y (1) 20c, and a second row. All the connection states of the selection switch circuit Y (2) 20d are switched to the second terminal b side shown in FIG. 5, and the buffering voltage is applied to all the detection wirings.

  Further, the detection processing circuit 19 stops all the capacitance detection circuits 21, and after the buffer circuit 22, the first column post-stage switch circuit 23a, the second column post-stage switch circuit 23b, the first row post-stage switch circuit 23c, and the Any one of the second row post-stage switch circuits 23d is made conductive. FIG. 8 shows an example in which the first column post-stage switch circuit 23a is made conductive.

  As described above, even when the detection wirings 6 and 7 are not scanned and detected, the detection voltage buffering voltage that appears at the detection node when the capacitance detection circuit 21 is stopped is applied to all the detection wirings 6 and 7. To do. In this embodiment, since the relaxation oscillation circuit is used as the capacitance detection circuit 21, the L level voltage appearing at the output when the RS flip-flop circuit 42 is in the reset state is applied to all the detection wirings 6 and 7.

  As a result, it is possible to prevent the detection wirings 6 and 7 from being in a floating state, so that external noise can be prevented from entering the power supply, the ground line, and the like of the detection processing circuit 19 via the detection wiring. Therefore, it is possible to prevent the malfunction of the circuit due to the external noise.

  FIG. 9 is a diagram illustrating a configuration of a portion that applies a buffering voltage of the detection voltage to the non-selection detection wiring according to the first embodiment of the present invention. FIG. 10 is a diagram illustrating a configuration of a portion that applies the buffering voltage of the detection voltage to the non-selected detection wiring in the comparative example.

  As shown in FIG. 9, in the present embodiment, buffers corresponding to the detection nodes Nx (1), Nx (2), Ny (1), and Ny (2) of the capacitance detection circuits 21a to 21d, respectively. The input terminals of the circuits 22a to 22d are connected. Then, one end of the corresponding post-stage switch circuit 23a-23d is connected to the output terminal of each buffer circuit 22a-22d, and the other end of the post-stage switch circuit 23a-23d is connected to the common node Na.

  On the other hand, in the comparative example shown in FIG. 10, the detection nodes Nx (1), Nx (2), Ny (1), and Ny (2) of the capacitance detection circuits 21a to 21d are first to fourth. One ends of the switch circuits 50a to 50d are connected to each other. The other ends of the first to fourth switch circuits 50a to 50d are connected in common and connected to the buffer circuit 51, and a buffering voltage is supplied to the selection switch circuits 20a to 20d via the buffer circuit 51. Yes.

  In the configuration of the present embodiment shown in FIG. 9, the parasitic capacitance when the buffer circuits 22a to 22d are viewed from the detection nodes Nx (1), Nx (2), Ny (1), Ny (2) Of all the buffer circuits 22a to 22d, only the input capacitance of the buffer circuit 22 connected to the detection node is included. On the other hand, in the configuration of the comparative example shown in FIG. 10, the parasitic capacitance when the buffer circuit 51 side is viewed from each detection node Nx (1), Nx (2), Ny (1), Ny (2) is Among the first to fourth switch circuits 50a to 50d, the parasitic capacitance of the switch circuit connected to the detection node, the output side parasitic capacitance connected to the other detection nodes, and the input capacitance of the buffer circuit 51 are included.

  Therefore, the configuration of the present embodiment shown in FIG. 9 can suppress the parasitic capacitance when the buffer circuit side is viewed from the detection node as compared with the configuration of the comparative example shown in FIG. As the buffer circuits 22a to 22d, it is desirable to use a low input capacitance operational amplifier or the like. Further, in the present embodiment, the case where the set of the column detection wiring 6 and the row detection wiring 7 is configured by continuous detection wiring has been described. For example, every other set, specifically, the odd-numbered detection You may make it comprise a wiring group and an even-numbered detection wiring group.

  As described above, in this embodiment, the column detection wiring 6 is divided into two sets of detection column wiring groups X (1) and X (2), and the row detection wiring 7 is divided into two sets of detection row wiring groups. It is divided into Y (1) and Y (2). Then, the detection wirings are scanned or selected corresponding to the two sets of detection column wiring groups X (1) and X (2) and the two sets of detection row wiring groups Y (1) and Y (2), respectively. Selection switch circuits 20a to 20d and capacitance detection circuits 21a to 21d are provided.

  The detection switch is sequentially selected by the selection switch circuits 20a to 20d and connected to the detection nodes of the corresponding capacitance detection circuits 21a to 21d to detect the capacitance. Therefore, the parasitic capacitances of the selection switch circuits 20a to 20d that dominate the parasitic capacitance viewed from the detection nodes of the capacitance detection circuits 21a to 21d can be significantly reduced.

  Accordingly, it is possible to improve the detection sensitivity of the touch capacitance formed between the indicator and the detection wiring in the detection time that is restricted from the desired response time. Specifically, since the difference detection value for the touch capacitance can be increased, the calculation accuracy of the touch coordinate value can be improved. In addition, the detection time required to detect the touch capacitance with the detection sensitivity required from the desired touch coordinate accuracy can be shortened. Specifically, it is possible to shorten the detection time necessary for obtaining a difference detection value having a magnitude required from the desired touch coordinate accuracy with respect to the touch capacitance.

  In the present embodiment, the selection switch circuits 20a to 20d switch the connection destinations of the selection detection wiring and the non-selection detection wiring, so that the detection voltage appearing at the detection node corresponding to the group to which the selection detection wiring belongs belongs to the buffer. The circuits 22a to 22d are buffered and applied to the non-selected detection wiring. Thereby, it is possible to cancel the cross capacitance between the selection detection wiring and the detection wiring crossing the selection detection wiring and the parasitic capacitance of the selection detection wiring formed between the adjacent detection wirings.

  Further, in the present embodiment, buffer circuits 22a to 22d for buffering the respective detection voltages are provided at the respective detection nodes, and the output terminals of the respective buffer circuits 22a to 22d are connected to one ends of the corresponding subsequent stage switch circuits 23a to 23d. ing. The other end of each post-stage switch circuit is connected to a common node, and the voltage of this common node is applied to the non-selection detection wiring via the selection switch circuits 20a to 20d. As a result, the parasitic capacitance with reference to each detection node can be made only the input capacitance of the buffer circuits 22a to 22d. Therefore, it is possible to reduce the parasitic capacitance of the detection wiring and to suppress the parasitic capacitance of the detection node by applying a buffering voltage of the detection voltage to at least the non-selected detection wiring.

  Further, in the present embodiment, the capacitance detection circuits 21 other than the capacitance detection circuit 21 that performs the detection operation are in a stopped state. As a result, it is possible to prevent the capacitance detection circuit 20 other than the capacitance detection circuit 21 that performs the detection operation from interfering with each other, so that this interference can be prevented from being mixed into the detection value as noise. .

  In the present embodiment, the oscillation output signal of the capacitance detection circuit 21 performing the detection operation is selected from the oscillation output signals of the relaxation oscillation circuits constituting the capacitance detection circuits 21a to 21d. And supplied to the first counting circuit 25. The oscillation output signal is counted by the first counting circuit 25 until the predetermined counting value Cp is reached, and is supplied to the second counting circuit 26. The second counting circuit 26 counts a period from when the first counting circuit 25 starts counting until the predetermined count value Cp is reached by a predetermined clock Clk. The count result of the second counting circuit 26 is acquired by the touch coordinate calculation circuit 27 as a detection value.

  As a result, the detection value based on the oscillation output signal can be smoothed, so that external noise can be filtered. Further, since the first and second counting circuits 25 and 26 are shared, the first counting circuit 25 and the second counting circuit 26 are compared with the case where the first counting circuit 25 and the second counting circuit 26 are individually provided corresponding to each capacitance detection circuit 23. It is possible to reduce the circuit scale of the detection processing circuits 19 and 19A.

  In addition, the capacitance detection circuit is stopped in a period in which the detection wiring is not selected and detected, that is, in a period in which no detection wiring is selected as a detection target. In the present embodiment, during the coordinate calculation process, all relaxation oscillation circuits used as the capacitance detection circuit are stopped, and the L level voltage appearing at the detection node is commonly applied to each detection wiring. .

  As a result, it is possible to prevent the detection wiring from being in a floating state during a period when no detection wiring is selected as a detection target. Therefore, it is possible to prevent external noise from entering the power supply, the ground line, and the like of the detection processing circuit 19 via the detection wiring, so that the malfunction of the circuit due to the external noise can be prevented.

<Second Embodiment>
In the first embodiment described above, as an example of the touch coordinate calculation process, the peak detection wiring is detected using the detection values of the peak detection wiring and the adjacent detection wirings on both sides of the column detection wiring and the row detection wiring. The touch coordinates between the center and the center of the adjacent detection wiring adjacent to the center are interpolated to obtain.

  The capacitance detection sensitivity of the capacitance detection circuits X (1) 21a and X (2) 21b corresponding to the two column detection wiring groups X (1) and X (2) is, for example, the first embodiment. When the relaxation oscillation circuit is used as described above, a deviation occurs due to variations in resistance elements and circuit propagation delay.

  Here, the mth column detection wiring Wx (m) or the (m + 1) th column detection wiring Wx (m + 1), which is the detection wiring at the boundary between the two column detection wiring groups X (1) and X (2), is the peak detection wiring. In such a case, one of the adjacent detection wirings on both sides belongs to the other column detection wiring group, and the electrostatic capacity is detected by another electrostatic capacity detection circuit.

  Therefore, in such a case, at least one of the detection values used for the interpolation calculation process for calculating touch coordinates is detected by another capacitance detection circuit, resulting in a deviation in detection sensitivity between the circuits. This deviation in detection sensitivity causes an error in the calculated touch coordinates. Such a problem similarly occurs in the detection of the capacitance in the row detection wiring.

  Therefore, in the present embodiment, the detection wiring at the boundary portion of the detection wiring group is also scanned by the capacitance detection circuit of the detection wiring group adjacent to the detection wiring group to detect the capacitance.

  FIG. 11 is a block diagram showing the configuration of the touch screen 1 and the detection processing circuit 19A in the second embodiment of the present invention. Since the touch screen 1 in the present embodiment has the same configuration as the touch screen 1 in the first embodiment described above, the same reference numerals are assigned to the corresponding portions, and description thereof is omitted. Further, since the detection processing circuit 19A in the present embodiment is similar in configuration to the detection processing circuit 19A in the first embodiment described above, the corresponding portions are denoted by the same reference numerals, and a common description is given. Omitted.

  In the present embodiment, as in the first embodiment described above, the number of column detection wirings 6 of the touch screen 1 is 2 m (m is a positive integer), and the number of row detection wirings 7 is 2n (n is A positive integer) is shown. The column detection wiring 6 is divided into two column detection wiring sets X (1) and X (2). The first column detection wiring set X (1) includes first to m-th m column detection wirings Wx (1) to Wx (m). The second column detection wiring set X (2) includes m + 1 to 2m m column detection wirings Wx (m + 1) to Wx (2m).

  The row detection wiring 7 is divided into two row detection wiring sets Y (1) and Y (2). The first row detection wiring set Y (1) includes first to nth n row detection wirings Wy (1) to Wy (n). The second row detection wiring set Y (2) includes n + 1 to 2nth row detection wirings Wy (n + 1) to Wy (2n).

  The two column detection wiring groups X (1) and X (2) are distributed and connected to the first column selection switch circuit X (1) 20a and the second column selection switch circuit X (2) 20b, respectively. Similarly, the two row detection wiring groups Y (1) and Y (2) are distributed and connected to the first row selection switch circuit Y (1) 20c and the second row selection switch circuit Y (2) 20d, respectively. The

  In the present embodiment, the first column detection wiring set X (1) among the column detection wirings Wx (m) and Wx (m + 1) at the boundary between the column detection wiring sets X (1) and X (2). The m-th column detection wiring Wx (m) belonging to is connected to the second column selection switch circuit X (2) 20b corresponding to the other second column detection wiring set X (2). In addition, the (m + 1) th column detection wiring Wx (m + 1) belonging to the second column detection wiring set X (2) is the first column selection switch circuit X () corresponding to the other first column detection wiring set X (1). 1) Also connected to 20a.

  The mth column detection wiring Wx (m) and the m + 1th column detection wiring Wx (m + 1) are connected to the first column capacitance detection circuit X (1) via the first column selection switch circuit X (1) 20a. Detection is performed by 21a, and detection is also performed by the second column capacitance detection circuit X (2) 21b via the second column selection switch circuit X (2) 20b. That is, the m-th column detection wiring Wx (m) and the (m + 1) th column detection wiring Wx (m + 1) are detected twice, respectively, and the touch coordinate calculation circuit 27 performs the same as in the first embodiment. The detected value is acquired.

  Similarly, of the row detection wirings Wy (n) and Wy (n + 1) at the boundary between the row detection wiring sets Y (1) and Y (2), the first one belonging to the first row detection wiring set Y (1). The n-row detection wiring Wy (n) is also connected to the second row selection switch circuit Y (2) 20d corresponding to the other second row detection wiring set Y (2). Further, the (n + 1) th row detection wiring Wy (n + 1) belonging to the second row detection wiring set Y (2) is the first row selection switch circuit Y () corresponding to the other first row detection wiring set Y (1). 1) Also connected to 20c.

  The n-th row detection wiring Wy (n) and the (n + 1) th row detection wiring Wy (n + 1) are connected to the first row capacitance detection circuit Y (1) via the first row selection switch circuit Y (1) 20c. 1) Detection is performed by 21c, and detection is also performed by the second row capacitance detection circuit Y (2) 21d via the second row selection switch circuit Y (2) 20d. That is, each of the n-th row detection wiring Wy (n) and the (n + 1) -th row detection wiring Wy (n + 1) is detected twice, and the touch coordinate calculation circuit 27 performs the same detection as in the first embodiment. The detected value is acquired.

  12 and 13 are timing charts showing the sequence of the touch detection operation in the second embodiment of the present invention. FIG. 12 is a timing chart showing a sequence of column detection wiring scan and detection operation, and FIG. 13 is a timing chart showing a sequence of row detection wiring scanning and detection operation and touch coordinate calculation processing operation. In the timing charts shown in FIG. 12 and FIG. 13, time advances from the left side to the right side as viewed in the drawing.

  Also in the present embodiment, similarly to the first embodiment, the selection switch circuits 20a to 20d are switched by the instruction of the detection control circuit 28, and the first column detection wiring Wx (1),. The detection target wirings are sequentially selected, scanned, and detected in the order of m-th column detection wiring Wx (m), m + 1-th column detection wiring Wx (m + 1),..., 2m-th column detection wiring Wx (2m). Thereafter, the first row detection wiring Wy (1),..., The nth row detection wiring Wy (n), the (n + 1) th row detection wiring Wy (n + 1),. In order, detection target wiring is selected, that is, scanned and detected.

  At this time, in the present embodiment, the m-th column detection wiring Wx (m) and the (m + 1) -th column detection wiring Wx (m + 1) that are adjacent at the boundary between the two column detection wiring sets X (1), X (2). Performs detection twice. The n-th row detection wiring Wy (n) and the (n + 1) -th row detection wiring Wy (n + 1) adjacent at the boundary between the two row detection wiring sets Y (1) and Y (2) are detected twice.

  After the detection values of all the detection wirings are thus obtained, the touch coordinate calculation circuit 27 performs touch determination for determining presence / absence of touch based on the detection values. When the touch coordinate calculation circuit 27 determines that there is a touch, the touch coordinate calculation circuit 27 calculates the coordinates and then outputs the calculation result to the outside as detected coordinate data. The detection processing circuit 19A repeats a series of operations including selection of the detection wiring, detection of capacitance, acquisition of detection values, and coordinate calculation processing.

  More specifically, first, the first column detection wiring set X (1) is selected as the detection target wiring set, and each column detection wiring Wx ( 1),..., Wx (m) scan and capacitance detection.

  At this time, similarly to the detection processing circuit 19 in the first embodiment, the detection processing circuit 19A corresponds to the detection target wiring among the column detection wirings constituting the first column detection wiring set X (1). The selector circuit 30 of the first column selection switch circuit X (1) 20a is sequentially switched to the first terminal a side shown in FIG. As a result, the detection processing circuit 19A sequentially selects the column detection wirings constituting the first column detection wiring set X (1) one by one as the detection target wiring, and detects the first column detection that is the detection target wiring set. Connected to the detection node Nx (1) of the first column capacitance detection circuit X (1) 21a corresponding to the wiring set X (1).

  At this time, the first column rear-stage switch circuit 23a in the rear stage of the first buffer circuit 22a is turned on, the second column rear-stage switch circuit 23b in the rear stage of the other buffer circuits 22b to 22d, and the first row rear-stage switch circuit. 23c and the second row latter stage switch circuit 23d are cut off. As a result, the voltage obtained by buffering the detection voltage appearing at the detection node Nx (1) of the first column capacitance detection circuit X (1) 21a by the first buffer circuit 22a is commonly connected to the post-stage switch circuits 23a to 23d. Output to node Na. In the present embodiment, the detection voltage that appears at the detection node Nx (1) of the first column capacitance detection circuit X (1) 21a is the charge / discharge voltage of the relaxation oscillation circuit that constitutes the capacitance detection circuit.

  In the present embodiment, among the switch selector circuits 30 corresponding to the non-selected detection wirings of the selection switch circuits 20a to 20d, the switch selector circuit 30 connected to the detection wiring at the boundary portion of the detection wiring group is shown in FIG. 5 is not switched to either the first terminal a side or the second terminal b side (hereinafter sometimes referred to as “non-connected state”), and the other selector circuit 30 has the second terminal shown in FIG. It is switched to the b side. In FIG. 12 and FIG. 13, the unconnected state is represented by the symbol “z”. A voltage obtained by buffering the detection voltage of the detection node Nx (1) of the first column capacitance detection circuit X (1) 21a by the first buffer circuit 22a is applied to the non-selection detection wiring.

  In the first column selection switch circuit X (1) 20a, the switch selector circuit 30 to be disconnected is the switch selector circuit 30 connected to the (m + 1) th column detection wiring Wx (m + 1). In the second column selection switch circuit X (2) 20b, the switch selector circuit 30 to be disconnected is the switch selector circuit 30 connected to the mth column detection wiring Wx (m).

  In the first row selection switch circuit Y (1) 20c, the switch selector circuit 30 to be disconnected is the switch selector circuit 30 connected to the (n + 1) th column detection wiring Wy (n + 1). In the second row selection switch circuit Y (2) 20d, the switch selector circuit 30 that is disconnected is the switch selector circuit 30 that is connected to the nth column detection wiring Wy (n).

  The selector circuit 24 selects the first input terminal a shown in FIG. 11 based on the control signal given from the detection control circuit 28. As a result, the output of the first column capacitance detection circuit X (1) 21a is input to the first counting circuit 25. As in the first embodiment described above, the count value of the first count circuit 25 is given to the second count circuit 26, and the count value of the second count circuit 26 is used as the detected value of the detection target wiring as touch coordinates. The calculation circuit 27 sequentially obtains them.

  Thereafter, the m-th column detection wiring Wx (m) at the boundary with the adjacent second column detection wiring set X (2) is once again connected to the second column detection wiring set X (2). Scanning is performed by the corresponding second column selection switch circuit X (2) 20b, and detection is performed by the second column capacitance detection circuit X (2) 21b.

  At this time, the switch selector circuit 30 corresponding to the m-th column detection wiring Wx (m) of the second column selection switch circuit X (2) 20b is switched to the first terminal a side shown in FIG. The switch selector circuit 30 corresponding to the m-th column detection wiring Wx (m) of the selection switch circuit X (1) 20a is set to the unconnected state z. Accordingly, the m-th column detection wiring Wx (m) is connected to the detection node Nx (b) of the second column capacitance detection circuit X (2) 21b corresponding to the second column detection wiring set X (2). Is done. All the switch selector circuits 30 other than the first column selection switch circuit X (1) 20a and the second column selection switch circuit X (2) 20b are switched to the second terminal b side.

  Further, the second column rear switch circuit 23b in the rear stage of the second buffer circuit 22b is turned on, and the other first column rear switch circuit 23a, the first row rear switch circuit 23c, and the second row rear switch circuit 23d are cut off. State. A voltage obtained by buffering the detection voltage of the detection node Nx (2) of the second column capacitance detection circuit X (2) 21b by the second buffer circuit 22b is applied to the non-selection detection wiring.

  At the second scan and detection of the m-th column detection wiring Wx (m), the selector circuit 24 selects the second input terminal b shown in FIG. 11 based on the control signal supplied from the detection control circuit 28. As a result, the output of the second column capacitance detection circuit X (2) is input to the first counting circuit 25. Similarly to the first scan and detection described above, the count value of the first count circuit 25 is given to the second count circuit 26, and the count value of the second count circuit 26 is used as the detection value of the detection target wiring. Obtained by the touch coordinate calculation circuit 27.

  Next, the column detection wiring scan and detection operation of the second column detection wiring set X (2) is started. First, the (m + 1) th column detection wiring Wx (m + 1) at the boundary with the adjacent first column detection wiring set X (1) selects the first column corresponding to the first column detection wiring set X (1). Scanning is performed by the switch circuit X (1) 20a, and detection is performed by the first column capacitance detection circuit X (1) 21a.

  At this time, the switch selector circuit 30 corresponding to the (m + 1) th column detection wiring Wx (m + 1) of the first column selection switch circuit X (1) 20a is switched to the first terminal a side shown in FIG. The switch selector circuit 30 corresponding to the (m + 1) th column detection wiring Wx (m + 1) of the selection switch circuit X (2) 20b is set to the non-connection state z. Thus, the (m + 1) th column detection wiring Wx (m + 1) is connected to the detection node Nx (a) of the first column capacitance detection circuit X (1) 21a corresponding to the first column detection wiring set X (1). Is done. All the switch selector circuits 30 other than the first column selection switch circuit X (1) 20a and the second column selection switch circuit X (2) 20b are switched to the second terminal b side shown in FIG.

  Further, the first column post-stage switch circuit 23a in the rear stage of the first buffer circuit 22a is turned on, and the other second column post-stage switch circuit 23b, the first row post-stage switch circuit 23c, and the second row post-stage switch circuit 23d are cut off. State. A voltage obtained by buffering the detection voltage of the detection node Nx (1) of the first column capacitance detection circuit X (1) 21a by the first buffer circuit 22a is applied to the non-selection detection wiring.

  At the first scan and detection of the (m + 1) th column detection wiring Wx (m + 1), the selector circuit 24 selects the first input terminal a shown in FIG. 11 based on the control signal supplied from the detection control circuit 28. As a result, the output of the first column capacitance detection circuit X (1) is input to the first counting circuit 25. Then, as described above, the count value of the first count circuit 25 is given to the second count circuit 26, and the count value of the second count circuit 26 is calculated as the detected value of the (m + 1) th column detection wiring Wx (m + 1) to calculate touch coordinates. Acquired by the circuit 27.

  The (m + 1) th column detection wiring Wx (m + 1) is scanned again by the second column selection switch circuit X (2) 20b corresponding to the second column detection wiring set X (2) to detect the second capacitance. Detection is performed by the circuit X (2) 21b, and the detected value is obtained. Thereafter, the remaining column detection wirings Wx (m + 2) to Wx (2m) are sequentially scanned and detected as in the first embodiment.

  The same applies to the row detection wiring. Specifically, first, the first row detection wiring Wy (1),..., The nth row detection wiring Wy (n) of the first row detection wiring set Y (1) are sequentially switched to the first row selection switch. After being scanned by the circuit Y (1) 20c and subjected to detection processing by the first row capacitance detection circuit Y (1) 21c, the detected value is acquired. The n-th row detection wiring Wy (n) at the boundary with the adjacent second row detection wiring set Y (2) is scanned again by the second row selection switch circuit Y (2) 20d, After the detection process is performed by the two-row capacitance detection circuit Y (2) 21d, the detection value is acquired.

  Furthermore, among the row detection wirings of the second row detection wiring set Y (2), the (n + 1) th row detection wiring Wy (n + 1) at the boundary portion of the adjacent first row detection wiring set Y (1) Scanning is performed by the one-row selection switch circuit Y (1) 20c. Then, detection processing is performed by the first row capacitance detection circuit Y (1) 21c, and a detection value is acquired. Thereafter, the (n + 1) th row detection wiring Wy (n + 1) is scanned again by the second row selection switch circuit Y (2) 20d corresponding to the second row detection wiring set Y (2). Then, detection is performed by the second row capacitance detection circuit Y (2) 21d, and the detection value is obtained.

  Next, scanning and detection processing of the remaining n + 2 row detection wirings Wy (n + 2),..., The second nth row detection wiring Wy (2n) are performed. As described above, the scan and detection processing of all detection wirings is completed. At this point, the touch coordinate calculation circuit 27 has acquired the detection values of all the detection wirings, and a coordinate calculation process including touch determination and calculation of touch coordinate values is performed.

  Here, the peak detection wiring is the mth column detection wiring Wx (m) or the (m + 1) th column detection at the boundary between the first column detection wiring set X (1) and the second column detection wiring set X (2). Consider the case of the wiring Wx (m + 1). In this case, of the two column detection wiring groups, one column detection wiring group has a peak detection wiring, and the other column detection wiring group has one of the adjacent detection wirings of the peak detection wiring. Become.

  Regarding the adjacent detection wirings present in the other column detection wiring group, as described above, the first column capacitance detection circuit 23a corresponding to the first detection wiring group X (1) and the second detection wiring group X Two detection values are acquired by the second column capacitance detection circuit 23b corresponding to (2). Of the two acquired detection values, the detection value detected by the capacitance detection circuit 23 corresponding to the column detection wiring set in which the peak detection wiring exists is used as the detection value of the adjacent detection wiring, and touched. Coordinates are calculated.

  For example, when the peak detection wiring is the m-th column detection wiring Wx (m), the first column detection wiring among the two detection values acquired by the m + 1-th column detection wiring Wx (m + 1) that is the adjacent detection wiring. The detection value acquired by the first column capacitance detection circuit 23a corresponding to the set X (1) is used as the detection value of the adjacent detection wiring.

  The peak detection wiring is the nth row detection wiring Wy (n) or the (n + 1) th row detection wiring Wy () at the boundary between the first row detection wiring set Y (1) and the second row detection wiring set Y (2). The same applies to the case of (n + 1). Specifically, when the peak detection wiring is present in one row detection wiring set, the peak detection is detected among the two detection values of the adjacent detection wiring Wy (n + 1) or Wy (n) in the other row detection wiring set. The detection value detected by the capacitance detection circuit 23 corresponding to the row detection wiring group in which the wiring exists is used as the detection value of the adjacent detection wiring, and the touch coordinates are calculated.

  As described above, when the peak detection wiring exists in the boundary portion between the adjacent detection wiring groups, the detection value by the detection system on the side where the peak detection wiring exists is used for calculating the touch coordinates. As a result, it is possible to prevent the accuracy of calculating touch coordinates from deteriorating due to a difference in detection sensitivity between the capacitance detection circuits corresponding to adjacent detection wiring groups.

  As described above, in the second embodiment of the present invention, the column detection wiring Wx (m) at the boundary between the first column detection wiring set X (1) and the second column detection wiring set X (2). ) And Wx (m + 1) are connected to the detection nodes of the capacitance detection circuits 23a and 23b corresponding to each set in different periods, detected twice, and two detection values are acquired.

  Similarly, the row detection wirings Wy (n) and Wy (n + 1) at the boundary between the first row detection wiring set Y (1) and the second row detection wiring set Y (2) correspond to each set. The detection nodes of the capacitance detection circuits 23c and 23d are connected to the detection nodes in different periods, respectively, are detected twice, and two detection values are acquired.

  Then, the touch coordinate calculation circuit 27 obtains a difference detection value using the detection value of the adjacent detection wiring of the group to which the peak detection wiring belongs, and performs coordinate calculation. As a result, between the first column capacitance detection circuit X (1) and the second column capacitance detection circuit X (2), and between the first row capacitance detection circuit Y (1) and the second row static. Even when there is a difference in detection sensitivity with respect to the capacitance detection circuit Y (2), it is possible to calculate touch coordinates using a difference detection value based on the detection value of the same capacitance detection circuit. Therefore, the accuracy of touch coordinates can be ensured.

  In the present embodiment described above, for the column detection wiring 6 and the row detection wiring 7, the touch coordinates are calculated from the detection values of the three detection wirings of the peak detection wiring and the adjacent detection wirings on both sides thereof. However, the touch coordinates may be calculated using detection values of more detection wirings 6 and 7. In this case, the selection switch circuit and the electrostatic capacitance corresponding to the adjacent detection wiring group among the detection wirings 6 and 7 at the boundary portion of the detection wiring group according to the number of the detection wirings 6 and 7 using the detection value. In the capacitance detection circuit, the number of detection wirings 6 and 7 to be scanned and detected redundantly is increased. This can be carried out in the same manner as in the present embodiment.

<Third Embodiment>
In the present embodiment, a liquid crystal display device in which a touch panel and a liquid crystal display panel are integrally formed by bonding the touch screen 1 in the first embodiment to the liquid crystal display panel 61 will be described.

  FIG. 14 is a cross-sectional view showing a configuration of a liquid crystal display device according to the third embodiment of the present invention. The liquid crystal display device includes a touch panel 100 including the touch screen 1 shown in FIG. 3 described above, a liquid crystal display panel 61, and a backlight 69. The liquid crystal display panel 61 includes a polarizing plate 62, an adhesive layer 63, a color filter substrate 64, a liquid crystal layer 65, a TFT array substrate 66, an adhesive layer 67, and a polarizing plate 68. In FIG. 14, the description of the FPC board 17 and the controller board 18 shown in FIG. 3 is omitted for easy understanding.

  The color filter substrate 64 is formed by forming a color filter, a black matrix, a transparent electrode, and an alignment film on a glass substrate. The TFT array substrate 66 is formed by forming a switching element such as a thin film transistor (abbreviation: TFT) on a glass substrate. The liquid crystal layer 65 is sandwiched between the color filter substrate 64 and the TFT array substrate 66, and is made of, for example, twisted nematic (abbreviated as TN) liquid crystal.

  The polarizing plate 68 is adhered to the surface on the other side in the thickness direction of the TFT array substrate 66 by the adhesive layer 67. Further, a polarizing plate 62 is adhered to the surface of one side in the thickness direction of the color filter substrate 64 by an adhesive layer 63. A backlight 69 as a light source is disposed on the other side in the thickness direction, which is the back side of the liquid crystal display panel 61.

  The touch screen 1 according to the first embodiment is adhered to the polarizing plate 62 disposed on the one side in the thickness direction, which is the front side of the liquid crystal display panel 61, by the adhesive layer 60.

  A signal corresponding to an image to be displayed (hereinafter also referred to as “image signal”) is input to the TFT array substrate 66 from an external driver circuit (not shown). The TFT array substrate 66 changes the alignment direction of the liquid crystal molecules by controlling the voltage applied to the liquid crystal layer 65 via a switching element formed by the TFT formed for each pixel in accordance with the input image signal.

  Incident light from the backlight 69 passes through the polarizing plate 68 to become linearly polarized light, and passes through the liquid crystal layer 65 so that the vibration direction is bent according to the signal of the image to be displayed. The light whose vibration direction is bent passes through the color filter formed on the color filter substrate 64 and is separated into light of the three primary colors, and further passes through the polarizing plate 62 on the front side, so as to respond to the image signal. The light has a high light intensity. Further, the light passing through the polarizing plate 62 passes through the touch screen 1 on the front surface and is visually recognized by the user as display light.

  In this way, the liquid crystal display device performs a desired display by controlling the transmittance of light from the backlight 69 in accordance with the image signal. Further, the touch panel 100 including the touch screen 1 calculates the touch coordinate value based on the change in the oscillation cycle, and outputs the calculated touch coordinate value as touch coordinate data, as in the first embodiment. To do.

  As described above, in the touch panel 100, the detection sensitivity of the touch capacitance formed between the indicator and the detection wiring can be improved in a detection time that is restricted from a desired response time. In addition, the detection time required to detect the touch capacitance with the detection sensitivity required from the desired touch coordinate accuracy can be shortened. Therefore, since the detection sensitivity of the touch capacitance in the touch panel is improved and the detection time is shortened, a liquid crystal display device having a touch panel function that can obtain a desired detection sensitivity for the touch capacitance in as short a detection time as possible. Can be realized.

  Further, in the liquid crystal display device of the present embodiment, the touch screen 1 is attached to the display panel 61 and integrally configured. Therefore, the touch screen holding mechanism that has been conventionally required can be eliminated, and the entire device can be made thin. It becomes possible.

  In addition, since the touch screen 1 and the display panel 61 are integrally formed, dust and the like are prevented from entering the gap between the touch screen 1 and the display panel 61, and adverse effects on the display caused by the dust and the like are prevented. be able to.

  Further, as described in the first embodiment, in the touch screen 1, the detection wiring groups 6 and 7 are configured by the plurality of detection wirings 2 and 3, and the detection wirings 2 and 3 are connected to each other. By setting the area of the slit-shaped opening large, a decrease in the transmittance of display light is suppressed. As a result, most of the light passing through the polarizing plate 62 passes through the touch screen 1 and becomes display light. Therefore, even if the touch screen 1 is disposed on the front surface of the liquid crystal display panel 61, the display luminance is hardly lowered.

  In the present embodiment, the liquid crystal display device is configured to include the touch panel 100 including the touch screen 1 according to the first embodiment described above, but the touch screen 1 according to the second embodiment described above is included. You may comprise with the touch panel containing.

  In each of the above-described embodiments, the case in which the detection column wiring group and the detection row wiring group are divided into two sets has been described. It can be implemented in the same way as the form.

  Further, the number of detection column wiring groups and the number of detection row wiring groups need not necessarily be the same, and only one of the detection column wiring group and the detection row wiring group may be a plurality of sets. You may comprise so that it may divide into.

  Further, there may be a detection wiring group including both the detection column wiring group and the detection row wiring group.

  In each of the above-described embodiments, the first column selection switch circuit X (1) 20a, the second column selection switch circuit X (2) 20b, the first row selection switch circuit Y (1) 20c, and the second row selection Although the switch circuit Y (2) 20d is configured to include a plurality of switch selector circuits 30, the connection between each detection wiring and the capacitance detection circuit is selected and switched, and at the time of detection of the capacitance detection circuit Any configuration may be employed as long as a voltage obtained by buffering the detection voltage appearing at the detection node can be applied to the non-selected wiring.

  1 touch screen, 2 detection column wiring, 3 detection row wiring, 4 column connection wiring, 5 row connection wiring, 6 detection column wiring group, 7 detection row wiring group, 8, 9 lead wiring, 10 terminals , 12 base substrate, 13 interlayer insulating film, 14 protective film, 17 flexible printed circuit board (FPC), 18 controller substrate, 19, 19A detection processing circuit, 20a first column selection switch circuit X (1), 20b second column selection Switch circuit X (2), 20c first row selection switch circuit Y (1), 20d second row selection switch circuit Y (2), 21a first column capacitance detection circuit X (1), 21b second column static Capacitance detection circuit X (2), 21c 1st row capacitance detection circuit Y (1), 21d 2nd row capacitance detection circuit Y (2), 24 selector circuit, 25 1st counting circuit, 26 2nd Total Number circuit, 27 touch coordinate calculation circuit, 28 detection control circuit, 61 liquid crystal display panel, 100 touch panel.

Claims (8)

Have a plurality of test Dehai lines arranged in the row and column directions, the plurality of detection wires, that are divided into a plurality of detection wires group composed by the detection wiring in the number of predetermined touch Screen,
Provided corresponding to said multiple detection wire assembly, a plurality of selection switches for sequentially selecting said analyzing Dehai lines included in the corresponding detection line pair,
Wherein one each in a plurality of detection wires pairs are provided corresponding, has a detection node that said analyzing Dehai line selected by the selection switch circuit corresponding to the corresponding detection wire pair are electrically connected , it is sequentially operated state, and a plurality of capacitance detection circuits for detecting an electrostatic capacitance of the connected said analyzing Dehai line to the detection node,
Obtained from the capacitance is sequentially detected by the capacitance detection circuit of the multiple, based on the values given as the detection result of the electrostatic capacitance, the touch coordinates representing the position of the indicator in the touch screen A touch coordinate calculation circuit for calculating,
The plurality of detection wires are
A plurality of row detection wirings extending in the row direction;
A plurality of column detection wirings intersecting each row detection wiring and extending in the column direction,
The plurality of detection wiring sets are:
A plurality of row detection wiring sets composed of a predetermined number of the row detection wirings;
Including a plurality of column detection wiring sets composed of a predetermined number of the column detection wirings,
The plurality of selection switch circuits are:
A plurality of row selection switch circuits that are respectively provided corresponding to the plurality of row detection wiring groups and sequentially select the row detection wirings included in the corresponding row detection wiring groups;
A touch panel comprising: a plurality of column selection switch circuits which are provided corresponding to the plurality of column detection wiring groups, and sequentially select the column detection wirings included in the corresponding column detection wiring group . When test Dehai line selected by said selection switch circuit, connected to the detection node of the capacitance detection circuit corresponding to the detection interconnect assembly that contains the test Dehai line, the detected voltage appearing at the detection node the buffered touch panel according to claim 1, characterized in that it comprises a detecting voltage application means for applying common to test Dehai lines other than the test Dehai line selected by the selection switch circuit. The detection voltage applying means includes
Provided corresponding to said plurality of capacitance detection circuits, a plurality of buffer circuits for outputting the voltage of the detection node capacitance detection circuit that corresponds to bus Ffaringu,
Provided after the respective buffer circuits, and a state for outputting a voltage outputted from the corresponding to Luba Ffa circuit to a common node, and a plurality of secondary switch circuit for switching between a state for blocking the output to the common node of said voltage ,
The touch panel of claim 2, wherein the voltage of the common node, characterized in that it comprises a common node voltage applying means for applying to at least the detection Dehai lines other than the selected test Dehai lines by the selection switch circuit. Among the plurality of capacitance detection circuits, one of the electrostatic capacitance detection circuit is in an operating state, the detection operation of the electrostatic capacitance to the connected the detection wire in the detection node line Utoki , the other capacitance detection circuit is a stopped state, either of claims 1-3, characterized in that stopping the detection operation of the capacitance to the connected the detection wire in the detection node 1 Touch panel described in one . Among the pre-defined number of test Dehai lines composing each said detection wire pairs, at least one test Dehai line exists at the boundary between the adjacent detection wires set is detected that test Dehai line belongs in different periods from a time selected by you that selection switch circuit corresponding to the wiring group, the selected by the selection switch circuit corresponding to the adjacent detection wires set, the electrostatic capacitance detection corresponding to the adjacent detection wire pair Connected to the detection node of the circuit to detect the capacitance,
The touch coordinate calculation circuit, with respect to detection Dehai lines present in the boundary portion, the electrostatic detected when connected to the detection node of the capacitance detection circuit corresponding to the detection wiring sets its test Dehai line belongs and the detection results obtained from the capacitance, of the obtained that the detection result obtained from the electrostatic capacitance detected when connected to said detection node capacitance detection circuit corresponding to the detection wiring sets adjacent, from the electrostatic capacitance detected when the detection result of the plurality of test Dehai line is connected to the detection node of the capacitance detection circuit corresponding to the detection wiring sets the maximum and name Ru detection wiring belongs the detection results obtained by using as the detection result of the detection Dehai lines present in the boundary portion, a touch panel according to any one of claims 1-4, characterized in that calculating the touch coordinates . Each pre Kisei capacitance detection circuit includes a relaxation oscillator circuit oscillation cycle is changed in accordance with the electrostatic capacity before Symbol detection node,
Between the plurality of capacitance detection circuits and the touch coordinate calculation circuit,
A selector circuit for selecting one of a plurality of the oscillation output signal outputted from the pre-Symbol relaxation oscillator circuit that is part of the plurality of capacitance detection circuits,
A first counting circuit that counts the oscillation output signal selected by the selector circuit until a predetermined count value is reached;
A second counting circuit that counts a period required from when the first counting circuit starts the counting operation until the predetermined counting value is reached, and outputs the counting result as the detection result to the touch coordinate calculation circuit; The touch panel according to any one of claims 1 to 5, further comprising: The touch panel according to any one of claims 1 to 6,
And a display panel mounted on the touch screen of the touch panel.   The display device according to claim 7, wherein the touch screen is adhesively fixed to a front side of the display panel.

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