JP5516620B2 - Collation processing apparatus, control method therefor, and computer program - Google Patents

Description

  The present invention relates to a technical field for avoiding obstacles such as a collation processing apparatus that collates data.

  2. Description of the Related Art Today, for example, for a personal identification, a collation processing device is used that compares obtained data such as a fingerprint with a plurality of registered data.

  Such a collation processing device is not only accurate in collation and quickness of collation with a large amount of registered data, but also has a high availability as a collation processing system from its use, that is, the system is always available. It has been demanded.

  In such a collation processing apparatus, in order to execute collation accurately and at high speed, data collation is performed using, for example, a pattern recognition technique using a highly parallel collation processor. High parallelism is one of the techniques for performing high-speed processing in parallel on input data using a plurality of collation processors having individual memories.

  Then, the external device, which is the host device, transfers data to be verified (that is, search data; hereinafter referred to as “S data”) in advance to each memory of a plurality of highly parallel verification processors. . Further, the external device sequentially collates with the S data by sequentially transferring a plurality of registered collation data to be collated (that is, File data; hereinafter referred to as “F data”) to the memory of each collation processor. By doing so, high-speed processing is realized.

  On the other hand, if a failure occurs in any one of the plurality of matching processors constituting the matching processing device, data transferred to the matching processor may be lost. At that time, the lost data needs to be transferred again from the external device to the memory of another collation processor in the collation processing device that has not failed, so that it takes time to restart the process, There is a problem of reduced availability.

  Even if the collation processing devices are duplicated, it is difficult to make the entire system non-stop if there is a possibility that the installed collation processor may fail.

  In order to solve such a problem, the technique disclosed in Patent Document 1 stores a copy of S data and a copy of F data transferred in advance by an external device in the memory of another processor, When a failure occurs, the copy of the S data and the copy of the F data stored in the memory of the other processor are read again by one of the other non-failed processors, A method for continuing the verification process is disclosed.

JP 2010-182141 A

  In a general technique referred to in Patent Document 1, in a database that is distributedly processed by a plurality of modules, a spare database that is a copy of the current database is stored from the management server when the contents of the memory that holds the current database are broken. It is described that the processing is continued by transferring to the spare module.

  This is a general technique referred to in Patent Document 1. It takes time to transfer and switch the backup database from the management server to the backup module, and the database cannot be accessed during the switching. It is something to try.

  In Patent Document 1, since a standby database of the active database is arranged in advance in each module, data transfer from the switching management server to a plurality of modules becomes unnecessary at the time of switching. This reduces the time during which database access is disabled.

  However, the technique described in Patent Document 1 requires that another processor holds a copy of data stored in the memories of all processors. That is, there is a problem that the memory capacity for storing the verification information in the entire apparatus is doubled, which increases the cost of the apparatus, and it is intended to hold the minimum necessary data based on the failure prediction. is not.

  Therefore, in a system that operates such that F data replacement frequently occurs based on an instruction from an external device, the time for data replacement work becomes enormous and the operation efficiency is significantly reduced. 1 has a problem that it cannot be applied to such an operation mode.

The main purpose of the present invention is to solve the above-mentioned problems.
Control of a verification processor that predicts the occurrence of a failure in the verification processor and can recover in a short time and reduce the amount of processing resources such as memory and data transfer required for recovery when a failure occurs It is to provide a device or the like.

  The present invention has been made for the purpose of solving the above-described problems. That is, the collation processing device according to the present invention detects a failure sign of a specific processing unit among the plurality of processing units based on diagnostic information for diagnosing the states of the plurality of processing units that collate data. The data to be transferred to the specific processing unit is also stored in the storage device, and when the specific processing unit fails, the data stored in the storage device is not detected as a sign of failure. The data is transferred to the processing unit and the collation process by the other processing unit is designated.

  It is to be noted that the same object is achieved by a computer program that realizes the control method of the verification processing apparatus having the above-described configuration and its failure avoidance method by a computer, and a computer-readable storage medium that stores the computer program. Is also achieved.

  In addition, the collation processing system which is another aspect of the present invention that solves the same object stores the data of the processing unit in which the failure is predicted based on the failure prediction of the processing unit described above in the storage device, and When a failure occurs in a processing unit where a failure is predicted, an integrated circuit is added to a function that realizes a method of performing a matching process by transferring data stored in a storage device to another processing unit where a failure is not predicted. This is achieved by a collation processing system as a system for performing collation processing by controlling the collation processing device on which the integrated circuit is mounted.

  According to the present invention, while predicting the occurrence of a failure of a verification processor, when a failure occurs, the failure can be recovered in a short time and the amount of processing resources such as memory and data transfer required for recovery can be suppressed. it can.

It is a block diagram which shows the outline | summary of the collation processing apparatus which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the detail of the collation processing apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the data backup operation | movement based on the diagnosis of the failure precursor of the collation processor which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows transfer operation | movement of the backup data based on the diagnosis of the failure sign of the collation processor which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows operation | movement of the general collation processing apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the application example of the collation processing apparatus which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the collation processing system as a system which used the integrated circuit for each control function of the collation processing apparatus which concerns on the 4th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
The configuration of the first embodiment of the present invention will be described. FIG. 1 is a block diagram showing an overview of a collation processing apparatus according to the first embodiment of the present invention.

  The collation processing apparatus 1 according to the present embodiment includes a control unit 2, a storage device 3, and a collation processing unit 8 including a first processing unit 4 and a second processing unit 5. In addition, the control unit 2 transfers S data, which is data to be collated, and F data, which is collation data, to the first processing unit 4 and the second processing unit 5. In addition, the control unit 2 obtains diagnostic information 6 from the first processing unit 4 or the second processing unit 5.

  It continues and demonstrates operation | movement of the collation processing apparatus 1 of this embodiment.

  The collation processing device 1 according to the present embodiment is configured so that any processing unit is based on the diagnostic information 6 that is the result of examining the state of the collation processing unit 8 having a plurality of processing units that collate S data with a plurality of F data. The control unit 2 that detects the failure sign also stores the F data to be transferred to any of the processing units that have detected the failure sign in the storage device 3.

  At the same time, when the specific processing unit that has detected the failure sign described above fails, the control unit 2 uses other F data stored in the storage device 3 for other processes that have not detected the failure sign. And instructing collation processing by another processing unit.

  That is, according to the present embodiment, even if one of the processing units fails, by transferring the F data held by the storage device to the processing unit that has no sign of other failure, the loss of F data is prevented, Since it is not necessary to transfer the F data again from an external device (not shown), the recovery process can be performed quickly.

  In addition, since the F data of only the processing unit that has determined the sign of failure is backed up in advance to the storage device, the amount of processing resources such as storage device and data transfer required for continuation of recovery and verification processing is minimized. There is an effect that it can be completed with.

  Furthermore, even after the control unit diagnoses the failure sign, the verification process can be continued until a failure actually occurs, so that an effect of suppressing a period of performance degradation can be achieved.

  Note that a readable / writable memory or the like may be used as the storage device in the present embodiment.

  In other words, according to the present embodiment, while predicting the occurrence of a failure in the verification processing unit, when a failure occurs, it is recovered in a short time, and the amount of processing resources such as memory and data transfer required for the recovery is reduced. Can be suppressed.

  The first embodiment of the present invention has been described above by taking the configuration and operation described above as examples. However, the present invention is not necessarily limited to the configuration and operation.

<Second Embodiment>
Next, a second embodiment of the present invention based on the first embodiment will be described in detail with reference to FIGS. FIG. 2 is a block diagram showing details of the collation processing apparatus according to the second embodiment of the present invention.

  The collation processing device 1 of the present embodiment is connected to the external device 20 and receives data transfer from the external device 20 with S data and F data (not shown) as collation information 7 and a collation instruction. . The collation processing device 1 includes an overall control unit 10, a plurality of collation processors, a collation processor A15, a collation processor B18,..., And a collation processor n19 (n is an integer; hereinafter the same).

  The overall control unit 10 of the verification processing apparatus 1 includes a data transfer / verification instruction control unit 11, a verification result editing unit 12, an overall memory 13, and a diagnosis control unit 14.

  In addition, each of the verification processors A15, B18,..., N19 in the verification processing device 1 has a verification memory 16 that holds S data and F data.

  The overall control unit 10 performs the above-described data transfer with the S data and F data from the external device 20 and the data transfer / collation instruction control unit 11 based on the collation instruction to the plurality of collation processors. Sent data transfer and verification instructions.

  Specifically, the external device 20 first transfers S data to the data transfer / collation instruction control unit 11 in the overall control unit 10. Then, the S data is transferred from the data transfer / collation instruction control unit 11 to each collation processor.

  Next, the external device 20 sequentially transfers a plurality of data sets of F data to the data transfer / collation instruction control unit 11 of the overall control unit 10. Then, the data transfer / collation instruction control unit 11 sequentially allocates each collation memory 16 of each collation processor A15, B18,.

  Then, based on the collation instructions output from the external device 20 to the collation processors A15, B18,..., N19, the data transfer / collation instruction control unit 11 sequentially sends collation instructions to the collation processors. .

  As a result, for the S data previously transferred from the external device 20 to the collation memory 16 of each collation processor via the data transfer / collation instruction control unit 11, the overall control unit 10 also performs data transfer / Collation with the F data sequentially transferred to the collation memory 16 of each collation processor via the collation instruction control unit 11 is sequentially performed, and collation result information 9 as the collation result is sent to the collation result editing unit 12 of the overall control unit 10. .

  In addition, each verification processor A15, B18,..., N19 has a diagnostic unit 17, and each diagnostic unit 17 has each verification unit in each verification processor A15, B18,. Detection of error checking and correction (hereinafter referred to as “ECC”) errors that can be detected and corrected when data is read from or written to the memory 16, and each of the matching processors A15, B18,. It collects and calculates a value obtained by integrating the temperature of heat generated by the operation of the verification processor itself and the time at which the verification processing is executed at that temperature.

  The collation result editing unit 12 edits the collation result information 9 sent from each collation processor A15, B18,..., N19, and all S data and F data sent from the external device 20 to the collation processing device 1. Are compared together and stored in the entire memory 13.

  Here, the collation result editing unit 12 grasps the collation information 7 transferred from the data transfer / collation instruction unit 11 of the overall control unit 10 to each collation processor and the collation result information 9 which is the collation result. Therefore, it is possible to know whether any of the verification processors has failed during the verification process.

  Then, the external device 20 takes the collation result from the entire memory 13 after the collation process is completed.

  In addition, the diagnosis control unit 14 included in the overall control unit 10 includes the verification processors A15, B18,..., N19 obtained by the respective diagnosis units 17 of the verification processors A15, B18,. Based on the collected information on the number of occurrences of ECC errors, which are detection errors and correctable errors of the collation memory 16 included in each of them, it is predicted whether or not a failure that makes collation processing impossible will occur in the future. It has a function.

  Similarly, the diagnosis controller 14 obtains each collation processor A15, B18,..., N19 each collation processor itself obtained by each diagnosis unit 17 of each collation processor A15, B18,. Based on the collected information on the temperature of the heat generated and the operating time at that temperature, it has a function to predict whether or not a failure will occur that will make collation processing impossible in the future. .

  The temperature information of the collation processor collected by the diagnosis unit 17 is obtained by using, for example, the temperature dependence of the current-voltage characteristic of the temperature measurement thermal diode built in the semiconductor of the collation processor in advance. Information obtained by converting the value into temperature information may be used, or temperature information from an external temperature sensor attached to the heat generation surface of the verification processor may be used.

  In the prediction of the failure, the diagnosis control unit 14 assigns points by performing weighting, which will be described later, on each information of the ECC error and the temperature of the verification processor itself and the operation time at the temperature, and the score is a predetermined threshold value. When the score is exceeded, it is determined that the processor has a sign of failure.

  As a specific example, when an ECC error occurs, +1000 points are added per time.

  In addition, the average value of the actual temperature of the verification processor measured by the temperature measurement function built in the verification processor is a plus value with respect to, for example, 80% of the upper limit value of the guaranteed operating temperature range. The temperature difference in the direction, that is, + ΔT ° C. (Celsius, hereinafter the same) and the integration of the time D during which collation processing was performed at a temperature exceeding the set value, that is, (+ ΔT × D) are added.

  If the sum of these values exceeds a predetermined threshold, it is determined that there is a possibility of failure, that is, a failure predictor verification processor.

  For example, when the set value is exceeded by 10 ° C. and operated for 10 hours, +100 points are added, so the total when an ECC error occurs once is 1100 points.

  Here, for example, if the threshold value is set as 1500 points, the prediction of failure is determined as a verification processor that has a possibility of failure when the above-described total value exceeds 1500 points, and the verification processor will The F data transferred from the external device 20 to be processed to the collation memory 16 of the collation processor via the data transfer / collation instruction control unit 11 is also stored in a backup area (not shown) for the collation processor of the entire memory 13. In preparation for the occurrence of a failure of the actual verification processor.

  In addition, what is necessary is just to let the average value of the actually measured temperature of the collation processor mentioned above be the average value for 10 seconds etc., for example. The target to be compared with the average value of the actually measured temperatures may be determined according to the median value of the operation guarantee temperature range of the collation processor or between the median value and the upper limit value according to the installation environment of the collation processing device 1.

  Further, an ECC error in a cache memory (not shown) used when data is transferred between the data transfer / collation instruction control unit 11 of the overall control unit 10 and the collation memory 16 included in each collation processor is also a target of failure indication. You may make it diagnose in the diagnostic part 17. FIG.

  It should be noted that the parameters for observing the above-mentioned failure signs and their threshold values are given as an example for convenience of explanation, and are not limited to the parameters and threshold values described above.

  Next, the operation will be described based on the configuration of the present embodiment described above. The operation will be described with reference to the block diagrams of FIGS. 2 to 4 based on the flowchart of FIG. 5 showing the operation of the general verification processing apparatus according to the present embodiment.

  First, a general operation flow will be described below.

  The overall control unit 10 of the verification processing device 1 receives S data not shown in FIG. 2 from the external device 20 (step S1).

  Next, the data transfer / collation instruction control unit 11 of the overall control unit 10 that has received the S data transfers the received S data to all the collation processors A15, B18,. S2).

  Next, the data transfer / collation instruction control unit 11 of the overall control unit 10 of the collation processing apparatus 1 receives a plurality of F data not shown in FIG. Is received (step S3). Here, the plurality of F data represents, for example, registered biometric data, a data set for a plurality of persons (that is, for a plurality of persons).

  Then, the data transfer / collation instruction control unit 11 of the overall control unit 10 sequentially transfers the individual F data among the plurality of F data to a collation processor that is free of processing, and sequentially issues a collation instruction ( Step S4).

  Here, the individual F data represents, for example, data for one person if it is registered biometric data or the like. That is, the data transfer / collation instruction control unit 11 sequentially allocates F data for one person for each collation processor.

  The collation processor to which the overall control unit 10 assigns the F data is an unprocessed collation processor, and the collation processor to which the collation result editing unit 12 of the overall control unit 10 has assigned the process is completed. This means that a collation processor that has not yet been allocated processing or has completed collation processing.

  Next, each verification processor individually transmits the S data previously transferred by the data transfer / verification instruction control unit 11 in step S2 and the verification processor in which the data transfer / verification instruction control unit 11 has an empty process in step 4. A collation process is performed on the F data transferred to, and collation result information 9 of each collation processor is sent to the collation result editing unit 12 (step S5).

  Then, the collation result editing unit 12 edits individual collation result information 9 obtained from each collation processor by the collation result editing unit 12, and is sent from the external device 20 to the overall control unit 10 of the collation processing device 1. A collation result of all the F data is created (step S6).

Finally, the overall control unit 10 transmits the collation result obtained in step S6 to the external device 20 (step S7).
Here, if a failure occurs in any of the verification processors in step S4 or step S5, the S data and the F data transferred to the verification processor are lost.

  In general collation processing, the overall control unit 10 does not manage information on which F data has been transferred to which collation processor, and therefore, data is again obtained for all F data transferred from the external device 20. It is necessary to transfer and re-execute the collation process from the beginning.

  Next, the operation in the present embodiment will be described with reference to FIGS. 3 and 4 focusing on the difference from the general operation flow described above. Here, the operation when the diagnosis control unit 14 determines that the possibility of failure is high in the verification processor A15 will be described as an example.

FIG. 3 is a block diagram showing a data backup operation based on the diagnosis of the failure sign of the verification processor according to the present embodiment.
FIG. 4 is a block diagram showing the backup data transfer operation based on the diagnosis of the failure sign of the verification processor according to this embodiment.

  As shown in FIG. 3, when the data transfer / collation instruction control unit 11 determines that there is a possibility that a failure may occur in the collation processor A15 based on the diagnosis information 6, the data transfer / collation instruction control unit 11 F data (not shown) to be transferred to the verification memory 16 is also stored in the overall memory 13 of the overall control unit 10 (that is, backed up).

  At this time, the overall control unit 10 stores the verification result information 9 in the overall memory 13 of the overall control unit 10 when the verification processor A15 operates normally and the verification processor sends the verification result information 9 to the verification result editing unit 12. Discarded data (hereinafter the same).

  Here, consider a case where the verification processor A15 fails during the verification process.

  Whether or not any of the verification processors has failed is determined by a response of an acknowledgment (not shown) from each verification processor in response to a verification instruction from the data transfer / verification instruction control unit 11 by a predetermined period. It is determined whether or not the verification result information 9 does not come to the verification result editing unit 12 by a predetermined period after the verification process is started.

  As shown in FIG. 4, when the overall control unit 10 does not send the response to the collation instruction to the collation processor A15 or the collation result information 9 after the collation processing is started within a predetermined period, the collation processor A15. Is determined to have failed. Then, the data transfer / collation instruction control unit 11 of the overall control unit 10 sends the F data stored in the backup area of the overall memory 13 to the collation memory of the collation processor (for example, the collation processor B18) with no other signs of failure from the overall memory 13. 16 and a collation instruction is issued to the collation processor B18.

  According to the above method, even if any verification processor fails during the verification process, it is not necessary to retransmit the F data from the external device 20, and there is a possibility that the F data stored in the backup area is also defective. Since only a certain verification processor is required, a memory capacity for storing F data, a data transfer amount, and a bus occupation rate associated therewith can be reduced.

  In the present embodiment, the storage of the F data in the backup area is described as being stored in a backup area (not shown) of the overall memory 13 of the overall control unit 10 as an example. Depending on the size of the F data, the data may be stored in the collation memory 16 of another collation processor having no sign of failure.

  That is, according to the verification processing apparatus according to the present embodiment, even if any of the processing units fails, the F data lost by transferring the F data held in the entire memory to the other processing unit without any sign of failure. In addition, it is not necessary to transfer the F data again from the external device, so that the recovery process can be performed quickly.

  In addition, since the F data of only the processing unit that has determined the sign of failure is backed up to the entire memory in advance, the amount of memory resources required for recovery and continued verification processing can be minimized. Can be played.

  Furthermore, even after the diagnosis control unit of the overall control unit diagnoses a sign of failure, the collation process can be continued until a failure actually occurs, so that the performance degradation period can be suppressed. Can do.

  That is, while predicting the occurrence of a failure of the verification processor, when a failure occurs, it can be recovered in a short time and the amount of processing resources such as memory and data transfer required for recovery can be suppressed.

  As described above, the configuration and operation described above have been described as examples of the second embodiment of the present invention, but the present invention is not necessarily limited to such configuration and operation.

<Third Embodiment>
Next, a third embodiment based on the second embodiment will be described with reference to FIG.

  FIG. 6 is a block diagram illustrating an application example of the matching processing device according to the present embodiment. The block diagram of this embodiment shown in FIG. 6 is different from the second embodiment shown in FIG. 2 in that a threshold control unit 25 is added to the overall control unit 10.

  Therefore, in the following description, parts that perform the same operations as those in FIG. 2 described in the second embodiment are denoted by the same reference numerals, description thereof is omitted, and the configuration is mainly configured with the above-described differences in the present embodiment. The operation and effect will be described.

  In the present embodiment, parameters for monitoring a failure sign and a threshold value for determining a failure sign are determined according to the available memory capacity of the overall memory 13 included in the overall control unit 10 of the verification processing device 1. Variable. That is, if the capacity that can be used for storing F data is large, the number of processors that can predict a failure is increased by lowering the threshold value for determining that it is a failure sign.

  As a result, it is possible to improve fault tolerance by storing more F data.

  The threshold control unit 25 of the overall control unit 10 uses, as a backup area for F data, an area other than the memory area for controlling the verification processing device 1 including the overall control unit 10 among the entire capacity of the overall memory 13. When the backup area is larger than a certain capacity, as described in the second embodiment, the threshold for diagnosing a failure sign is lowered.

  That is, for example, a point value based on the accumulated time of a point value based on the number of occurrences of an ECC error and a time D operated exceeding + ΔT ° C. from a set value that is, for example, 80% of the upper limit value of the operation guarantee temperature range of the verification processor; Lower the threshold for the total point value that is added together.

  As an example, the threshold for determining a sign of failure is lowered from 1500 points to 1200 points. As a result, the condition for monitoring the failure signs becomes stricter, so that the failure signs of more verification processors can be monitored.

  Thus, the overall control unit 10 stores the F data of each of the plurality of collation processors in the backup area of the overall memory 13 for each collation processor, so that even if a plurality of collation processors fail, a sign of failure F data to be transferred to the collation memory 16 can be prepared in advance by using another collation processor with no replacement as an alternative destination.

  If a failure occurs, the F data for each verification processor is quickly transferred from the backup area of the entire memory 13, so that the verification operation can be continued almost without delay, unlike when it is transferred again from the external device 20. can do.

  Also, as an application example of the present embodiment, a central processing unit (not shown) (hereinafter referred to as “CPU”), a chip set, a readable / writable nonvolatile storage, and the entire memory shown in FIG. In order to realize the collation processing device 1 controlled by the overall control unit 10 consisting of 13, the functions of the block diagrams shown in FIGS. 2 to 6 and the operations of the flowcharts described above can be realized by an application program (hereinafter, “ In other words, after being supplied as a computer program, the computer program prepared as a method for controlling the collation processing apparatus by the overall control unit 10 and a cooperating operating system (hereinafter referred to as “OS”) are provided. And AP in memory It may be accomplished by running out.

  That is, according to the verification processing apparatus according to the present embodiment, even if any of the processing units fails, the verification data can be lost by transferring the F data held in the memory to the processing unit having no other failure sign. In addition to preventing this, it is not necessary to transfer the F data again from the external device, so that the recovery process can be performed quickly.

  In addition, since the F data of only the processing unit that has determined the failure sign is stored in the entire memory in advance, it is possible to minimize the amount of memory resources required for the recovery and the continuation of the verification process. Can play.

  Furthermore, even after the diagnosis control unit of the overall control unit diagnoses a sign of failure, the collation process can be continued until a failure actually occurs, so that the performance degradation period can be suppressed. Can do.

  In addition, the threshold value of the sign of failure is automatically varied while monitoring the size of the backup area of the F data in the entire memory corresponding to the plurality of verification processors and the point value of the sign of failure. As a result, it is possible to achieve an effect that the fault tolerance and the necessary resources can be balanced.

  That is, while predicting the occurrence of a failure of the verification processor, when a failure occurs, it can be recovered in a short time and the amount of processing resources such as memory and data transfer required for recovery can be suppressed.

  As described above, the configuration and operation described above have been described as examples as the third embodiment of the present invention, but the present invention is not necessarily limited to such configuration and operation.

<Fourth Embodiment>
Next, a fourth embodiment based on the second to third embodiments will be described.

  This embodiment will be described with reference to a block diagram showing a verification processing system as a system using an integrated circuit for each control function of the verification processing apparatus according to the present embodiment shown in FIG.

  This embodiment can be understood as, for example, a collation processing system 30 as a system in which each function for realizing the failure avoidance method in the application example of the collation processing device shown in FIG. 6 is integrated.

  In other words, the control functions of the data transfer / collation instruction control unit 11, the collation result editing unit 12, the diagnosis control unit 14, and the threshold control chip 25 shown in FIG. 6 are configured as an integrated circuit.

  Therefore, in the following description, the same configuration as the block diagram shown in FIGS. 2 and 6 described in the second to third embodiments, the flowchart shown in FIG. 5, the second embodiment, and the third embodiment. The description of the portions that perform the same operations as the contents described in the embodiments will be omitted, and the configuration, operations, and effects will be described focusing on the above-described differences in the present embodiment.

  In the present embodiment, among the functions of the overall control unit 10 that controls the highly parallel matching processor in the matching processing system 30, the data transfer / matching instruction control unit 11 shown in FIG. 6, the matching result editing unit 12, The control functions of the diagnosis control unit 14 and the threshold control unit 25 are realized using the data transfer / collation instruction control chip 31, the collation result editing chip 32, and the diagnosis / threshold control chip 33 shown in FIG. The diagnosis control unit 14 and the threshold control unit 25 may be separate chips.

  The operation of the collation processing system 30 in the present embodiment is the same as the operation described as the collation processing device 1 in the second and third embodiments, and will not be repeated.

  And this collation processing system 30 uses the integrated circuit which is a general technique now as a modification of the basic embodiment mentioned above, in addition to the effect of the basic embodiment mentioned above, it is small-sized. And lower power consumption can be achieved, and the effect of improving the degree of freedom of installation can be obtained.

  Further, by using an integrated circuit, it is possible to obtain an additional effect that processing of each function of the overall control unit 10 of the verification processing system 30 can be performed at high speed.

  In addition, as a device configuration in which the functional blocks shown in FIG. 6 described above are partly integrated into an integrated circuit according to the size of the verification processing system and power consumption, and the rest are processed by software. Also good.

  That is, according to the verification processing apparatus according to the present embodiment, even if any of the processing units fails, the verification data is lost by transferring the F data held in the memory to a processing unit that has no sign of failure. In addition, it is not necessary to transfer the F data again from the external device, so that the recovery process can be performed quickly.

  In addition, since the F data of only the processing unit that has determined the failure sign is stored in the entire memory in advance, it is possible to minimize the amount of memory resources required for the recovery and the continuation of the verification process. Can play.

  Furthermore, even after the diagnosis control unit of the overall control unit diagnoses a sign of failure, the collation process can be continued until a failure actually occurs, so that the performance degradation period can be suppressed. Can do.

  In addition, by automatically changing the threshold value of the failure sign while monitoring the size of the F data backup area of the entire memory corresponding to the plurality of check processors and the point value of the sign of failure by the plurality of check processors Thus, it is possible to achieve an effect that the fault tolerance and the necessary resources can be balanced.

  In addition, by integrating the processing functions of the overall control unit into an integrated circuit, additional effects such as downsizing, lower power consumption, improvement in the degree of freedom of installation, and higher processing speed can be achieved.

  In other words, while predicting the occurrence of a failure in the verification processor, when a failure occurs, it can be recovered in a short time and the amount of processing resources such as memory and data transfer required for recovery can be suppressed.

  As described above, the configuration and operation described above have been described as examples as the fourth embodiment of the present invention, but the present invention is not necessarily limited to such configuration and operation.

  The present invention is not limited to the above-described embodiments, and can be applied to a collation processing device for collating data to be collated with a plurality of pieces of collation data, for example, biometric data such as fingerprints and palm prints.

DESCRIPTION OF SYMBOLS 1 Collation processing apparatus 2 Control part 3 Storage device 4 1st process part 5 2nd process part 6 Diagnostic information 7 Collation information 8 Collation process part 9 Collation result information 10 Overall control part 11 Data transfer and collation instruction control part 12 Collation result edit Unit 13 Overall memory 14 Diagnosis control unit 15 Verification processor A
16 collation memory 17 diagnostic unit 18 collation processor B
19 Matching processor n
20 External Device 25 Threshold Control Unit 30 Verification Processing System 31 Data Transfer / Verification Instruction Control Chip 32 Verification Result Editing Chip 33 Diagnosis / Threshold Control Chip

Claims (10)

Based on diagnostic information for diagnosing the status of a plurality of processing units that collate data, when a sign of failure of a specific processing unit among the plurality of processing units is detected, data to be transferred to the specific processing unit while store in the storage device, when said specific processing unit fails, the data stored in the storage device, with also transferred to other processing units does not detect a sign of failure, and transfer collation processing equipment having a control unit for instructing the verification processing by the other processing unit to the data. The data to be collated by each processing unit includes data to be collated to be collated and a plurality of pieces of collation data to be compared with the data to be collated.
The controller is
The verification data is transferred to a plurality of verification processors as the plurality of processing units, and individual verification data of the plurality of verification data is individually assigned to the verification processors and transferred to the verification processors. wherein the collated data, verification processing equipment according to claim 1, characterized in that an instruction to matching with the collation data. The controller is
And error detection and the number of occurrences of the error correctable ECC (Error Checking and Correction) error from the diagnostic unit in collating the memory that each collation processor Yusuke of the verification processor, respective with the the operation of the verification processor receiving diagnostic information collation processor itself consists an integrated value of the operating time at temperature and the temperature of the heat generated, based on the diagnostic information received, characterized by identifying the matching processor with a sign of failure collation processing equipment according to claim 2,. The controller is
And the number of occurrences of the ECC error forming the diagnostic information from the diagnostic portion of at least one of the verification processor, to the integrated value of the operating time at temperature and the temperature of the heat which the matching processor itself occurs In addition, each weighted value is assigned as the number of points, and the number of points of the integrated value of the number of occurrences of the ECC error, the temperature of the heat generated by the verification processor itself, and the operating time at that temperature when exceeding the threshold stipulated bets in advance the total number of points which is the sum of, collation processing equipment according to 請 Motomeko 3 you and determines that the verification processor is the symptom of failure. The controller is
Further comprising an overall memory that is the storage device;
Collation processing equipment according to the verification data to be transferred to a particular verification processor which has detected the failure sign, the 請 Motomeko 4 you and transferring the the entire memory. The controller is
From the storage area before Symbol entire memory, the verification processing apparatus has a region backup area excluding the memory area to be used when running, the storage capacity of the backup area can store a plurality of said verification data If, in determining whether at least the certain sign of failure in any of the verification processor based on the diagnostic information, as well as dynamically changing the threshold value of the total number of points, before Symbol failure sign to the backup area collation processing equipment according to 請 Motomeko 4 it and storing the amount of the plurality of matching data to be assigned to the plurality of the verification processor is determined to be. The controller is
Wherein wherein matching further verification result editing unit for editing the verification result information is collation result from the processor, when said specific verification processor is working properly, and sends the verification result information to the verification result editing unit together, collation processing equipment according to claim 5, characterized in that discarding the data stored in the entire memory. The controller is
A data transfer / collation instruction control unit for transferring the collation data and the collation data and instructing execution of the collation, and receiving the diagnostic information from the diagnostic units of the collation processors, and receiving the received diagnostic information A diagnostic control unit for diagnosing which verification processor has a failure sign based on the failure information, and at least one verification processor based on the diagnostic information according to a storage capacity in the backup area of the entire memory A threshold value control unit that dynamically changes a threshold value that is determined to be present ;
Claims, characterized and the data transfer and matching instruction control unit, and the comparison result editing unit, and the entire memory, and the diagnosis controller, to a semiconductor integrated circuit at least one of said threshold control unit collation processing equipment according to 5. Based on diagnostic information for diagnosing the status of a plurality of processing units that collate data, when a sign of failure of a specific processing unit among the plurality of processing units is detected, data to be transferred to the specific processing unit while store in the storage device,
Wherein when a specific processing unit fails, the said data stored in the storage device, with also transferred to other processing units does not detect a sign of failure, those said other processing unit for transferring data A method for controlling a collation processing apparatus, characterized by instructing collation processing using A computer program for controlling the verification processing device, the computer program
Based on diagnostic information for diagnosing the status of a plurality of processing units that collate data, when a sign of failure of a specific processing unit among the plurality of processing units is detected, data to be transferred to the specific processing unit while store in the storage device, when said specific processing unit fails, the data stored in the storage device, with also transferred to other processing units does not detect a sign of failure, and transfer A computer program for causing a computer to realize control for instructing collation processing by the other processing unit for data.

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