JP5510184B2 - Semiconductor switching element driving apparatus and semiconductor switching element driving method - Google Patents

Description

  The present invention relates to a driving apparatus and a driving method for driving a semiconductor switching element connected in series with a load between a power source and a ground by a PWM signal.

  Conventionally, in order to suppress switching noise when PWM control is performed, a technique for providing an inclination to the rising edge and falling edge of a PWM signal is disclosed in, for example, Patent Document 1.

JP-A-6-141590

  However, as a result of performing such control, the time during which a semiconductor switching element such as a MOSFET to be controlled is actually turned on is longer than the duty specified by the original PWM signal before controlling the slope. Therefore, there is a problem that an intended control result cannot be obtained.

That is, as shown in FIG. 14, the MOSFET is turned on when the gate potential exceeds the on-threshold voltage Vt of the MOSFET in the rising period of the gate signal to which the slope is applied, so that the voltage output to the load via the MOSFET The rising edge of the signal is delayed by a time a from the rising edge of the input signal. In the falling period of the gate signal, the MOSFET is turned off when the gate potential falls below the ON threshold voltage Vt, so that the falling of the voltage signal is delayed by time b from the falling of the input signal. As a result, when the duty y of the output signal is x, the duty y of the output signal is
y = x + ba
It becomes. In this case, (b> a) is assumed, but the duty y of the output signal is expanded by (b−a) with respect to the duty x of the input signal.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a driving device and a semiconductor switching element that can turn on the semiconductor switching element only during the same period as the originally intended duty even when controlling the slope of the PWM signal. It is to provide a driving method.

According to the driving device of the semiconductor switching element according to claim 1 or 3, wherein the signal output means, PWM signal input (hereinafter, simply referred to as "PWM signal" indicating the signal) to the rise and fall of When outputting an inclination giving signal with an inclination to the control terminal of the semiconductor switching element, the duty adjustment means detects a voltage signal output to the load via the semiconductor switching element, and the voltage signal is detected from the rising edge of the PWM signal. The time a until the rise and the time b from the fall of the PWM signal to the fall of the voltage signal are obtained, and if the duty of the PWM signal is x, a signal set to duty z = (x + a−b) is output as a signal. Output to the means.

  That is, the duty x is shortened by the rising delay time a of the voltage signal, and the duty x is extended by the falling delay time b of the voltage signal. Therefore, if a signal that is set to duty z = (x + a−b) is applied to the signal output means in place of the duty x of the PWM signal to generate a slope giving signal, a voltage signal that is output according to the slope giving signal. Is equal to “x”. As a result, a voltage signal having a duty equal to the duty x, which is the original control target, can be output to the load. In the present invention, as described above, it is assumed that the magnitude relationship between the times a and b is (a <b).

Further, according to the driving device of the semiconductor switching element according to claim 1, wherein the duty adjusting means, first, the time the second counter a, when b the counting respectively, subtractors than their count value (b-a ) Is calculated. The third counter starts counting from the rising edge of the PWM signal, outputs a count end signal when the time corresponding to (b−a) is counted, and outputs a logical product signal of the PWM signal and the count end signal. Output to output means. If comprised in this way, the rise of the signal output to the signal output means by the duty adjustment means will be delayed by the time (b−a) from the rise timing of the PWM signal. As a result, the duty z becomes z = x− (b−a) = (x + a−b), so that the duty z of the inclination imparting signal can be set as expected by the above calculation process.

According to the driving device of the semiconductor switching element according to claim 2, wherein the duty adjusting means, first, the time the second counter a, when b and counts respectively, the first subtractor from their count value (b-a ) And the second subtractor calculates (x + a−b). The third counter starts a count operation from the rising edge of the PWM signal, outputs a count end signal when a time corresponding to (x + a−b) is counted, and outputs a logical product signal of the PWM signal and the count end signal. Output to output means. If comprised in this way, the fall of the signal output to a signal output means by a duty adjustment means will advance the time (ba) from the fall timing of a PWM signal. As a result, since the duty z becomes z = (x + a−b), the duty z of the inclination imparting signal can be set as expected by the above arithmetic processing.

  According to another aspect of the present invention, the signal selecting means is adjusted to the duty z by the duty adjusting means when the duty x of the PWM signal becomes a value less than the time (b−a). Instead of the signal, the PWM signal is output to the signal output means. That is, in the present invention, as described above, it is assumed that (a <b), that is, (b−a> 0). Therefore, when (x <b−a), the duty adjustment is performed. The means cannot generate an output signal. Therefore, in the above case, the operation of the duty adjusting means is invalidated, and the input PWM signal is given to the signal output means to perform an exceptional process so that a voltage signal can be output to the load.

Functional block diagram showing the configuration of the driving apparatus according to the first embodiment Timing chart showing signal waveforms of each part Diagram showing mainly the internal configuration of the duty adjustment unit Timing chart showing processing of duty adjustment unit Timing chart showing (a) input signal, (b) drive signal, (c) gate signal, (d) output signal FIG. 5 equivalent diagram in the case of the prior art FIG. 5 equivalent diagram when the duty of the input signal is extremely short FIG. 3 equivalent view showing the second embodiment 4 equivalent diagram FIG. 1 equivalent view showing the third embodiment Figure equivalent to FIG. FIG. 3 equivalent view showing the fourth embodiment Figure equivalent to FIG. FIG. 2 equivalent diagram showing the prior art

(First embodiment)
The first embodiment will be described below with reference to FIGS. FIG. 1 is a functional block diagram showing a configuration of a driving apparatus when a lamp is a driving target, for example, and FIG. 2 is a timing chart showing signal waveforms of respective parts. A series circuit of an N-channel MOSFET (semiconductor switching element) 1 and a lamp (load) 2 is connected between the power supply and the ground (high-side drive system). The duty adjustment unit (duty adjustment means) 3 is supplied with a PWM signal generated in accordance with a duty command given from a host control device as an input signal (see FIG. 2A). The duty adjustment unit 3 outputs a signal obtained by adjusting the PWM duty of the input signal to the next stage gate drive circuit (signal output means) 4 as a drive signal as described later (see FIG. 2B).

  The gate drive circuit 4 generates a trapezoidal wave-like signal (gradient imparting signal) with a slope applied to the rising edge and the falling edge of the PWM signal with the duty adjusted by the duty adjusting section 3, and uses this as a gate signal. Output to the gate (control terminal) of the N-channel MOSFET 1 (see FIG. 2C). Here, the PWM signal is given such that the falling slope is smaller than the rising slope. The source of the N-channel MOSFET 1 is connected to the input terminal of the duty adjustment unit 3, and the duty adjustment unit 3 outputs a voltage signal (output signal, see FIG. 2D) output to the lamp 2 via the N-channel MOSFET 1. ).

  FIG. 3 mainly shows the internal configuration of the duty adjustment unit 3. The first counter 5 counts the time (rise delay time) a from the rising edge of the input signal to the rising edge of the output signal. The second counter 6 counts a time (falling delay time) b from the falling edge of the input signal to the falling edge of the output signal. The first flip-flop 7 holds the count data of the first counter 5; time a at the timing when the output signal becomes high level, and the second flip-flop 8 counts the count data of the second counter 6; time b as the output signal Is held at the timing when becomes low level.

  The subtracter 9 subtracts the data held in the second flip-flop 8; the data held in the first flip-flop 7 from the time b; the time a, and outputs a subtraction result (b−a). The third flip-flop 10 holds the subtraction result data (b−a) of the subtracter 9 at the timing when the output signal becomes low level. If setup time is required for the first to third flip-flops 7, 8, and 10 to hold data reliably, an output signal with an appropriate delay may be used as a data latch signal.

  The down counter (third counter) 11 is loaded with the data held in the third flip-flop 10 as a count value, and starts down counting from the rising edge of the input signal. When the count value becomes “0”, a count end signal (high active) is output to one input terminal of the AND gate 12. The down counter 11 is cleared when the input signal becomes low level. An input signal is applied to the other input terminal of the AND gate 12, and an output signal of the AND gate 12 is applied to the gate drive circuit 4 as a drive signal. Note that the first to third flip-flops 7, 8, and 10 all output data “0” in the initial state after being reset by a reset signal (not shown).

  Next, the operation of the present embodiment will be described with reference to FIGS. In the initial state, since the data value output from the third flip-flop 10 is zero as described above, (a) at the time of the rising edge when the PWM signal with the duty x1 is given as the input signal, the down counter 11 Outputs a high level. Therefore, (b) the drive signal rises almost simultaneously with the input signal, and (c) the gate signal starts to rise with a predetermined slope from the rise time.

  (C) When the gate signal exceeds the ON threshold voltage Vt of the N-channel MOSFET 1, (d) the output signal that is the source potential rises. Then, the first counter 5 counts the time a1 from the rising edge of the input signal to the rising edge of the output signal, and the count value is held in (f) the first flip-flop 7 (FF1).

  (A) When the input signal falls, the drive signal (b) output from the AND gate 12 also falls at that time. Therefore, the duty z1 of the drive signal output first is equal to the duty x1 of the input signal. (C) The gate signal starts to fall with a predetermined slope from the time of the fall. The second counter 6 counts the time b1 from the falling edge of the input signal to the falling edge of the output signal, and (g) the second flip-flop 8 (FF2) holds the count data. The subtracter 9 subtracts the data held in the second flip-flop 8; the data held in the first flip-flop 7 from the time b1; the time a1 and outputs the subtraction result (b1-a1) to the third flip-flop 10. (H) The third flip-flop 10 (FF3) holds the data.

Next, (a) when a PWM signal having a duty x2 is given as an input signal, the down counter 11 starts to count down the loaded data (b1-a1) from the rising edge, and when the count ends, the high level count is started. Output an end signal. As a result, (b) the rising edge of the drive signal is delayed by the time (b1-a1) from the rising edge of the input signal. Subsequent operations are the same as described above. Therefore, the duty z2 of the drive signal is obtained by subtracting the time (b1-a1) from the duty x2 of the input signal.
z2 = x2- (b1-a1) (1)

Then, (c) the gate signal output based on the drive signal has a rise timing delayed by a time a2 from the rise of the drive signal (duty is reduced accordingly), and the fall timing is a time b2 from the rise of the drive signal. Delayed by the same amount (the duty increases by that amount). Therefore, (d) When the duty of the output signal is y2,
y2 = z2-a2 + b2 (2)
In general, a1 = a2 and b1 = b2, so
The relationship between x2 and y2 is
y2 = x2- (b2-a2) -a2 + b2
= X2 (3)
Thus, the duty y2 of the output signal is equal to the duty x2 of the input signal.

  The system of this embodiment is based on the premise that the waveform of the gate signal is trapezoidal and the duty of the drive signal is set shorter than the duty of the input signal. Therefore, it is necessary to limit the setting range of the duty of the input signal, and the limitation will be described with reference to FIGS.

In FIG. 5, (a) the duty x2 of the input signal (hereinafter, x, y, z in parentheses indicate the duty of the corresponding signal) is extremely long, and the time until the next input signal rises is shortened. This is the case. Each rising delay time is indicated by “a”, and each falling delay time is indicated by “b”. In this case, even if (c) the gate signal starts to fall at the fall of the drive signal (z2), the next drive signal (z3) is given before it falls below the ON threshold voltage Vt. Then, the duty y2 of the output signal corresponding to the input signal (x2) is extended beyond the original control, and the output signal (y3) corresponding to the input signal (x3) is not output, and as a result The number of output pulses decreases.
FIG. 6 shows the case of the prior art that does not employ the method of this embodiment. However, if the duty x2 of the input signal is extremely long, the same problem occurs, and this is not a problem specific to this embodiment.

On the other hand, FIG. 7 shows a case where the duty x2 of the input signal is extremely short. From equation (1)
z = x + a−b
Because
x <ba (4)
That is, when the duty x of the input signal is shorter than (ba), the drive signal cannot be output, and as a result, the gate signal and the output signal are not output. Therefore, with respect to the duty x of the input signal, it is assumed that the upper and lower limits shown in FIGS.

  As described above, according to the present embodiment, when the gate drive circuit 4 outputs the gate signal in which the rising and falling edges of the input PWM signal are respectively given to the gate of the N-channel MOSFET 1, the duty adjustment unit 3 Detects a voltage signal output to the lamp 2 via the N-channel MOSFET 1, and a time a from the rise of the input signal to the rise of the voltage signal and a time b from the fall of the PWM signal to the fall of the voltage signal And the drive signal set to the duty z = (x + a−b) is output to the gate drive circuit 4. Therefore, the on-duty of the voltage signal output according to the drive signal can be output to the lamp 2 so as to be equal to the duty x which is the original control target, and the brightness of the lamp 2 can be controlled as expected. .

  Further, when the duty adjustment unit 3 counts the times a and b by the first and second counters 5 and 6, respectively, the subtractor 9 calculates (b−a) from the count values, and the down counter 11 The count operation is started from the rise of the PWM signal, and when the time corresponding to (b−a) is counted, a count end signal is output, and a logical product signal of the PWM signal and the count end signal is output to the gate drive circuit 4. Therefore, the duty z can be set as expected by delaying the rise of the drive signal by (b−a) by the above arithmetic processing.

(Second embodiment)
8 and 9 show the second embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Hereinafter, different parts will be described. In the second embodiment, the duty adjustment section (duty adjustment means) 13 instead of the duty adjustment section 3 is configured such that the duty x of the input signal is the lower limit (ba) of the limit range as shown in FIG. 7 of the first embodiment. The input signal is output to the gate drive circuit 4 as it is, instead of the drive signal that is the output signal of the AND gate 12.

For this reason, a multiplexer (signal selection means) 14 is inserted between the AND gate 12 and the gate drive circuit 4, and an input signal and a drive signal are given to the multiplexer 14 and either one is selected. Is output. The multiplexer 14 also includes a control logic for performing selection switching, and therefore, an input signal and subtraction result data (b−a) held in the third flip-flop 10 are given. Then, the multiplexer 14 measures the duty x from the rising edge of the input signal, measures the time with a counter, and compares the size of the duty x with the subtraction result (ba).
x> (ba) → drive signal
x <(b−a) → Selects and outputs each signal as an input signal.

  Next, the operation of the second embodiment will be described with reference to FIG. FIG. 9 corresponds to FIG. (A) When the duty x1 of the input signal is larger than the previous subtraction result (ba) (not shown) (when the counter value exceeds (ba)), (b) the multiplexer 14 is driven. A signal is selected and output to the gate drive circuit 4. When (a) the duty x2 of the next input signal is larger than the subtraction result (b1-a1), (b) the multiplexer 14 selects the input signal and outputs it to the gate drive circuit 4. The “delay input signal” shown in the process (e) is the time required to count the duty x2 in the multiplexer 14 and compare it with the subtraction result (b1-a1).

As described above, according to the second embodiment, the multiplexer 14 is driven to be adjusted to the duty z by the duty adjustment unit 13 when the duty x of the PWM signal becomes a value equal to or less than the time (b−a). An input signal is output to the gate drive circuit 4 instead of the signal. Therefore, when the duty x becomes an irregular value below the lower limit, the operation of the duty adjustment unit 13 is invalidated, an input signal is given to the gate drive circuit 4 to perform an exceptional process, and the voltage is applied to the lamp 2. A signal can be output.
As described in the first embodiment, if the output range of the duty x is limited in advance, the configuration as in the second embodiment is unnecessary, but the case where the duty x exceptionally falls below the lower limit. The multiplexer 14 is arranged as a fail safe.

(Third embodiment)
10 and 11 show the third embodiment, and only the parts different from the first embodiment will be described. In the third embodiment, the N-channel MOSFET 1 is replaced with a P-channel MOSFET (semiconductor switching element) 15 and the gate drive circuit 4 is replaced with a gate drive circuit (signal output means) 16. In this case, as shown in FIG. 11C, the gate drive circuit 16 generates a gate signal that is inverted in level and given a slope with respect to the drive signal output by the duty adjustment unit 3, and generates a P-channel MOSFET 15 Output to the gate. Therefore, in this case, the same effect as that of the first embodiment can be obtained.

(Fourth embodiment)
12 and 13 show the fourth embodiment, and only the parts different from the first embodiment will be described. The duty adjusting unit (duty adjusting means) 17 of the fourth embodiment adds a subtracter 18 (second subtractor) and a fourth flip-flop (FF4) 19 to the duty adjusting unit 3 of the first embodiment, and A down counter 20 (third counter) is provided in place of the counter 11. The subtracter 18 is supplied with the duty x of the input signal from the outside as data, and is also given the subtraction result (b−a) of the subtracter 9, and {x− (b−a)} = (x + a−b). Is subtracted. The subtraction result (x + a−b) of the subtracter 18 is held by the fourth flip-flop 19 at the rising edge of the input signal.

  The down counter 20 is loaded with the data (x + a−b) held in the fourth flip-flop 19 and starts the down-counting operation from the rising edge of the input signal as in the down counter 11. The down counter 20 keeps the level of the signal output to the AND gate 12 high during the down count operation, and when the down count operation ends, changes the level of the signal to low (count end signal). Therefore, the output signal of the AND gate 12 becomes high level when the down counter 20 is in the down count operation, and becomes low level when the down count operation is completed. As a result, as shown in FIG. 13B, the falling edge of the drive signal is advanced by the time (b−a) with respect to the falling edge of the input signal, and the duty z of the drive signal is ( x + a−b).

  As described above, according to the fourth embodiment, when the duty adjustment unit 17 counts the times a and b by the first and second counters 5 and 6, respectively, the subtracter 9 (first subtractor) is calculated from those count values. ) Calculates (b−a) and the subtractor 18 calculates (x + a−b), the down counter 20 starts counting from the rising edge of the PWM signal, and calculates a time corresponding to (x + a−b). When counted, a count end signal is output, and a logical product signal of the PWM signal and the count end signal is output to the gate drive circuit 4. Accordingly, the duty z can be set as expected by advancing the fall of the drive signal by (b−a) by the above arithmetic processing.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
You may apply to a low side drive system.
The load is not limited to the lamp but may be a motor or the like.
The third counter may be a counter that performs an up-count operation.
In the second embodiment, when the duty x of the input signal is given to the multiplexer 14 as digital data, the drive signal can be output without passing through the “delay” time shown in the process (e).
The semiconductor switching element is not limited to a MOSFET, but may be an IGBT or a bipolar transistor.

  In the drawing, 1 is an N-channel MOSFET (semiconductor switching element), 2 is a lamp (load), 3 is a duty adjustment unit (duty adjustment means), 4 is a gate drive circuit (signal output means), 5 is a first counter, 6 Is a second counter, 9 is a subtractor, 11 is a down counter (third counter), 12 is an AND gate, 13 is a duty adjustment unit (duty adjustment means), 14 is a multiplexer (signal selection means), and 15 is a P-channel MOSFET. (Semiconductor switching element), 16 is a gate drive circuit (signal output means), 17 is a duty adjustment unit (duty adjustment means), 18 is a subtractor (second subtractor), and 20 is a down counter (third counter). .

Claims (6)

In a driving device for driving a semiconductor switching element connected in series with a load between a power source and a ground by a PWM (Pulse Width Modulation) signal,
A signal output means for outputting an inclination applying signal having an inclination to the rising edge and falling edge of the input PWM signal to the control terminal of the semiconductor switching element;
In response to the inclination giving signal, a voltage signal output to the load via the semiconductor switching element is detected,
Obtaining a time a from the rise of the input PWM signal to the rise of the voltage signal and a time b from the fall of the PWM signal to the fall of the voltage signal;
When the duty of the PWM signal is x, it is provided with duty adjustment means for outputting a signal set to duty z = (x + a−b) to the signal output means ,
The duty adjustment means includes
A first counter for counting the time a;
A second counter for counting the time b;
A subtractor for calculating (b−a) from the count values obtained from the first and second counters;
The subtraction result data (b−a) of this subtracter is loaded, the count operation starts from the rising edge of the PWM signal, and the count end signal is output when the time corresponding to the (b−a) is counted. 3 counters,
A logical product gate that takes a logical product of the PWM signal and the count end signal;
A driving device for a semiconductor switching element , wherein an output signal of the AND gate is output to the signal output means . In a driving device for driving a semiconductor switching element connected in series with a load between a power source and a ground by a PWM (Pulse Width Modulation) signal,
A signal output means for outputting an inclination applying signal having an inclination to the rising edge and falling edge of the input PWM signal to the control terminal of the semiconductor switching element;
In response to the inclination giving signal, a voltage signal output to the load via the semiconductor switching element is detected,
Obtaining a time a from the rise of the input PWM signal to the rise of the voltage signal and a time b from the fall of the PWM signal to the fall of the voltage signal;
When the duty of the PWM signal is x, it is provided with duty adjustment means for outputting a signal set to duty z = (x + a−b) to the signal output means,
The duty adjustment means includes
A first counter for counting the time a;
A second counter for counting the time b;
A first subtractor for calculating (b−a) from count values obtained from the first and second counters;
When the duty x of the PWM signal is given as data, a second subtracter that subtracts (b−a), which is the subtraction result data of the first subtractor, from data x to calculate (x + a−b);
(X + a−b), which is the subtraction result of the second subtractor, is loaded, starts a count operation from the rising edge of the PWM signal, and outputs a count end signal when a time corresponding to the (x + a−b) is counted. A third counter;
A logical product gate that takes a logical product of the PWM signal and the count end signal;
The logical product of the output signal of the gate, the driving device of the semi-conductor switching elements you and outputs to said signal output means.
In a driving device for driving a semiconductor switching element connected in series with a load between a power source and a ground by a PWM (Pulse Width Modulation) signal,
A signal output means for outputting an inclination applying signal having an inclination to the rising edge and falling edge of the input PWM signal to the control terminal of the semiconductor switching element;
In response to the inclination giving signal, a voltage signal output to the load via the semiconductor switching element is detected,
Obtaining a time a from the rise of the input PWM signal to the rise of the voltage signal and a time b from the fall of the PWM signal to the fall of the voltage signal;
When the duty of the PWM signal is x, the duty of the voltage signal output in response to the inclination giving signal is x, so that a signal set to duty z = (x + a−b) is output to the signal output means. A drive device for a semiconductor switching element, comprising: a duty adjustment unit . A signal for outputting the PWM signal to the signal output means instead of the signal adjusted to the duty z by the duty adjustment means when the duty x of the PWM signal becomes a value equal to or less than time (b−a). drive of the semiconductor switching element according to any one of claims 1 to 3, further comprising a selection means. In a method of driving a semiconductor switching element connected in series with a load between a power source and a ground by a PWM (Pulse Width Modulation) signal,
Output an inclination applying signal with an inclination to the rising and falling edges of the input PWM signal to the control terminal of the semiconductor switching element,
When a voltage signal output to the load via the semiconductor switching element is detected according to the tilt giving signal,
Obtaining a time a from the rise of the input PWM signal to the rise of the voltage signal and a time b from the fall of the PWM signal to the fall of the voltage signal;
If the duty of the PWM signal is x, the duty of the voltage signal output in response to the slope giving signal is x, so that the slope giving signal is generated from the signal set to duty z = (x + a−b). A method for driving a semiconductor switching element.   When the duty x of the PWM signal is equal to or less than time (b−a), the slope giving signal is generated from the PWM signal instead of the signal adjusted to the duty z. The method for driving a semiconductor switching element according to claim 5.

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