JP5507195B2 - Heat treatment method and heat treatment apparatus - Google Patents

Description

  The present invention relates to a heat treatment method and a heat treatment apparatus for heating a thin plate-shaped precision electronic substrate (hereinafter simply referred to as “substrate”) such as a semiconductor wafer or a glass substrate for a liquid crystal display device by irradiating light. About.

  Conventionally, a lamp annealing apparatus using a halogen lamp has been generally used in an impurity (ion) activation process of a semiconductor wafer after ion implantation. In such a lamp annealing apparatus, the semiconductor wafer is heated (annealed) to a temperature of about 1000 ° C. to 1100 ° C., for example, to activate the impurities of the semiconductor wafer. In such a heat treatment apparatus, the temperature of the semiconductor wafer is increased at a rate of several hundred degrees per second by using the energy of light emitted from the halogen lamp.

  On the other hand, in recent years, as semiconductor devices have been highly integrated, it is desired to reduce the junction depth as the gate length becomes shorter. However, even when the impurity activation of the semiconductor wafer is performed using the above-described lamp annealing apparatus that raises the temperature of the semiconductor wafer at a speed of about several hundred degrees per second, impurities such as boron and phosphorus implanted in the semiconductor wafer are heated. It was found that the phenomenon of deep diffusion occurs. When such a phenomenon occurs, there is a concern that the junction depth becomes deeper than required, which hinders good device formation.

  For this reason, the surface of the semiconductor wafer into which ions have been implanted by irradiating the surface of the semiconductor wafer with flash light using a xenon flash lamp (hereinafter simply referred to as “flash lamp” means xenon flash lamp). Have been proposed in which the temperature is raised to about 1300 ° C. in a very short time (several milliseconds or less) (for example, Patent Documents 1 and 2). The radiation spectral distribution of a xenon flash lamp ranges from the ultraviolet region to the near infrared region, has a shorter wavelength than the conventional halogen lamp, and almost coincides with the fundamental absorption band of a silicon semiconductor wafer. Therefore, when the semiconductor wafer is irradiated with flash light from the xenon flash lamp, the semiconductor wafer can be rapidly heated with little transmitted light. Further, it has been found that if the flash light is irradiated for a very short time of several milliseconds or less, only the vicinity of the surface of the semiconductor wafer can be selectively heated. For this reason, if the temperature is raised for a very short time by the xenon flash lamp, only the impurity activation can be performed without deeply diffusing the impurities.

  However, since it is difficult to raise the surface temperature of the semiconductor wafer to a processing temperature of about 1300 ° C. only with flash light from a xenon flash lamp, preheating of the semiconductor wafer may be performed before flash light irradiation. Necessary. Also in the heat treatment techniques disclosed in Patent Documents 1 and 2, flash heating is performed after the semiconductor wafer is preheated to a predetermined preheating temperature by a hot plate.

JP 2004-55821 A JP 2004-88052 A

  If the preheating temperature before flash heating is low (500 ° C. or less), the diffusion of the implanted impurities is suppressed, but the surface temperature of the semiconductor wafer is set to a desired processing temperature unless the intensity of the flash light to be irradiated is increased. Cannot be reached. If it does so, rapid thermal expansion will arise only on the surface of a semiconductor wafer at the time of flash light irradiation, and it will become easy to generate wafer cracking (Shattering).

  On the other hand, if the preheating temperature is high (700 ° C. or higher), the surface temperature of the semiconductor wafer can reach the desired processing temperature even if the intensity of the flash light to be irradiated is weak. For this reason, although the crack of the semiconductor wafer at the time of flash light irradiation can be prevented, there arises a problem that the implanted impurities diffuse in the preheating stage. In addition, even if diffusion does not occur, there arises a problem that the inactivation ratio of impurities becomes high and favorable activation is inhibited.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a heat treatment method and a heat treatment apparatus that can perform good activation of implanted impurities while suppressing cracking of a substrate. .

In order to solve the above-mentioned problems, the invention of claim 1 is a heat treatment method for heating a substrate by irradiating the substrate with a plurality of light irradiations within a range of 1 second or less. The substrate is irradiated with light with an output waveform having a plurality of emission peaks, and in the temperature profile drawn on the surface of the substrate by the light irradiation, a temperature rising process and a temperature lowering for each of the plurality of temperature peaks corresponding to the plurality of emission peaks total 700 ° C. or higher 900 ° C. or less of the residence time of the process Ri der than 15 msec, the peak interval of the plurality of emission peaks is 100 ms or more 5 ms, the emission of light by the peak interval The average light emission output is 50% or less of the light emission output of the minimum light emission peak among the plurality of light emission peaks .

According to a second aspect of the present invention, there is provided a heat treatment apparatus for heating a substrate by irradiating the substrate with light, a holding unit for holding the substrate, and light for irradiating the substrate held by the holding unit with light. And a light emission control means for controlling a light emission output of the light irradiation means, wherein the light emission control means has a plurality of light emission peaks within a range where the total light irradiation time is 1 second or less. The substrate is irradiated with light with an output waveform, and in the temperature profile drawn on the surface of the substrate by the light irradiation, 700 ° C. or more of the temperature rising process and the temperature falling process for each of the plurality of temperature peaks corresponding to the plurality of light emission peaks with a total of 900 ° C. or less of the residence time to control the light irradiation unit to be equal to or less than 15 milliseconds, the plurality of peak intervals of the emission peak 5 ms to 100 ms or more The light irradiation means continues to emit light even at the peak interval, and the average light output is 50% or less of the light output of the minimum light emission peak of the plurality of light emission peaks. The irradiation means is controlled .

According to a third aspect of the present invention, in the heat treatment apparatus according to the second aspect of the invention , the light irradiation means includes a flash lamp, and the light emission control means is a switching connected in series with the flash lamp, a capacitor, and a coil. An element is provided.

According to a fourth aspect of the present invention, in the heat treatment apparatus according to the third aspect of the present invention, the switching element is an insulated gate bipolar transistor.

According to the invention of claim 1, the substrate is irradiated with an output waveform having a plurality of emission peaks within a range in which the total time of light irradiation is 1 second or less, and the surface of the substrate is irradiated by the light irradiation. In the drawn temperature profile, the total stay time of 700 ° C. or more and 900 ° C. or less in each of the plurality of temperature peaks corresponding to the plurality of emission peaks is 15 milliseconds or less. While the substrate surface is heated several times at the peak, the thermal shock given to the substrate by one emission peak can be weakened, and the activated impurities can be activated well while suppressing the cracking of the substrate. It can be carried out. In addition, inactivation of the implanted impurities can be suppressed. Moreover, since the peak intervals of the plurality of light emission peaks are 5 milliseconds or more and 100 milliseconds or less, the plurality of temperature peaks appear reliably in the temperature profile drawn by the surface of the substrate, and the above effect can be obtained more reliably. be able to. Furthermore, since the average light emission output at the peak interval is 50% or less of the light emission output of the minimum light emission peak among the plurality of light emission peaks, the plurality of temperature peaks reliably appear in the temperature profile drawn by the surface of the substrate. As a result, the above effects can be obtained more reliably.

Further, according to the inventions of claims 2 to 4 , the substrate is irradiated with light with an output waveform having a plurality of emission peaks within a range in which the total light irradiation time is 1 second or less, and the light In the temperature profile drawn on the surface of the substrate by irradiation, the total stay time of 700 ° C. or more and 900 ° C. or less of the temperature rising process and the temperature falling process for each of the plurality of temperature peaks corresponding to the plurality of emission peaks is 15 milliseconds or less. Therefore, while the temperature of the substrate is raised multiple times at a plurality of emission peaks, the thermal shock given to the substrate by one emission peak can be weakened, and the implanted impurities while suppressing cracking of the substrate Can be activated well. In addition, inactivation of the implanted impurities can be suppressed. Moreover, since the peak intervals of the plurality of light emission peaks are 5 milliseconds or more and 100 milliseconds or less, the plurality of temperature peaks appear reliably in the temperature profile drawn by the surface of the substrate, and the above effect can be obtained more reliably. be able to. Furthermore, since the average light emission output at the peak interval is 50% or less of the light emission output of the minimum light emission peak among the plurality of light emission peaks, the plurality of temperature peaks reliably appear in the temperature profile drawn by the surface of the substrate. As a result, the above effects can be obtained more reliably.

It is a longitudinal cross-sectional view which shows the structure of the heat processing apparatus which concerns on this invention. It is sectional drawing which shows the gas path of the heat processing apparatus of FIG. It is sectional drawing which shows the structure of a holding | maintenance part. It is a top view which shows a hot plate. It is a longitudinal cross-sectional view which shows the structure of the heat processing apparatus of FIG. It is a figure which shows the drive circuit of a flash lamp. It is a figure which shows the structure of the element formed in the semiconductor wafer used as the process target with the heat processing apparatus of FIG. It is a figure which shows the change of the surface temperature of the semiconductor wafer after preheating is started. It is a figure which shows an example of the correlation with the waveform of a pulse signal, and the electric current which flows into a circuit. It is a figure which shows an example of the correlation with the light emission output of a flash lamp, and the surface temperature of a semiconductor wafer. It is a figure which shows the other example of the light emission output profile of a flash lamp. It is a figure which shows the other example of the light emission output profile of a flash lamp.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, the overall configuration of the heat treatment apparatus according to the present invention will be outlined. FIG. 1 is a longitudinal sectional view showing a configuration of a heat treatment apparatus 1 according to the present invention. The heat treatment apparatus 1 is a lamp annealing apparatus that irradiates a substantially circular semiconductor wafer W as a substrate with light and heats the semiconductor wafer W.

  The heat treatment apparatus 1 includes a substantially cylindrical chamber 6 that accommodates a semiconductor wafer W, and a lamp house 5 that houses a plurality of flash lamps FL. Further, the heat treatment apparatus 1 includes a control unit 3 that controls each operation mechanism provided in the chamber 6 and the lamp house 5 to execute the heat treatment of the semiconductor wafer W.

  The chamber 6 is provided below the lamp house 5 and includes a chamber side 63 having a substantially cylindrical inner wall and a chamber bottom 62 covering the lower part of the chamber side 63. A space surrounded by the chamber side 63 and the chamber bottom 62 is defined as a heat treatment space 65. An upper opening 60 is formed above the heat treatment space 65, and a chamber window 61 is attached to the upper opening 60 to be closed.

  The chamber window 61 constituting the ceiling portion of the chamber 6 is a disk-shaped member made of quartz and functions as a quartz window that transmits the light emitted from the lamp house 5 to the heat treatment space 65. The chamber bottom 62 and the chamber side 63 constituting the main body of the chamber 6 are formed of, for example, a metal material having excellent strength and heat resistance such as stainless steel, and a ring on the upper side of the inner side surface of the chamber side 63. 631 is formed of an aluminum (Al) alloy or the like having durability superior to stainless steel against deterioration due to light irradiation.

  Further, in order to maintain the airtightness of the heat treatment space 65, the chamber window 61 and the chamber side portion 63 are sealed by an O-ring. That is, the O-ring is sandwiched between the lower surface peripheral portion of the chamber window 61 and the chamber side portion 63, the clamp ring 90 is brought into contact with the upper peripheral portion of the chamber window 61, and the clamp ring 90 is attached to the chamber side portion 63. The chamber window 61 is pressed against the O-ring by screwing.

  The chamber bottom 62 has a plurality (in this embodiment) for supporting the semiconductor wafer W from the lower surface (surface opposite to the side irradiated with light from the lamp house 5) through the holding portion 7. 3) support pins 70 are provided upright. The support pin 70 is made of, for example, quartz and is fixed from the outside of the chamber 6 and can be easily replaced.

The chamber side 63 has a transfer opening 66 for carrying in and out the semiconductor wafer W, and the transfer opening 66 can be opened and closed by a gate valve 185 that rotates about a shaft 662. In a portion of the chamber side 63 opposite to the transfer opening 66, an inert gas such as nitrogen (N ₂ ) gas, helium (He) gas, argon (Ar) gas, etc. Alternatively, an introduction path 81 for introducing oxygen (O ₂ ) gas or the like is formed, one end of which is connected to an air supply mechanism (not shown) via a valve 82, and the other end is formed inside the chamber side portion 63. Connected to the gas introduction buffer 83. A discharge passage 86 for discharging the gas in the heat treatment space 65 is formed in the transfer opening 66 and is connected to an exhaust mechanism (not shown) through a valve 87.

  FIG. 2 is a cross-sectional view of the chamber 6 cut along a horizontal plane at the position of the gas introduction buffer 83. As shown in FIG. 2, the gas introduction buffer 83 is formed over about ３ of the inner periphery of the chamber side 63 on the opposite side of the transfer opening 66 shown in FIG. Then, the processing gas guided to the gas introduction buffer 83 is supplied into the heat treatment space 65 from the plurality of gas supply holes 84.

  The heat treatment apparatus 1 also includes a substantially disk-shaped holding unit 7 that holds the semiconductor wafer W in a horizontal position in the chamber 6 and performs preheating of the semiconductor wafer W held before light irradiation, and a holding unit. And a holding unit elevating mechanism 4 that elevates 7 with respect to the chamber bottom 62 which is the bottom surface of the chamber 6. 1 includes a substantially cylindrical shaft 41, a moving plate 42, guide members 43 (three arranged around the shaft 41 in the present embodiment), a fixed plate 44, a ball screw 45, It has a nut 46 and a motor 40. A substantially circular lower opening 64 having a smaller diameter than the holding portion 7 is formed in the chamber bottom 62 which is the lower portion of the chamber 6, and the stainless steel shaft 41 is inserted through the lower opening 64 to hold the holding portion. 7 (strictly speaking, the hot plate 71 of the holding unit 7) is connected to the lower surface of the holding unit 7 to support it.

  A nut 46 that is screwed into the ball screw 45 is fixed to the moving plate 42. The moving plate 42 is slidably guided by a guide member 43 that is fixed to the chamber bottom 62 and extends downward, and is movable in the vertical direction. Further, the moving plate 42 is connected to the holding unit 7 via the shaft 41.

  The motor 40 is installed on a fixed plate 44 attached to the lower end of the guide member 43, and is connected to the ball screw 45 via the timing belt 401. When the holding part 7 is raised and lowered by the holding part raising / lowering mechanism 4, the motor 40 as the driving part rotates the ball screw 45 under the control of the control part 3, and the moving plate 42 to which the nut 46 is fixed follows the guide member 43. Move vertically. As a result, the shaft 41 fixed to the moving plate 42 moves along the vertical direction, and the holding unit 7 connected to the shaft 41 moves between the delivery position of the semiconductor wafer W shown in FIG. 1 and the semiconductor wafer W shown in FIG. Move up and down smoothly between the processing positions.

  On the upper surface of the moving plate 42, a mechanical stopper 451 having a substantially semi-cylindrical shape (a shape obtained by cutting the cylinder in half along the longitudinal direction) is provided so as to extend along the ball screw 45. If the upper limit of the mechanical stopper 451 is struck against the end plate 452 provided at the end of the ball screw 45, the moving plate 42 is prevented from rising abnormally. Thereby, the holding part 7 does not rise above a predetermined position below the chamber window 61, and the collision between the holding part 7 and the chamber window 61 is prevented.

  The holding unit lifting mechanism 4 has a manual lifting unit 49 that manually lifts and lowers the holding unit 7 when performing maintenance inside the chamber 6. The manual elevating part 49 has a handle 491 and a rotating shaft 492. By rotating the rotating shaft 492 via the handle 491, the ball screw 45 connected to the rotating shaft 492 is rotated via the timing belt 495 to hold the holding part. 7 can be moved up and down.

  A telescopic bellows 47 that surrounds the shaft 41 and extends downward is provided below the chamber bottom 62, and its upper end is connected to the lower surface of the chamber bottom 62. On the other hand, the lower end of the bellows 47 is attached to the bellows lower end plate 471. The bellows lower end plate 471 is attached by being screwed to the shaft 41 by a flange-shaped member 411. The bellows 47 is contracted when the holding portion 7 is raised with respect to the chamber bottom 62 by the holding portion lifting mechanism 4, and the bellows 47 is expanded when the holding portion 7 is lowered. When the holding unit 7 moves up and down, the airtight state in the heat treatment space 65 is maintained by the expansion and contraction of the bellows 47.

  FIG. 3 is a cross-sectional view showing the configuration of the holding unit 7. The holding unit 7 is installed on a hot plate (heating plate) 71 that preheats the semiconductor wafer W (so-called assist heating), and an upper surface of the hot plate 71 (a surface on the side where the holding unit 7 holds the semiconductor wafer W). The susceptor 72 is provided. As described above, the shaft 41 that moves up and down the holding unit 7 is connected to the lower surface of the holding unit 7. The susceptor 72 is made of quartz (or may be aluminum nitride (AIN) or the like), and a pin 75 for preventing displacement of the semiconductor wafer W is provided on the upper surface thereof. The susceptor 72 is installed on the hot plate 71 with its lower surface in surface contact with the upper surface of the hot plate 71. Thus, the susceptor 72 diffuses the thermal energy from the hot plate 71 and transmits it to the semiconductor wafer W placed on the upper surface of the susceptor 72, and can be removed from the hot plate 71 and cleaned during maintenance.

  The hot plate 71 includes an upper plate 73 and a lower plate 74 made of stainless steel. A resistance heating wire 76 such as a nichrome wire for heating the hot plate 71 is disposed between the upper plate 73 and the lower plate 74, and is filled with a conductive nickel (Ni) solder and sealed. The end portions of the upper plate 73 and the lower plate 74 are bonded by brazing.

  FIG. 4 is a plan view showing the hot plate 71. As shown in FIG. 4, the hot plate 71 includes a disc-shaped zone 711 and an annular zone 712 that are concentrically arranged in a central portion of a region facing the held semiconductor wafer W, and a zone 712. There are four zones 713 to 716 obtained by equally dividing a peripheral substantially annular region into four equal parts in the circumferential direction, and a slight gap is formed between the zones. The hot plate 71 is provided with three through holes 77 through which the support pins 70 are inserted, every 120 ° on the circumference of the gap between the zone 711 and the zone 712.

  In each of the six zones 711 to 716, heaters are individually formed so that mutually independent resistance heating wires 76 circulate, and each zone is individually formed by a heater built in each zone. Heated. The semiconductor wafer W held by the holding unit 7 is heated by heaters built in the six zones 711 to 716. Each of the zones 711 to 716 is provided with a sensor 710 that measures the temperature of each zone using a thermocouple. Each sensor 710 passes through the inside of a substantially cylindrical shaft 41 and is connected to the control unit 3.

  When the hot plate 71 is heated, the resistance heating wire disposed in each zone is set so that the temperature of each of the six zones 711 to 716 measured by the sensor 710 becomes a predetermined temperature. The amount of power supplied to 76 is controlled by the control unit 3. The temperature control of each zone by the control unit 3 is performed by PID (Proportional, Integral, Derivative) control. In the hot plate 71, the temperature of each of the zones 711 to 716 is continuously measured until the heat treatment of the semiconductor wafer W (when plural semiconductor wafers W are continuously processed, the heat treatment of all the semiconductor wafers W) is completed. Then, the power supply amount to the resistance heating wire 76 disposed in each zone is individually controlled, that is, the temperature of the heater built in each zone is individually controlled, and the temperature of each zone becomes the set temperature. Maintained. The set temperature of each zone can be changed by an offset value set individually from the reference temperature.

  The resistance heating wires 76 respectively disposed in the six zones 711 to 716 are connected to a power supply source (not shown) via a power line passing through the inside of the shaft 41. On the way from the power supply source to each zone, the power lines from the power supply source are arranged so as to be electrically insulated from each other inside a stainless tube filled with an insulator such as magnesia (magnesium oxide). The The interior of the shaft 41 is open to the atmosphere.

  Next, the lamp house 5 includes a light source composed of a plurality of (30 in this embodiment) xenon flash lamps FL inside the housing 51, and a reflector 52 provided so as to cover the light source, It is configured with. A lamp light emission window 53 is attached to the bottom of the casing 51 of the lamp house 5. The lamp light radiation window 53 constituting the floor of the lamp house 5 is a plate-like member made of quartz. By installing the lamp house 5 above the chamber 6, the lamp light emission window 53 faces the chamber window 61. The lamp house 5 heats the semiconductor wafer W by irradiating the semiconductor wafer W held by the holding unit 7 in the chamber 6 with light from the flash lamp FL through the lamp light emission window 53 and the chamber window 61.

  Each of the plurality of flash lamps FL is a rod-shaped lamp having a long cylindrical shape, and the longitudinal direction of each of the flash lamps FL is along the main surface of the semiconductor wafer W held by the holding unit 7 (that is, along the horizontal direction). They are arranged in a plane so as to be parallel to each other. Therefore, the plane formed by the arrangement of the flash lamps FL is also a horizontal plane.

  FIG. 6 is a diagram showing a driving circuit for the flash lamp FL. As shown in the figure, a capacitor 93, a coil 94, a flash lamp FL, and a switching element 96 are connected in series. The flash lamp FL includes a rod-shaped glass tube (discharge tube) 92 in which xenon gas is sealed and an anode and a cathode are disposed at both ends thereof, and a trigger electrode provided on the outer peripheral surface of the glass tube 92. 91. A predetermined voltage is applied to the capacitor 93 by the power supply unit 95, and a charge corresponding to the applied voltage is charged. A voltage can be applied from the trigger circuit 97 to the trigger electrode 91. The timing at which the trigger circuit 97 applies a voltage to the trigger electrode 91 is controlled by the control unit 3.

  In the present embodiment, an insulated gate bipolar transistor (IGBT) is used as the switching element 96. The IGBT is a bipolar transistor in which a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is incorporated in a gate portion, and is a switching element suitable for handling high power. A pulse signal is applied from the pulse generator 31 of the control unit 3 to the gate of the switching element 96.

  Even when a pulse is output to the gate of the switching element 96 with the capacitor 93 charged and a high voltage is applied to both ends of the glass tube 92, the xenon gas is normally an insulator, so In this state, electricity does not flow in the glass tube 92. However, when the trigger circuit 97 applies a voltage to the trigger electrode 91 to break the insulation, an electric current instantaneously flows in the glass tube 92 due to the discharge between the two end electrodes, and the excitation of the xenon atoms or molecules at that time Light is emitted.

  Further, the reflector 52 of FIG. 1 is provided above the plurality of flash lamps FL so as to cover all of them. The basic function of the reflector 52 is to reflect the light emitted from the plurality of flash lamps FL toward the holding unit 7. The reflector 52 is formed of an aluminum alloy plate, and the surface (the surface facing the flash lamp FL) is roughened by blasting to exhibit a satin pattern. The roughening process is performed when the surface of the reflector 52 is a perfect mirror surface, and a regular pattern is generated in the intensity of the reflected light from the plurality of flash lamps FL, so that the surface temperature distribution of the semiconductor wafer W is obtained. This is because the uniformity of the is reduced.

  The control unit 3 controls the various operation mechanisms provided in the heat treatment apparatus 1. The configuration of the control unit 3 as hardware is the same as that of a general computer. That is, the control unit 3 stores a CPU that performs various arithmetic processes, a ROM that is a read-only memory that stores basic programs, a RAM that is a readable and writable memory that stores various information, control software, data, and the like. It is configured with a magnetic disk. The control unit 3 includes a pulse generator 31 and a waveform setting unit 32 and is connected to the input unit 33. As the input unit 33, various known input devices such as a keyboard, a mouse, and a touch panel can be employed. The waveform setting unit 32 sets the waveform of the pulse signal based on the input content from the input unit 33, and the pulse generator 31 generates the pulse signal according to the waveform.

  In addition to the above configuration, the heat treatment apparatus 1 is used for various cooling purposes in order to prevent excessive temperature rise of the chamber 6 and the lamp house 5 due to the heat energy generated from the flash lamp FL and the hot plate 71 during the heat treatment of the semiconductor wafer W. It has the structure of For example, water-cooled tubes (not shown) are provided on the chamber side 63 and the chamber bottom 62 of the chamber 6. The lamp house 5 has an air cooling structure provided with a gas supply pipe 55 and an exhaust pipe 56 for exhausting heat by forming a gas flow therein (see FIGS. 1 and 5). Air is also supplied to the gap between the chamber window 61 and the lamp light emission window 53 to cool the lamp house 5 and the chamber window 61.

  Next, a processing procedure for the semiconductor wafer W in the heat treatment apparatus 1 will be described. The semiconductor wafer W to be processed here is a semiconductor substrate to which impurities (ions) are added by an ion implantation method. FIG. 7 is a view showing the structure of elements formed on the semiconductor wafer W to be processed in the heat treatment apparatus 1. A source / drain region 12 and an extension region 13 are formed on the silicon substrate 11, and a gate electrode 15 is provided on the upper surface thereof. The extension region 13 is an electrical connection between the source / drain region 12 and the channel. A metal gate electrode 15 is provided on the silicon substrate 11 via a gate insulating film 14, and a ceramic side wall 16 is formed for the measurement. Impurities are introduced into the source / drain regions 12 and the extension regions 13 by an ion implantation method, and the activation of the impurities is performed by light irradiation heat treatment (annealing) by the heat treatment apparatus 1. The processing procedure of the heat treatment apparatus 1 described below proceeds by the control unit 3 controlling each operation mechanism of the heat treatment apparatus 1.

  First, the holding unit 7 is lowered from the processing position shown in FIG. 5 to the delivery position shown in FIG. The “processing position” is the position of the holding unit 7 when the semiconductor wafer W is irradiated with light from the flash lamp FL, and is the position in the chamber 6 of the holding unit 7 shown in FIG. Further, the “delivery position” is the position of the holding unit 7 when the semiconductor wafer W is carried in and out of the chamber 6, and is the position of the holding unit 7 shown in FIG. The reference position of the holding unit 7 in the heat treatment apparatus 1 is the processing position. Before the processing, the holding unit 7 is located at the processing position, and this is lowered to the delivery position at the start of processing. As shown in FIG. 1, when the holding portion 7 is lowered to the delivery position, the holding portion 7 comes close to the chamber bottom portion 62, and the tip of the support pin 70 penetrates the holding portion 7 and protrudes above the holding portion 7.

  Next, when the holding unit 7 is lowered to the delivery position, the valve 82 and the valve 87 are opened, and normal temperature nitrogen gas is introduced into the heat treatment space 65 of the chamber 6. Subsequently, the gate valve 185 is opened to open the transfer opening 66, and the semiconductor wafer W is loaded into the chamber 6 through the transfer opening 66 by the transfer robot outside the apparatus and placed on the plurality of support pins 70. Is done.

  The purge amount of nitrogen gas into the chamber 6 when the semiconductor wafer W is loaded is about 40 liters / minute, and the supplied nitrogen gas is moved from the gas introduction buffer 83 in the direction of the arrow AR4 shown in FIG. Then, the exhaust gas is exhausted by utility exhaust via the discharge path 86 and the valve 87 shown in FIG. A part of the nitrogen gas supplied to the chamber 6 is also discharged from an outlet (not shown) provided inside the bellows 47. In each step described below, nitrogen gas is continuously supplied to and exhausted from the chamber 6, and the supply amount of the nitrogen gas is variously changed according to the processing process of the semiconductor wafer W.

  When the semiconductor wafer W is loaded into the chamber 6, the transfer opening 66 is closed by the gate valve 185. The holding unit lifting mechanism 4 raises the holding unit 7 from the delivery position to a processing position close to the chamber window 61. In the process in which the holding unit 7 is lifted from the delivery position, the semiconductor wafer W is transferred from the support pins 70 to the susceptor 72 of the holding unit 7 and is placed and held on the upper surface of the susceptor 72. When the holding unit 7 is raised to the processing position, the semiconductor wafer W held by the susceptor 72 is also held at the processing position.

  Each of the six zones 711 to 716 of the hot plate 71 is heated to a predetermined temperature by a heater (resistive heating wire 76) individually incorporated in each zone (between the upper plate 73 and the lower plate 74). ing. When the holding unit 7 rises to the processing position and the semiconductor wafer W comes into contact with the holding unit 7, the semiconductor wafer W is preheated by the heater built in the hot plate 71 and the temperature gradually rises.

  FIG. 8 is a diagram showing a change in the surface temperature of the semiconductor wafer W since the preheating is started. Preheating is performed for a time tp at the processing position, and the temperature of the semiconductor wafer W rises to a preset preheating temperature T1. The preheating temperature T1 is set to about 200 ° C. to 700 ° C., preferably about 350 ° C. to 600 ° C. (in this embodiment, 600 ° C.) at which the impurities added to the semiconductor wafer W are not likely to diffuse due to heat. . The time tp for preheating the semiconductor wafer W is about 3 seconds to 200 seconds (60 seconds in the present embodiment). The distance between the holding unit 7 and the chamber window 61 can be arbitrarily adjusted by controlling the rotation amount of the motor 40 of the holding unit lifting mechanism 4.

  After the preheating time of time tp has elapsed, light irradiation heating of the semiconductor wafer W by the flash lamp FL is started at time A. When irradiating light from the flash lamp FL, charges are accumulated in the capacitor 93 by the power supply unit 95 in advance. Then, a pulse signal is output from the pulse generator 31 of the control unit 3 to the switching element 96 in a state where charges are accumulated in the capacitor 93.

  FIG. 9 is a diagram illustrating an example of the correlation between the waveform of the pulse signal and the current flowing through the circuit. Here, a pulse signal having a waveform as shown in FIG. 9A is output from the pulse generator 31. The waveform of the pulse signal can be specified by inputting from the input unit 33 a recipe as shown in the following Table 1 in which a pulse width time (on time) and a pulse interval time (off time) are sequentially set. it can. The unit of time in Table 1 is microseconds (μs).

  When the operator inputs such a recipe from the input unit 33 to the control unit 3, the waveform setting unit 32 of the control unit 3 sets a pulse waveform as shown in FIG. 9A based on the recipe. In the pulse waveform shown in FIG. 9A, first, a relatively long single pulse PA having a width of 0.8 milliseconds is set, followed by 20 pulses having a width of 0.1 milliseconds. PB is set, followed by a single pulse PC having a width of 1.4 milliseconds. Then, the pulse generator 31 outputs a pulse signal according to the pulse waveform set by the waveform setting unit 32. As a result, a pulse signal having a waveform as shown in FIG. 9A is applied to the gate of the switching element 96, and the on / off driving of the switching element 96 is controlled. Specifically, the switching element 96 is turned on when the pulse signal input to the gate of the switching element 96 is on, and the switching element 96 is turned off when the pulse signal is off.

  Further, in synchronization with the timing at which the first pulse PA is output from the pulse generator 31, the control unit 3 controls the trigger circuit 97 to apply a voltage to the trigger electrode 91. When a pulse PA is input to the gate of the switching element 96 in a state where electric charges are accumulated in the capacitor 93 and a high voltage is applied to the trigger electrode 91 in synchronization therewith, the inside of the glass tube 92 of the flash lamp FL A current begins to flow between the electrodes at both ends, and light is emitted by excitation of atoms or molecules of xenon at that time. The energization of the flash lamp FL is once started, and the next plurality of pulses PB are intermittently input to the gate of the switching element 96 in a state where the current value remains at a predetermined value or more. Even if a high voltage is not applied to the flash lamp FL, the current continues to flow. That is, if a high voltage is applied to the trigger electrode 91 only when the first pulse PA is input to the gate of the switching element 96, then the current continues to flow through the flash lamp FL without applying the trigger voltage. When the pulse signal input to the gate of the switching element 96 is on, the current value flowing in the glass tube 92 of the flash lamp FL increases, and when the pulse signal is off, the current value decreases. A current having a waveform as shown in b) flows. Each current waveform corresponding to each pulse is defined by a constant of the coil 94.

  A current having a waveform as shown in FIG. 9B flows, and the flash lamp FL emits light. The light emission output of the flash lamp FL is substantially proportional to the current flowing through the flash lamp FL. Accordingly, the output waveform (profile) of the light emission output of the flash lamp FL has a pattern as shown in FIG. With the output waveform from the flash lamp FL as shown in FIG. 10A, the semiconductor wafer W held on the processing position holding unit 7 is irradiated with light. A temperature profile drawn on the surface of the semiconductor wafer W by this light irradiation is as shown in FIG.

  When the flash lamp FL is caused to emit light without using the switching element 96 as in the prior art, the charge accumulated in the capacitor 93 is consumed by one light emission, and the output waveform from the flash lamp FL has a width. Becomes a single pulse of about 0.1 to 10 milliseconds. On the other hand, as in the present embodiment, the switching element 96 is connected in the circuit and the pulse signal as shown in FIG. As a result, the electric charge accumulated in the capacitor 93 is divided and consumed, and the flash lamp FL repeatedly blinks in a very short time. As shown in FIG. 9, since the next pulse is applied to the gate of the switching element 96 before the current value completely becomes “0” and the current value increases again, the flash lamp FL repeatedly blinks. The light emission output does not become “0” completely during the period.

  The output waveform of the flash lamp FL shown in FIG. 10 (a) has two emission peaks EP1 and EP2. That is, after irradiating the semiconductor wafer W with an output waveform having the first emission peak EP1 with the highest attained output L1, the output waveform having the second emission peak EP2 with the highest attained output L2 is obtained. The semiconductor wafer W is irradiated with light. In the example of FIG. 10 (a), the flash lamp FL continues to emit light with a relatively weak light emission output whose average value is L3 between the light emission peak EP1 and the light emission peak EP2.

  More specifically, first, the pulse generator 31 outputs a pulse PA having a width of 0.8 milliseconds to the gate of the switching element 96, so that the switching element 96 is turned on for 0.8 milliseconds. A current having the waveform shown at the top of FIG. 9B flows through the circuit including FL. As a result, the flash lamp FL emits light with an output waveform having a first emission peak EP1 at which the maximum output reaches L1 as shown at the top of FIG. Then, the surface temperature of the semiconductor wafer W that has been irradiated with light from the flash lamp FL with such an output waveform rapidly rises to a temperature T2 and then suddenly drops as shown in FIG. 10B.

  Next, the pulse generator 31 intermittently outputs 20 pulses PB having a width of 0.1 milliseconds to the gate of the switching element 96, whereby the switching element 96 is repeatedly turned on and off to include a flash lamp FL. A current having a sawtooth waveform as shown in the middle of FIG. As a result, the flash lamp FL emits light with a substantially flat output waveform in which the average value as shown in the middle of FIG. The light emitted from the flash lamp FL at this stage is relatively weak, and the surface temperature of the semiconductor wafer W gradually decreases as shown in FIG.

  Following the 20 pulses PB, the pulse generator 31 outputs a relatively long last pulse PC having a width of 1.4 milliseconds to the gate of the switching element 96, whereby the switching element 96 is turned on for 1.4 milliseconds. A current having a waveform shown at the end of FIG. 9B flows through the circuit including the flash lamp FL. As a result, the flash lamp FL emits light with an output waveform having a second emission peak EP2 at which the maximum attained output is L2 as shown at the end of FIG. Then, the surface temperature of the semiconductor wafer W irradiated with light from the flash lamp FL with such an output waveform rapidly rises again to the temperature T3 and then falls, as shown in FIG. 10B.

  Thus, by irradiating the semiconductor wafer W with light having an output waveform having two emission peaks EP1 and EP2 as shown in FIG. 10A, the surface temperature of the semiconductor wafer W is as shown in FIG. It changes as shown. Here, the temperature profile drawn on the surface of the semiconductor wafer W by the light irradiation of the output waveform as shown in FIG. 10A corresponds to two emission peaks EP1 and EP2, as shown in FIG. 10B. Two temperature peaks TP1, TP2 appear. The total stay time of 700 ° C. or more and 900 ° C. or less in the temperature raising process and the temperature lowering process for each of the two temperature peaks TP1 and TP2 corresponding to the two emission peaks EP1 and EP2 is 15 milliseconds or less.

  Specifically, in the surface temperature profile of the semiconductor wafer W shown in FIG. 10B, the first temperature peak TP1 corresponds to the first emission peak EP1. The total of the stay time t11 of 700 ° C. or more and 900 ° C. or less in the temperature rising process and the stay time t12 of 700 ° C. or more and 900 ° C. or less in the temperature lowering process for the first temperature peak TP1 is 15 milliseconds or less. . That is, the total transit time of 700 ° C. or more and 900 ° C. or less before and after the surface temperature of the semiconductor wafer W reaches the first temperature peak TP1 is about 5 milliseconds of 15 milliseconds or less. The highest temperature reached at the first temperature peak TP1 is 900 ° C. or higher.

  Similarly, in the surface temperature profile of the semiconductor wafer W shown in FIG. 10B, the second temperature peak TP2 corresponds to the second emission peak EP2. The total of the stay time t21 from 700 ° C. to 900 ° C. in the temperature rising process and the stay time t22 from 700 ° C. to 900 ° C. in the temperature lowering process for the second temperature peak TP2 is 15 milliseconds or less. . That is, the total transit time of 700 ° C. or more and 900 ° C. or less before and after the surface temperature of the semiconductor wafer W reaches the second temperature peak TP2 is about 11 milliseconds of 15 milliseconds or less. The maximum temperature reached by the second temperature peak TP2 is 900 ° C. or higher.

  The total time of light irradiation of the flash lamp FL in one flash heating is 1 second or less, and the peak interval tp between the light emission peak EP1 and the light emission peak EP2 is 5 milliseconds or more and 100 milliseconds or less. Further, the average light emission output L3 of the flash lamp FL in the peak interval is 50% or less of the maximum attained output L1 of the minimum light emission peak EP1 of the two light emission peaks EP1 and EP2.

  As described above, the light irradiation heating by the flash lamp FL is completed, and after waiting for about 10 seconds at the processing position, the holding unit 7 is lowered again to the delivery position shown in FIG. W is passed from the holding portion 7 to the support pin 70. Subsequently, the transfer opening 66 closed by the gate valve 185 is opened, and the semiconductor wafer W placed on the support pins 70 is unloaded by the transfer robot outside the apparatus, and the light of the semiconductor wafer W in the heat treatment apparatus 1 is transferred. Irradiation heat treatment is completed.

  As described above, nitrogen gas is continuously supplied to the chamber 6 during the heat treatment of the semiconductor wafer W in the heat treatment apparatus 1, and the supply amount is about 30 liters / minute when the holding unit 7 is located at the processing position. When the holding unit 7 is located at a position other than the processing position, the rate is about 40 liters / minute.

  In this embodiment, since the semiconductor wafer W is irradiated with light with an output waveform having two emission peaks EP1 and EP2, it is compared with the case where the charge of the capacitor 93 is consumed by one emission as in the prior art. As a result, the thermal shock given to the semiconductor wafer W by one emission peak is weakened, and cracking of the semiconductor wafer W can be suppressed.

  Even if the thermal energy given to the semiconductor wafer W by each emission peak is small, the surface temperature of the semiconductor wafer W is raised to 900 ° C. or more by each emission peak. That is, by irradiating the semiconductor wafer W with light with an output waveform having two emission peaks EP1 and EP2, the surface temperature of the semiconductor wafer W is raised to 900 ° C. or more twice, so that the semiconductor wafer W Good activation of impurities implanted into the substrate can be performed.

  Further, in the temperature profile drawn by the surface of the semiconductor wafer W, the residence time of 700 ° C. or more and 900 ° C. or less of the temperature rising process and the temperature falling process for each of the two temperature peaks TP1 and TP2 corresponding to the two emission peaks EP1 and EP2. Is set to 15 milliseconds or less. The temperature range of 700 ° C. or higher and 900 ° C. or lower is a temperature range where the inactivation of the implanted impurities proceeds. Therefore, if the semiconductor wafer W stays in this temperature range for a long time, the inactivation ratio of the implanted impurities becomes high and good activation is inhibited. In this embodiment, since the total stay time of 700 ° C. or more and 900 ° C. or less in each temperature peak in the surface temperature profile of the semiconductor wafer W is 15 milliseconds or less, the implanted impurities Almost no inactivation occurs. For this reason, good activation of impurities implanted into the semiconductor wafer W can be performed.

  In addition, the peak interval tp between the emission peak EP1 and the emission peak EP2 is set to 5 milliseconds or more and 100 milliseconds or less, and the average emission output L3 in the peak interval is the smallest of the two emission peaks EP1 and EP2. The maximum peak output L1 of the emission peak EP1 is 50% or less. For this reason, the surface temperature of the semiconductor wafer W does not continue to rise continuously over the two emission peaks EP1 and EP2, and two temperature peaks surely appear in the temperature profile drawn by the surface of the semiconductor wafer W. Therefore, since the surface temperature of the semiconductor wafer W is repeatedly raised and lowered for each emission peak, it is possible to perform good activation of the implanted impurities while suppressing the above-described cracking of the semiconductor wafer W. The effect that it is possible can be obtained reliably.

  While the embodiments of the present invention have been described above, the present invention can be modified in various ways other than those described above without departing from the spirit of the present invention. For example, the light emission output profile of the flash lamp FL is not limited to the example of FIG. 10A, and may be as shown in FIG. The output waveform of the light emission output of the flash lamp FL shown in FIG. 11 also has two light emission peaks EP11 and EP12. That is, after irradiating the semiconductor wafer W with an output waveform having the first emission peak EP11 where the maximum attained output is L11, the output waveform has the second emission peak EP12 where the highest attained output is L12. The semiconductor wafer W is irradiated with light. However, in the example shown in FIG. 11, the flash lamp FL is completely turned off between the emission peak EP11 and the emission peak EP12.

  In order to obtain such a light emission output profile, first, the pulse generator 31 outputs a relatively long single pulse (which may be the same as the pulse PA in FIG. 9) to the gate of the switching element 96. Further, the control unit 3 controls the trigger circuit 97 in synchronization with the timing of outputting this pulse to apply a high voltage to the trigger electrode 91. A pulse is output from the pulse generator 31 to the gate of the switching element 96 in a state where electric charges are accumulated in the capacitor 93, and a high voltage is applied to the trigger electrode 91 in synchronization therewith. The current flows through the flash lamp FL by turning on for the width of the pulse. As a result, the flash lamp FL emits light with an output waveform having the first emission peak EP11 where the maximum output reaches L11.

  In the example shown in FIG. 11, after the pulse generator 31 outputs the first pulse for a relatively long time, the output of the temporary pulse is stopped. That is, a pulse group corresponding to the plurality of pulses PB in FIG. 9 is not output. For this reason, the switching element 96 is turned off, and the energization to the flash lamp FL is also stopped. As a result, the flash lamp FL is also completely turned off.

  Thereafter, after a predetermined time elapses, the pulse generator 31 again outputs a relatively long single pulse (which may be the same as the pulse PC in FIG. 9) to the gate of the switching element 96. At this time, the control unit 3 controls the trigger circuit 97 to apply a high voltage to the trigger electrode 91 in synchronization with the timing at which the pulse generator 31 outputs the pulse again. As a result, a current flows again through the flash lamp FL, and as a result, the flash lamp FL once turned off emits light again. The output waveform of the light emission output has a second light emission peak EP12 in which the maximum attained output is L12. In the example shown in FIG. 11 as well, the total light irradiation time of the flash lamp FL is 1 second or less.

  Even when the semiconductor wafer W is irradiated with light with an output waveform as shown in FIG. 11, the temperature profile drawn by the surface of the semiconductor wafer W is the same as that shown in FIG. . That is, in the temperature profile drawn on the surface of the semiconductor wafer W by the light irradiation of the output waveform shown in FIG. 11, the temperature rising process and the temperature falling process of each of the two temperature peaks corresponding to the two emission peaks EP11 and EP12 are 700 ° C. The total stay time at 900 ° C. or less is 15 milliseconds or less. For this reason, it is possible to perform good activation of the implanted impurities while suppressing cracking of the semiconductor wafer W as in the above embodiment.

  This means that weak light emission of the flash lamp FL between two light emission peaks due to a plurality of pulses PB is not always necessary. In the above embodiment, the plurality of pulses PB are intermittently output between the two emission peaks and the weak light emission of the flash lamp FL is continued even when the last pulse PC is output. This is because the current continues to flow through the flash lamp FL without applying the trigger voltage. That is, if the control unit 3 controls the trigger circuit 97 to apply a high voltage to the trigger electrode 91 every time the pulse generator 31 outputs a pulse, weak light emission between light emission peaks is not necessarily required.

  The light emission output profile of the flash lamp FL may be as shown in FIG. The output waveform of the light emission output of the flash lamp FL shown in FIG. 12 has three light emission peaks EP21, EP22, and EP23. Between each light emission peak, the flash lamp FL may be completely extinguished or may emit light weakly as shown in FIG. When the flash lamp FL emits light weakly between the emission peaks, the average emission output between the peaks is 50% or less of the maximum output of the minimum emission peak among the three emission peaks EP21, EP22, EP23. To. Also in the example shown in FIG. 12, the total light irradiation time of the flash lamp FL is 1 second or less.

  When the semiconductor wafer W is irradiated with light with an output waveform as shown in FIG. 12, three temperature peaks also appear in the temperature profile drawn by the surface of the semiconductor wafer W. The maximum temperature reached at each temperature peak is 900 ° C. or higher. The total stay time of 700 ° C. or more and 900 ° C. or less in the temperature raising process and the temperature lowering process for each of the three temperature peaks is 15 milliseconds or less. Even if it does in this way, since the semiconductor wafer W is light-irradiated with the output waveform which has three light emission peaks EP21, EP22, EP23, the thermal shock which one light emission peak gives to the semiconductor wafer W becomes weak, Breaking of the semiconductor wafer W can be suppressed. Moreover, since the surface temperature of the semiconductor wafer W is raised to 900 ° C. or more three times, good activation of the impurities implanted into the semiconductor wafer W can be performed. Furthermore, since the total stay time of 700 ° C. or more and 900 ° C. or less in the temperature rising process and the temperature decreasing process for each of the three temperature peaks is 15 milliseconds or less, inactivation of the implanted impurities hardly occurs.

  In summary, the output waveform of the light emission output of the flash lamp FL may be any as long as it has two or more light emission peaks. Between a plurality of light emission peaks, the flash lamp FL may be completely turned off, or weak light emission may be continued. When the flash lamp FL emits light weakly between the light emission peaks, the average light emission output between the light emission peaks is set to be 50% or less of the maximum attained output of the minimum light emission peak among the plurality of light emission peaks.

  In addition, the magnitude relationship of the maximum attained output of the plurality of emission peaks is arbitrary. For example, in the example of FIG. 10A, the maximum output L2 of the second emission peak EP2 is larger than the maximum output L1 of the first emission peak EP1, but in the example of FIG. The highest attained output L11 of the emission peak EP11 is greater than the highest attained output L12 of the second emission peak EP12. The peak interval between the plurality of emission peaks is 5 milliseconds or more and 100 milliseconds or less, and the total light irradiation time of the flash lamp FL is 1 second or less.

  When the semiconductor wafer W is irradiated with light having such an output waveform having a plurality of emission peaks, the same temperature peaks as the emission peaks appear in the temperature profile drawn by the surface of the semiconductor wafer W. The maximum temperature reached at each temperature peak is 900 ° C. or more, and the total stay time of 700 ° C. or more and 900 ° C. or less in the temperature rising process and the temperature falling process for each of the plurality of temperature peaks corresponding to the plurality of emission peaks is 15 mm The light emission output profile of the flash lamp FL is set so as to be less than or equal to seconds. If it does in this way, like the above-mentioned embodiment, good activation of an implanted impurity can be performed, suppressing a crack of semiconductor wafer W.

  The setting of the waveform of the pulse signal is not limited to inputting parameters such as the pulse width one by one from the input unit 33. For example, the operator directly inputs the waveform graphically from the input unit 33. Alternatively, the waveform previously set and stored in the storage unit such as a magnetic disk may be read, or may be downloaded from the outside of the heat treatment apparatus 1.

  In the above embodiment, the lamp house 5 is provided with 30 flash lamps FL. However, the present invention is not limited to this, and the number of flash lamps FL can be any number. The flash lamp FL is not limited to a xenon flash lamp, and may be a krypton flash lamp.

  In the above-described embodiment, the IGBT is used as the switching element 96. However, the present invention is not limited to this, and other transistors other than the IGBT may be used. The waveform of the input pulse signal may be used. Any element can be used as long as the circuit can be turned on and off accordingly. However, since a considerable amount of power is consumed for the light emission of the flash lamp FL, it is preferable to employ an IGBT or a GTO (Gate Turn Off) thyristor suitable for handling a large amount of power as the switching element 96.

  In the above embodiment, the semiconductor wafer W is preheated by placing it on the hot plate 71. However, the preheating method is not limited to this, and a halogen lamp is provided to provide light. The semiconductor wafer W may be preheated to the preheating temperature T1 by irradiation.

  Further, as long as light irradiation can be performed with an output waveform having a plurality of emission peaks, a circuit configuration different from that of FIG. 6 may be used. For example, a plurality of power supply circuits provided with delay circuits having different delay times may be used. It may be connected to one flash lamp FL.

  Furthermore, as long as light irradiation can be performed with an output waveform having a plurality of emission peaks, the light source is not limited to the flash lamp FL, as long as light irradiation with an irradiation time of 1 second or less is possible. For example, a laser may be used.

  The substrate to be processed by the heat treatment apparatus according to the present invention is not limited to a semiconductor wafer, and may be a glass substrate used for a liquid crystal display device or the like. Further, the technique according to the present invention may be applied to bonding of metal and silicon or crystallization of polysilicon.

DESCRIPTION OF SYMBOLS 1 Heat processing apparatus 3 Control part 4 Holding part raising / lowering mechanism 5 Lamphouse 6 Chamber 7 Holding part 31 Pulse generator 32 Waveform setting part 33 Input part 60 Upper opening 61 Chamber window 65 Heat treatment space 71 Hot plate 72 Susceptor 91 Trigger electrode 92 Glass tube 93 Capacitor 94 Coil 96 Switching element 97 Trigger circuit FL Flash lamp W Semiconductor wafer

Claims (4)

A heat treatment method for heating a substrate by irradiating the substrate with light,
In the range where the total time of light irradiation is 1 second or less, the substrate is irradiated with light with an output waveform having a plurality of emission peaks,
In the temperature profile drawn by the surface of the substrate by the light irradiation, the total stay time of 700 ° C. or more and 900 ° C. or less of the temperature rising process and the temperature falling process for each of the plurality of temperature peaks corresponding to the plurality of emission peaks is 15 mm. seconds Ri der below,
The peak interval between the plurality of emission peaks is not less than 5 milliseconds and not more than 100 milliseconds,
Emission is continued even at the peak interval, and the average emission output is 50% or less of the emission output of the minimum emission peak among the plurality of emission peaks . A heat treatment apparatus for heating a substrate by irradiating the substrate with light,
Holding means for holding the substrate;
Light irradiation means for irradiating light onto the substrate held by the holding means;
Light emission control means for controlling the light emission output of the light irradiation means;
With
The light emission control means irradiates the substrate with an output waveform having a plurality of light emission peaks within a range where the total light irradiation time is 1 second or less, and a temperature profile drawn on the surface of the substrate by the light irradiation. In the above, the light irradiation means is set so that the total stay time of 700 ° C. or more and 900 ° C. or less in each of the plurality of temperature peaks corresponding to the plurality of emission peaks is 15 milliseconds or less. And the peak interval of the plurality of emission peaks is not less than 5 milliseconds and not more than 100 milliseconds, and the light irradiating means continues to emit light even in the peak interval, and the average emission output is equal to the plurality of emission peaks. A heat treatment apparatus, wherein the light irradiation means is controlled so as to be 50% or less of a light emission output of a minimum light emission peak among the peaks . The heat treatment apparatus according to claim 2 ,
The light irradiation means comprises a flash lamp,
The light emission control means comprises a switching element connected in series with the flash lamp, a capacitor and a coil . The heat treatment apparatus according to claim 3, wherein
The heat treatment apparatus, wherein the switching element is an insulated gate bipolar transistor .

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