JP5505963B2 - Vector processing apparatus and vector operation processing method - Google Patents

Description

  The present invention relates to a vector processing device and a vector operation processing method.

  In recent years, various techniques have been disclosed in order to process a large amount of vector data quickly and accurately.

  In the vector processing device described in Patent Document 1, a data buffer is disposed between a vector register connected to a plurality of arithmetic pipelines and a main storage device. The vector processing device counts the number of data read from the vector register to the data buffer, and interrupts the transmission of an access request from the vector unit to the main memory based on the counted number of data. Thus, when it is necessary to stop the operation of the operation pipeline, only the minimum necessary access request is interrupted.

  The vector processing device described in Patent Document 2 includes an arbiter that performs contention arbitration between output ports for even-numbered input ports and odd-numbered input ports when a vector data memory access instruction is issued. Since the vector processing apparatus divides the contention arbitration process, it suppresses a decrease in the throughput of the contention arbitration process.

  The vector processing device described in Patent Document 3 realizes a conversion instruction for compressing and expanding vector data. The vector processing apparatus is provided with a data buffer having a storage area smaller than the number of vector data elements. The vector processing apparatus writes vector data in which data that does not require calculation between vector data or data whose calculation result is 0 is excluded from data. With the above configuration, the data buffer size can be reduced.

  The vector processing device described in Patent Document 4 realizes high-speed processing of vector instructions that require synchronization. The vector processing device calculates the number of vector elements allocated to the vector pipeline operation unit, and predicts the issue timing of the vector instruction in advance. This eliminates the need for synchronization control signal exchange and the like, and speeds up the processing.

JP-A-6-168264 Japanese Patent Laid-Open No. 9-6759 JP 2000-35958 A JP 2000-222390 A

  However, in the above-described vector processing apparatus, processing for reading and writing data from the vector register may cause a performance problem. Details will be described below.

  In general, a vector processing apparatus is composed of a plurality of vector processing units (vector pipe subunits). The vector pipe subunit can have a plurality of vector operation pipes that perform vector operation processing. Vector operation pipes can mutually input and output vector data (in the following description, processing in which data input / output occurs between vector operation pipes is referred to as an inter-vector pipe operation instruction).

  FIG. 8 shows the configuration of a vector processing apparatus related to one of the problems to be solved by the present invention. The vector processing apparatus includes an inter-pipe crossbar unit 10, a vector pipe subunit 20, and a signal line 30. The vector pipe unit 20 is composed of a plurality of vector pipe subunits 200. The vector pipe subunit 200 includes a vector operation pipe 210.

  In general, when the number of vector operation pipes 210 in the vector pipe subunit 200 increases, the number of signal lines connecting the vector pipe unit 20 and the cross-pipe cross-bar unit 10 increases. This imposes pressure on the wiring capacity and makes LSI design difficult. Therefore, as shown in FIG. 8, the vector operation pipe 210 in the vector pipe subunit 200 performs control (interleaved) that interleaves vector data reading with each other. However, the process tends to be difficult to finish at an early stage by performing interleaving.

  While data is being read from the vector operation pipe in the vector pipe subunit based on a certain instruction, processing on the resource associated with the instruction is prohibited. For this reason, processing takes a long time due to interleave control, and subsequent processing to be processed by the vector operation pipe enters a waiting state, which may delay the entire processing.

  The present invention has been made to solve such problems, and an object of the present invention is to provide a vector processing apparatus that solves the problem that a vector operation instruction in a vector processing apparatus is delayed by an operation instruction between vector pipes. And

  One aspect of the vector processing apparatus according to the present invention includes a first processing unit including first and second vector operation pipes, a second processing unit, the first processing unit, and the second processing unit. A data transfer circuit configured to transfer data between the first processing unit and the data transfer circuit, and output data of the first and second vector operation pipes to the data transfer circuit. A first data path used for supplying data to the data transfer circuit or for supplying input data from the data transfer circuit to the first and second vector operation pipes. A unit is a data buffer arranged between the first and second vector operation pipes and the first data path, and holding the output data or the input data And the first and second vector operation pipes depend on whether the other vector operation pipe is accessing the data buffer and whether the first data path is in use. The data buffer is configured to be accessible.

  According to the present invention, it is possible to solve the problem that the vector operation instruction in the vector processing apparatus is delayed by the operation instruction between vector pipes.

1 is a block diagram of a vector processing apparatus according to a first embodiment; 1 is a block diagram of a vector processing apparatus according to a first embodiment; It is a block diagram which shows the structure of the vector pipe subunit concerning Embodiment 1. FIG. 1 is a block diagram showing a configuration of a vector register according to a first embodiment. FIG. 3 is a block diagram illustrating a configuration of an issue control unit according to the first exemplary embodiment. 6 is a timing chart showing an operation at the time of instruction execution of the vector processing apparatus according to the first exemplary embodiment; 6 is a timing chart showing an operation at the time of instruction execution of the vector processing apparatus according to the first exemplary embodiment; It is a block diagram which shows the vector processing apparatus relevant to one of the problems which this invention tends to solve. It is a timing chart which shows the operation | movement at the time of instruction execution of the vector processing apparatus relevant to one of the problems which this invention tends to solve.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. First, the basic configuration of the vector processing apparatus according to the first embodiment and the outline of the operation will be described with reference to FIG.

  The vector subunit 200 in the vector processing apparatus includes a vector operation pipe 210, a transmission data buffer 220, a reception data buffer 230, and a vector data selection circuit 270. Data input / output of the vector operation pipe 210 is performed using the transmission data buffer 220 and the reception data buffer 230. The vector operation pipe 210 only outputs vector data to the corresponding transmission data buffer 220, and other processing is performed outside the vector operation pipe 210. That is, the vector data selection circuit 270 interleaves the data stored in each transmission data buffer 220 and outputs it.

  With the configuration of the vector processing apparatus shown in FIG. 1, the vector operation pipe 210 executes only input / output of vector data for each vector operation pipe, and other processing (interleave processing and the like) is performed outside the vector operation pipe 210. Therefore, the input / output time of vector data in the vector calculation pipe 210 can be shortened, and the subsequent processing in the vector calculation pipe 210 can be started early.

  Next, a basic configuration of the vector processing apparatus according to the first embodiment will be described with reference to FIG. The vector processing apparatus includes an inter-pipe crossbar unit 10, a vector pipe unit 20, and a signal line 30. The inter-pipe crossbar unit 10 is a processing unit for performing data transfer between the vector pipe subunits 200.

  The vector pipe unit 20 is composed of a plurality of vector pipe subunits 200. The vector pipe subunit 200 includes a vector operation pipe 210, a transmission data buffer 220, and a reception data buffer 230. The vector pipe subunit 200 includes a plurality (two in the figure) of vector operation pipes 210. The vector pipe subunit 200 is a processing unit for performing vector operations. The detailed configuration of the vector pipe subunit 200 will be described later.

  The signal line 30 is a signal line connecting between the vector pipe subunit 200 and the inter-pipe crossbar unit 10. The signal line 30 is a signal line for inputting the output data from the vector pipe subunit 200 to the cross-pipe crossbar unit 10 and a signal for inputting the output data from the cross-pipe crossbar unit 10 to the vector pipe subunit 200. Including lines.

  Next, a detailed configuration of the vector pipe subunit 200 will be described with reference to FIG. The vector pipe subunit 200 includes a vector operation pipe 210, a transmission data buffer 220, a reception data buffer 230, and a vector data selection circuit 270.

  The vector operation pipe 210 performs vector instruction processing. Vector instruction processing refers to a series of processing of reading a vector register, performing an operation using the read value, and writing the operation result to the register. Further, the vector operation pipe 210 writes transmission data in the transmission data buffer 220 when performing processing for outputting data to other vector operation pipes 210.

  The transmission data buffer 220 is a data buffer for temporarily storing output data when processing for outputting data to another vector operation pipe 210 is performed. The transmission data buffer 220 is arranged corresponding to each vector operation pipe 210 in the vector pipe subunit 200. The reception data buffer 230 is a data buffer for temporarily storing data input from the inter-pipe crossbar unit 10. The reception data buffer 230 is arranged corresponding to each vector operation pipe 210 in the vector pipe subunit 200.

  The vector data selection circuit 270 is a selection circuit for interleaving the data output from each reception data buffer 220 and outputting it to the inter-pipe crossbar unit 10.

  The vector operation pipe 210 includes an in-pipe crossbar 240, a vector register 250, and an arithmetic unit 260. The in-pipe crossbar 240 inputs the value output from the calculator 260 to the vector register 250. The vector register 250 is a register that temporarily stores the calculation result of the calculator 260, and a plurality of vector registers 250 exist in the vector calculation pipe 210 (in FIG. 3, the vector calculation pipe 210 includes eight vector registers 250). ing). The computing unit 260 is a processing unit for performing vector computation.

  FIG. 4 is a diagram showing details of the vector register 250. The vector register 250 has a vector register write path for writing data to the vector register 250 and a vector register read path for reading data from the vector register 250. Each vector register 250 includes a plurality of registers having vector register numbers. In FIG. 4, the vector register 250 is composed of registers having vector register numbers VR0, VR8, VR16, VR24, VR32, VR40, VR48, and VR56. Also, a vector register 250 different from the vector register 250 shown in FIG. 4 (for example, the vector register 250 arranged next to the vector register 250 shown in FIG. 4) has a different vector register number (for example, VR1). Consists of registers. Here, since data reading from registers (for example, VR0 and VR8) in the same vector register 250 uses the same vector register read path, there is a contention relationship (relationship that must wait for the other processing). . Similarly, writing data to registers (for example, VR0 and VR8) in the same vector register 250 uses the same vector register write path, and therefore has a conflicting relationship (relationship that must wait for the other process). . (In the following description, it is assumed that there is a competitive relationship when the difference between the vector register numbers is a multiple of 8.)

  Next, the configuration of the issue control unit 400 that issues a vector data processing command to the vector processing device will be described with reference to FIG. The issue control unit 400 includes an instruction request A storage unit 401, an instruction request B storage unit 402, an issue check circuit A403, an issue check circuit B404, a GOA 405, a GOB 406, a busy flag storage unit 407, and a vector register write bus. A busy flag storage unit 408, a WS register 409, a vector register write path use inhibition flag storage unit 410, a VTB read inhibition flag 411, a PXB instruction secondary request storage unit 412, an issue check circuit C413, an RGO 414, Is provided.

  The instruction request A storage unit 401 is a storage unit that temporarily stores a vector instruction to be issued. Similarly, the instruction request B storage unit 402 is a storage unit that temporarily stores a vector instruction to be issued.

  The busy flag storage unit 407 stores a busy flag indicating the usage state of each resource. However, the busy flag does not include state information regarding the usage status of the vector register write path of the vector register 250. The vector register write path busy flag storage unit 408 stores a vector register write path busy flag indicating a state relating to the usage status of the vector register write path in the vector register 250.

  The issue check circuit A 403 checks the contents of the instruction request stored in the instruction request A storage unit 401. Then, the issue check circuit A403 inquires the busy flag storage unit 407 about the state of the resource to be used in response to the instruction request. The issue check circuit A403 writes a check result on whether or not the resource is in use in the GOA 405. The issue check circuit A403 notifies the GOA 405 of an instruction to be issued if the resource usage status is empty. Here, in the case of processing including writing to the vector register 250 (VMV instruction or the like), the issue check circuit A 403 separates the instructions (primary instruction and secondary instruction) and issues instructions other than writing to the vector register 250 ( Primary instruction) is notified to the GOA 405. For example, in the case of a VMV instruction, the primary instruction is an instruction of processing (such as writing from the vector register 250 to the inter-pipe crossbar unit 10) in the stage before the writing process to the vector register 250 in the VMV instruction. The next instruction is an instruction to instruct writing to the vector register 250. Further, the issue check circuit A403 stores the secondary instruction in the PXB instruction secondary request storage unit 412.

  The issue check circuit B 404 checks the content of the instruction request stored in the instruction request B storage unit 402. Then, the issue check circuit B404 inquires the busy flag storage unit 407 about the state of the resource to be used in response to the instruction request. The issue check circuit B404 writes a check result on whether or not the resource is in use in the GOB 406. The issue check circuit B404 notifies the GOB 406 of an instruction to be issued if the resource usage status is empty. Here, similarly to the issue check circuit A 403, the issue check circuit B 404 separates processing (such as a VMV instruction) including writing to the vector register 250 and notifies the GOB 406 of the primary instruction.

  The GOA 405 is a register in which a resource check result by the issue check circuit A403 is written. The processing unit managing the GOA 405 issues a vector instruction execution instruction to all the vector operation pipes 210 at the same time as writing the resource check result.

  The GOB 406 is a register in which a resource check result by the issue check circuit B 404 is written. The processing unit that manages the GOB 406 issues an instruction to execute a vector instruction to all the vector operation pipes 210 at the same time as writing the resource check result.

  The WS register 409 is a register that stores a VTB write start signal that is a control signal. The VTB write start signal is a control signal for notifying that vector data is written from the inter-pipe crossbar unit 10 to the reception data buffer 230 during an inter-vector pipe instruction operation.

  The vector register write path use inhibition flag storage unit 410 stores a vector register write path use inhibition flag indicating whether or not to inhibit use of the vector register write path in the vector register 250. When a VTB write start signal is input, the vector register write path use inhibition flag is updated to prohibit the use of the vector register write path by another instruction.

The VTB read inhibition flag storage unit 411 stores a VTB read inhibition flag indicating whether or not to inhibit reading of the reception data buffer 230. VTB read inhibition flag is used to prohibit reading the receive buffer 230 before vector data vector data is inputted from the inter-pipe crossbar unit 10 is stored in the receive buffer 230.

  The PXB instruction secondary request storage unit 412 is necessary for writing vector data in the vector register 250 when the instruction request stored in the instruction request A storage unit 401 or the instruction request B storage unit 402 is an inter-vector operation instruction. Stores an instruction request (secondary instruction).

  The issue check circuit C413 operates when writing from the received data buffer 230 to the vector register 250. The issue check circuit C413 checks the vector register write pass busy flag corresponding to the instruction request stored in the PXB instruction secondary request storage unit 412, the VTB read inhibition flag, and the value of the WS register 409. The issue check circuit C413 writes the check result in the RGO 414.

  The RGO 414 is a register for writing the check result by the issue check circuit C413. The processing unit that manages the RGO 414 instructs all the vector operation pipes 210 to execute data writing from the reception data buffer 230 to the vector register 250 simultaneously with the writing of the check result by the issue check circuit C413.

Subsequently, when the vector processing apparatus according to the present embodiment executes the following two vector pipe operation instructions (VMV: move instruction between pipes, VADD: vector addition instruction, VR: vector register number, S: constant) Will be described.
(1) VMV VRm ← VRn
(2) VADD VRo ← Sy + VRp

  First, a general operation of the vector processing apparatus according to the present embodiment when a VADD instruction is issued after a VMV instruction is issued will be described below. First, the VMV instruction is stored in the instruction request A storage unit 401. The issue check circuit A403 checks the usage status of resources used by the VMV instruction. Specifically, the issue check circuit A403 checks the busy flag storage unit 407, the vector register write path busy flag storage unit 408, and the vector register write path use inhibition flag storage unit 410 to confirm the resource usage status. To do.

  The issue check circuit A403 sets the VMV instruction in the GOA 405 if the resource usage status is empty, and instructs the vector pipe subunit 200 to start processing the VMV instruction via the GOA 403 (issue primary instruction). That is, the issue check circuit A 403 issues an instruction (primary instruction) of a process (such as writing from the vector register 250 to the cross-pipe crossbar unit 10) in the previous stage of writing the VMV instruction to the vector register 250. Simultaneously with the start of processing of the VMV instruction, the value of the busy flag stored in the busy flag storage unit 407 is updated. As a result, issuance of subsequent instructions to resources used in the VMV instruction is suppressed. In addition, information (secondary instruction) necessary for writing vector data into the vector register 250 among the instructions constituting the VMV instruction is stored in the PXB instruction secondary request storage unit 412.

  After the execution of the VMV instruction by the vector operation pipe 210 is completed, the inter-pipe crossbar unit 10 inputs a VTB write start signal to the WS register 409. When the VTB write start signal is input to the WS register 409, the vector register write path use inhibition flag in the vector register write path use inhibition flag storage unit 410 is updated. By updating the vector register write path use inhibition flag, writing to the vector register 250 by an instruction different from the VMV instruction is inhibited. This is preparation for writing data input from the cross-pipe crossbar unit 10 into the input destination vector register 250.

  The inter-pipe crossbar unit 10 writes vector data to the reception data buffer 230 corresponding to the output destination vector operation pipe 210. Here, the timing of writing from the reception data buffer 230 to the vector operation pipe 210 is managed by the VTB read inhibition flag in the VTB read inhibition flag storage unit 411.

  The issue check circuit C413 checks whether the vector data input from the inter-vector crossbar unit 10 to the reception data buffer 230 can be input to the vector operation pipe 210. In other words, the issue check circuit C413 checks whether or not the resource related to the input process is free. The issue check circuit C413 holds the vector register write pass busy flag stored in the vector register write pass busy flag storage unit 408, the VTB read suppression flag stored in the VTB read suppression flag storage unit 411, and the WS register 409. Check the value. Here, the vector register write pass busy flag checks the usage status of the vector register 250 related to the instruction request stored in the PXB instruction secondary request storage unit 412.

  The issuance check circuit C413 writes a write command from the reception data buffer 230 to the vector operation pipe 210 in the RGO 414 if the resource usage status is empty. In addition, the issue check circuit C413 issues an instruction to write vector data from the received data buffer 230 to the vector operation pipe 210 along with writing to the RGO 414 (secondary instruction issue). Further, a vector register write path busy flag is set for the resource corresponding to the PXB secondary request stored in the PXB secondary request storage unit 412. Execution of subsequent instructions for the same resource is suppressed by setting the vector register write pass busy flag. In addition, after the RGO 414 is set, the vector register write path use inhibition flag storage unit 410 and the value of the WS register 409 are reset.

  Subsequent VADD instructions are stored in the instruction request B storage unit 402. The issue check circuit B404 checks the correspondence status of resources used by the VMV instruction. Specifically, the issue check circuit B404 checks the busy flag storage unit 407, the vector register write path busy flag storage unit 408, and the vector register write path use inhibition flag storage unit 410 to confirm the resource usage status. To do.

  The issuance check circuit B404 sets the VADD instruction in the GOB 406 if the resource usage state is empty, and instructs the start of processing of the VADD instruction. Here, the VADD instruction is a subsequent instruction of the VMV instruction, but if the resource to be used is empty, execution of the VADD instruction is started when the instruction is issued. Simultaneously with the processing start of the VADD instruction, the value of the busy flag stored in the busy flag storage unit 407 and the value of the vector register write pass busy flag stored in the vector register write pass busy flag storage unit 408 are updated. In general, the processing time of the VADD instruction is shorter than that of the VMV instruction. For this reason, if the VADD instruction is issued immediately after the execution of the VMV instruction without waiting, the VADD instruction may end before the VMV instruction. That is, the execution of the VADD instruction is finished in a manner that overtakes the execution of the VMV instruction.

Next, processing when the vector processing apparatus according to the present embodiment executes the VMV instruction and the VADD instruction will be described with reference to FIG. FIG. 6 is a timing chart when the following instructions are executed. VR0 and VR8 are in a competitive relationship for writing to the vector register 250. The machine cycle in the figure is synonymous with clock.
(1) VMV VR0 ← VR14
(2) VADD VR8 ← Sy + VR7

  First, the issue control unit 400 primarily issues a VMV command (S1). In this case, a busy flag that suppresses the use of resources related to the VMV instruction is set. Since the instruction relating to the primary issue does not write to the vector register 250, the vector register write pass busy flag is not set.

  Thereafter, all the vector operation pipes 210 enter the processing state, and the vector operation pipe 210 reads vector data (S11). The reading process is a process that does not require interleaving. Therefore, the process can be completed in a short time. The vector operation pipe 210 stores the read vector data in the transmission data buffer 220 (S12). The inter-pipe crossbar unit 10 reads the transmission data buffer 220 based on the read control of the transmission buffer 220. Here, since the vector pipe subunit 200 includes two vector operation pipes 210, data interleaving is considered in the read control of the transmission data buffer 220. The inter-pipe crossbar unit 10 acquires vector data from each vector pipe subunit 200 and performs processing (S14).

  On the other hand, execution of the VADD instruction is started after the primary issue of the VMV instruction is completed (S2). This is because it is determined that the VADD instruction can be executed because the vector register write path busy flag is not set even if VR0 and VR8 are in a competitive relationship using the same vector register write path. In the execution of the VADD instruction, reading of vector data from the vector operation pipe 210, addition processing of vector data, and writing of vector data to the vector operation pipe 210 are executed.

  A VTB write start signal from the cross pipe unit 10 between pipes is input to the WS register 409. Here, the vector register write path use inhibition flag and the VTB read inhibition flag are set simultaneously. After that, the inter-vector crossbar unit 10 writes vector data to the reception data buffer 230 (S15). When the data in the reception data buffer 230 can be read, the VTB read inhibition flag is reset (S16). The issue check circuit C413 checks the vector register write pass busy flag, the VTB read inhibition flag, and the value of the WS register 409. The issue check circuit C413 checks that the secondary issue of the VMV instruction is possible, and issues an instruction instructing to write the vector data stored in the reception data buffer 230 into the vector register 250 after the check (VMV secondary) Issue). When the VMV secondary issue is issued, the vector register write path use inhibition flag is reset. In addition, the vector register write busy flag is set to suppress the use of the same vector register write path.

  As described above, vector data read / write (VR Read, VR Write) of the vector operation pipe 210 can be completed by a process of only reading and writing data. This is because each vector operation pipe 210 transmits and receives data using the transmission data buffer 220 and the reception data buffer 230, and therefore the vector operation pipe 210 does not need to perform interleaving processing.

  Further, as described above, the writing to the vector register 250 is controlled by the vector register write pass busy flag. The instruction issuing unit 400 according to the present embodiment issues the VMV instruction separately into a primary instruction that does not cause writing to the vector register 250 and a secondary instruction that causes writing to the vector register 250. The vector register write pass busy flag is set as in use only when a secondary instruction is issued. Thus, the succeeding VADD instruction can be completed while the preceding VMV instruction is not performing the writing process to the vector register 250, and an efficient vector operation process is realized.

Next, processing when the vector processing apparatus according to the present embodiment executes the following VMV instruction and VADD instruction will be described with reference to FIG. FIG. 7 is a timing chart when the following instructions are executed. VR6 and VR14 are in a competitive relationship for reading from the vector register 250. Note that since writing to the vector register 250 is not in a competitive relationship, the description relating to the writing processing to the vector register 250 is omitted in FIG. 7 and the following description.
(1) VMV VR0 ← VR14
(2) 'VADD VR4 ← VR6 + VR7

  First, the issue control unit 400 issues a primary instruction of the VMV instruction (S1). In this case, a busy flag that suppresses the use of resources related to the VMV instruction is set. Thereafter, all the vector operation pipes 210 enter the processing state, and the vector operation pipe 210 reads vector data (S11). The reading process is a process that does not require interleaving. Therefore, the process can be completed in a short time. During the execution of the read process, the vector register read pass busy flag is set, and read processes by other instructions are prohibited. The vector operation pipe 210 stores the read vector data in the transmission data buffer 220 (S12).

  The inter-pipe crossbar unit 10 reads the transmission data buffer 220 based on the read control of the transmission buffer 220. Here, since the vector pipe subunit 200 includes two vector operation pipes 210, read control of the transmission data buffer 220 requires data interleaving processing. The inter-pipe crossbar unit 10 acquires vector data from each vector pipe subunit 200 and performs processing (S14).

  On the other hand, the VADD instruction has a conflict (V6 and V14) between the preceding VMV instruction and the vector register read path. Therefore, the VADD instruction can be issued after the vector register read pass busy flag is reset. Here, the vector data read process (S11) of the VMV instruction is a process that does not require interleaving, so that the process can be completed at an early stage. Therefore, the VADD instruction is issued early from the issue of the VMV instruction. The subsequent processing is the same as that shown in FIG.

  As described above, since the transmission data buffer 220 is provided, the vector data read processing (S11) does not require interleaving, so that early processing can be completed. Therefore, even if there is a competitive relationship regarding the reading of the vector register, the subsequent instruction can be executed after the vector data reading process.

  Subsequently, for comparison with the vector processing apparatus according to the present embodiment, FIG. 9 shows reading of the vector register 250 in the configuration of the vector processing apparatus (FIG. 8) related to one of the problems to be solved by the present invention. The operation in the case where there is contention between the processing and the writing processing is shown. In the vector processing apparatus according to the present embodiment, since the reading process from the vector register performs an interleaving process, a considerable processing time is required ((1) in the figure). Therefore, when the vector register read paths are in conflict, the vector processing apparatus according to the present embodiment delays the start of execution of the VADD instruction.

  When the vector register write path is in conflict, the vector register write path busy flag is set from the time when the VMV instruction is issued. The actual writing process to the vector register is executed at the time of writing from the cross-pipe crossbar unit 10 to the vector register (S13). However, the writing of the vector register from the time when the VMV instruction is issued by another instruction is prohibited from the time when the VMV instruction is issued. This is because the VMV instruction is issued as one instruction, and the vector register write pass busy flag is not rewritten for a long time.

  The effects of the vector processing apparatus according to this embodiment will be summarized below. As shown in the examples of FIGS. 6 and 7, by providing the transmission data buffer 220 and the reception data buffer 230 in the vector pipe subunit 200, reading and writing of vector data from the vector operation pipe 210 can be performed at an early stage. finish. This is because an output destination is provided for each vector calculation pipe 210 so that the processing in the vector calculation pipe 210 can be completed early. As a result, processing that normally takes time for interleaving processing can be shortened. Since the time for reading and writing vector data from the vector operation pipe 210 is shortened, the timing at which the subsequent instruction can be started is accelerated, and the processing time is shortened.

  Further, as shown in FIG. 6, the writing to the vector register 250 is controlled by the vector register write pass busy flag. The instruction issuing unit 400 according to the present embodiment issues the VMV instruction separately into a primary instruction that does not cause writing to the vector register 250 and a secondary instruction that causes writing to the vector register 250. The vector register write pass busy flag is set as in use only when a secondary instruction is issued. Thus, the succeeding VADD instruction can be completed while the preceding VMV instruction is not performing the writing process to the vector register 250, and an efficient vector operation process is realized.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

10 pipe crossbar unit 20 vector pipe unit 200 vector pipe subunit 210 vector operation pipe 220 transmission data buffer 230 reception data buffer 240 pipe crossbar 250 vector register 260 operator 270 vector data selection circuit 30 signal line 400 issuance control unit 401 instruction Request A storage unit 402 Instruction request B storage unit 403 Issue check circuit A
404 Issue check circuit B
405 GOA
406 GOB
407 Busy flag storage unit 408 Vector register write path busy flag storage unit 409 WS register 410 Vector register write path use inhibition flag storage unit 411 VTB read inhibition flag storage unit 412 PXB instruction secondary request storage unit 413 Issue check circuit C
414 RGO

Claims (10)

A first processing unit comprising first and second vector operation pipes;
A second processing unit;
A data transfer circuit configured to transfer data between the first processing unit and the second processing unit;
The first processing unit and the data transfer circuit are connected and output data of the first and second vector operation pipes are supplied to the data transfer circuit or from the data transfer circuit. And a first data path used to provide input data to a second vector operation pipe;
With
The first processing unit includes a data buffer disposed between the first and second vector operation pipes and the first data path, and holding the output data or the input data.
The first and second vector operation pipes do not depend on whether the other vector operation pipe is accessing the data buffer and whether the first data path is in use, The data buffer is configured to be accessible ;
The data buffer is arranged between the first data operation pipe and the first data path, and between the second vector operation pipe and the first data path. A second data buffer provided,
Vector arithmetic processing unit. The first data buffer is configured to hold output data of the first vector operation pipe;
The second data buffer is configured to hold output data of the second vector operation pipe;
The first processing unit further includes a selection circuit for supplying to said first data buffer or said data held in the second data buffer selectively the first data path, according to claim 1 Vector arithmetic processing unit. The first processing unit further includes an issue control unit that issues an instruction to the first vector operation pipe,
The first vector operation pipe includes a first register for storing data used for operation in the operation pipe and operation result data,
The first data buffer is configured to hold input data to the first vector operation pipe;
The issuance control unit depends on whether or not the first vector operation pipe is executing a preceding instruction that causes data to be written from the data transfer circuit via the first data buffer to the first register. Without being performed, neither data transfer from the data transfer circuit to the first data buffer nor data transfer from the first data buffer to the first register due to execution of the preceding instruction is performed. A subsequent instruction is issued to the first vector operation pipe on the condition that
The vector operation processing apparatus according to claim 1 . A first flag indicating whether or not a write path for writing data to the first register is in use;
A second flag indicating whether or not the first data path for transferring data from the data transfer circuit to the first data buffer is in use;
Further comprising
The issuance control unit refers to the first and second flags to transfer data from the data transfer circuit to the first data buffer and from the first data buffer to the first register. The vector operation processing apparatus according to claim 3 , wherein it is determined that neither data transfer is performed. The issuance control unit, when the first flag is not set and data transfer from the data transfer circuit to the first data buffer is started,
The vector operation processing device according to claim 4 , wherein data transfer from the data buffer to the first register is started and the first flag is set. The second flag is supplied from the data transfer circuit to the first processing unit, and is set according to a control signal indicating the start of data transfer from the data transfer circuit to the first data buffer. The vector arithmetic processing apparatus according to claim 4 or 5 . The data buffer, said output data output by said first and second vector operation pipes, any of claims 1 to 6 independent of the transfer of the output data to said first data path The vector operation processing device according to claim 1. The data buffer separates the supply of the input data from the first data path to the data buffer and the supply of the input data from the data buffer to the first and second vector operation pipes. The vector arithmetic processing apparatus of any one of Claim 1 thru | or 6 . It said data transfer circuit is a crossbar switch, the vector processing apparatus according to any one of claims 1 to 8. A first processing unit comprising first and second vector operation pipes;
A second processing unit;
A data transfer circuit configured to transfer data between the first processing unit and the second processing unit;
The first processing unit and the data transfer circuit are connected and output data of the first and second vector operation pipes are supplied to the data transfer circuit or from the data transfer circuit. And a first data path used to provide input data to a second vector operation pipe;
A processing method in a vector processing device comprising:
The first processing unit includes a data buffer disposed between the first and second vector operation pipes and the first data path, and holding the output data or the input data.
The data buffer is arranged between the first data operation pipe and the first data path, and between the second vector operation pipe and the first data path. A second data buffer,
The first and second vector operation pipes do not depend on whether the other vector operation pipe is accessing the data buffer and whether the first data path is in use, A vector operation processing method for accessing the data buffer.

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