JP5500114B2 - Access device and access method - Google Patents

Description

  The present invention relates to an access device and an access method for accessing a storage device, an input / output device, and the like.

  The extended memory unit (EMU (Extended Memory Unit)) has a high-speed memory extended unit (EU (Extended Unit)), and the storage hierarchy gap between the main memory of the connected computer (host) and the external secondary memory In a cluster system in which multiple hosts are joined together to improve scalability and availability of mainframes, etc., it is mainly used as a means to realize high-speed data sharing among multiple hosts. Has been. For the control of the EMU, an EMUFW (Extended Memory Unit Firmware) that operates on a CPU (Central Processing Unit) provided in the EMU is used. The EMUFW mainly performs control such as exclusive control and EU configuration control when the host accesses the EU.

  FIG. 1 shows a first configuration of a normal EMU. The normal EMU (71) in FIG. 1 includes a CPU (73) in which the EU (72) and the EMUFW (731) operate, and host connection ports (740, 741,... 74n) corresponding to the number of hosts for connecting to the host. . In this configuration, since the CPU (73) is directly connected to the EU (72) and all the host connection ports (740, 741,... 74n), the failure of the CPU (73) cannot be localized and the EMU (71). There was a problem that would lead to an overall obstacle.

In order to solve this problem, the second configuration of the normal EMU shown in FIG. 2 was invented. In FIG. 2, the EMU 81 includes an EU 82 and a plurality of FW platforms HW (firmware platform hardware) # 0 to #n (reference numerals 830, 831,..., 83n). FW platforms HW # 0 to #n (reference numerals 830, 831,... 83n) are IF HWs (interface hardware) (8301, 8311,..., 83n1) and EMUFWs (830211, 83121,..., 83n21), respectively. , And LM (8303, 8313,..., 83n2), and a local memory (Local Memory) (hereinafter referred to as LM) used by the CPUs (8302, 8312,..., 83n2). 83n3) and host connection ports (Port) (8304, 8314, ..., 83n4). The IF HW (8301, 8311,..., 83n1) is hardware that serves as an interface between the CPU (8302, 8312,..., 83n2) and the EU2. The FW platforms HW # 0 to #n (830, 831,... 83n) are independent of each other, but the EMUFW (830211, 83121,...,) That operates on the internal CPU (8302, 8312,..., 83n2). 83N21) can be a cooperative operation by sharing data by EU 8 2.

  The inventions related to the present invention are described in Patent Documents 1 to 3.

JP 2003-196251 A JP 2003-271573 A JP 05-225154 A

  In the configuration of FIG. 2, the CPU (8302, 8312,..., 83n2) on which the EMUFW (83021, 83121,..., 83n21) operates is disconnected from the EU (2), and a plurality of CPUs (8302, 8312,. By distributing the load, the CPU failure can be localized in the FW platform HW in which the CPU is operating, and the problem in the configuration of FIG. 1 can be solved. However, since the CPU (8302, 8312,..., 83n2) is disconnected from the EU (2) in the configuration of FIG. 2, the IF HW (8301) is used to access the EU (2) from the EMUFW (83021, 83121,..., 83n21). , 8311,..., 83n1), and there is a problem in that overhead is generated in the processing of EMUFW (830211, 83121,..., 83n21) by interposing HW.

  Accordingly, an object of the present invention is to provide an access device and an access method that can reduce overhead due to access processing when viewed from other processing.

  According to a first aspect of the present invention, there is provided an access device in an extended storage device comprising an expansion unit and one or more access devices having a function of accessing the expansion unit, wherein the access device is a multi-core CPU or a plurality of CPUs. The access device is provided with a plurality of cores, the first core executes the expansion unit access dedicated firmware, the second core executes the extended storage device firmware, and the expansion unit access dedicated firmware The first core is caused to execute at least a part of processing for accessing an expansion unit, and the expansion storage device firmware is an intermediary between a program executed in the second core and the expansion unit access dedicated firmware. To cause the second core to execute the process of Access device is provided, wherein Rukoto.

According to a second aspect of the present invention, an access method from the access device to the expansion unit in an extended storage device comprising an expansion unit and one or more access devices having a function of accessing the expansion unit. a is, in the access device, features a Rifuku number of cores by the multi-core CPU or multiple CPU, the access method, and that the first core executes the expansion unit access only firmware, second core of, which comprises performing the extended storage unit firmware, the expansion unit access only firmware, which makes out at least part of the process of accessing the expansion unit to the first core, The extended storage device firmware includes a program executed by the second core and the extended user firmware. Ttoakusesu access wherein the processing for the mediation of a dedicated firmware is intended to be executed by the second core is provided.

  According to the present invention, it is possible to reduce overhead due to access processing when viewed from other processing.

It is a figure which shows the 1st structure of normal EMU. It is a figure which shows the 2nd structure of normal EMU. It is a figure which shows the structure of EMU by embodiment of this invention. It is a figure which shows the structure of the Example of this invention. It is a figure which shows the data structure of the list | wrist used in the Example of this invention. It is a flowchart of the main loop of EMUFW and the WAIT restart process of the Example of this invention. It is a flowchart (the 1) at the time of EU access of the Example of this invention. It is a flowchart (the 2) at the time of EU access of the Example of this invention.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 3 shows the configuration of the EMU in the embodiment of the present invention. Compared with the normal configuration of FIG. 2, there is a difference inside the FW platform HW # 0 to #n (30, 31,..., 3n). Since each of the FW platforms HW # 0 to #n (30, 31,... 3n) is the same, only the FW platform HW # n (3n) will be described below, and the FW platform HW # n (3n) Description of other than that is omitted. A multi-core CPU (3n2) is used as a CPU for executing EMUFW (3n23). The multi-core CPU (3n2) includes Core # 0 (3n21) and Core # 1 (3n24), and each Core has an inter-core communication function (3n22, 3n25). Although FIG. 3 shows a multi-core CPU (3n2) having two cores, in the present invention, two or more cores are sufficient, and the number of cores is not limited to two. Absent. The EMUFW (3n23) is operated on one Core and the EU access dedicated FW (3n26) is operated on the other Core. Here, for the sake of explanation, it is assumed that the Core # 0 (3n21) operates the EMUFW (3n23), and the Core # 1 (3n24) operates the EU access dedicated FW (3n26). The LM (3n3) is provided with a shared memory (3n31), which is an area where data can be shared among the cores (Core # 0 (3n21), Core # 1 (3n24)) of the multi-Core CPU (3n2).

  An operation for solving the above-described normal problem with the above configuration will be described below. The EMUFW (3n23) operating on the Core # 0 (3n21) of the multi-Core CPU (3n2) writes an EU access request to the shared memory (3n31) of the LM (3n3). The EU access dedicated FW (3n26) operating on the Core # 1 (3n24) acquires the request from the shared memory (3n31), and requests EU access to the IF HW (3n1). The IF HW (3n1) performs EU access. The EU access dedicated FW (3n26) waits for completion of EU access (for example, the EU access dedicated FW (3n26) can know the completion of EU access from the IF HW (3n1) by polling)). When the EU access is completed, the EU access dedicated FW (3n26) acquires the access result from the IF HW (3n1), stores it in the shared memory (3n31), and the Core # 1 (3n24) by the inter-core communication function (3n25). From Core to Core # 0 (3n21), inter-core communication is performed, and EUMU completion (3n23) is notified of EU access completion. The EMUFW (3n23) that has received the notification acquires the access result from the shared memory (3n31). Through the above operation, the EU access is made to the EU access dedicated FW (3n26) of the Core # 1 (3n24), and the EMUFW (3n23) of the Core # 0 (3n21) is communicated between the shared memory (3n31) and the Core. By acquiring the access result, it is possible to reduce the processing overhead of EMUFW (3n23) at the time of EU access, which was a problem.

  FIG. 4 shows the configuration of the embodiment of the present invention. 4, the EMU (1) according to the embodiment of the present invention includes an EU (2) and a plurality of IOCs (Input Output Controllers) (IOC # 0 (30), IOC # 1 (31),..., IOC #n). (3n)). Since the configuration of each IOC (IOC # 0 (30), IOC # 1 (31),..., IOC #n (3n)) is the same, only IOC #n (3n) will be described below, and IOC # The description is omitted except for n (3n). The IOC functions as an improvement of the FW platform HW.

  IOC # n (3n) corresponds to the FW platform HW # n (3n) of FIG. 3 described above, and the EMUFW operates in each IOC. EU (2) includes a UBAR area (Under Base address Register Area) (21). This area is an area for storing data to be shared among the EMUFWs operating on each IOC. By accessing the data in this area, the EMUFWs of a plurality of IOCs can perform a cooperative operation.

  Next, the configuration in IOC # n (3n) will be described. The IOC #n (3n) includes an IF LSI (Large Scale Integrated Circuit for Interface) (3n1), a multi-core CPU (3n2), an LM (3n3), and a host connection Port (3n4).

The IF LSI (3n1) corresponds to the IF HW (3n1) of FIG. 3 , and has an EU access function (3n11). The EU access function (3n11) can be used via the control register. The EU access is performed by writing a request in the control register, and the access result is reflected on the control register after the access is completed. By referring to this control register, the EMUFW (3n2 3 ) can acquire the result of EU access (access success / failure or read data).

  The multi-core CPU (3n2) is a CPU including two cores of Core # 0 (3n21) and Core # 1 (3n24). Both Cores have an inter-core communication function (3n22, 3n25). With this inter-core communication function (3n22, 3n25), each Core can communicate with the other Core. This communication is performed by generating an interrupt from the communication source Core to the communication destination Core, and processing the communication data in the interrupt processing of the communication destination Core that has received the interrupt. The EMUFW (3n23) is operated on the Core # 0 (3n21), and the EU access dedicated FW (3n26) is operated on the Core # 1 (3n24).

  The LM (3n3) includes a Core # 0 dedicated memory (3n31), a Core # 1 dedicated memory (3n33), and a shared memory (3n34). The Core # 0 dedicated memory (3n31) is an area accessible only from the EMUFW (3n23) operating on the Core # 0 (3n21), and has a WAIT list (3n32). The WAIT list (3n32) will be described later. The Core # 1 dedicated memory (3n33) is an area accessible only from the EU access dedicated FW (3n26) operating on the Core # 1 (3n24). The shared memory (3n34) is a memory area that can be shared between Cores, and is accessible from both the EMUFW (3n23) and the EU access dedicated FW (3n26). The shared memory (3n34) includes a request list (3n35) and a result list (3n36). Both lists will be described later.

  The host connection port (3n4) is a port that is connected to the host to realize the IF, and can receive a request from the host or return a response via the port. In this embodiment, since there is one host connection port for each IOC, the number of IOCs is determined by the number of hosts.

  FIG. 5 shows the data structure of each list used in the embodiment of the present invention. The list used in this embodiment includes the above-described WAIT list (3n32) in the Core # 0 dedicated memory (3n31), the request list (3n35) in the shared memory (3n34), and the result list (3n36). The EMUFW (3n23) executes processing corresponding to the generated factor in accordance with the occurrence of each factor such as communication from the host, communication from other EMUFW, and failure.

  The WAIT list (3n32) indicates that when the EMUFW (3n23) accesses the UBAR area (21) of the EU (2) by processing of a certain factor, the access to the UBAR area (21) of the EU (2) is completed. This is a list used to wait for the processing of the factor being executed in the WAIT state, execute the processing of another factor, and resume the processing of the factor after the access is completed.

  Each element of the WAIT list has a process ID, a restart point, a state, an EU access key number, and a member of EU data. The process ID is an ID for distinguishing each process for each factor that called the EU access process, and is defined as “host communication factor process = 0, communication factor process from other EMUFW = 1,...”. The restart point is data specifying where to restart the factor process in the WAIT state when the factor process is restarted. The status includes WAIT and waiting for resumption, and is set when shifting to each status. The EU access key number is a number designated by the EMUFW (3n23) when issuing an access request to the UBAR area (21) of the EU (2), and uniquely identifies the access request. The EU data is for storing access result data when the access to the UBAR area (21) of the EU (2) is completed, and is used to pass the access result data to the cause process to be resumed. . If the access is a write, the EU data is data indicating the success / failure of the access. If the access is a read, the EU data is the data indicating the success / failure of the access and the read data.

  Next, the request list (3n35) and the result list (3n36) will be described. The request list (3n35) is a list used when the EMUFW (3n23) requests access to the UBAR area (21) of the EU (2) from the EU access dedicated FW (3n26), and the result list (3n36) is an access. A list that stores the results. The members of the request list (3n35) and the result list (3n36) are the same, and the result list (3n36) is the EU access dedicated FW (3n26) when the access to the UBAR area (21) of the EU (2) is completed. Is created by removing the element of the request list completed from the request list (3n35), adding it to the result list (3n36), and storing the access result.

  Each element of the request list and the result list has EU access key number, access destination address, access type, size, EU data, status, and result components. Since the EU access key number is the same as that of the WAIT list (3n32), the description is omitted. The access destination address designates the address of the UBAR area (21) of the EU (2) to be accessed, the access type designates read or write, and the size designates the data size to be accessed. The EU data stores data to be written to the UBAR area (21) of the EU (2) when the access type is write, and data read from the UBAR area (21) of the EU (2) when read. The status includes waiting for access, waiting for completion, and completion. The result (OK / NG) of the access to the UBAR area (21) of EU (2) is stored in the result.

  The operation of the embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 6 shows a flowchart of the main loop which is the main process of EMUFW (3n23). FIG. 7 and FIG. 8 show flowcharts when accessing the EU (2) from the EMUFW (3n23).

  As shown in FIG. 6, the EMUFW (3n23) checks whether the host communication factor, other EMUFW communication factor, failure processing factor, and WAIT factor are generated in the main loop (steps A1 and A3 in FIG. 6). , A5, A7), the processing corresponding to each factor (steps A2, A4, A6, A8 in FIG. 6) when it occurs, the detection of this factor and the processing corresponding to the generated factor are repeated.

  Next, details of processing corresponding to the WAIT factor will be described. In the detection of the WAIT factor in step A7 in FIG. 6, if there is an element in the WAIT list (3n32), the EMUFW 3n23 determines that there is a factor (Yes in step A7 in FIG. 6), and the WAIT restart processing (step in FIG. 6). A8) is executed. A detailed flowchart of the WAIT restart process is shown in the right-hand balloon of FIG. In the WAIT restart process, the EMUFW (3n23) reads an element of the WAIT list (3n32) (step B1 in FIG. 6) and checks whether the state is waiting for restart (step B2 in FIG. 6). If the state is not waiting for resumption, it is confirmed whether all elements have been checked (step B5 in FIG. 6). If all elements have been checked, the process returns to the main loop assuming that there is no process to be resumed. If there is an unconfirmed element in the WAIT list (3n32), the check target is moved to the next element (step B6 in FIG. 6), and it is searched whether there is an element whose state is awaiting resumption. If there is an element whose state is waiting to be resumed (Yes in step B2 in FIG. 6), the process corresponding to the process ID is executed from the restart point. At that time, by passing the EU data in the element to the process, the data acquired by accessing the UBAR area (21) of the EU (2) is passed to the process of restarting (step B3 in FIG. 6). When the resumed process is completed, the element is deleted from the WAIT list (3n32) (step B4 in FIG. 6), and the process returns to the main loop. As described above, the WAIT restart process of the main loop can restart the elements whose status in the WAIT list (3n32) is waiting for restart.

  Next, an operation when accessing the UBAR area (21) of the EU (2) while executing the process of a certain factor (here, for the sake of explanation, the host communication process is being executed) is shown. 7 and will be described with reference to the flowchart of FIG.

  7 and 8 are started from the host communication process A2, the other EMUFW communication process A4, or the failure process A6 shown in FIG.

  The EMUFW (3n23) writes to each constituent member of the element of the request list (3n35) according to the access contents to the UBAR area (21) of the EU (2), and accesses the UBAR area (21) of the EU (2). A request is made to the EU access dedicated FW (3n26) (step C1 in FIG. 7). Here, the EU access key number (unique number for each access), access destination address, access type, size, data (content according to access content), and state (waiting for access) are set as constituent members of each element. . The EMUFW (3n23) adds an element to the WAIT list (3n32), writes the element, puts the process being executed (for example, host communication process) into the WAIT state (step C2 in FIG. 7), and enters the main loop. Return. Here, an element is added to the WAIT list (3n32). The element to be added is 0 as the process ID (in the case of host communication process), the data indicating the next process interrupted as the restart point, the status to WAIT, and the EU The EU access key number set in the element of the request list (3n35) in step C1 in FIG. 7 is set as the access key number. The EMUFW (3n23) that has returned to the main loop continues the main loop processing.

  The EU access dedicated FW (3n26) reads an element from the request list (step D1 in FIG. 7), and checks whether the status is a request waiting for access (step D2 in FIG. 7). If the status is an element waiting for access (Yes in step D2 in FIG. 7), write data as EU data (only when access is write), an access destination address, an access type, and a size are attached. Then, write to the control register of the EU access function (3n11) of the IF LSI (3n1) to make an access request (step D3 in FIG. 7).

  Upon receiving the request, the IF LSI (3n1) accesses the EU (2) (step E1 in FIG. 7). The accessed EU (2) returns the result (steps F1 and F2 in FIG. 7), but it takes time until the access is completed and the result is output.

  The EU access dedicated FW (3n26) sets the state of the element of the request list from waiting for access to waiting for completion in order to confirm the completion of EU access, and the control register of the EU access function (3n11) of the IF LSI (3n1) It is checked whether the EU access has been completed by watching the above, and polling waiting for completion is performed (step D5 in FIG. 7). If the EU access is not completed as a result of the polling (No in step D6 in FIG. 7), the process moves to the next element in the request list (3n35) and repeats the scanning of the request list (step D7 in FIG. 7).

  When the target becomes the element again, the status is waiting for completion, so it is determined that the request is waiting for completion (Yes in step D4 in FIG. 7), and polling waiting for completion is performed again (FIG. 7). Step D5). If the EU access is completed, the EU (2) returns the result to the IF LSI (3n1) (step F2 in FIG. 7), and the IF LSI (3n1) returns the received access result. This is reflected in the control register of the EU access function (3n11) (step E2 in FIG. 7). When the access is a write, a write result (OK / NG) is written to the control register, and when the access is a read, the read result (OK / NG) and read data are written. The EU access dedicated FW (3n26) polls for completion (step D5 in FIG. 7), and detects the completion of access (Yes in step D6 in FIG. 7).

  The EU access dedicated FW (3n26) that has detected the access completion acquires the access result from the control register of the EU access function (3n11) of the IF LSI (3n1) (step D8 in FIG. 7), and the request list (3n35) The element is moved to the result list (3n36), and the access result is reflected in the EU data and the result (OK / NG) of the element to set the state from waiting for completion to completion (step D9 in FIG. 7).

  Then, the EU access dedicated FW (3n26) uses the inter-core communication function (3n25) to notify the EMUFW (3n23) of EU access completion through inter-core communication (step D10 in FIG. 7). Thereafter, the EU access dedicated FW (3n26) returns to step D1 of FIG. 7, scans the request list (3n35), and repeats the process of EU access and polling waiting for completion.

  The EMUFW (3n23) that has received the inter-Core communication starts the interrupt process, and performs the EU access completion process (state A in FIGS. 7 and 8). The EMUFW (3n23) reads the element from the result list (3n36) (step C3 in FIG. 8), searches the WAIT list (3n32) for the element having the EU access key that matches the EU access key of the element, That is, the process element that has completed EU access) is acquired from the WAIT list (step C4 in FIG. 8).

  The EMUFW (3n23) is in the WAIT state, and in order to resume the processing that has completed the EU access, the state of the element in the WAIT list is changed from WAIT to waiting for resumption, and the data acquired by the EU access is changed to the corresponding in the result list. Read from the element and store it in the EU data of the element in the WAIT list (step C5 in FIG. 8).

  Then, EMUFW (3n23) deletes the element in the result list (3n36) (step C6 in FIG. 8) and returns to the main loop. The EMUFW (3n23) that has returned to the main loop restarts the processing (host communication processing) of the element of EU access completion from the WAIT list (3n23) by the WAIT restart processing described above. The resumed EU access process (host communication process) continues using the EU access result acquired from the elements of the WAIT list.

  With the above operation, the overhead of EMUFW processing at the time of EU access, which was a problem, can be reduced.

  In the above description, the example of accessing the UBAR area (21) of the EU (2) is used in the EU access processing. However, other areas (areas used by the operating system and the user) of the EU (2) are used. The present invention can also be applied.

  In the above description, a multi-core CPU is used. However, a plurality of single-core CPUs may be provided, and a plurality of single-CPU cores may be used.

  The first effect of the present embodiment is that the EU, which has been a problem in the case of taking a configuration in which the CPU and the EU on which the EMUFW operates are separated and the load is distributed by operating a plurality of CPUs in order to improve the fault tolerance of the EMU, The overhead of the processing of EMUFW at the time of access can be reduced. The reason is that, using a multi-core CPU, the EU access dedicated FW is operated by a core different from the core executing the EMUFW, and the EU access dedicated FW is performed by the EU access dedicated FW, via the communication between the shared memory and the core, This is because the EMUFW can reduce the overhead by acquiring the access result.

  The second effect is that the first effect can be realized at low cost. This is because the present invention can be implemented without using a special HW other than the multi-core CPU. Multi-Core CPUs have become mainstream in the current CPU market and can be obtained at low cost. This embodiment is also effective from the viewpoint of effective utilization of Core. Now that multi-core CPUs have become mainstream, there has been an opportunity to adopt multi-core CPUs even when not using all cores. For FW that requires high reliability such as EMUFW, even if a multi-core CPU is adopted to avoid quality degradation due to complicated processing due to parallel processing, only one core may be used. It becomes uneconomical because Core is used. In the present embodiment, the EMUFW processing itself is not parallelized, and other Cores are used only for EU access. Therefore, the Core of the multi-Core CPU can be effectively used without complicating the EMUFW processing.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
An expansion unit,
One or more access devices having a function of accessing the extension unit;
An access device in an extended storage device comprising:
The access device is provided with a plurality of cores by a multi-core CPU or a plurality of CPUs,
In the first core, the firmware dedicated to expansion unit access is executed,
In the second core, the extended storage firmware is executed,
The expansion unit access dedicated firmware causes the first core to execute at least a part of processing for accessing the expansion unit,
The extended storage device firmware causes the second core to execute a process that mediates between a program executed in the second core and the extended unit access dedicated firmware.

(Appendix 2)
The access device according to attachment 1, wherein
The extended storage device firmware includes an extended unit access processing unit, an extended unit access completion interrupt processing unit, and a WAIT restart processing unit.
When the expansion unit access processing unit needs to access the expansion unit with a program executed by the second core, the expansion unit access processing unit starts up the expansion unit access dedicated firmware and then performs a process other than the process that requires access. For causing the second core to execute a process;
The extension unit access completion interrupt processing unit is started by the extension unit access dedicated firmware, and is for passing a result of accessing the extension unit to a program executed by the second core,
The WAIT restart processing unit is included in a main loop of a program executed by the second core, and is for passing a result of accessing the extension unit to a program executed by the second core. An access device characterized by.

(Appendix 3)
The access device according to attachment 2, wherein
Local memory,
An interface circuit;
Further comprising
The local memory is provided with a dedicated area dedicated to the second core, a shared area shared by the first core and the second core,
In the dedicated area, a WAIT list is generated,
In the shared area, a request list and a result list are generated,
The extension unit access processing unit adds an element to the request list, writes “waiting for access” as a status to the added element, writes an extension unit access key number, write data, and access destination information, An element is added to the WAIT list, “WAIT” is written as a state in the added element, and the identification information of the process that called the extension unit access processing unit and the extension unit access key number are written. A process for causing the second core to execute a process for causing the process that called the extension unit access processing unit to WAIT,
The expansion unit access dedicated firmware is:
When an element whose state is “waiting for access” is in the request list, the state of the element is set to “waiting for completion”, and write data and access destination information included in the element are attached to the request list. A process of issuing an access request to the extension unit via a circuit;
When an element whose status is “waiting for completion” is in the request list and there is extension unit data as a result of accessing the extension unit in the interface circuit, the status of the element is set to “complete” The extension unit data is acquired from the interface circuit, the element whose state is “completed” is moved from the request list to the result list, and the extension unit data is included in the element, and then the extension unit data is included. Causing the first core to execute a process for starting a completion interrupt processing unit;
The extension unit access completion interrupt processing unit reads the extension unit access key number and the extension unit data from the result list element, and then includes the extension unit included in the WAIT list and read from the result list element. A process of changing the state of the element including the unit access key number from “WAIT” to “waiting for restart” and including the extension unit data read from the element of the result list in the element of the WAIT list. To be executed,
When there is an element whose state is “waiting for restart” in the WAIT list, the WAIT restart processing unit passes the extension unit data included in the element to the process having the identification information included in the element. An access device that causes the second core to execute a process for resuming the process.

(Appendix 4)
The access device according to attachment 2, wherein
Local memory,
An interface circuit;
Further comprising
The local memory is provided with a dedicated area dedicated to the second core, a shared area shared by the first core and the second core,
In the dedicated area, a WAIT list is generated,
In the shared area, a request list and a result list are generated,
The extension unit access processing unit adds an element to the request list, writes “waiting for access” as a status in the added element, writes an extension unit access key number and access destination information, and further adds to the WAIT list. An element is added, “WAIT” is written in the added element as a state, and the identification information of the process that called the extension unit access processing unit and the extension unit access key number are written, and then the extension unit access process The second core executes a process that causes the process that called the section to WAIT,
The expansion unit access dedicated firmware is:
When an element whose status is “waiting for access” is in the request list, the status of the element is set to “waiting for completion” and the access destination information included in the element is attached to the request list via the interface circuit. Issuing an access request to the extension unit;
When an element whose status is “waiting for completion” is in the request list and there is extension unit data as a result of accessing the extension unit in the interface circuit, the status of the element is set to “complete” The extension unit data is acquired from the interface circuit, the element whose state is “completed” is moved from the request list to the result list, and the extension unit data is included in the element, and then the extension unit data is included. Causing the first core to execute a process for starting a completion interrupt processing unit;
The extension unit access completion interrupt processing unit reads the extension unit access key number and the extension unit data from the result list element, and then includes the extension unit included in the WAIT list and read from the result list element. The state of the element including the unit access key number is changed from “WAIT” to “Waiting for restart”, the extension unit data read from the element of the result list is included in the element of the WAIT list, and the process is performed in the second state. Which is what the core does
When there is an element whose state is “waiting for restart” in the WAIT list, the WAIT restart processing unit passes the extension unit data included in the element to the process having the identification information included in the element. An access device that causes the second core to execute a process for resuming the process.

(Appendix 5)
The access device according to appendix 3 or 4,
An access device characterized in that the identification information is accompanied by a restart point of the process.

(Appendix 6)
The access device according to any one of appendices 3 to 5,
In the first core and the second core, an inter-core communication function program is also executed,
The extension unit access dedicated firmware activates the extension unit completion interrupt processing unit using the inter-core communication function program.

(Appendix 7)
An extended storage device comprising the access device according to any one of appendices 1 to 6.

(Appendix 8)
The expansion unit access dedicated firmware according to any one of appendices 1 to 6.

(Appendix 9)
The extended storage device firmware according to any one of appendices 1 to 6.

(Appendix 10)
An expansion unit,
One or more access devices having a function of accessing the extension unit;
An access method from the access device to the expansion unit in an extended storage device comprising:
The access device is provided with a plurality of cores in the access device by a multi-core CPU or a plurality of CPUs,
The first core executes firmware for exclusive use of expansion unit access,
The second core executes the extended storage firmware;
The expansion unit access dedicated firmware causes the first core to execute at least a part of processing for accessing the expansion unit,
2. The access method according to claim 1, wherein the extended storage device firmware causes the second core to execute a process that mediates between the program executed in the second core and the extended unit access dedicated firmware.

(Appendix 11)
The access method according to attachment 10, wherein
The extended storage device firmware includes an extended unit access processing unit, an extended unit access completion interrupt processing unit, and a WAIT restart processing unit.
When the expansion unit access processing unit needs to access the expansion unit with a program executed by the second core, the expansion unit access processing unit starts up the expansion unit access dedicated firmware and then performs a process other than the process that requires access. For causing the second core to execute a process;
The extension unit access completion interrupt processing unit is started by the extension unit access dedicated firmware, and is for passing a result of accessing the extension unit to a program executed by the second core,
The WAIT restart processing unit is included in a main loop of a program executed by the second core, and is for passing a result of accessing the extension unit to a program executed by the second core. An access method characterized by.

(Appendix 12)
The access method according to attachment 11, wherein
The access device is:
Local memory,
An interface circuit;
Further comprising
The local memory is provided with a dedicated area dedicated to the second core, a shared area shared by the first core and the second core,
In the dedicated area, a WAIT list is generated,
In the shared area, a request list and a result list are generated,
The extension unit access processing unit adds an element to the request list, writes “waiting for access” as a status to the added element, writes an extension unit access key number, write data, and access destination information, An element is added to the WAIT list, “WAIT” is written as a state in the added element, and the identification information of the process that called the extension unit access processing unit and the extension unit access key number are written. A process for causing the second core to execute a process for causing the process that called the extension unit access processing unit to WAIT,
The expansion unit access dedicated firmware is:
When an element whose state is “waiting for access” is in the request list, the state of the element is set to “waiting for completion”, and write data and access destination information included in the element are attached to the request list. A process of issuing an access request to the extension unit via a circuit;
When an element whose status is “waiting for completion” is in the request list and there is extension unit data as a result of accessing the extension unit in the interface circuit, the status of the element is set to “complete” The extension unit data is acquired from the interface circuit, the element whose state is “completed” is moved from the request list to the result list, and the extension unit data is included in the element, and then the extension unit data is included. Causing the first core to execute a process for starting a completion interrupt processing unit;
The extension unit access completion interrupt processing unit reads the extension unit access key number and the extension unit data from the result list element, and then includes the extension unit included in the WAIT list and read from the result list element. A process of changing the state of the element including the unit access key number from “WAIT” to “waiting for restart” and including the extension unit data read from the element of the result list in the element of the WAIT list. To be executed,
When there is an element whose state is “waiting for restart” in the WAIT list, the WAIT restart processing unit passes the extension unit data included in the element to the process having the identification information included in the element. An access method characterized by causing the second core to execute a process for resuming the process.

(Appendix 13)
The access method according to attachment 11, wherein
The access device is:
Local memory,
An interface circuit;
Further comprising
The local memory is provided with a dedicated area dedicated to the second core, a shared area shared by the first core and the second core,
In the dedicated area, a WAIT list is generated,
In the shared area, a request list and a result list are generated,
The extension unit access processing unit adds an element to the request list, writes “waiting for access” as a status in the added element, writes an extension unit access key number and access destination information, and further adds to the WAIT list. An element is added, “WAIT” is written in the added element as a state, and the identification information of the process that called the extension unit access processing unit and the extension unit access key number are written, and then the extension unit access process The second core executes a process that causes the process that called the section to WAIT,
The expansion unit access dedicated firmware is:
When an element whose status is “waiting for access” is in the request list, the status of the element is set to “waiting for completion” and the access destination information included in the element is attached to the request list via the interface circuit. Issuing an access request to the extension unit;
When an element whose status is “waiting for completion” is in the request list and there is extension unit data as a result of accessing the extension unit in the interface circuit, the status of the element is set to “complete” The extension unit data is acquired from the interface circuit, the element whose state is “completed” is moved from the request list to the result list, and the extension unit data is included in the element, and then the extension unit data is included. Causing the first core to execute a process for starting a completion interrupt processing unit;
The extension unit access completion interrupt processing unit reads the extension unit access key number and the extension unit data from the result list element, and then includes the extension unit included in the WAIT list and read from the result list element. The state of the element including the unit access key number is changed from “WAIT” to “Waiting for restart”, the extension unit data read from the element of the result list is included in the element of the WAIT list, and the process is performed in the second state. Which is what the core does
When there is an element whose state is “waiting for restart” in the WAIT list, the WAIT restart processing unit passes the extension unit data included in the element to the process having the identification information included in the element. An access method characterized by causing the second core to execute a process for resuming the process.

(Appendix 14)
The access method according to attachment 12 or 13,
An access method characterized in that the identification information is accompanied by a restart point of the process.

(Appendix 15)
The access method according to any one of appendices 12 to 14,
In the first core and the second core, an inter-core communication function program is also executed,
The extension unit access dedicated firmware activates the extension unit completion interrupt processing unit by using a program of the inter-core communication function.

  The present invention can be used not only for firmware platform hardware to access expansion units, but also for devices with multiple cores to access storage devices or input / output devices. The apparatus provided with a plurality of cores may be singular rather than plural.

1 EMU
2 EU
21 UBAR area 30, 31, ..., 3n IOC
301, ... 3n1 IF LSI
302, ... 3n2 multi-core CPU
303, ... 3n3 LM
3023, ... 3n23 EMUFW
3026, ... 3n26 EU access dedicated FW

Claims (10)

An expansion unit,
One or more access devices having a function of accessing the extension unit;
An access device in an extended storage device comprising:
The access device is provided with a plurality of cores by a multi-core CPU or a plurality of CPUs,
In the first core, the firmware dedicated to expansion unit access is executed,
In the second core, the extended storage firmware is executed,
The expansion unit access dedicated firmware causes the first core to execute at least a part of processing for accessing the expansion unit,
The extended storage device firmware causes the second core to execute a process that mediates between a program executed in the second core and the extended unit access dedicated firmware. The access device according to claim 1,
The extended storage device firmware includes an extended unit access processing unit, an extended unit access completion interrupt processing unit, and a WAIT restart processing unit.
When the expansion unit access processing unit needs to access the expansion unit with a program executed by the second core, the expansion unit access processing unit starts up the expansion unit access dedicated firmware and then performs a process other than the process that requires access. For causing the second core to execute a process;
The extension unit access completion interrupt processing unit is started by the extension unit access dedicated firmware, and is for passing a result of accessing the extension unit to a program executed by the second core,
The WAIT restart processing unit is included in a main loop of the extended storage device firmware , and is used to pass a result of accessing the extended unit to a program executed by the second core. apparatus. The access device according to claim 2,
Local memory,
An interface circuit;
Further comprising
The local memory is provided with a dedicated area dedicated to the second core, a shared area shared by the first core and the second core,
In the dedicated area, a WAIT list is generated,
In the shared area, a request list and a result list are generated,
The extension unit access processing unit adds an element to the request list, writes “waiting for access” as a status to the added element, writes an extension unit access key number, write data, and access destination information, An element is added to the WAIT list, “WAIT” is written as a state in the added element, and the identification information of the process that called the extension unit access processing unit and the extension unit access key number are written. A process for causing the second core to execute a process for causing the process that called the extension unit access processing unit to WAIT,
The expansion unit access dedicated firmware is:
When an element whose state is “waiting for access” is in the request list, the state of the element is set to “waiting for completion”, and write data and access destination information included in the element are attached to the request list. A process of issuing an access request to the extension unit via a circuit;
When an element whose status is “waiting for completion” is in the request list and there is extension unit data as a result of accessing the extension unit in the interface circuit, the status of the element is set to “complete” The extension unit data is acquired from the interface circuit, the element whose state is “completed” is moved from the request list to the result list, and the extension unit data is included in the element, and then the extension unit data is included. Causing the first core to execute processing for starting an access completion interrupt processing unit;
The extension unit access completion interrupt processing unit reads the extension unit access key number and the extension unit data from the result list element, and then includes the extension unit included in the WAIT list and read from the result list element. A process of changing the state of the element including the unit access key number from “WAIT” to “waiting for restart” and including the extension unit data read from the element of the result list in the element of the WAIT list. To be executed,
When there is an element whose state is “waiting for restart” in the WAIT list, the WAIT restart processing unit passes the extension unit data included in the element to the process having the identification information included in the element. An access device that causes the second core to execute a process for resuming the process. The access device according to claim 2,
Local memory,
An interface circuit;
Further comprising
The local memory is provided with a dedicated area dedicated to the second core, a shared area shared by the first core and the second core,
In the dedicated area, a WAIT list is generated,
In the shared area, a request list and a result list are generated,
The extension unit access processing unit adds an element to the request list, writes “waiting for access” as a status in the added element, writes an extension unit access key number and access destination information, and further adds to the WAIT list. An element is added, “WAIT” is written in the added element as a state, and the identification information of the process that called the extension unit access processing unit and the extension unit access key number are written, and then the extension unit access process The second core executes a process that causes the process that called the section to WAIT,
The expansion unit access dedicated firmware is:
When an element whose status is “waiting for access” is in the request list, the status of the element is set to “waiting for completion” and the access destination information included in the element is attached to the request list via the interface circuit. Issuing an access request to the extension unit;
When an element whose status is “waiting for completion” is in the request list and there is extension unit data as a result of accessing the extension unit in the interface circuit, the status of the element is set to “complete” The extension unit data is acquired from the interface circuit, the element whose state is “completed” is moved from the request list to the result list, and the extension unit data is included in the element, and then the extension unit data is included. Causing the first core to execute processing for starting an access completion interrupt processing unit;
The extension unit access completion interrupt processing unit reads the extension unit access key number and the extension unit data from the result list element, and then includes the extension unit included in the WAIT list and read from the result list element. the state of the element containing a unit access key number from the "wAIT" to "resume waiting", the results list element from the read extension unit data processing for allowed Ru contained in the element the second of the wAIT list Which is what the core does
When there is an element whose state is “waiting for restart” in the WAIT list, the WAIT restart processing unit passes the extension unit data included in the element to the process having the identification information included in the element. An access device that causes the second core to execute a process for resuming the process. The access device according to claim 3 or 4,
An access device characterized in that the identification information is accompanied by a restart point of the process. The access device according to any one of claims 3 to 5,
In the first core and the second core, an inter-core communication function program is also executed,
The extension unit access-dedicated firmware causes the first core to execute processing for starting the extension unit access completion interrupt processing unit using the inter-core communication function program. Access device.   An extended storage device comprising the access device according to claim 1. The dedicated firmware for accessing the expansion unit in the access device according to any one of claims 1 to 6. The extended storage device firmware in the access device according to claim 1. An expansion unit,
One or more access devices having a function of accessing the extension unit;
An access method from the access device to the expansion unit in an extended storage device comprising:
The said access device, equipped with Rifuku number of cores by the multi-core CPU or multiple CPU,
The access method is:
The first core executes dedicated firmware for expansion unit access;
The second core includes executing the extended storage firmware;
The expansion unit access dedicated firmware causes the first core to execute at least a part of processing for accessing the expansion unit,
2. The access method according to claim 1, wherein the extended storage device firmware causes the second core to execute a process that mediates between the program executed in the second core and the extended unit access dedicated firmware.

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