JP5495037B2 - Power factor correction circuit - Google Patents

Description

  The present invention relates to a power factor correction circuit in high frequency regulation. Further, the present invention relates to ENERGY STAR defined for a single voltage power supply (AC / DC).

  FIG. 10 is a circuit diagram showing an AC-DC converter including a conventional power factor correction circuit. The AC-DC converter shown in FIG. 10 includes a rectifier DB that rectifies an AC input voltage from an AC power supply Vac and outputs a rectified voltage, a boost chopper circuit 2 that boosts the rectified voltage from the rectifier DB, and a boost chopper circuit 2. A DC-DC converter circuit 3 for converting the voltage boosted by the above to a stabilized DC voltage and supplying it to a load.

  In the DC-DC converter circuit 3, a series circuit of a primary winding P1 of a transformer T1 and a switching element Q2 composed of a MOSFET is connected to both ends of a capacitor C2 of the power factor correction circuit 2. A series circuit of a diode Ds and a capacitor Cs is connected to both ends of the secondary winding S1 of the transformer T1, and a voltage detection amplifier circuit (VAMP) 30 for detecting the output voltage of the capacitor Cs is connected to both ends of the capacitor Cs. ing. A photocoupler PC1 is connected to the voltage detection amplifier circuit 30, and the photocoupler PC1 outputs a current corresponding to the output voltage detected by the voltage detection amplifier circuit 30 to the DD control circuit 20.

A series circuit of a diode D2 and a capacitor C3 is connected to both ends of the auxiliary winding P2 of the transformer T1, and a connection point between the diode D2 and the capacitor C3 is a resistance for starting the DD control circuit 20 and the DD control circuit 20. It is connected to one end of R3.
The DD control circuit 20 generates a pulse signal having a pulse width corresponding to the output voltage from the photocoupler PC1, and controls the output voltage to a predetermined voltage by controlling the on / off of the switching element Q2 with this pulse signal.

Next, the power factor correction circuit 2 will be described. The power factor correction circuit 2 constitutes a step-up chopper circuit, and a series circuit of a step-up reactor L1 and a switching element Q1 composed of a MOSFET is connected to both ends of the smoothing capacitor. A series circuit of a diode D1 and a capacitor C2 is connected between the drain and source of the switching element Q1.
A series circuit of resistors R1 and R2 is connected to both ends of the output of the rectifier DB, and a connection point between the resistors R1 and R2 is connected to the PFC control circuit 10. The PFC control circuit 10 inputs a gate pulse signal (hereinafter abbreviated as a pulse signal) of the switching element Q2 made of a MOSFET from the DD control circuit 20 of the DC-DC converter circuit 3 and applies it to the gate of the switching element Q1. To do. The PFC control circuit 10 improves the power factor by turning on / off the switching element Q1 based on the pulse signal of the switching element Q2 and the voltage obtained by dividing the rectified voltage of the rectifier DB by the resistors R1 and R2.

Hereinafter, the power factor correction circuit 2 will be described in detail.
In FIG. 10, the detection unit 11 including a resistor R1 and a resistor R2 detects a rectified voltage obtained by rectifying an AC input voltage, and outputs the detected rectified voltage to the cathode of the diode D3.
The PFC control circuit 10 receives the pulse signal (first pulse signal) from the DD control circuit 20 and has a pulse width corresponding to a rectified voltage obtained by rectifying the AC input voltage when an ON pulse of the pulse signal is generated. A delay circuit 12 that generates a signal and generates a PFC gate signal (second pulse signal) by synthesizing the pulse signal and the delayed pulse signal, and drive circuits Q3 and Q4 that drive the switching element Q1 by the PFC gate signal , R6 and overcurrent protection circuits R4, R5, C4, Q5, R7, R8, Q6, D4 for limiting the current flowing through the switching element Q1.

  In the delay circuit 12, a series circuit of a capacitor C5 and a resistor R13 is connected between the gate side terminal of the switching element Q2 of the DD control circuit 20 and the negative terminal of the rectifier DB, and a resistor R11 and a resistor R12 are connected. Are connected in series.

  The base of the transistor Q8 is connected to the connection point between the resistors R11 and R12, and the emitter of the transistor Q8 is connected to the connection point between the capacitor C5 and the resistor R13. The gate side terminal of the DD control circuit 20 is connected to the emitter of the transistor Q7, and the base of the transistor Q7 is connected to the anode of the diode D3 and the collector of the transistor Q8 via the resistor R10. The cathode of the diode D3 is connected to the connection point between the resistor R1 and the resistor R2.

  The collector of the transistor Q7 is connected to the base of the transistor Q3, the base of the transistor Q4, and the anode of the diode D4 via the resistor R9. The cathode of the diode D4 is connected to the collector of the transistor Q5 and one end of the resistor R8. The emitter of the transistor Q5 is connected to the negative terminal of the rectifier DB, and the base of the transistor Q5 is connected to one end of the resistor R5, one end of the resistor R7, and one end of the capacitor C4.

  In the drive circuit, the collector of the transistor Q3 is connected to the gate side terminal of the DD control circuit 20, the emitter of the transistor Q3 is connected to the emitter of the transistor Q4 and one end of the resistor R6, and the other end of the resistor R6 is the switching element Q1. Connected to the gate. The collector of the transistor Q4 is connected to the negative terminal of the rectifier DB.

  Next, the operation of the PFC control circuit 10 configured as described above and shown in FIG. 10 will be described with reference to FIGS. FIG. 11 shows a rectified divided signal obtained by rectifying the AC input voltage. FIG. 12 is a timing chart of each signal in the delay circuit near the top A of the divided voltage signal after rectification at the rated load. FIG. 13 is a timing chart of each signal in the delay circuit near the bottom B of the divided voltage signal after rectification at the rated load.

  The delay circuit 12 receives the pulse signal from the DD control circuit 20 and, when an on-pulse of the pulse signal is generated, the pulse width corresponding to the voltage value of the collector voltage signal of the transistor Q8 based on the rectified voltage obtained by rectifying the AC input voltage Is generated, and the PFC gate signal is generated by combining the pulse signal and the delayed pulse signal. The PFC gate signal has a pulse width that is narrower by the pulse width of the delayed pulse signal than the pulse width of the pulse signal.

  The delay circuit 12 widens the pulse width of the delayed pulse signal as the rectified voltage increases, makes the PFC gate signal a pulse width narrower than the pulse width of the pulse signal, narrows the pulse width of the delayed pulse signal as the rectified voltage decreases, When the rectified voltage reaches the bottom region, the pulse width of the delayed pulse signal is made zero.

  First, the operation of the delay circuit 12 near the top A of the rectified divided signal will be described with reference to FIG. Based on the point c voltage (pulse divided signal c) obtained by dividing the pulse signal a from the DD control circuit 20 by the resistors R11 and R12, the point b voltage (differentiating circuit) of the differentiating circuit by the capacitor C5 and the resistor R13. When the difference voltage between the signal b) and the voltage at point c reaches the base-emitter voltage Vbe of the transistor Q8, the transistor Q8 is turned on.

  In addition, since the rectified voltage at the connection point between the resistor R1 and the resistor R2 near the top A of the divided voltage signal f after rectification is higher than the potential at the point e, the diode D3 is off.

  For this reason, the differentiation circuit signal b, which is the voltage at the point b of the differentiation circuit by the capacitor C5 and the resistor R13, starts from the time t1 when the pulse signal a from the DD control circuit 20 is turned on, as shown in FIG. The PFC gate signal d is output from time t2 which decreases with the elapsed time and becomes lower by the base-emitter voltage Vbe of the transistor Q8 than the pulse divided signal c which is the potential at the point c. The transistor Q3 is turned on by the PFC gate signal d, and the switching element Q1 is turned on.

  Next, when the pulse signal a from the DD control circuit 20 becomes zero, a current flows through the path of the gate of the switching element Q1, the emitter and base of the transistor Q4, and the base and collector of the transistor Q3. As a result, since the transistor Q4 is turned on, the gate voltage of the switching element Q1 becomes zero, and the switching element Q1 is turned off.

  As described above, when the rectified voltage at the connection point f between the resistor R1 and the resistor R2 is high, the delay circuit 12 has the PFC gate signal d with a delay time fixed by the time constant between the capacitor C5 and the resistor R13. Is output.

  Next, the operation of the delay circuit 12 near the bottom B of the rectified divided signal f will be described with reference to FIG. The voltage waveform of the collector voltage signal e 'of the transistor Q8 in FIG. 13 is a value close to zero volts.

  When the rectified voltage at the connection point f between the resistor R1 and the resistor R2 becomes equal to or lower than the voltage obtained by subtracting the base-emitter voltage Vbe of the transistor Q7 and the forward voltage of the diode D3 from the pulse signal a voltage of the DD control circuit 20. A current flows through the path of the pulse signal a → the transistor Q7 → the resistor R10 → the diode D3 → the resistor R2 → the ground of the DD control circuit 20.

  For this reason, the transistor Q7 is in an on state during a period in which the pulse signal a from the DD control circuit 20 is on. Therefore, the PFC gate signal d ′ is turned on in synchronization with the pulse signal a from the DD control circuit 20 regardless of the period from time t1 to time t2.

That is, when the rectified voltage obtained by rectifying the AC input voltage is near the bottom B, the delay time is zero, and when the rectified voltage is near the top A, the PFC pulse signal d ′ is set with a preset delay time. Is output to the switching element Q1 to control the power factor.
Therefore, the boosting rate is reduced, and the power factor can be sufficiently improved. For this reason, the power factor is improved by conforming to the new standard LEVEL V of “ENAGY STAR”, and an inexpensive power factor improvement circuit is provided.

  FIG. 14 shows waveforms of the rectified divided signal f of the AC input voltage and the drain current PFCId flowing through the switching element Q1 at this time. FIG. 15 shows the relationship between the AC input voltage and the PFC output voltage.

  Further, when the load current becomes light, the pulse width of the pulse signal a from the DD control circuit 20 becomes narrower in order to stabilize the output voltage of the DC-DC converter circuit 3. The waveform of each signal of the power factor correction circuit at light load is shown in FIG. In the example of FIG. 16, the pulse width of the pulse signal a is a period from time t1 to time t2. Since the delay time by the differentiating circuit does not change with respect to the load current, the differentiating circuit signal b is always in a high potential state with respect to the pulse divided signal c. For this reason, the transistor Q8 is not turned on.

  Further, since the discharge current of the capacitor C1 can be reduced by a light load, the charging voltage of the capacitor C1 does not vary greatly regardless of the input voltage waveform. Therefore, the transistor Q7 does not turn on because the voltage at the voltage dividing point f of the rectified voltage is higher than the voltage of the pulse signal due to the influence of the charging voltage of the capacitor C1. For this reason, when the pulse width of the pulse signal from the DD control circuit 20 becomes a predetermined delay time or less, the PFC pulse signal d is not output.

  That is, the delay circuit sets the PFC gate signal d to a pulse width that is narrower than the pulse width of the pulse signal a as the load of the DC-DC converter circuit 3 becomes lighter, and the load of the DC-DC converter circuit 3 is less than or equal to a predetermined load power Then, the pulse width of the PFC gate signal d is set to zero. For this reason, in the light load state, the operation of the power factor correction circuit 2 is not performed, the power consumption of the power factor correction circuit 2 is eliminated, and conversion efficiency can be improved.

  The AC input overvoltage correction circuit 13 shown in FIG. 10 limits the boosting rate so that the power factor correction circuit does not continue boosting when the AC input overvoltage occurs. The pulse width of the delayed pulse signal is set based on the PFC output voltage. A correction circuit for correction is configured.

Patent No. 4400680

However, in the conventional AC-DC converter, a delayed pulse signal having a pulse width corresponding to the rectified voltage is generated with respect to the rectified voltage obtained by rectifying the commercial power supply. Here, since the input voltage of 100V to 200V is supported, since the rectified voltage continues to be lower in the input voltage 100V system than in the input voltage 200V system, the second pulse signal having almost no delayed pulse signal width is generated. The power is output to the switch drive unit that drives the switching element of the power factor correction circuit. That is, when the delay pulse signal is an input voltage 200V system, the pulse width of the second pulse signal is greatly changed by the delay pulse signal corresponding to the rectified voltage, but in the case of the input voltage 100V system, the delay pulse signal is Since there is almost no influence on the pulse width of the second pulse signal.
Here, with respect to the output power of recent AC adapters, a rated power about 1.5 times higher than the conventional output power has been required due to an increase in demand such as conversion of desktop PCs to AC adapters. However, the conversion efficiency and the power factor are also not restricted by legal regulations due to the energy saving regulations. Considering the conditions when the output power increases, in the current discontinuous mode of the conventional power factor correction circuit, the peak value of the switching current of the switching element of the power factor correction circuit is proportional to the square of the power. Therefore, as shown in Fig. 17 (b), the switching current suddenly increases as the output power increases, so the switching loss of the switching element and the loss due to the copper loss of the booster coil increase, and the conversion efficiency decreases. End up.
Here, by adjusting the ratio of the number of turns of the primary / secondary winding of the transformer of the DC-DC converter, adjustment of widening the pulse width of the first pulse signal, or the inductance value of the reactor of the power factor correction circuit The peak value of the switching current of the power factor correction circuit can be suppressed by adjusting and changing the design of the power factor improvement circuit from the current discontinuous mode to the current continuous mode.
When the design of the power factor correction circuit is changed to the continuous current mode, in the AC100V system input with a large input current, the switching current of the power factor correction circuit becomes a DC continuous current continuous mode only near the top of the rectified voltage, It will operate in the conventional current discontinuous mode.
However, since almost no delayed pulse signal is generated at the AC100V input, the second pulse signal that is the drive signal of the power factor correction circuit has a pulse width equivalent to that of the first pulse signal that is the drive signal of the DC-DC converter. Become.
Therefore, as shown in FIG. 17 (a), the current value rapidly increases only near the top of the rectified voltage, and the input current of the power factor correction circuit becomes a distorted waveform in which the vicinity of the top protrudes from a sine wave shape. Deteriorate rate and conversion efficiency. This is a major obstacle to strengthening the regulation values of energy conservation regulations (EPA, ErP, etc.) that are being demanded in the future.
Further, near the top of the rectified voltage, the power factor correction circuit operates in the continuous current mode, and the recovery current of the diode D1 flows at the timing when the switching element Q1 is turned on, which causes generation of EMI noise. Here, since the second pulse signal and the first pulse signal have the same pulse width, the switching element Q1 of the power factor correction circuit and the switching element Q2 of the DC-DC converter are turned on and off at the same time. The generation of EMI noise at the time of turn-on of the elements overlaps and noise increases.
In addition, when the continuous current mode design is performed in the entire range from the top to the bottom of the rectified voltage of the AC100V system input, the inductance value of the reactor of the power factor correction circuit becomes small, and the peak of the switching current of the switching element Since the value increases, the efficiency of the power factor correction circuit is reduced instead.

  Therefore, only by changing the constant for the purpose of increasing the output power, the regulation value of the energy saving regulations (EPA, ErP, etc.) for the single output power supply defined by the EPA in the United States, that is, the average efficiency of 87% when the input voltage is AC 115V / 230V As described above, it becomes difficult to conform to a standard having a power factor of 0.9 or more (further demanding in the future than the left).

  An object of the present invention is to provide a simple and inexpensive power factor correction circuit that improves efficiency and power factor that can more reliably meet energy saving regulations (EPA, ErP, etc.).

In order to solve the above problems, a power factor correction circuit according to the present invention boosts a rectified voltage obtained by rectifying an AC input voltage from an AC power source by turning on / off a switching element and improves a power factor to increase a boosted output voltage. A power factor correction circuit that outputs to a DC-DC converter circuit driven by a first pulse signal,
When the first pulse signal having a pulse width corresponding to the output voltage of the DC-DC converter circuit is input and an ON pulse of the first pulse signal is generated, a delayed pulse signal having a pulse width corresponding to the rectified voltage is generated. A delay circuit that generates and generates a second pulse signal by combining the first pulse signal and the delayed pulse signal from the delay circuit;
A switch driving circuit for driving the switching element by the second pulse signal generated by the delay circuit;
The delay circuit includes a correction circuit that narrows the pulse width of the delayed pulse signal as the rectified voltage decreases when the boosted output voltage exceeds a predetermined first voltage,
The delay circuit reduces the pulse width of the delay pulse signal of the correction circuit to a narrower pulse width when the boosted output voltage exceeds a second voltage set higher than a predetermined first voltage. And a correction switching circuit.

  Also, in the power factor correction circuit according to the present invention, the delay circuit makes the second pulse signal have a pulse width narrower than the pulse width of the first pulse signal by the pulse width of the delayed pulse signal. .

  In the power factor correction circuit according to the present invention, the delay circuit increases the pulse width of the delayed pulse signal as the rectified voltage increases, and the second pulse signal is narrower than the pulse width of the first pulse signal. It is characterized by its width.

  In the power factor correction circuit according to the present invention, the delay circuit narrows the pulse width of the delayed pulse signal as the rectified voltage becomes smaller, and the pulse of the delayed pulse signal when the rectified voltage becomes the bottom region. The delay circuit is characterized in that the delay circuit narrows the pulse width of the delayed pulse signal as the rectified voltage becomes smaller, and the pulse width of the delayed pulse signal when the rectified voltage becomes a bottom region. Is zero.

  In the power factor correction circuit according to the present invention, the delay circuit makes the second pulse signal a pulse width narrower than the pulse width of the first pulse signal as the load of the DC-DC converter circuit becomes lighter. When the load of the DC-DC converter circuit becomes a predetermined load power or less, the pulse width of the second pulse signal is made zero.

  The power factor correction circuit according to the present invention includes a boosting reactor, and when the boosted output voltage is smaller than a predetermined first voltage, the switching that flows to the boosting reactor as the rectified voltage increases The current is set so as to be superimposed on a direct current.

According to the present invention, in the delayed pulse signal in which the delay circuit has a pulse width corresponding to the rectified voltage,
The first pulse signal and the delayed pulse signal obtained from the DC-DC converter are generated by switching the ratio according to the input voltage of the pulse width of the delayed pulse signal under the condition of the AC100V system input and the AC200V system input. Are combined to generate the second pulse signal of the power factor correction circuit. Therefore, the second pulse signal is an on-pulse signal that changes the pulse width in accordance with the voltage obtained by rectifying the alternating current when the AC 100 V system input and the AC 200 V system input.
Here, when the AC 100 V system is input, the power factor and efficiency can be further improved by increasing the rate of change of the pulse width according to the rectified voltage obtained by rectifying the alternating current as compared with the AC 200 V input. That is, the switching element can be driven on and off by the second pulse signal whose pulse width is changed according to the rectified voltage obtained by rectifying the alternating current, regardless of whether the input is AC100V system input or AC200V system input. Etc.), the efficiency and power factor can be improved in conjunction with the output power, and noise such as EMI can be suppressed to provide a simple and inexpensive power factor correction circuit.

  Hereinafter, embodiments of the power factor correction circuit of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram illustrating an AC-DC converter including a power factor correction circuit according to the first embodiment. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.
The AC-DC converter shown in FIG. 1 rectifies an AC input voltage from an AC power supply Vac and outputs a rectified voltage, a smoothing capacitor C1 connected to the output terminal of the rectifier DB, and a rectified voltage of the rectifier DB. A power factor correction circuit (PFC) 2a that boosts the power factor and improves the power factor, and a DC-DC converter circuit 3 that converts the voltage boosted by the power factor correction circuit 2 into a stabilized DC voltage and supplies it to the load, have.

  Next, the power factor correction circuit 2a will be described. The power factor improvement circuit 2a differs from the conventional power factor improvement circuit 2 in the detection unit 11a and the PFC control circuit 10a. That is, a resistor R2a is added to the detection unit 11a configured by a resistor R1 and a resistor R2 that detect a rectified voltage obtained by rectifying an AC input voltage, and a PNP transistor Q10 is added to the PFC control circuit 10a.

  In FIG. 1, a detection unit 11a including a resistor R1, a resistor R2, and a resistor R2a detects a rectified voltage obtained by rectifying an AC input voltage, and outputs the detected rectified voltage to the cathode of the diode D3. Here, both ends of the resistor R2a are connected to the emitter terminal and the collector terminal of the PNP transistor Q10, and the detected rectified voltage value is switched and output to the cathode of the diode D3 by switching the ON / OFF operation of the PNP transistor Q10 as will be described later. To do.

The base terminal of the PNP transistor Q10 of the PFC control circuit 10a is connected to the AC input overvoltage correction circuit 13a. The AC input overvoltage correction circuit 13a includes resistors R15 to R18, a transistor Q9, and a diode D5. The collector and emitter terminals of the transistor Q9 are connected to both ends of the resistor R14 of the PFC control circuit 10a, the resistor R17 is connected between the base and emitter of the transistor Q9, and one end of the resistor R16 is connected to the base terminal of the transistor Q9. The other end of the resistor R14, the emitter terminal of the transistor Q9, and the other end of the resistor R17 are connected to the negative terminal of the rectifier DB.
The other end of the resistor R16 is connected to one end of the resistor R15, one end of the resistor R18, and the base terminal of the PNP transistor Q10. The other end of the resistor R15 is connected to one end of the resistor R3, the cathode of the diode D2, and one end of the capacitor C3. It is connected to the Vcc voltage terminal of the DD control circuit 20. The other end of the resistor R18 is connected to the anode of the diode D5, and is connected to the anode of the diode D2 and one end of the auxiliary winding P2 via the diode D5. The other end of the auxiliary winding P2 is connected to the negative terminal of the rectifier DB.

According to the above configuration, the ON-ON voltage (the voltage in the same polarity direction as the voltage of the primary winding P1) of the auxiliary winding P2 of the transformer T1 is a negative voltage proportional to the PFC output voltage. The series voltage of the ON-ON voltage of the auxiliary winding P2 and the + Vcc voltage is divided by the series resistance of the resistor R15 and the resistor R18, and the voltage between the voltage dividing point of the series resistor and the ground GND is the resistor R16 and the resistor. The voltage is divided by R17 and detected, and the detected divided voltage is applied to the base of the transistor Q9.
Further, the potential difference between the voltage dividing point h of the resistor R15 and the resistor R18 and the voltage dividing point g of the series resistance of the resistor R1 and the resistor R2 and the resistor R2a of the detection unit 11a is the emitter-base voltage of the PNP transistor Q10. Detect with. Here, in the case of the AC input voltage AC100V system, the potential difference between the potential at the voltage dividing point g of the series resistance of the detecting portion 11a and the voltage dividing point h between the resistors R15 and R18 is the emitter-base of the PNP transistor Q10. Set it to be less than the voltage. That is, the resistance value is set so that the PNP transistor Q10 is turned on during the AC input voltage AC200V system so as to switch within the voltage range between the AC100V system and the AC200V system.
FIG. 2 shows the relationship between the AC input voltage and the PFC output voltage. As shown in FIG. 2, the PFC output voltage rises in proportion to the AC input voltage.

FIG. 3 shows a relationship diagram between the AC input voltage and the cathode potential of the diode D3 which is the output voltage f of the detection unit 11.
As shown in FIG. 3A, in the case of the AC 100V system, the output voltage f of the detection unit 11 outputs a higher ratio of voltage than that of the AC 200V system.
In the AC200V system, the PNP transistor Q10 is turned on by an AC input voltage exceeding the input voltage α point, and the detection voltage of the detection unit 11 is switched to shift to the characteristics shown in FIG. . When the amplitude of the AC input voltage becomes less than or equal to the input voltage β near 0 V, the voltage applied between the emitter and base of the PNP transistor Q10 becomes less than the threshold value, the PNP transistor Q10 is turned off, and the output voltage f of the detector 11 increases. Since the AC input voltage is a low voltage, the delayed pulse signal is not affected.

Next, the operation of the PFC control circuit 10 configured as described above and shown in FIG. 1 will be described with reference to FIGS.
FIG. 4 shows a rectified divided signal obtained by rectifying the AC input voltage. FIG. 5 is a timing chart of each signal in the delay circuit near the top A of the divided voltage signal after rectification at the rated load. FIG. 6 is a timing chart of each signal in the delay circuit in the vicinity of the bottom B of the divided voltage signal after rectification at the rated load. FIG. 7 shows a divided waveform signal f after rectification of the AC input voltage and a current waveform flowing through the switching element Q1.

As shown in FIG. 4, in the AC input voltage 100V system, the rectified divided signal of Example 1 of the present invention has a larger value than the rectified divided signal obtained by rectifying the conventional AC input voltage. Yes.
As shown in FIG. 12, conventionally, only in the AC input voltage 200V system, the delay pulse signal is generated by the delay circuit 12, and the delay is started from the time t1 when the pulse signal a from the DD control circuit 20 is turned on. The PFC gate signal d is output from the time t2 delayed by the pulse signal, and the switching element Q1 is turned on by the PFC gate signal d. However, in this embodiment, as shown in FIG. 5, even in the AC input voltage 100V system, a delay pulse signal is generated by the delay circuit 12 near the top A of the AC input voltage waveform, and the pulse width of the PFC gate signal d is narrowed. Make corrections.

Here, when the load of the DC-DC converter circuit 3 is 1.5 times the conventional power, the width of the pulse signal a from the DD control circuit 20 also increases in proportion. For this reason, the current flowing through the reactor L1 of the power factor correction circuit 2a increases, and as shown in FIG. 7, DC superposition is performed near the top A of the AC input voltage waveform. However, since the correction for narrowing the pulse width of the PFC gate signal d is performed near the top A of the AC input voltage waveform described above, the switching current of the switching element Q1 is suppressed, and the envelope is almost similar to the AC input voltage waveform. Switching current.
As shown in FIG. 6, each signal in the delay circuit in the vicinity of the bottom B of the divided voltage signal after rectification at the rated load has a low potential at the detection unit 11, so that the transistor Q8 is turned on and no delayed pulse signal is generated. .

Further, in the AC input voltage 200V system, the potential f of the detection unit 11 is switched to the same potential as the conventional one, and a delay pulse signal is generated by the delay circuit 12 near the top A of the AC input voltage waveform, and the PFC gate signal d Perform correction to narrow the pulse width. Here, even when the load of the DC-DC converter circuit 3 is 1.5 times higher than that of the conventional load, the input current in the 200V system is ½ that of the input voltage that is twice as high as that in the 100V system. The switching current flowing through L1 does not lead to DC superposition.
FIG. 8 shows the output power versus efficiency characteristics of the AC-DC converter using the first embodiment or the conventional power factor correction circuit.

  FIG. 9 is a detailed diagram of a PFC control circuit diagram in the power factor correction circuit according to the second embodiment. In the first embodiment, the voltage of the detection unit 11 is input to the PFC control circuit by the diode D3. However, in the second embodiment, the diode D3 is configured by the transistor Q11. By replacing the transistor Q11, the voltage of the detection unit 11 is detected with higher sensitivity.

  As described above, according to the first and second embodiments, the switching element Q1 can be driven by the PFC gate signal whose on-pulse width is changed according to the AC input voltage, so that the force can be adjusted in accordance with the energy saving regulations (EPA, ErP, etc.). It is possible to provide a simple and inexpensive power factor correction circuit that can improve the rate.

  Further, the boosting amount of the power factor and the PFC output voltage can be controlled, and a simple, inexpensive and highly efficient active filter can be configured without using a control IC dedicated to the power factor correction circuit.

  In addition, since the pulse width of the delayed pulse signal changes according to the rectified voltage obtained by rectifying the AC input voltage, there is a jitter effect during the period when the switching frequency is on and the oscillation frequency is fixed, and generation of noise such as EMI can be suppressed . In particular, in the case where the input voltage is a 100V system, when the direct current is superimposed near the top A of the alternating current input voltage waveform, the timing when the switching element Q1 of the power factor correction circuit based on the delayed pulse signal is turned on is the DC-DC converter circuit 3 Therefore, the generation of EMI noise by the switching elements can be dispersed and suppressed.

1 is a circuit diagram illustrating an AC-DC converter including a power factor correction circuit according to Embodiment 1. FIG. It is a figure which shows the relationship between the alternating current input voltage of Example 1, and a PFC output voltage. It is a figure which shows the divided voltage signal after rectification | rectification which rectified the alternating current input voltage. It is a figure which shows the divided voltage signal after the rectification | rectification which rectified the alternating current input voltage in Example 1 and alternating current input voltage AC100V type | system | group of a prior art. 6 is a timing chart of each signal in the delay circuit in the vicinity of the top of the divided voltage signal after rectification at the rated load of the first embodiment. 6 is a timing chart of each signal in the delay circuit in the vicinity of the bottom of the divided voltage signal after rectification at the rated load of the first embodiment. It is a figure which shows the waveform of the rectified partial pressure signal f and the drain current PFCId which flows into the switching element Q1 in the alternating current input voltage AC100V type | system | group of alternating current input voltage of Example 1. FIG. It is an output power versus efficiency characteristic diagram in the AC input voltage AC100V system of the AC-DC converter using the first embodiment or the conventional power factor correction circuit. FIG. 10 is a detailed diagram of a PFC control circuit diagram in the power factor correction circuit according to the second embodiment. It is a circuit diagram which shows the AC-DC converter containing the conventional power factor improvement circuit. It is a figure which shows the divided voltage signal after rectification | rectification which rectified the alternating current input voltage of the prior art. It is a timing chart of each signal in the delay circuit in the vicinity of the top of the divided voltage signal after rectification at the rated load of the prior art. It is a timing chart of each signal in the delay circuit near the bottom of the divided voltage signal after rectification at the rated load of the prior art. It is the divided voltage signal f after the rectification of the alternating current input voltage of the prior art and the current waveform flowing through the switching element Q1. It is a figure which shows the relationship between the alternating current input voltage and PFC output voltage of a prior art. It is a figure which shows the waveform of each signal of the power factor improvement circuit at the time of the light load of a prior art. In a prior art, it is a figure which shows an input current waveform at the time of increasing load electric power 1.5 times.

Vac AC power supply DB Rectifier T1 Transformer P1 Primary winding S1 Secondary winding P2 Auxiliary winding L1 Boosting reactors D1-D5 Diodes Q1, Q2 Switching elements Q3-Q11 Transistors C2, C12 Smoothing capacitors C1, C3, C4 Capacitors R1- R19 Resistor PC1 Photocoupler 2, 2a, 2b Power factor correction circuit 3 DC-DC converter circuit 10, 10a, 10b PFC control circuit 11, 11a Detection unit 12 Delay circuit 13, 13a AC input overvoltage correction circuit 20 DD control circuit

Claims (6)

The rectified voltage obtained by rectifying the AC input voltage from the AC power source is boosted by turning on / off the switching element, and the power factor is improved to output the boosted output voltage to the DC-DC converter circuit driven by the first pulse signal. A power factor correction circuit,
When the first pulse signal having a pulse width corresponding to the output voltage of the DC-DC converter circuit is input and an ON pulse of the first pulse signal is generated, a delayed pulse signal having a pulse width corresponding to the rectified voltage is generated. A delay circuit that generates and generates a second pulse signal by combining the first pulse signal and the delayed pulse signal from the delay circuit;
A switch driving circuit for driving the switching element by the second pulse signal generated by the delay circuit;
The delay circuit includes a correction circuit that narrows the pulse width of the delayed pulse signal as the rectified voltage decreases when the boosted output voltage is smaller than a predetermined first voltage;
The delay circuit increases the pulse width of the delay pulse signal of the correction circuit when the boosted output voltage exceeds a predetermined second voltage set higher than a predetermined first voltage. A power factor correction circuit comprising a correction switching circuit for changing to a narrower pulse width.   2. The power factor correction circuit according to claim 1, wherein the delay circuit makes the second pulse signal have a pulse width narrower than a pulse width of the first pulse signal by a pulse width of the delay pulse signal.   The delay circuit widens the pulse width of the delayed pulse signal as the rectified voltage increases, and makes the second pulse signal a pulse width narrower than the pulse width of the first pulse signal. The power factor correction circuit according to claim 2.   The delay circuit narrows the pulse width of the delayed pulse signal as the rectified voltage decreases, and sets the pulse width of the delayed pulse signal to zero when the rectified voltage reaches a bottom region. The power factor correction circuit according to any one of claims 1 to 3.   The delay circuit sets the second pulse signal to a pulse width narrower than the pulse width of the first pulse signal as the load of the DC-DC converter circuit becomes lighter, and the load of the DC-DC converter circuit is a predetermined load. 5. The power factor correction circuit according to claim 1, wherein the pulse width of the second pulse signal is set to zero when the power is equal to or lower than electric power.   The power factor correction circuit includes a boosting reactor, and when the boosted output voltage is smaller than a predetermined first voltage, the switching current flowing through the boosting reactor is DC superimposed as the rectified voltage increases. The power factor correction circuit according to claim 1, wherein the power factor correction circuit is set to

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