JP5487777B2 - Fault detection circuit, fault detection method, and semiconductor integrated circuit - Google Patents

Description

  The embodiments referred to in this application relate to a failure detection circuit, a failure detection method, and a semiconductor integrated circuit.

  2. Description of the Related Art In recent years, attention has been focused on semiconductor integrated circuits for various electronic devices, for example, those having a plurality of power domains (Power Domain: PD) in order to reduce power consumption.

  When designing such a semiconductor integrated circuit having a plurality of PDs, for example, an isolator is inserted to suppress indefinite propagation due to the state of the power supply between the PDs.

  The isolators are inserted into, for example, data lines and scan chains, the data line isolators are controlled by user logic in the power management unit, and the scan chain isolators are controlled from the test mode.

  Conventionally, various types of semiconductor integrated circuits in which isolators are inserted between different power domains and fault detection circuits for detecting faults in a scan chain in which a plurality of flip-flops are connected in series are known.

JP 2004-248143 A JP 58-186852 A JP-A-4-30227

  As described above, a semiconductor integrated circuit having a plurality of PDs has been proposed in which, for example, an isolator is inserted into a data line and a scan chain, and the isolator is controlled from a test mode.

  However, a semiconductor integrated circuit in which such an isolator is inserted in a data line and a scan chain may not be able to detect all failures.

  The purpose of this application is to provide a failure detection circuit, a failure detection method, and a semiconductor integrated circuit capable of reliably detecting an isolator failure.

According to the first embodiment, the first power domain and the second power domain are connected by the data line and the scan chain via the isolator, and the isolator includes the first circuit connected to the scan chain; A second circuit connected to the data line, and the logic of the second control signal supplied from the power management unit controlled by the first control signal to the first circuit is inverted according to the third control signal Thus, it is possible to detect a stuck-at fault having the same logic as the logic of the second control signal at the input of the first circuit to which the second control signal is supplied, and the power management unit to the second circuit By supplying the output of the logic circuit whose output value is not fixed by the first control signal and the third control signal, To be detected by the automatic test pattern generation a disabled fault detection circuit is provided.

According to the second embodiment, the first power domain and the second power domain are connected by the data line and the scan chain via the isolator, and the isolator includes the first circuit connected to the scan chain; A second circuit connected to the data line, and the logic of the second control signal supplied from the power management unit controlled by the first control signal to the first circuit is inverted according to the third control signal Thus, it is possible to detect a stuck-at fault having the same logic as the logic of the second control signal at the input of the first circuit to which the second control signal is supplied, and the power management unit to the second circuit By supplying the output of the logic circuit whose output value is not fixed by the first control signal and the third control signal, To be detected by the automatic test pattern generation a disabled fault detection method is provided.

According to the third embodiment, the first power domain, the first power domain, the second power domain connected by the data line and the scan chain via the isolator, and the power management unit controlled by the first control signal The isolator has a first circuit connected to the scan chain and a second circuit connected to the data line, and the first circuit is connected to the first line from the power management unit. By inverting the logic of the second control signal supplied to the circuit according to the third control signal, the same logic as the second control signal at the input of the first circuit to which the second control signal is supplied A logic stuck-at fault can be detected, and the first control signal and the previous signal are transferred from the power management unit to the second circuit. By output value by the third control signal to provide an output of the logic circuit which is not fixed, and can be detected by the automatic test pattern generation for failure of the second circuit, the semiconductor integrated circuit is provided.

  As a result, a stuck-at fault having the same logic as that of the second control signal at the input of the first circuit to which the second control signal is supplied can be detected.

  The disclosed failure detection circuit, failure detection method, and semiconductor integrated circuit have an effect that the failure detection of the isolator can be reliably performed.

It is a block diagram which shows an example of a semiconductor integrated circuit. FIG. 2 is a diagram for explaining a test operation of the semiconductor integrated circuit of FIG. 1. FIG. 2 is a circuit diagram showing an example of an AND type isolator in the semiconductor integrated circuit of FIG. 1. It is a figure for demonstrating operation | movement of the transistor in the AND type isolator of FIG. 1 is a block diagram illustrating a semiconductor integrated circuit according to a first embodiment. It is a block diagram which shows the semiconductor integrated circuit of 2nd Example. It is a block diagram which shows the semiconductor integrated circuit of 3rd Example. It is a block diagram which shows the semiconductor integrated circuit of 4th Example. It is a block diagram which shows the semiconductor integrated circuit of 5th Example. It is a block diagram which shows the semiconductor integrated circuit of 6th Example.

  First, before describing the embodiment in detail, a test operation and its problems in an example of a semiconductor integrated circuit will be described with reference to FIGS.

  FIG. 1 is a block diagram showing an example of a semiconductor integrated circuit, and shows a semiconductor integrated circuit having two PDs (power domains) and PMUs (Power Management Units) with an isolator inserted. ing.

  In FIG. 1, reference numeral 101 denotes a first PD, 102 denotes a second PD, and 103 denotes a PMU. Reference sign Sin indicates an input scan signal, and Sout indicates an output scan signal.

  The first PD 101 includes a first logic circuit 111 and a first flip-flop (FF) 112, and the second PD 102 includes an isolator 120, a second logic circuit 121, and a second FF 122. Here, the logic circuits 111 and 121 are user logic circuits used by the user.

  The PMU 103 includes third and fourth logic circuits 131 and 132 and an OR gate 133. Here, the output signal of the third logic circuit 131 and the test mode signal TMS are supplied to the OR gate 133.

  As shown in FIG. 1, the isolator 120 has a second AND gate 120b inserted into the data line and a first AND gate 120a inserted into the scan chain.

  The output signal (OUT) of the first logic circuit 111 and the output signal of the fourth logic circuit 132 are supplied to the second AND gate 120b.

  Further, the Q output signal of the first FF 112 and the output signal SS of the OR gate 133 are supplied to the first AND gate 120a. The isolator 120 is controlled by a test mode signal TMS.

  The isolator 120 (and gates 120a and 120b) is inserted on each wiring in order to suppress indefinite propagation from the first PD 101 to the second PD 102 when the first PD 101 is off and the second PD 102 is on.

  FIG. 2 is a diagram for explaining the test operation of the semiconductor integrated circuit of FIG. 1, and shows the first AND gate 120a of the isolator 120 in FIG.

  The symbol sa indicates a stuck-at fault, sa-0 represents a stuck-at fault where the detection target (line) is “0”, and sa-1 represents a stuck-at fault where the detection target is “1”.

  By the way, when testing a semiconductor integrated circuit in which the isolator 120 is inserted, it is necessary to detect an input / output failure of the isolator 120.

  Here, in the isolator 120, the failure of the second AND gate 120b on the data line can be detected by ATPG (Automatic Test Pattern Generation).

However, in the isolator 120, the failure of the first AND gate 120a inserted in the scan chain cannot detect the failure sa-1 of the input B. This is due to the following reason described with reference to Table 1.

  Table 1 shows the state of the inputs A and B of the first AND gate 120a of the isolator 120 in the test mode.

  As shown in Table 1, since the signal SS from the PMU 103 to the input B of the first AND gate 120a of the isolator 120 is controlled by the test mode signal TMS, it is always fixed to “1” during the shift and capture tests. The

  That is, when the test mode signal TMS is “1”, the output signal SS of the OR gate 133 becomes “1” regardless of the level of the output signal of the third logic circuit 131, so that the input B of the first AND gate 120 a The fault sa-1 cannot be detected.

  Here, when the input B of the first AND gate 120a becomes sa-1, there is no influence on the user logic. However, when the first PD 101 is OFF, a signal that reaches the input A of the first AND gate 120a (of the first FF 101). Q output signal) cannot be fixed to “0”.

  FIG. 3 is a circuit diagram showing an example of an AND type isolator in the semiconductor integrated circuit of FIG. 1, and shows a circuit example of the AND gate 120 b in the isolator 120.

  As shown in FIG. 3, the first AND gate 120 a includes pMOS transistors 121 to 123 and nMOS transistors 124 to 126.

  In the first AND gate 120a (AND type isolator) shown in FIG. 3, when the input B is degenerated to "1" (sa-1), the nMOS transistor 125 is always turned on, and the level of the output Z is the value of the input A. Depends on.

  By the way, a MOS transistor (FET) has a threshold voltage for switching on and off, and the threshold voltage is different between an nMOS transistor and a pMOS transistor.

  FIG. 4 is a diagram for explaining the operation of the transistor in the AND type isolator (AND gate 120b) of FIG. Here, the reference symbol nVth indicates the threshold voltage of the nMOS transistor, and pVth indicates the threshold voltage of the pMOS transistor.

  As shown in FIG. 4, when the gate voltage Vg applied to the gate of each transistor is smaller than nVth, only the pMOS transistor is turned on. When the gate voltage Vg is larger than pVth, only the nMOS transistor is turned on. Turn on.

  However, when the gate voltage Vg is larger than nVth and smaller than pVth (nVth <Vg <pVth), both the nMOS transistor and the pMOS transistor are turned on.

  By the way, as described with reference to FIG. 3, for example, when the input B is degenerated to 1 (sa-1), the output Z of the isolator (first AND gate 120a) depends on the value of the input A.

  At this time, when the first PD 101 is off and the input A has an indefinite value, and the voltage of the input A (the gate voltage Vg of the transistors 121 and 124) is nVth <Vg <pVth, the pMOS transistor 121 and the nMOS transistor 124 Both are turned on.

  As a result, a current (through current) flows from the high potential power supply line Vdd to the low potential power supply line Vss through the transistors 121, 124, and 125 in the on state.

  That is, when sa-1 is generated on the path from the PMU 103 to the isolator 120 (first AND gate 120a), and the first PD 101 is turned off and the second PD 102 is turned on, a through current is generated in the isolator 120, resulting in power consumption. Will increase.

  The above-described problem is not limited to the case where the isolator 120 has an AND gate (first AND gate 120a), but detection of a stuck-at fault having the same logic as the control signal SS from the PMU 103 to the circuit inserted in the scan chain. Becomes impossible.

  Hereinafter, embodiments of a failure detection circuit, a failure detection method, and a semiconductor integrated circuit will be described in detail with reference to the accompanying drawings.

  FIG. 5 is a block diagram showing the semiconductor integrated circuit of the first embodiment, and shows a semiconductor integrated circuit having two power domains (PD) and a power management unit (PMU) in which an isolator is inserted. Yes.

  In FIG. 5, reference numeral 1 is the first PD, 2 is the second PD, and 3 is the PMU. The first PD 1 includes a first logic circuit 11 and a first flip-flop (FF) 12, and the second PD 2 includes an isolator 20, a second logic circuit 21, and a second FF 22.

  In FIG. 5 and FIGS. 6 to 10 to be described later, reference numeral Sin indicates an input scan signal, and Sout indicates an output scan signal. The logic circuits 11 and 21 are user logic circuits used by the user.

  The PMU 3 includes third and fourth logic circuits 31 and 32, an OR gate 33, and an AND gate (failure detection circuit) 34.

  Here, the output signal of the third logic circuit 31 and the test mode signal TMS are supplied to the OR gate 33, and the output signal of the OR gate 33 and the isolator enable signal IE are supplied to the AND gate 34.

  As shown in FIG. 5, the isolator 20 has a second AND gate 20b inserted into the data line and a first AND gate 20a inserted into the scan chain.

  The output signal (OUT) of the first logic circuit 11 and the output signal of the fourth logic circuit 32 are supplied to the second AND gate 20b.

  Further, the Q output signal of the first FF 12 and the output signal SS1 of the AND gate 34 are supplied to the first AND gate 20a. The first AND gate (isolator) 20a is controlled by user logic in the power management unit, and the second AND gate 20b (isolator) 20b is controlled by a test mode signal TMS.

  The isolator 20 (and gates 20a and 20b) is inserted on each wiring in order to suppress indefinite propagation from the first PD1 to the second PD2 when the first PD1 is off and the second PD2 is on.

  As described above, in the semiconductor integrated circuit of the first embodiment, the output signal SS1 of the AND gate 34 is supplied to the input B of the first AND gate 20a, and the output signal SS of the OR gate 33 is supplied to the AND gate 34. The isolator enable signal IE is supplied.

  Accordingly, for example, even when the test mode signal TMS is “1”, the isolator enable signal IE is set to “0”, thereby setting the output signal SS1 of the AND gate 34 to “0” and the first AND gate 20a. It becomes possible to detect the failure sa-1 of the input B.

  As described with reference to FIG. 2, other failures of the inputs A and B of the first AND gate 20a, that is, the failures sa-0 and sa-1 of the input A and the failure sa- of the input B 0 can also be detected.

  Further, as described above, the failure of the second AND gate 20b on the data line can be detected by the ATPG.

  FIG. 6 is a block diagram showing a semiconductor integrated circuit according to the second embodiment. Here, reference numeral 2a indicates the second PD, and 3a indicates the PMU.

  In the second PD 2a in the semiconductor integrated circuit of the second embodiment, an isolator 20 ′ having two OR gates 20c and 20d is used instead of the isolator 20 having two AND gates 20a and 20b in the PD 2 of the first embodiment of FIG. Is provided.

  Here, when the one having the first and second OR gates 20c and 20d is used as the isolator without providing the AND gate 34 to which the isolator enable signal IE is supplied, the fault Sa-0 at the input B of the first OR gate 20c. Becomes undetectable.

  Therefore, in the PMU 3a of the second embodiment, the output signal SS1 of the AND gate 34 supplied with the isolator enable signal IE and the output signal SS of the OR gate 33 is inverted by the inverter 35, and the signal SS2 is input to the first OR gate 20c. Supply to B.

  For example, even when the test mode signal TMS is “1”, the output signal SS1 of the AND gate (failure detection circuit) 34 is set to “0” by setting the isolator enable signal IE to “0”. The output signal SS2 is set to “1”. As a result, it is possible to detect the failure sa-0 at the input B of the first OR gate 20c.

  It is possible to detect other failures of the inputs A and B of the first OR gate 20c, that is, the failures sa-0 and sa-1 of the input A, and the failure sa-1 of the input B, and the data line The failure of the upper second OR gate 20d can also be detected by ATPG.

  FIG. 7 is a block diagram showing a semiconductor integrated circuit according to the third embodiment. Here, reference numeral 3b indicates a PMU, and 36 indicates a failure detection circuit.

  As apparent from a comparison between FIG. 7 and FIG. 5 of the first embodiment, the failure detection circuit 36 of the PMU 3b in the third embodiment has an AND gate 361 and an OR gate 362.

  As described above, a circuit (fault detection circuit) inserted to detect an isolator failure requires one terminal for receiving at least one control signal IE. In the third embodiment, two terminals are required. Two terminals for receiving control signals IE1 and IE2 are provided.

  That is, the output signal SS of the OR gate 33 and the first isolator enable signal IE1 are supplied to the AND gate 361, and the output signal of the AND gate 361 and the second isolator enable signal IE2 are supplied to the OR gate 362.

  The output signal SS3 of the OR gate 362 is supplied to the input B of the first AND gate 20a of the isolator 20.

  Thereby, for example, even when the test mode signal TMS is “1”, the output signal SS3 of the OR gate 362 is set to “0” by setting both the first and second isolator enable signals IE1 and IE2 to “0”. To do.

  As a result, the failure sa-1 at the input B of the first AND gate 20a in the isolator 20 can be detected as in the semiconductor integrated circuit of the first embodiment.

Specifically, the relationship shown in Table 2 below is established between the first and second isolator enable signals IE1 and IE2 and the failure detection of the input B of the first AND gate 20a. In Table 2, “X” indicates that either “0” or “1” may be used.

  As shown in Table 2, at the normal time, the two isolator enable signals IE1 and IE2 are set to “1” and “0”. As a result, the control signal SS3 supplied from the PMU 3b to the input B of the first AND gate 20a inserted in the scan chain in the isolator 20 becomes a signal having the same logic as the output signal SS of the OR gate 33.

  When detecting the failure sa-0 at the input B of the first AND gate 20a, the second isolator enable signal IE2 is set to "1". As a result, the control signal SS3, which is the output of the OR gate 362, becomes "1", and the failure sa-0 at the input B is detected.

  Then, when detecting the failure sa-1 at the input B of the first AND gate 20a, the first and second isolator enable signals IE1 and IE2 are set to "0" and "0". As a result, the control signal SS3 becomes “0”, and the failure sa-1 at the input B can be detected.

  Note that the fault sa-0 at the input B of the first OR gate 20c of the isolator 20 'in the second embodiment described with reference to FIG. 6 can also be detected by setting the two isolator enable signals IE1 and IE2.

  As described above, the combination of the first and second isolator enable signals IE1 and IE2 causes the failure of sa-1 and sa-0 in the path reaching the isolator inserted in the scan chain from the PMU without depending on the type of the isolator. Can be detected.

  FIG. 8 is a block diagram showing a semiconductor integrated circuit according to the fourth embodiment. 8, reference numerals 41 to 43 are PDs, 420 and 430 are isolators, 411, 421, 423, and 431 are user logic circuits, and 412 and 422 and 432 are FFs.

  As described above, the semiconductor integrated circuit according to the fourth embodiment includes the three PDs 41 to 43. However, each embodiment can be applied even if the semiconductor integrated circuit includes a larger number of PDs.

  In each embodiment, for example, a plurality of power domain sets of a first power domain set in which PD41 is the first PD and PD42 is the second PD, and a second power domain set in which PD42 is the first PD and PD43 is the second PD (FIG. 8). The present invention is applicable to a semiconductor integrated circuit having two sets.

  In the fourth embodiment shown in FIG. 8, isolators 420 and 430 are inserted into the data lines and scan chains between the PDs, respectively, and logic gates with different types of isolators are applied.

  That is, the isolator 420 is inserted between the PD 41 and the PD 42, and the isolator 430 is inserted between the PD 42 and the PD 43.

  Here, the isolator 420 includes a first AND gate 420a inserted into the scan chain and a second AND gate 420b inserted into the data line. The isolator 430 includes a first OR gate 430a inserted into the scan chain and a second OR gate 430b inserted into the data line.

  The output signal SS1 of the AND gate 34 described with reference to FIG. 5 is supplied to the input B of the AND gate 420a, and the inverter 35 described with reference to FIG. 6 is supplied to the input B of the OR gate 430a. Output signal SS2 is supplied.

  As a result, the failure sa-1 at the input B of the AND gate 420a and the failure sa-0 at the input B of the OR gate 430a can be detected.

  As described above, for various types of isolators in a semiconductor integrated circuit having a plurality of PDs, all stuck-at faults can be detected even at an input for receiving a control signal from a PMU in a circuit inserted in each scan chain. It will be possible.

FIG. 9 is a block diagram showing a semiconductor integrated circuit according to the fifth embodiment.
As is clear from the comparison between FIG. 9 and FIG. 6 described above, the PMU 3d in the fifth embodiment is a modification of the PMU 3a in the second embodiment shown in FIG. 6, and the input B of the first OR gate 20c is A similar control signal SS2 is supplied.

  That is, the PMU 3d in the fifth embodiment is provided with an OR gate 37 and an inverter 38 instead of the AND gate 34 and the inverter 35 in the PMU 3a of FIG.

  In the PMU 3a in FIG. 6, even when the test mode signal TMS is “1”, the input B of the first OR gate 20c of the isolator 20 ′ is set to “1” by setting the isolator enable signal IE to “0”. The fault sa-0 of the input B was made detectable.

  On the other hand, in the PMU 3d of FIG. 9, even when the test mode signal TMS is “1”, the input B of the first OR gate 20c of the isolator 20 ′ is set to “1” by setting the isolator enable signal IE to “1”. Thus, the failure sa-0 of the input B can be detected.

  Thus, the PMU (power management unit) that controls the isolator can be variously modified.

FIG. 10 is a block diagram showing a semiconductor integrated circuit according to the sixth embodiment.
As shown in FIG. 10, in the sixth embodiment, an isolator 20 ″ is inserted into a scan chain, an OR gate 20e having an input B as an inverting input, and an AND gate (second AND) inserted in a data line. Gate) 20b.

  Here, the PMU of the sixth embodiment is the same as the PMU 3 of the first embodiment described with reference to FIG. 5, and the fault sa at the inverting input B of the OR gate 20e is controlled by the control signal SS from the PMU 3. -1 can be detected.

  As described above, the circuit of the isolator inserted into the scan chain and the circuit configuration of the PMU corresponding thereto can be variously modified.

  As described above, the failure detection circuit of each embodiment receives at least one isolator enable signal, and at the input of the circuit inserted in the scan chain of the isolator, the same logical degeneration as the signal supplied to the input from the PMU Make the fault detectable. Thereby, the failure detection of an isolator can be performed reliably.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
When the first power domain and the second power domain are connected by a data line and a scan chain, and the first power domain is off and the second power domain is on, indefiniteness propagates to the second power domain. A fault detection circuit for an isolator having a first circuit inserted in the scan chain,
The second control signal is supplied by inverting the logic of the second control signal supplied to the first circuit from the power management unit controlled by the first control signal according to the third control signal. A fault detection circuit, wherein a stuck-at fault having the same logic as that of the second control signal at the input of the first circuit can be detected.

(Appendix 2)
In the failure detection circuit according to attachment 1, the failure detection circuit includes:
A failure detection circuit comprising: a first logic gate that receives the second control signal and the third control signal and changes a logic of the second control signal according to a logic of the third control signal.

(Appendix 3)
In the failure detection circuit according to attachment 2,
A failure detection circuit comprising: a second logic gate that receives an output signal of the first logic gate and a fourth control signal and changes a logic of the output signal of the first logic gate according to the fourth control signal.

(Appendix 4)
In the failure detection circuit according to any one of appendices 1 to 3,
The isolator further includes a second circuit inserted in the data line between the first power domain and the second power domain.

(Appendix 5)
In the failure detection circuit according to any one of appendices 1 to 4,
The failure detection circuit, wherein the first control signal is a test mode signal.

(Appendix 6)
When the first power domain and the second power domain are connected by a data line and a scan chain, and the first power domain is off and the second power domain is on, indefiniteness propagates to the second power domain. A method for detecting a failure of an isolator having a first circuit inserted in the scan chain,
The logic of the second control signal supplied to the first circuit from the power management unit controlled by the first control signal is inverted according to the third control signal, whereby the second control signal is supplied. A fault detection method comprising detecting a stuck-at fault having the same logic as that of the second control signal at the input of one circuit.

(Appendix 7)
A first power domain;
A second power domain connected to the first power domain by a data line and a scan chain;
An isolator having a first circuit inserted in the scan chain between the first power domain and the second power domain;
A power management unit that receives a first control signal and supplies the second control signal to the first circuit to control the first circuit, and a semiconductor integrated circuit comprising:
The semiconductor integrated circuit according to claim 1, wherein the power management unit includes a failure detection circuit that enables detection of a stuck-at failure at an input of the first circuit to which the second control signal is supplied.

(Appendix 8)
In the semiconductor integrated circuit according to appendix 7,
The failure detection circuit receives a third control signal, and at the input of the first circuit to which the second control signal is supplied, the failure detection circuit can detect a stuck-at failure having the same logic as the second control signal. 2. A semiconductor integrated circuit characterized by inverting the logic of a control signal.

(Appendix 9)
In the semiconductor integrated circuit according to appendix 7 or 8,
The semiconductor integrated circuit according to claim 1, wherein the first control signal is a test mode signal.

(Appendix 10)
In the semiconductor integrated circuit according to any one of appendices 7 to 9,
The semiconductor integrated circuit according to claim 1, wherein the first circuit includes an AND gate.

(Appendix 11)
In the semiconductor integrated circuit according to any one of appendices 7 to 9,
The semiconductor integrated circuit according to claim 1, wherein the first circuit includes an OR gate.

(Appendix 12)
In the semiconductor integrated circuit according to any one of appendices 7 to 9,
The isolator further includes a second circuit inserted in the data line between the first power domain and the second power domain.

(Appendix 13)
The semiconductor integrated circuit according to appendix 12, wherein each of the first circuit and the second circuit has an AND gate.

(Appendix 14)
The semiconductor integrated circuit according to appendix 12, wherein each of the first circuit and the second circuit has an OR gate.

(Appendix 15)
15. The semiconductor integrated circuit according to any one of appendices 7 to 14, wherein the semiconductor integrated circuit has a plurality of sets of the first power domain and the second power domain.

1,2,41-43,101,102 Power domain (PD)
3, 3a, 3b, 3c, 3d, 103 Power management unit (PMU)
3 RS flip-flop 20, 20 ', 20 ", 420, 430, 120 Isolator 34, 36, 37 Fault detection circuit

Claims (4)

The first power domain and the second power domain are connected by a data line and a scan chain via an isolator ,
The isolator includes a first circuit connected to the scan chain and a second circuit connected to the data line,
The second control signal is supplied by inverting the logic of the second control signal supplied to the first circuit from the power management unit controlled by the first control signal according to the third control signal. A stuck-at fault having the same logic as that of the second control signal at the input of the first circuit can be detected ;
By supplying the output of the logic circuit whose output value is not fixed by the first control signal and the third control signal from the power management unit to the second circuit, the failure of the second circuit is detected by automatic test pattern generation. Detectable,
A failure detection circuit. The failure detection circuit is
A first logic gate that receives the second control signal and the third control signal and changes a logic of the second control signal according to a logic of the third control signal ;
The fault detection circuit according to claim 1 . The first power domain and the second power domain are connected by a data line and a scan chain via an isolator ,
The isolator includes a first circuit connected to the scan chain and a second circuit connected to the data line,
The logic of the second control signal that will be supplied to the first circuit from the power management unit controlled by the first control signal, by inverting accordance with a third control signal, the said second control signal is supplied A stuck-at fault having the same logic as that of the second control signal at the input of the first circuit can be detected ;
By supplying the output of the logic circuit whose output value is not fixed by the first control signal and the third control signal from the power management unit to the second circuit, the failure of the second circuit is detected by automatic test pattern generation. Detectable,
The fault detection method characterized by the above-mentioned. A first power domain;
A first power domain and a second power domain connected by a data line and a scan chain via an isolator ;
A power management unit controlled by the first control signal, a semiconductor integrated circuit having,
The isolator includes a first circuit connected to the scan chain and a second circuit connected to the data line,
The logic of the second control signal supplied from the power management unit to the first circuit is inverted according to the third control signal, so that the input at the first circuit to which the second control signal is supplied A stuck-at fault with the same logic as that of the second control signal can be detected,
By supplying the output of the logic circuit whose output value is not fixed by the first control signal and the third control signal from the power management unit to the second circuit, the failure of the second circuit is detected by automatic test pattern generation. Detectable,
A semiconductor integrated circuit.

Images