JP5478916B2 - Method for manufacturing SOI substrate - Google Patents

Description

  The present invention relates to a method for manufacturing an SOI substrate (Silicon on Insulator). Further, the present invention relates to a method for manufacturing a semiconductor device using an SOI substrate.

  A semiconductor substrate (SOI substrate) called SOI in which a thin single crystal semiconductor layer is provided on an insulating layer has been developed instead of a silicon wafer manufactured by thinly cutting an ingot of a single crystal semiconductor. The integrated circuit provided over the SOI substrate can reduce the parasitic capacitance of the transistor as compared with the case where the integrated circuit is formed over a silicon wafer, and thus is said to be effective in improving operation speed and reducing power consumption. Therefore, application to a high-performance semiconductor device such as a microprocessor is being studied.

  One method for manufacturing an SOI substrate is a method disclosed in Patent Document 1 (sometimes referred to as a hydrogen ion implantation separation method). In the method disclosed in Patent Document 1, hydrogen ions are implanted into a first silicon wafer to form a microbubble layer at a predetermined depth from the surface, and the first silicon wafer is placed on the second silicon wafer. This is a technique for forming a thin silicon layer (SOI layer) on a second silicon wafer by bonding and cleaving with a microbubble layer as a cleavage plane. According to this technique, in addition to performing a heat treatment for separating the SOI layer, the silicon oxide film is removed after the silicon oxide film is formed on the SOI layer by a heat treatment in an oxidizing atmosphere, and then the temperature of 1000 to 1300 ° C. is removed. It is said that it is necessary to increase the bonding strength by performing a heat treatment in a reducing atmosphere.

  On the other hand, a semiconductor device in which a single crystal silicon layer is provided over an insulating substrate such as heat resistant glass is known (see Patent Document 2). This semiconductor device has a configuration in which the entire surface of crystallized glass having a strain point of 750 ° C. or higher is protected with an insulating silicon film, and a single crystal silicon layer obtained by a hydrogen ion implantation separation method is fixed on the insulating silicon film. Have.

Japanese Patent Application Laid-Open No. 2000-124092 JP 11-163363 A

  Two substrates are bonded to each other by the method disclosed in Patent Document 1, and a microbubble layer or a modified layer formed on one substrate (also referred to as an embrittlement layer. Hereinafter, referred to as an embrittlement layer in this specification). When an SOI substrate is manufactured by separating the substrate starting from (), the crystallinity in the embrittled layer is extremely low. Therefore, it is necessary to remove these layers by chemical mechanical polishing (Chemical Mechanical Polishing, hereinafter referred to as CMP) or dry etching.

  However, when a large-area substrate is used, the amount of polishing or etching varies within the substrate surface in CMP or dry etching. In CMP, polishing is performed while rotating a polishing cloth relative to a substrate while supplying a liquid containing a polishing liquid, and the amount of movement of the polishing cloth increases as the distance from the rotation center increases. For this reason, the polishing amount tends to be smaller as it is closer to the center of the substrate to be processed, and the polishing amount tends to be larger toward the periphery. In dry etching, the distribution of the etching rate in the substrate surface varies greatly depending on the configuration of the apparatus (chamber shape, etc.) or etching conditions (gas type, gas flow ratio, pressure, power, etc.). In general, in a dry etching apparatus compatible with a large area substrate, it is difficult to uniformly supply power, and the difference in distance between the substrate to be processed and the exhaust hole becomes large, so that in-plane uniformity of the plasma distribution can be maintained. Have difficulty. Therefore, the closer to the center of the substrate to be processed, the larger the etching amount, and when the substrates with the fragile layer formed at the same depth are bonded together, the thickness of the SOI layer after CMP or dry etching processing is as follows: Variations will occur within the substrate plane.

  In view of the above, an object of one embodiment of the present invention is to provide a method for manufacturing an SOI substrate with excellent uniformity in thickness of an SOI layer.

  According to one embodiment of the present invention, the depths of the embrittlement layers formed on the plurality of semiconductor substrates from the surface of the semiconductor substrate are different from each other, and the semiconductor substrates having different embrittlement layer depths are etched or polished. Deploy. Specifically, a portion where the embrittlement layer is formed at a deep position is disposed in a portion where the etching amount or the polishing amount is large, and a brittle layer is formed at a shallow position in a portion where the etching amount or the polishing amount is small. An SOI substrate with high uniformity of the SOI layer in the substrate surface is manufactured by arranging what is to be processed and performing CMP or etching. What is necessary is just to control the depth from the surface of a semiconductor substrate to an embrittlement layer with the acceleration voltage at the time of forming an embrittlement layer by dope, for example.

  Even when a large-area substrate is used, an SOI substrate having an SOI layer with a uniform thickness in the substrate surface can be manufactured.

8A and 8B illustrate an example of a method for manufacturing an SOI substrate. 8A and 8B illustrate an example of a method for manufacturing an SOI substrate. 8A and 8B illustrate an example of a method for manufacturing an SOI substrate. 8A and 8B illustrate an example of a method for manufacturing an SOI substrate. 8A and 8B illustrate an example of a method for manufacturing an SOI substrate. 8A and 8B illustrate an example of a method for manufacturing an SOI substrate. 10A and 10B illustrate an example of a method for manufacturing a semiconductor device using an SOI substrate. 10A and 10B illustrate an example of a method for manufacturing a semiconductor device using an SOI substrate. FIG. 11 illustrates an example of a semiconductor device using an SOI substrate. FIG. 11 illustrates an example of a semiconductor device using an SOI substrate. FIG. 11 illustrates an example of a display device using an SOI substrate. FIG. 11 illustrates an example of a display device using an SOI substrate. It is a figure which shows the electronic device using an SOI substrate. It is a figure which shows the electronic device using an SOI substrate.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in describing the structure of the present invention with reference to drawings, the same portions are denoted by the same reference numerals in different drawings. Moreover, when referring to the same thing, a hatch pattern is made the same and there is a case where a reference numeral is not particularly attached. For convenience, the insulating film may not be shown in the top view.

(Embodiment 1)
In this embodiment, an example of a method for manufacturing an SOI substrate which is one embodiment of the present invention will be described with reference to drawings. First, a first substrate 100 (also referred to as a base substrate or a base wafer) and a second substrate 200 (also referred to as a bonded substrate or a bond wafer) are prepared.

  The first substrate 100 needs to have at least heat resistance that can withstand the manufacturing process and chemical resistance that does not cause alteration during the manufacturing process. As long as this is the case, the material of the first substrate 100 is not limited to a specific material. For example, a glass substrate, a quartz substrate, a single crystal silicon substrate, a stainless steel substrate, or the like, or a substrate in which an insulating layer is provided over these substrates can be used. Here, a glass substrate is used. This is because a glass substrate having a larger area than other substrates can be easily manufactured and is preferable as the first substrate. Note that when a light-transmitting substrate (a substrate having a light-transmitting property) is used as the first substrate 100, an SOI substrate that can be used for a display device can be manufactured.

  As the second substrate 200, a semiconductor substrate is used. As a typical material used for a semiconductor substrate, silicon or germanium can be given. Alternatively, a compound semiconductor such as gallium arsenide or indium phosphide may be used. A silicon substrate having a diameter of 5 inches (about 120 mm), 8 inches (about 200 mm), or 12 inches (about 300 mm) is typically used. Further, the shape of the silicon substrate is not limited to a circle, and may be a rectangle. The second substrate 200 is not limited to a single crystal semiconductor substrate, and may be a polycrystalline semiconductor substrate. In this embodiment, a single crystal silicon substrate processed into a rectangular shape is used as the second substrate 200.

First, the first bonding layer 110 is formed using an insulating layer over the first substrate 100 (see FIG. 1A-1). The first bonding layer 110 can be formed using silicon oxide, silicon oxynitride, or silicon nitride oxide. In particular, when the first substrate 100 is a glass substrate, it is preferably formed using silicon nitride oxide. When silicon nitride oxide is used for the first bonding layer 110, impurity elements such as sodium and potassium contained in the glass substrate can be prevented from entering the single crystal semiconductor. Alternatively, a silicon oxide layer formed by a CVD method (chemical vapor deposition method) using a silane-based gas such as a silane gas, a disilane gas, a trisilane gas, or an organic silane gas can be used. By forming the layer, a bonding layer having higher surface flatness than other formation methods can be formed. When silane gas is used, it is preferable to include nitrogen dioxide or dinitrogen monoxide in the forming gas. As the organic silane gas, tetraethoxysilane (abbreviation: TEOS, chemical formula: Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (chemical formula: Si (CH ₃ ) ₄ ), trimethylsilane (chemical formula: (CH ₃ ) ₃ SiH ), Tetramethylcyclotetrasiloxane (abbreviation: TMCTS), octamethylcyclotetrasiloxane (abbreviation: OMTS), hexamethyldisilazane (abbreviation: HMDS), triethoxysilane (chemical formula: SiH (OC ₂ H ₅ ) ₃ ) or A silicon-containing compound such as trisdimethylaminosilane (chemical formula: SiH (N (CH ₃ ) ₂ ) ₃ ) can be used.

  Note that the first bonding layer 110 can be formed by a CVD method or a sputtering method. Here, the CVD method includes plasma CVD, thermal CVD, or photo-CVD. Alternatively, an oxide layer formed by oxidizing the substrate with heat may be used. Alternatively, an insulating layer formed by treating the surface of the first substrate 100 with ozone water, hydrogen peroxide water, sulfuric acid / hydrogen peroxide, or the like may be used. Note that the first bonding layer 110 is preferably provided with a thickness of approximately 5 nm to 500 nm.

  Note that the first bonding layer 110 needs to be provided using a material having high surface flatness and hydrophilicity on the surface. Specifically, the average surface roughness (Ra) of the surface of the first bonding layer 110 is 0.5 nm or less, the root mean square roughness (Rms) is 0.6 nm or less, and preferably the average surface roughness is 0.00. It is formed so as to be 3 nm or less and the root mean square roughness is 0.4 nm or less.

  While processing the first substrate 100 as described above, the second substrate 200 is also processed.

  An embrittlement layer 202 is formed on the second substrate 200 at a predetermined depth from the surface. The embrittlement layer 202 is formed by injecting ions accelerated by an electric field to a predetermined depth from the cleaned surface of the second substrate 200 (see FIG. 1A-2). Here, the acceleration voltage and the like are adjusted in consideration of the thickness of a crystalline semiconductor layer (hereinafter referred to as an SOI layer) formed over the first substrate 100. The thickness of the SOI layer is 5 nm to 500 nm, preferably 10 nm to 200 nm. For the formation of the embrittlement layer 202, hydrogen gas, inert gas, or halogen gas is used. Here, helium is preferable as the inert gas, and fluorine is preferable as the halogen. This is because the light element can penetrate deeper into the substrate, so that it is relatively easy to form the embrittlement layer by adjusting the acceleration voltage.

  In the formation of the embrittlement layer 202, ion implantation is performed at a high acceleration voltage, so that the surface of the second substrate 200 may become rough. Therefore, a protective layer 201 is preferably provided in advance on the surface to be ion-implanted. The protective layer 201 may be formed of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like as a single layer or a thickness of 0.5 nm to 200 nm.

  Here, the depth from the surface of the semiconductor substrate to the embrittlement layer 202 is determined by doping conditions. That is, the thickness of the formed SOI layer can be changed by changing the doping conditions (particularly the acceleration voltage).

  FIG. 2 shows an example of the relationship between the acceleration voltage during ion implantation (horizontal axis) and the thickness of the semiconductor layer immediately after separation (vertical axis). Here, the thickness of the semiconductor layer immediately after the separation shown on the vertical axis is based on the embrittlement layer 202 provided on the second substrate 200 by bonding the first substrate 100 and the plurality of second substrates 200. The semiconductor layer immediately after separation was measured with a spectroscopic ellipsometer (manufactured by Horiba, Ltd., fully automatic ultra-thin film measurement system (UT-300)). For example, if the polishing amount in the region where the polishing amount by the subsequent CMP process is large is about twice the polishing amount in the region where the polishing amount is small, for the second substrate 200 disposed in the region where the polishing amount is large Doping is performed at an acceleration voltage of about 50 kV so that the thickness of the semiconductor layer is about 120 nm. For the second substrate 200 disposed in a region where the polishing amount is small, doping is performed at an acceleration voltage of about 30 kV to reduce the thickness of the semiconductor layer. What is necessary is just to be 60 nm.

Alternatively, if the amount of polishing in the region with a large amount of polishing by the subsequent CMP process is about three times the amount of polishing in the region with a small amount of polishing, for the second substrate 200 disposed in the region with a large amount of polishing. Doping is performed at an acceleration voltage of about 50 kV so that the thickness of the semiconductor layer is about 120 nm. For the second substrate 200 disposed in a region where the polishing amount is small, doping is performed at an acceleration voltage of about 30 kV to reduce the thickness of the semiconductor layer. What is necessary is just to be 40 nm. Here, H ⁺ is used as the ion species to be doped, but there is a similar tendency when other ion species are used. Further, when the acceleration voltage at the time of doping is made constant and H ₃ ⁺ is used as the ion species, an embrittlement layer is formed at a depth of about 1/3 of that when H ⁺ is used. Therefore, the depth from the surface to the embrittlement layer may be varied by making the acceleration voltage constant and varying the ion species used for doping. For example, if the polishing amount in a region with a large polishing amount by the subsequent CMP process is about three times the polishing amount in a region with a small polishing amount, the second substrate 200 disposed in the region with a large polishing amount Doping is performed using H ⁺ , and doping is performed using H ₃ ⁺ for the second substrate 200 disposed in a region where the polishing amount is small, and acceleration voltages at the time of doping are equal (for example, 40 kV) )And it is sufficient. However, it is not limited to these conditions.

  Next, the second bonding layer 210 is formed over the second substrate 200 (see FIG. 1B-2). The second bonding layer 210 may be formed in the same manner as the first bonding layer 110. However, in the case of using the CVD method or the like, it is preferable that the temperature be such that degassing from the embrittlement layer 202 provided on the second substrate 200 does not occur (for example, 350 ° C. or less). The heat treatment for separating the SOI layer from the single crystal semiconductor substrate or the polycrystalline semiconductor substrate is preferably performed at a temperature higher than the temperature for forming the bonding layer.

Note that a plasma CVD method, a thermal CVD method, or a photo CVD method may be used as the chemical vapor deposition method. In particular, according to the plasma CVD method using TEOS and oxygen, a flat silicon oxide layer suitable for the bonding layer can be formed at a low temperature (approximately 350 ° C. or lower). Alternatively, a thermal CVD method using SiH ₄ and NO ₂ may be applied.

  Further, the silicon oxide layer to be the second bonding layer 210 may be formed by a chemical treatment including ozone water and hydrogen peroxide water, or may be formed only by treatment with ozone water. In that case, the thickness is about 0.5 nm to 5 nm.

Alternatively, as the second bonding layer 210, an oxide layer formed by oxidizing the second substrate 200 with heat may be used. In the case where a single crystal silicon substrate is used as the second substrate 200, a suitable oxide layer can be formed by oxidizing the substrate with heat. In the case where the oxide layer is formed by oxidation with heat, a gas containing halogen is preferably included in the atmosphere. As the gas containing halogen to be included in the atmosphere, one or more kinds such as HCl, HF, NF ₃ , HBr, Cl ₂ , ClF ₃ , BCl ₃ , F ₂ , and Br ₂ are used. A gas containing halogen is contained in the atmosphere and oxidized by heat, whereby an oxide layer containing halogen can be formed. When halogen is contained in the second bonding layer 210, for example, when bonding a glass substrate and a semiconductor substrate, an impurity element such as sodium or potassium contained in the glass substrate invades and diffuses into the semiconductor substrate. Can be prevented.

  Note that if there is no problem in the bonding strength between the first bonding layer 110 and the second substrate 200, the first bonding layer 110 and the second substrate 200 are bonded without forming the second bonding layer 210. You may join directly.

  Similarly, the first substrate 100 and the second bonding layer 210 may be directly bonded without forming the first bonding layer 110.

  That is, the bonding layer is not necessarily formed on both the first substrate 100 and the second substrate 200. In the case where the bonding layer is not formed, the number of steps is reduced, and thus throughput can be improved.

  Next, the first bonding layer 110 formed over the first substrate 100 and the second bonding layer 210 formed over the second substrate 200 are closely bonded to each other. The bonding layer 112 is formed by bonding the first bonding layer 110 and the second bonding layer 210 (see FIG. 1C). In order to bond more firmly, pressure may be applied to the first substrate 100 and the second substrate 200. Here, the direction of the pressure to be applied is a direction substantially perpendicular to the bonding surface of the first bonding layer 110 and the second bonding layer 210. Further, the bonding strength is improved by performing the heat treatment. Moreover, you may heat-process in the state which applied the pressure. By performing the heat treatment in a state where pressure is applied, the bonding between the first bonding layer 110 and the second bonding layer 210 becomes stronger, so that the separation between the bonding layers can be reduced and the yield is improved. Further, the reliability of the manufactured semiconductor device is improved.

  In this embodiment mode, the first bonding layer 110 (or the first substrate 100) and the second bonding layer 210 (or the second substrate 200) are bonded, and the second embrittlement layer 202 is used as a starting point. An SOI layer is formed by separating the substrate 200 and removing a part of the remaining embrittlement layer. In this embodiment mode, the remaining embrittled layer is removed by CMP (Chemical Mechanical Polishing). However, when a large-area substrate is polished by CMP, the amount of polishing varies greatly within the surface of the workpiece. Accordingly, if the depth from the surface to the embrittlement layer is uniform in the second substrate 200, the variation in the amount of polishing processing by CMP becomes the variation in the thickness of the SOI layer.

  Therefore, in the present embodiment, a second substrate provided with an embrittlement layer is disposed in a deep position from the surface in a region where the polishing amount by CMP is large, and a shallow position from the surface in a region where the polishing amount by CMP is small. A second substrate provided with an embrittlement layer is disposed. That is, a second substrate provided with an embrittlement layer is disposed and bonded to a central portion of the first substrate at a position shallow from the surface, and a peripheral portion of the first substrate is disposed at a position deep from the surface. A second substrate provided with an embrittlement layer is placed and bonded. The plurality of second substrates having different depths from the surface to the embrittlement layer may be arranged by setting the depth to the embrittlement layer in multiple stages. This will be specifically described with reference to FIG.

  FIG. 3A shows a side view of the second substrates 200A to 200D. The second substrates 200A to 200D have different depths from the bonding layer surface to the embrittlement layer. The second substrate 200A has an embrittlement layer 202A at a distance a from the bonding layer surface, and the second substrate 200B has an embrittlement layer 202B at a distance b from the bonding layer surface. 200C has an embrittlement layer 202C at a position c from the bonding layer surface, and the second substrate 200D has an embrittlement layer 202D at a distance d from the bonding layer surface. Note that the size relationship between a to d is a <b <c <d. That is, in this embodiment, the depth from the surface to the embrittlement layer is set to four stages. However, the present invention is not limited to this, and it may be set in two or three stages, or may be set in more stages.

  FIG. 3B is a top view of the first substrate 100 to which the second substrates 200A to 200D are attached. The first substrate 100 is divided into four regions. Here, the size of the first substrate 100 is about 600 mm in length and about 720 mm in width, and the sizes of the second substrates 200A to 200D are about 120 mm in length and about 120 mm in width. Accordingly, a plurality of second substrates 200 can be arranged in 6 rows and 5 columns on the first substrate 100. However, the present invention is not limited to this, and substrates of any size can be used. Then, a second substrate provided with an embrittlement layer at a deep position from the surface is disposed in a region where the polishing amount by CMP is large (periphery of the first substrate 100) in the post-bonding step, and polishing by CMP is performed. A second substrate provided with an embrittlement layer is disposed in a shallow region from the surface in a small amount region (central portion of the first substrate 100). That is, the second substrate 200A is disposed in the first region 221 on the first substrate 100, the second substrate 200B is disposed in the second region 222, and the second region 200 is disposed in the second region 223. The second substrate 200 </ b> C is disposed in the fourth region 224. By arranging and bonding in this manner, a thick layer is formed in a region where the polishing amount by CMP is large, and a thin layer is formed in a region where the polishing amount by CMP is small (FIG. 3 ( See C)).

  Note that in order to perform bonding at a low temperature, it is preferable to clean the surface on which the bond is formed. When the cleaned first bonding layer 110 and the cleaned second bonding layer 210 are brought into close contact with each other, the bonding forming layer 112 is formed by an attractive force between the surfaces. In order to make the cleaned surface a hydrophilic surface, a large number of hydroxyl groups may be added to the cleaned surface. For example, one or both surfaces of the first bonding layer 110 and the second bonding layer 210 are subjected to oxygen plasma treatment or ozone treatment so that these surfaces can be made hydrophilic. By making the surface hydrophilic in this way, the surface hydroxyl group acts and a strong bond is formed by hydrogen bonding. When the first bonding layer 110 and the second bonding layer 210 are made of different materials, it is particularly preferable to go through a cleaning process.

  Further, in order to form a good bond, the surface on which the bond is formed may be activated. For example, an atomic beam or an ion beam is irradiated to the surface on which the junction is formed. When an atomic beam or an ion beam is used, for example, an inert gas neutral atom beam or inert gas ion beam such as argon can be used. By irradiation with such a beam, dangling bonds are exposed on the surface of the first bonding layer 110 or the second bonding layer 210, and a chemically active surface is formed. Alternatively, plasma irradiation or radical treatment may be performed. By performing such a surface treatment on the surface on which the bonding is formed, even if the first bonding layer 110 and the second bonding layer 210 are made of different materials, the bonding forming layer 112 is formed at approximately 200 to 400 ° C. Can be formed. In order to activate and join the surfaces, it is required to highly clean the surfaces. Therefore, it is preferably performed in a vacuum, and more preferably in a high vacuum. In this manner, in the bonding formation layer 112 bonded through the surface treatment, the bonding strength is improved, and thus the yield is improved.

  In order to further increase the bonding strength of the bonding formation layer 112, it is preferable to perform heat treatment or pressure treatment after bonding. In the case where the first bonding layer 110 and the second bonding layer 210 are bonded together at room temperature, it is particularly preferable to perform heat treatment after bonding. By performing the heat treatment or the pressure treatment, a main bond contributing to the bonding can be changed from a hydrogen bond to a covalent bond on the surface where the bonding is formed, and the bonding strength is improved. The temperature of the heat treatment is lower than the heat resistance temperature of the first substrate 100. In the pressure treatment, pressure is applied in a direction substantially perpendicular to the joint surface. The pressure applied here is determined in consideration of the mechanical strength of the first substrate 100 and the second substrate 200.

  Next, heat treatment is performed on the first substrate 100 to which the plurality of second substrates 200 are bonded, and the second substrate 200 is separated from the first substrate 100 using the embrittlement layer 202 as a starting point ( (See FIGS. 1D and 3C). Here, physical means may be used for the separation. The temperature of the heat treatment is preferably higher than the formation temperature of the first bonding layer 110 and the second bonding layer 210 and lower than the heat resistance temperature of the first substrate 100. For example, in the case where a glass substrate is used as the first substrate 100, the volume of a minute cavity formed in the embrittlement layer 202 is changed by performing heat treatment at approximately 400 to 600 ° C., and the embrittlement layer 202 is changed. It becomes easy to cleave along. In the case where a single crystal silicon substrate is used as the first substrate 100, heat treatment can be performed at a temperature up to about 1000 ° C. Since the bonding formation layer 112 is bonded to the first substrate 100, the same crystalline SOI layer as that of the second substrate 200 remains on the first substrate 100.

  The physical means means mechanical means or mechanical means. In other words, it refers to a means for applying mechanical energy (mechanical energy) to an object, and the means typically applies mechanical force (for example, with a human hand or a grip jig). A process of peeling, a process of separating while rotating a roller). Further, a method of cleaving and separating with a water jet may be applied.

  In this embodiment mode, polishing is performed by CMP after the above-described separation step, so that the remaining damaged layer 114 is removed and planarized and thinned to form an SOI layer 116 (FIGS. 1E and 3). (See (D)). The thickness of the SOI layer 116 is made smaller than the distance a from the surface of the second substrate 200A to the embrittlement layer 202A. Specifically, the thickness of the SOI layer 116 is approximately 5 to 500 nm, preferably 10 to 200 nm. As described above, an SOI layer with small variation in thickness is formed on the first substrate 100 by polishing the first substrate 100 on which the plurality of second substrates 200A to 200D are arranged by CMP. Can do. Note that an SOI layer formed by the plurality of second substrates 200 </ b> A to 200 </ b> D is collectively referred to as an SOI layer 116.

  Next, heat treatment or the like for the purpose of improving crystallinity is preferably performed on the SOI layer at a temperature lower than or equal to the heat resistance temperature of the first substrate 100. Note that when the first substrate 100 is a single crystal silicon substrate, a quartz substrate, or the like, the treatment can be performed at about 1000 ° C., but when the first substrate 100 is a glass substrate, the processing is generally performed. Limited to heat treatment at 400-600 ° C. Therefore, when the first substrate 100 is a glass substrate, it is preferable to perform laser irradiation. A linear laser is preferably used for laser irradiation. By using a linear laser, processing can be performed with high throughput. As described above, since the variation in thickness of the SOI layer can be reduced, the crystallinity can be made uniform without causing in-plane variation even when processing is performed using a linear laser.

  In the present embodiment, the size of the first substrate 100 is 600 mm in length and 720 mm in width, but the present invention is not limited to this. When the size of the first substrate 100 is further increased, the in-plane variation due to CMP is further increased, so that the effect of arranging the second substrates having different thicknesses as described in this embodiment is further increased. Of course, the size of the second substrate 200 is not particularly limited.

  In addition, before the second substrate 200 is separated using the embrittlement layer 202 as a cleavage plane, a trigger for facilitating separation may be formed. Furthermore, when separating the second substrate 200, an adhesive sheet that can be peeled off by light or heat is provided on at least one surface of the first substrate 100 or the second substrate 200, and the first substrate 100 and the first substrate 100 are separated. When one of the two substrates 200 is fixed and the other is peeled off, the separation is further facilitated. At this time, by providing a support member on the other of the first substrate 100 or the second substrate 200, it can be easily peeled off.

  Note that a barrier layer may be provided between the SOI layer 116 and the bonding formation layer 112. The barrier layer is made of a material that can prevent the SOI layer 116 from being contaminated by diffusion of impurity elements that become mobile ions such as alkali metal or alkaline earth metal from the glass substrate used as the first substrate 100. Form. As the barrier layer, for example, a single layer or a stacked layer can be formed using an insulator containing nitrogen such as silicon nitride, silicon nitride oxide, or silicon oxynitride. For example, the barrier layer can be provided by stacking a silicon oxynitride layer and a silicon nitride oxide layer from the SOI layer 116 side.

  Note that the silicon oxynitride used herein has a higher oxygen content than nitrogen, and preferably Rutherford Backscattering Spectroscopy (RBS) and Hydrogen Forward Scattering (HFS). When measured using Hydrogen Forward Scattering), the composition ranges from 50 to 70 atomic% for oxygen, 0.5 to 15 atomic% for nitrogen, 25 to 35 atomic% for silicon, and 0.1 to 10 atomic% for hydrogen. The thing included in the range of. In addition, silicon nitride oxide has a composition containing more nitrogen than oxygen, and preferably has a composition range of 5 to 30 atomic% when measured using RBS and HFS. Nitrogen is contained in the range of 20 to 55 atomic%, silicon is contained in the range of 25 to 35 atomic%, and hydrogen is contained in the range of 10 to 30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, silicon, and hydrogen is included in the above range.

  Note that the first bonding layer 110 is not necessarily formed when the first bonding layer 110 is unnecessary (see FIG. 4). Alternatively, when the second bonding layer 210 is not necessary, the second bonding layer 210 is not necessarily formed (see FIG. 5). Note that the case where the bonding layer is not necessary refers to a case where the bonding surfaces can be bonded well without forming the bonding layer. By forming only one or both of the first bonding layer 110 and the second bonding layer 210, the number of steps is reduced and the throughput is improved.

(Embodiment 2)
In this embodiment, an example of a method for manufacturing an SOI substrate which is one embodiment of the present invention, which is different from that in Embodiment 1, will be described with reference to drawings. Specifically, an etching process is used instead of CMP to remove the embrittlement layer.

  First, as in the first embodiment, the first substrate 100 and the second substrate 200 are prepared, the first bonding layer 110 is formed on the first substrate 100, and the second substrate 200 is formed. Then, the second bonding layer 210 is formed. The first substrate 100 and the second substrate 200 can be the same as those used in Embodiment 1. In addition, the first bonding layer 110 and the second bonding layer 210 are formed using the same material and method as in Embodiment 1, and the surface of the bonding surface (the surface is activated by a treatment for improving flatness, an ion beam, or the like). The processing to be converted) can be performed in the same manner. Further, as in the first embodiment, the embrittlement layer 202 is formed on the second substrate 200 by ion implantation.

  Bonding is performed by bringing the first bonding layer 110 (or the first substrate 100) and the second bonding layer 210 (or the second substrate 200) into close contact with each other. By bonding the first bonding layer 110 and the second bonding layer 210, the bonding formation layer 112 is formed. In order to bond more firmly, pressure may be applied to the first substrate 100 and the second substrate 200. Here, the direction of the pressure to be applied is a direction substantially perpendicular to the bonding surface of the first bonding layer 110 and the second bonding layer 210. Further, the bonding strength is improved by performing the heat treatment. Moreover, you may heat-process in the state which applied the pressure. By performing the heat treatment in a state where pressure is applied, the bonding between the first bonding layer 110 and the second bonding layer 210 becomes stronger, so that the separation between the bonding layers can be reduced and the yield can be improved. To do. Further, the reliability of the manufactured semiconductor device is improved.

  Next, the second substrate 200 is separated from the embrittlement layer 202 included in the second substrate, and a part of the remaining embrittlement layer is removed, so that an SOI layer is formed. In this embodiment mode, the remaining embrittlement layer 202 is removed by an etching process. For the etching, dry etching is used. However, in dry etching, the etching amount in the surface to be processed varies depending on the electric field intensity distribution. In general, the electric field concentration in dry etching often shows a concentric distribution in the surface to be processed. The electric field strength is concentrated in the center of the object to be processed, and the electric field strength is weak in the peripheral part of the object to be processed. . Therefore, when a second substrate having a uniform depth from the surface to the embrittlement layer is used, variations in the etching amount due to etching appear as variations in the thickness of the SOI layer.

  Therefore, in this embodiment mode, a case where electric field concentration in dry etching shows a concentric distribution in the surface to be processed will be described. That is, in this embodiment mode, the second substrate provided with the embrittlement layer is disposed at a deep position from the surface in a region with a large etching amount, and the embrittlement layer is disposed at a shallow position from the surface in a region with a small etching amount. A second substrate provided with is disposed. That is, a second substrate provided with an embrittlement layer at a position shallow from the surface is disposed and bonded to the peripheral portion of the first substrate, and the embrittlement layer is disposed at a position deep from the surface at the center of the substrate. A second substrate provided with is disposed and bonded.

  The plurality of second substrates having different depths from the surface to the embrittlement layer may be arranged by setting the depth to the embrittlement layer in multiple stages. A specific example will be described with reference to FIG.

  FIG. 6A shows a side view of the second substrates 200A to 200D. The second substrates 200A to 200D have different depths from the bonding layer surface to the embrittlement layer. The second substrate 200A has an embrittled layer 202A formed at a distance a from the bonding layer surface, and the second substrate 200B has an embrittled layer 202B formed at a distance b from the bonding layer surface. 200C has a brittle layer 202C formed at a distance c from the bonding layer surface, and the second substrate 200D has a brittle layer 202D formed at a distance d from the bonding layer surface. Note that the size relationship between a to d is a <b <c <d. That is, in this embodiment, the depth from the surface to the embrittlement layer is set to four stages. However, the present invention is not limited to this, and it may be set in two or three stages, or may be set in more stages.

  FIG. 6B is a top view of the first substrate 100 to which the second substrates 200A to 200D are attached. The first substrate 100 is divided into four regions. Here, the size of the first substrate 100 is about 600 mm in length and about 720 mm in width, and the sizes of the second substrates 200A to 200D are about 120 mm in length and about 120 mm in width. Therefore, the second substrate 200 can be arranged in 6 rows and 5 columns on the first substrate 100. However, the present invention is not limited to this, and any size can be used. Then, a second substrate in which an embrittlement layer is provided at a deep position from the surface is disposed in a region where the etching amount is large (a central portion of the first substrate 100) in the post-bonding process, and a region where the etching amount is small ( A second substrate provided with an embrittlement layer is disposed in a shallow position from the surface on the periphery of the first substrate 100. That is, the second substrate 200 </ b> D is disposed in the first region 231 on the first substrate 100, the second substrate 200 </ b> C is disposed in the second region 232, and the second region 233 is in the second region 233. The second substrate 200 </ b> B is disposed in the fourth region 234. By arranging and bonding in this manner, a thick layer is formed in a region with a large etching amount, and a thin layer is formed in a region with a small etching amount (see FIG. 6C). ).

  After the bonding formation layer 112 is formed, the bonding strength can be improved by performing a heat treatment or a pressure treatment as in the first embodiment.

  After the first substrate 100 and the second substrate 200 are bonded to each other, the second substrate 200 is separated from the first substrate 100 with the embrittlement layer 202 as a starting point, as in the first embodiment. In this embodiment mode, planarization and thinning are performed by etching after the separation step, so that an SOI layer 116 is formed (see FIG. 6D). The thickness of the SOI layer 116 is made smaller than the distance a from the surface of the second substrate 200A to the embrittlement layer 202A. Specifically, the thickness of the SOI layer 116 is approximately 5 to 500 nm, preferably 10 to 200 nm. As described above, by etching the first substrate 100 on which the second substrates 200 </ b> A to 200 </ b> D are arranged, an SOI layer having a small thickness variation can be formed on the first substrate 100.

  In the present embodiment, the size of the first substrate 100 is 600 mm in length and 720 mm in width, but the present invention is not limited to this. When the size of the first substrate 100 is further increased, the in-plane variation due to CMP is further increased, so that the effect of arranging the second substrates having different thicknesses as described in this embodiment is further increased. Of course, the size of the second substrate 200 is not particularly limited.

  Note that the present invention is not limited to the above description, and the first bonding layer 110 may not be particularly formed (see FIG. 4). Alternatively, when the second bonding layer 210 is not necessary, the second bonding layer 210 is not necessarily formed (see FIG. 5). Note that the case where these bonding layers are not required refers to a case where the bonding surface and the bonding surface are bonded well and the bonding strength is sufficient without forming the bonding layer. By forming only one or both of the first bonding layer 110 and the second bonding layer 210, the number of steps is reduced and the throughput is improved.

  That is, as described in this embodiment mode, when an etching process is used instead of CMP after the separation of the second substrate, the arrangement method needs to be different.

(Embodiment 3)
In this embodiment, a method for manufacturing a semiconductor device using an SOI substrate manufactured by applying Embodiments 1 and 2 will be described.

  First, a method for manufacturing an n-channel thin film transistor (n-type TFT) and a p-channel thin film transistor (p-type TFT) will be described with reference to FIGS. Various semiconductor devices can be manufactured by combining a plurality of thin film transistors.

  Here, an SOI substrate manufactured by the method described in Embodiment 1 or 2 is used as a substrate for manufacturing a thin film transistor. FIG. 7A is a cross-sectional view of an SOI substrate used in this embodiment mode.

  First, the SOI layer 116 is element-isolated by etching, so that the island-shaped semiconductor layer 301 and the semiconductor layer 302 are formed. An n-type TFT is formed in the island-shaped semiconductor layer 301, and a p-type TFT is formed in the island-shaped semiconductor layer 302 (see FIG. 7B).

  Next, the insulating layer 304 is formed over the island-shaped semiconductor layer 301 and the island-shaped semiconductor layer 302. Next, the gate electrode 305 is formed over the island-shaped semiconductor layer 301 with the insulating layer 304 provided therebetween, and the gate electrode 306 is formed over the island-shaped semiconductor layer 302 (see FIG. 7C).

  Note that an impurity element imparting p-type conductivity or an impurity element imparting n-type conductivity is added to the SOI layer 116 in order to control the threshold voltage of the TFT before the SOI layer 116 is etched. It is preferable to add. For example, boron is added to a region where an n-type TFT is formed, and phosphorus or arsenic is added to a region where a p-channel TFT is formed.

  Next, an n-type impurity region 307 is formed in the island-shaped semiconductor layer 301, and a p-type high-concentration impurity region 309 is formed in the island-shaped semiconductor layer 302. First, an n-type impurity region 307 is formed in the island-shaped semiconductor layer 301. Therefore, the island-shaped semiconductor layer 302 to be a p-type TFT is covered with a resist mask, and an impurity element imparting n-type conductivity (eg, phosphorus or arsenic) is added to the island-shaped semiconductor layer 301. By adding an impurity element imparting n-type conductivity by an ion doping method, the gate electrode 305 serves as a mask, and an n-type impurity region 307 is formed in the island-shaped semiconductor layer 301 in a self-aligning manner. A region of the island-shaped semiconductor layer 301 that overlaps with the gate electrode 305 becomes a channel formation region 308 (see FIG. 7D).

  Next, after the mask covering the island-shaped semiconductor layer 302 is removed, the island-shaped semiconductor layer 301 to be an n-type TFT is covered with a resist mask. Next, an impurity element imparting p-type conductivity (eg, boron) is added to the island-shaped semiconductor layer 302 by ion doping. In the step of adding an impurity element imparting p-type conductivity, the gate electrode 306 functions as a mask, and a p-type high-concentration impurity region 309 is formed in the island-shaped semiconductor layer 302 in a self-aligning manner. The p-type high concentration impurity region 309 functions as a source region or a drain region. A region overlapping with the gate electrode 306 of the island-shaped semiconductor layer 302 becomes a channel formation region 310. Although the method of forming the p-type high concentration impurity region 309 after forming the n-type impurity region 307 has been described here, the n-type impurity region 307 is formed after the p-type high concentration impurity region 309 is formed. It may be formed.

  Next, after removing the resist mask covering the island-shaped semiconductor layer 301, an insulating layer having a single-layer structure or a stacked structure including a nitrogen compound such as silicon nitride and an oxide such as silicon oxide is formed. Here, for the formation of the insulating layer, a CVD method or the like may be used. For example, a plasma CVD method may be used. Then, side wall insulating layers 311 and 312 are formed in contact with the side surfaces of the gate electrode 305 and the gate electrode 306 by performing anisotropic etching in the vertical direction on the insulating layer. By this anisotropic etching, the insulating layer 304 is also etched except for a part. Note that the region where the insulating layer 304 is etched is a region which does not overlap with the gate electrode 305, the gate electrode 306, the sidewall insulating layer 311, and the sidewall insulating layer 312. Through this step, the insulating layer 313 and the insulating layer 314 are formed (see FIG. 8A).

  Next, the island-shaped semiconductor layer 302 is covered with a resist mask 315, and an impurity element imparting n-type conductivity is further added to the island-shaped semiconductor layer 301. In this addition, the n-type high concentration impurity region 317 is formed using the gate electrode 305 and the sidewall insulating layer 311 as a mask. Next, heat treatment is performed to activate the impurity element imparting p-type conductivity and the impurity element imparting n-type conductivity.

  After the heat treatment, an insulating layer 318 is formed as illustrated in FIG. The insulating layer 318 preferably contains hydrogen. After the insulating layer 318 is formed, heat treatment is performed at 350 ° C. to 450 ° C., so that hydrogen contained in the insulating layer 318 is diffused into the island-shaped semiconductor layer 301 and the island-shaped semiconductor layer 302. The insulating layer 318 can be formed by depositing silicon nitride or silicon nitride oxide by a plasma CVD method with a process temperature of 350 ° C. or lower. When hydrogen is contained in the insulating layer 318, hydrogen can be supplied to the island-shaped semiconductor layer 301 and the island-shaped semiconductor layer 302, and the island-shaped semiconductor layer 301 and the island-shaped semiconductor layer 302 can be supplied to each other. The defects serving as trapping centers existing at the interface between the semiconductor layer 301 and the insulating layer 313 and the interface between the island-shaped semiconductor layer 302 and the insulating layer 314 can be effectively terminated.

  Next, the insulating layer 319 is formed. The insulating layer 319 is a single layer or a laminate of an insulating layer made of an inorganic material such as silicon oxide or BPSG (borophosphosilicate glass), or an insulating layer made of an organic material such as polyimide or acrylic. Can be formed.

  Next, a contact hole is formed in the insulating layer 319 and a wiring 320 is formed. For example, the wiring 320 can be formed of a conductive layer having a three-layer structure in which a low-resistance metal such as aluminum or an aluminum alloy is sandwiched between barrier metals. The barrier metal can be formed of a metal material such as molybdenum, chromium, or titanium.

  Through the above steps, a semiconductor device having an n-channel TFT and a p-channel TFT can be manufactured. In the process of manufacturing the SOI substrate, the concentration of the metal element in the semiconductor layer included in the channel formation region is reduced, so that a TFT with small off-current and suppressed threshold voltage variation can be manufactured.

  As described above, the manufacturing method of the TFT has been described with reference to FIGS. 7 and 8. However, a semiconductor device with high added value can be manufactured by forming various semiconductor elements other than the TFT such as a capacitor or a resistor. Hereinafter, specific modes of the semiconductor device will be described with reference to the drawings.

  First, a microprocessor will be described as an example of a semiconductor device. FIG. 9 is a block diagram illustrating a configuration example of the microprocessor 330.

  The microprocessor 330 includes an arithmetic circuit 331 (also referred to as Arithmetic Logic Unit; ALU), an arithmetic circuit control unit 332, an instruction analysis unit 333, an interrupt control unit 334, a timing control unit 335, a register 336, a register control unit 337, and a bus interface. 338, a ROM 339 that is a read-only memory, and a ROM interface 340.

  An instruction input to the microprocessor 330 via the bus interface 338 is input to the instruction analysis unit 333 and decoded, and then is input to the arithmetic circuit control unit 332, the interrupt control unit 334, the register control unit 337, and the timing control unit 335. Entered. The arithmetic circuit control unit 332, the interrupt control unit 334, the register control unit 337, and the timing control unit 335 perform various controls based on the decoded instruction.

  The arithmetic circuit control unit 332 generates a signal for controlling the operation of the arithmetic circuit 331. The interrupt control unit 334 is a circuit that processes an interrupt request from an external input / output device or a peripheral circuit when the microprocessor 330 is executing a program. The interrupt control unit 334 determines the priority of the interrupt request and processes the interrupt request. The register control unit 337 generates an address of the register 336 and reads and writes the register 336 according to the state of the microprocessor 330. The timing control unit 335 generates a signal that controls the operation timing of the arithmetic circuit 331, the arithmetic circuit control unit 332, the instruction analysis unit 333, the interrupt control unit 334, and the register control unit 337. For example, the timing control unit 335 includes an internal clock generation unit that generates the internal clock signal CLK2 using the reference clock signal CLK1. As shown in FIG. 9, the internal clock signal CLK2 is input to another circuit.

  Next, an example of a semiconductor device having a function of performing transmission / reception of data without contact and an arithmetic function will be described. FIG. 10 is a block diagram illustrating a configuration example of such a semiconductor device. The semiconductor device illustrated in FIG. 10 can be referred to as a computer that operates by transmitting and receiving signals to and from an external device by wireless communication (hereinafter referred to as “RFCPU”).

  As illustrated in FIG. 10, the RFCPU 351 includes an analog circuit unit 352 and a digital circuit unit 353. The analog circuit portion 352 includes a resonance circuit 354 having a resonance capacitance, a rectifier circuit 355, a constant voltage circuit 356, a reset circuit 357, an oscillation circuit 358, a demodulation circuit 359, and a modulation circuit 360. The digital circuit unit 353 includes an RF interface 361, a control register 362, a clock controller 363, a CPU interface 364, a CPU 365, a RAM 366, and a ROM 367. Note that the CPU is a central processing unit, the RAM is a random access memory, and the ROM is a read-only memory.

  The outline of the operation of the RFCPU 351 is as follows. A signal received by the antenna 368 generates an induced electromotive force by the resonance circuit 354. The induced electromotive force charges the capacitor 369 through the rectifier circuit 355. The capacitor 369 is preferably formed of a capacitor such as a ceramic capacitor or an electric double layer capacitor. The capacitor 369 does not need to be integrated on the substrate constituting the RFCPU 351, and may be incorporated into the RFCPU 351 as another component.

  The reset circuit 357 generates a signal for initializing the digital circuit unit 353. For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The oscillation circuit 358 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the constant voltage circuit 356. The demodulation circuit 359 is a circuit that demodulates a received signal, and the modulation circuit 360 is a circuit that modulates data to be transmitted.

  For example, the demodulation circuit 359 is formed of a low-pass filter, and binarizes an amplitude modulation (ASK) reception signal based on the amplitude variation. In addition, in order to transmit transmission data by changing the amplitude of an amplitude modulation (ASK) transmission signal, the modulation circuit 360 changes the amplitude of the communication signal by changing the resonance point of the resonance circuit 354.

  The clock controller 363 generates a control signal for changing the frequency and duty ratio of the clock signal in accordance with the power supply voltage or the current consumption in the CPU 365. The power supply management circuit 370 monitors the power supply voltage.

  A signal input from the antenna 368 to the RFCPU 351 is demodulated by the demodulation circuit 359 and then decomposed into a control command, data, and the like by the RF interface 361. The control command is stored in the control register 362. The control command includes reading of data stored in the ROM 367, writing of data to the RAM 366, calculation instructions to the CPU 365, and the like.

  The CPU 365 accesses the ROM 367, the RAM 366, and the control register 362 through the CPU interface 364. The CPU interface 364 has a function of generating an access signal for any one of the ROM 367, the RAM 366, and the control register 362 according to an address requested by the CPU 365.

  As a calculation method of the CPU 365, a method in which an OS (operating system) is stored in the ROM 367 and a program is read and executed at the time of activation can be employed. Further, it is also possible to adopt a method in which an arithmetic circuit is configured by a dedicated circuit and arithmetic processing is processed in hardware. In the method using both hardware and software, a method in which a part of arithmetic processing is performed by a dedicated arithmetic circuit and the other processing is processed by the CPU 365 using a program can be applied.

  Next, a display device which is a kind of semiconductor device is described with reference to FIGS.

  In the SOI substrate manufacturing process described in Embodiments 1 and 2, the first substrate can be a glass substrate. Therefore, by using a glass substrate for the first substrate and forming a plurality of semiconductor layers on the first substrate, an SOI substrate having a large area with one side exceeding 1 meter can be manufactured.

  As the first substrate, for example, a large area glass substrate called mother glass can be used. FIG. 11 is a top view when a mother glass is used as the first substrate 100. A liquid crystal display device and an electroluminescence display device can be manufactured by providing a plurality of semiconductor elements over such a large substrate. In addition to such a display device, various semiconductor devices such as a solar cell, a photo IC, and a semiconductor memory device can be manufactured.

  As described in the first embodiment or the second embodiment, in the case where a mother glass is used as the first substrate, an SOI layer formed separately from a plurality of semiconductor substrates on one mother glass. Is provided. In order to cut out a plurality of display panels from the mother glass, it is preferable that the entire surface of a region where one display panel is formed is included in the SOI layer. A region for forming one display panel includes a scan line driver circuit, a signal line driver circuit, and a pixel portion.

  FIG. 11 is a diagram for explaining a liquid crystal display device. 11A is a top view of one pixel included in the pixel portion of the liquid crystal display device, and FIG. 11B is a cross-sectional view taken along line AB of FIG. 11A.

  In FIG. 11A, a pixel connects a semiconductor layer 420, a scanning line 422 intersecting with the semiconductor layer 420, a signal line 423 intersecting with the scanning line 422, a pixel electrode 424, and the pixel electrode 424 and the semiconductor layer 420. An electrode 428 is included. The semiconductor layer 420 is a layer formed from the SOI layer 116 attached to the first substrate 100 and constitutes a TFT 425 of the pixel.

  As the SOI substrate, an SOI substrate manufactured by the method described in Embodiment 1 or 2 is used. As illustrated in FIG. 11B, the bonding formation layer 112 is provided over the first substrate 100, and the semiconductor layer 420 is provided over the bonding formation layer 112. Here, a glass substrate is used as the first substrate 100. The semiconductor layer 420 included in the TFT 425 is a layer formed by element isolation of the SOI layer 116 by etching. In the semiconductor layer 420, a channel formation region 440 and an impurity region 441 to which an impurity element imparting n-type conductivity is added are formed. A gate electrode of the TFT 425 is included in the scanning line 422, and one of the source electrode and the drain electrode is included in the signal line 423.

  A signal line 423, a pixel electrode 424, and an electrode 428 are provided over the insulating layer 427. A columnar spacer 429 is formed over the insulating layer 427. An alignment film 430 is formed so as to cover the signal line 423, the pixel electrode 424, the electrode 428, and the columnar spacer 429. On the counter substrate 432, an alignment film 434 is formed to cover the counter electrode 433 and the counter electrode 433. The columnar spacer 429 is provided in order to keep a gap between the active matrix substrate formed by the first substrate 100 and the counter substrate 432 constant. A liquid crystal layer 435 is provided in the gap formed by the columnar spacers 429. As shown in FIG. 11, columnar spacers 429 are preferably arranged in a region overlapping with the contact hole.

  FIG. 12 is a diagram for explaining an electroluminescence display device (hereinafter referred to as an EL display device). 12A is a top view of one pixel included in the pixel portion of the EL display device, and FIG. 12B is a cross-sectional view taken along line CD in FIG. 12A.

  As shown in FIG. 12A, the pixel includes a selection transistor 451, a display control transistor 452, a scanning line 455, a signal line 456, a current supply line 457, and a first pixel electrode 458. Each pixel is provided with a light-emitting element having a structure in which a layer containing an electroluminescent material (EL layer) is sandwiched between a pair of electrodes. The first pixel electrode 458 is one of the electrodes that sandwich the EL layer. In addition, the semiconductor layer 453 forms a channel formation region, a source region, and a drain region of the selection transistor 451. The semiconductor layer 454 forms a channel formation region, a source region, and a drain region of the display control transistor 452. The semiconductor layer 453 and the semiconductor layer 454 are layers formed from the SOI layer 116 attached to the first substrate 100.

  In the selection transistor 451, the gate electrode is included in the scanning line 455, one of the source electrode and the drain electrode is included in the signal line 456, and the other is formed as the electrode 461. In the display control transistor 452, the gate electrode 462 is electrically connected to the electrode 461, and one of the source electrode and the drain electrode is formed as an electrode 463 electrically connected to the first pixel electrode 458. The other is included in the current supply line 457.

  The display control transistor 452 is a p-type TFT. As shown in FIG. 12B, a channel formation region 491 and an impurity region 492 to which an impurity element imparting p-type conductivity is added are formed in the semiconductor layer 454. Note that as the SOI substrate, an SOI substrate manufactured by the method described in Embodiment 1 or 2 is used.

  An insulating layer 477 is formed so as to cover the display control transistor 452. Over the insulating layer 477, a signal line 456, a current supply line 457, an electrode 461, an electrode 463, and the like are formed. A first pixel electrode 458 connected to the electrode 463 is formed over the insulating layer 477. A peripheral portion of the first pixel electrode 458 is surrounded by an insulating partition wall 478. An EL layer 479 is provided over the first pixel electrode 458, and a second pixel electrode 480 is provided over the EL layer 479. Further, a counter substrate 481 is provided as a reinforcing plate, and the counter substrate 481 is fixed to the first substrate 100 through a resin layer 482.

  There are two types of EL display device gray scale control methods: current drive method in which the luminance of a light-emitting element is controlled by current and voltage drive method in which voltage is controlled by voltage. In the current drive method, there is a difference in transistor characteristic values. If it is large, it is difficult to adopt it, and in order to adopt it, a correction circuit that corrects variation in characteristics is required. By using the method for manufacturing an SOI substrate described in Embodiments 1 and 2, variation in thickness of the SOI layer can be reduced, variation in semiconductor layer can be reduced, and variation in characteristics between transistors can be achieved. Thus, it is possible to adopt a current driving method without having a correction circuit.

  In addition, by using the SOI substrate described in Embodiments 1 and 2, not only a display device but also various electric devices can be manufactured. Such electric devices include video cameras, digital cameras, navigation systems, sound playback devices (car audio, audio components, etc.), computers, game devices, personal digital assistants (mobile computers, mobile phones, portable game machines or electronic devices). A display device capable of reproducing audio data stored on a recording medium such as a DVD (digital versatile disc) and displaying the stored image data. Equipment provided is included.

  With reference to FIG. 13, the specific aspect of an electric equipment is demonstrated. FIG. 13A illustrates an example of a mobile phone. A cellular phone 501 includes a display unit 502, an operation switch 503, and the like. By applying the liquid crystal display device described with reference to FIG. 11 or the EL display device described with reference to FIG. 12 to the display portion 502, the display portion 502 with less display unevenness and excellent image quality can be obtained. .

  FIG. 13B illustrates an example of a digital player. The digital player 511 includes a display unit 512, an operation unit 513, an earphone 514, and the like. Instead of the earphone 514, a headphone or a wireless earphone may be used. By applying the liquid crystal display device described with reference to FIG. 11 or the EL display device described with reference to FIG. 12 to the display unit 512, the screen size is about 0.3 inch to 2 inches. In addition, the display unit 502 with less display unevenness and excellent image quality can be obtained, and a high-definition image and a large amount of character information can be displayed on the display unit 502.

  FIG. 13C is an external view of the electronic book 521. The electronic book 521 includes a display unit 522 and operation switches 523. The electronic book 521 may have a built-in modem, or may have a configuration in which the RFCPU illustrated in FIG. By applying the liquid crystal display device described with reference to FIG. 11 or the EL display device described with reference to FIG. 12 to the display portion 522, the display portion 522 with less display unevenness and excellent image quality can be obtained. it can.

  FIG. 14 shows an example of a mobile phone having a different form from FIG. 13, in which FIG. 14 (A) is a front view, FIG. 14 (B) is a rear view, and FIG. 14 (C) is a slide of two housings. It is a front view at the time. The smart phone mobile phone shown in FIG. 14 includes two housings 601 and 602. The smart phone mobile phone shown in FIG. 14 is a so-called smart phone that has both functions of a mobile phone and a personal digital assistant, incorporates a computer, and can perform various data processing in addition to voice calls.

  The smart phone mobile phone shown in FIG. 14 includes two housings 601 and 602. The housing 601 includes a display portion 603, a speaker 604, a microphone 605, an operation key 606, a pointing device 607, a front camera lens 608, an external connection terminal jack 609, an earphone terminal 610, and the like, and the housing 602 includes a keyboard. 611, an external memory slot 612, a rear camera 613, a light 614, and the like. An antenna is built in the housing 601.

  In addition to the above structure, a non-contact IC chip, a small recording device, or the like may be incorporated.

  The overlapped housings 601 and 602 (shown in FIG. 14A) slide and expand as shown in FIG. 14C. The display portion 603 can incorporate the display device described in the above embodiment mode, and the display direction can be appropriately changed depending on a usage pattern. Since the front camera lens 608 is provided on the same surface as the display portion 603, a videophone can be used. Further, a still image and a moving image can be taken with the rear camera 613 and the light 614 using the display portion 603 as a viewfinder.

  The speaker 604 and the microphone 605 can be used not only for voice calls but also for videophone, recording, reproduction, and the like. The operation keys 606 can be used for making and receiving calls, inputting simple information such as e-mails, scrolling the screen, moving the cursor, and the like.

  In addition, when there is a lot of information to be handled, such as creation of a document or use as a portable information terminal, it is convenient to use the keyboard 611. Further, the housings 601 and 602 (FIG. 14A) which overlap with each other slide and expand as illustrated in FIG. 14C, and when the portable information terminal can be used, the keyboard 611 and the pointing device 607 are attached. The mouse can be operated with smooth operation. The external connection terminal jack 609 can be connected to an AC adapter and various cables such as a USB cable, and charging and data communication with a personal computer or the like are possible. Further, a recording medium can be inserted into the external memory slot 612 to cope with storing and moving a larger amount of data.

  The rear surface of the housing 602 (FIG. 14B) is provided with a rear camera 613 and a light 614, and a still image and a moving image can be taken using the display portion 603 as a viewfinder.

  Further, in addition to the above functional configuration, an infrared communication function, a USB port, a TV one-segment reception function, a non-contact IC chip, an earphone jack, and the like may be provided.

100 first substrate 110 first bonding layer 112 bonding formation layer 114 remaining damaged layer 116 SOI layer 200 second substrate 200A second substrate 200B second substrate 200C second substrate 200D second substrate 201 protection Layer 202 Embrittlement layer 202A Embrittlement layer 202B Embrittlement layer 202C Embrittlement layer 202D Embrittlement layer 210 Second bonding layer 221 First region 222 Second region 223 Third region 224 Fourth region 231 First Region 232 second region 233 third region 234 fourth region 301 semiconductor layer 302 semiconductor layer 304 insulating layer 305 gate electrode 306 gate electrode 307 impurity region 308 channel formation region 309 high concentration impurity region 310 channel formation region 311 side Wall insulating layer 312 Side wall insulating layer 313 Insulating layer 314 Insulating layer 315 Regis Mask 317 high-concentration impurity region 318 insulating layer 319 insulating layer 320 lines 330 microprocessor 331 operational circuit 332 ALU controller 333 instruction decoder 334 interrupt controller 335 a timing control unit 336 registers 337 the register controller 338 bus interface 339 ROM
340 ROM interface 351 RFCPU
352 Analog circuit section 353 Digital circuit section 354 Resonance circuit 355 Rectifier circuit 356 Constant voltage circuit 357 Reset circuit 358 Oscillation circuit 359 Demodulation circuit 360 Modulation circuit 361 RF interface 362 Control register 363 Clock controller 364 CPU interface 365 CPU
366 RAM
367 ROM
368 Antenna 369 Capacitance unit 370 Power management circuit 420 Semiconductor layer 422 Scan line 423 Signal line 424 Pixel electrode 425 TFT
427 Insulating layer 428 Electrode 429 Columnar spacer 430 Alignment film 432 Counter substrate 433 Counter electrode 434 Alignment film 435 Liquid crystal layer 440 Channel formation region 441 Impurity region 451 Selection transistor 452 Display control transistor 453 Semiconductor layer 454 Semiconductor layer 455 Scan line 456 Signal Line 457 Current supply line 458 First pixel electrode 461 Electrode 462 Gate electrode 463 Electrode 477 Insulating layer 478 Partition wall 479 EL layer 480 Second pixel electrode 481 Counter substrate 482 Resin layer 491 Channel formation region 492 Impurity region 501 Cell phone 502 Display Unit 503 operation switch 511 digital player 512 display unit 513 operation unit 514 earphone 521 electronic book 522 display unit 523 operation switch 601 case 602 case 603 display unit 604 speaker 6 05 Microphone 606 Operation key 607 Pointing device 608 Front camera lens 609 External connection terminal jack 610 Earphone terminal 611 Keyboard 612 External memory slot 613 Rear camera 614 Light

Claims (6)

A method for manufacturing an SOI substrate in which a semiconductor layer is formed on a base substrate and chemical mechanical polishing is performed,
In each of the plurality of semiconductor substrates, an embrittlement layer is formed at a position where the depth from the surface to be bonded to the base substrate is different,
In the region where the amount of polishing in the chemical mechanical polishing process in the base substrate surface is large, the plurality of semiconductor substrates provided with the embrittlement layer at a deep position from the surface,
Arranging the plurality of semiconductor substrates provided with the embrittlement layer in a shallow position from the surface in a region where the amount of polishing in the chemical mechanical polishing process in the base substrate surface is small,
Bonding the base substrate and the plurality of semiconductor substrates disposed on the base substrate;
Forming a plurality of first semiconductor layers by separating the plurality of semiconductor substrates bonded to the base substrate starting from the embrittlement layer;
A method for manufacturing an SOI substrate, wherein the second semiconductor layer is formed by polishing the plurality of first semiconductor layers by a chemical mechanical polishing process. A method for manufacturing an SOI substrate in which a semiconductor layer is formed over a base substrate and etching is performed.
In each of the plurality of semiconductor substrates, an embrittlement layer is formed at a position where the depth from the surface to be bonded to the base substrate is different,
Arranging the plurality of semiconductor substrates provided with the embrittlement layer at a deep position from the surface in a region where the etching rate of the etching process is large in the base substrate surface,
Arranging the plurality of semiconductor substrates provided with the embrittlement layer in a shallow position from the surface in a region where the etching rate of the etching process is small in the base substrate surface;
Bonding the base substrate and the plurality of semiconductor substrates disposed on the base substrate;
Forming a plurality of first semiconductor layers by separating the plurality of semiconductor substrates bonded to the base substrate starting from the embrittlement layer;
A method for manufacturing an SOI substrate, wherein the second semiconductor layer is formed by etching the plurality of first semiconductor layers. A method for manufacturing an SOI substrate in which a semiconductor layer is formed on a base substrate and chemical mechanical polishing is performed,
In each of the plurality of semiconductor substrates, an embrittlement layer is formed at a position where the depth from the surface to be bonded to the base substrate is different,
In the central portion of the base substrate, the plurality of semiconductor substrates provided with the embrittlement layer at a shallow position from the surface are arranged,
The plurality of semiconductor substrates each provided with the embrittlement layer at a deep position from the surface are disposed on the peripheral edge of the base substrate,
Bonding the base substrate and the plurality of semiconductor substrates disposed on the base substrate;
Forming a plurality of first semiconductor layers by separating the plurality of semiconductor substrates bonded to the base substrate starting from the embrittlement layer;
A method for manufacturing an SOI substrate, wherein the second semiconductor layer is formed by polishing the plurality of first semiconductor layers by a chemical mechanical polishing process. A method for manufacturing an SOI substrate in which a semiconductor layer is formed over a base substrate and etching is performed
In each of the plurality of semiconductor substrates, an embrittlement layer is formed at a position having a different depth from the surface to be bonded to the base substrate
In the central part of the base substrate, the plurality of semiconductor substrates provided with the embrittlement layer at a deep position from the surface are arranged,
The plurality of semiconductor substrates provided with the embrittlement layer at a shallow position from the surface are arranged on the periphery of the base substrate,
Bonding the base substrate and the plurality of semiconductor substrates disposed on the base substrate;
Forming a plurality of first semiconductor layers by separating the plurality of semiconductor substrates bonded to the base substrate starting from the embrittlement layer;
A method for manufacturing an SOI substrate, wherein the second semiconductor layer is formed by etching the plurality of first semiconductor layers. In any one of Claims 1 thru | or 4 ,
The formation of the embrittlement layer is performed by an ion doping method. In any one of Claims 1 thru | or 5 ,
The method for manufacturing an SOI substrate, wherein the base substrate is a light-transmitting substrate.

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