JP5474239B2 - Wiring board - Google Patents

Description

  The present invention relates to a wiring board.

  Conventionally, there is a semiconductor device provided with a plurality of electronic components and a wiring board on which the plurality of electronic components are mounted (see FIG. 1).

  FIG. 1 is a cross-sectional view of a conventional semiconductor device.

  Referring to FIG. 1, a conventional semiconductor device 200 includes a wiring board 201, electronic components 202 and 203, and external connection terminals 205 and 206.

  The wiring substrate 201 includes a substrate 211 made of a semiconductor material, an insulating film 212, through electrodes 213 and 214, pads 216 and 217, wiring 218, external connection pads 221 and 222, and solder resist layers 225 and 226. And have.

  The substrate 211 is plate-shaped and has through holes 231 and 232. The insulating film 212 is formed so as to cover the upper surface 211A and the lower surface 211B of the substrate 211 and the surface of the substrate 211 corresponding to the side surfaces of the through holes 231 and 232.

  The through electrode 213 is provided in the through hole 231 in which the insulating film 212 is formed. The through electrode 214 is provided in the through hole 232 in which the insulating film 212 is formed.

  The pad 216 is provided on the insulating film 212 formed on the upper surface 211A of the substrate 211. The pad 216 is connected to the upper end of the through electrode 213. The pad 216 has a connection surface 216A on which the electronic component 202 is mounted.

  The pad 217 is provided on the insulating film 212 formed on the upper surface 211A of the substrate 211. The pad 217 is connected to the upper end of the through electrode 214. The pad 217 has a connection surface 217A on which the electronic component 203 is mounted.

  The wiring 218 is provided on the insulating film 212 formed on the upper surface 211A of the substrate 211. The wiring 218 connects the pad 216 and the pad 217.

  The external connection pad 221 is provided on the lower surface of the insulating film 212 formed on the lower surface 211B of the substrate 211. The external connection pad 221 is connected to the lower end of the through electrode 213. As a result, the external connection pad 221 is electrically connected to the pad 216 via the through electrode 213. The external connection pad 221 has a connection surface 221A on which the external connection terminal 205 is disposed.

  The external connection pads 222 are provided on the lower surface of the insulating film 212 formed on the lower surface 211B of the substrate 211. The external connection pad 222 is connected to the lower end of the through electrode 214. As a result, the external connection pad 222 is electrically connected to the pad 217 via the through electrode 214. The external connection pad 222 has a connection surface 222A on which the external connection terminal 206 is disposed.

  The solder resist layer 225 is provided on the insulating film 212 so as to cover the pads 216 and 217 and the wiring 218 except for the connection surfaces 216A and 217A. The solder resist layer 225 has an opening 225A that exposes the connection surface 216A and an opening 225B that exposes the connection surface 217A.

  The solder resist layer 226 is provided on the lower surface of the insulating film 212 so as to cover the external connection pads 221 and 222 excluding the connection surfaces 221A and 222A. The solder resist layer 226 has an opening 226A that exposes the connection surface 221A and an opening 226B that exposes the connection surface 222A.

  The electronic component 202 is flip-chip mounted on the pad 216. As the electronic component 202, for example, a semiconductor chip (for example, a flash memory) can be used. When the electronic component 202 is a flash memory, the amount of heat generated during operation of the electronic component 202 is, for example, 0.5 W.

  The electronic component 203 is flip-chip mounted on the pad 217. The electronic component 203 is electrically connected to the electronic component 202 via the wiring pattern 218. The electronic component 203 is an electronic component that generates a larger amount of heat during operation than the electronic component 202. As the electronic component 203, for example, a semiconductor chip (for example, a semiconductor chip for CPU) can be used. When a CPU semiconductor chip is used as the electronic component 203, the amount of heat generated during operation of the electronic component 203 is, for example, 30W.

  The external connection terminal 205 is provided on the external connection pad 221. The external connection terminal 206 is provided on the external connection pad 222. The external connection terminals 205 and 206 are terminals that are electrically connected to pads (not shown) provided on the mounting board when the semiconductor device 200 is mounted on a mounting board (not shown) such as a mother board ( For example, see Patent Document 1.)

JP 2006-135174 A

  However, the substrate 211 made of a semiconductor material easily conducts heat. Therefore, heat during operation of the electronic component 203 mounted on the wiring board 201 is conducted to the electronic component 202 through the substrate 211. As a result, there is a problem that the electronic component 202 malfunctions and a problem that the electronic component 202 cannot exhibit its original performance.

  Therefore, the present invention has been made in view of the above-described problems, and heat generated when the second electronic component that generates a larger amount of heat during operation than the first electronic component generates heat is conducted to the first electronic component. It is an object of the present invention to provide a wiring board that can prevent this from happening.

  According to one aspect of the present invention, a substrate made of a semiconductor material, a first pad provided on the first surface side of the substrate, on which a first electronic component is mounted, and a first surface of the substrate And a second pad on which a second electronic component that generates a larger amount of heat during operation than the first electronic component is mounted, and penetrates the substrate, and one end thereof is the first electronic component. A wiring board having a first through electrode electrically connected to a pad, and a second through electrode penetrating the substrate and having one end electrically connected to the second pad The first electronic component mounted on the first mounting region and the second electronic component mounted on the portion of the substrate located between the first mounting region and the second mounting region. A groove not penetrating the substrate is provided in a portion of the substrate located on the opposite side of the surface of There is provided a wiring board characterized in that a heat blocking member is provided in the groove.

  According to the present invention, heat generated from the second electronic component during operation is conducted to the first electronic component through the portion of the substrate corresponding to the first mounting region on which the first electronic component is mounted. Can be prevented.

It is sectional drawing of the conventional semiconductor device. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment of the invention; FIG. 8 is a diagram (part 2) for illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention; It is FIG. (The 3) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 4 is a diagram (part 4) illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention; It is FIG. (5) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (6) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (The 7) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (The 8) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (9) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (10) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (11) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (12) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (13) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (14) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (15) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (16) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is a figure for demonstrating the penetration groove | channel and heat insulation member provided in the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is a figure which shows the example of arrangement | positioning of a heat-shielding member. It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (3) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (4) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (5) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (6) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (The 7) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (8) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (9) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (10) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (The 3) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (4) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (5) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (6) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (The 7) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (The 8) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (9) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (10) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (11) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (12) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (13) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (14) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (15) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (3) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (4) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (5) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (6) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (The 7) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (The 8) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (3) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (4) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (5) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (6) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (The 7) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (8) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (9) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (10) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. It is FIG. (11) which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 2, the semiconductor device 10 according to the first embodiment includes a wiring board 11, an electronic component 12 (first electronic component), and an electronic component that generates a larger amount of heat during operation than the electronic component 12. 13 (second electronic component) and external connection terminals 15 and 16.

  The wiring substrate 11 includes a substrate 21, insulating films 22 and 23, through electrodes 25 and 26, a pad 28 (first pad), a pad 29 (second pad), a wiring 31, and a heat blocking member. 32, vias 33 and 34, external connection pads 36 and 37, and solder resist layers 39 and 41.

  The substrate 21 has a plate shape and is made of a semiconductor material (for example, a compound semiconductor such as silicon or GaAs). The substrate 21 has through holes 45 and 46 and a through groove 47. The through hole 45 is formed in the first mounting region where the electronic component 12 is mounted. The through hole 46 is formed in the second mounting region where the electronic component 13 is mounted. The through groove 47 is formed so as to penetrate the portion of the substrate 21 located between the first mounting region and the second mounting region. The through groove 47 is a groove for disposing the heat blocking member 32. The width A of the through groove 47 can be set to 200 μm, for example.

  As the substrate 21, for example, a compound semiconductor substrate such as a silicon substrate or GaAs can be used. When a silicon substrate is used as the substrate 21, the thickness of the substrate 21 can be set to 200 μm, for example. In the present embodiment, the following description is given by taking as an example the case where a silicon substrate is used as the substrate 21.

The insulating film 22 is provided so as to cover the upper surface 21 </ b> A (first surface) of the substrate 21 and the surface of the substrate 21 corresponding to the side surfaces of the through holes 45 and 46. As the insulating film 22, for example, a thermal oxide film, an oxide film (for example, an oxide film formed by a CVD method), or the like can be used. Specifically, for example, a SiO ₂ film can be used as the insulating film 22. When a SiO ₂ film is used as the insulating film 22, the thickness of the insulating film 22 can be set to 1 μm, for example.

The insulating film 23 is provided so as to cover the lower surface 21 </ b> B (second surface) of the substrate 21. The insulating film 23 has an opening 48 that exposes the other end of the through electrode 25 and an opening 49 that exposes the other end of the through electrode 26. As the insulating film 23, for example, an oxide film (for example, an oxide film formed by a CVD method), an insulating resin, or the like can be used. As the oxide film, for example, a SiO ₂ film can be used. The thickness of the insulating film 23 can be set to 1 μm, for example.

  The through electrode 25 is provided in the through hole 45 in which the insulating film 22 is formed. The through electrode 26 is provided in the through hole 46 in which the insulating film 22 is formed. One end surfaces 25 </ b> A and 26 </ b> A of the through electrodes 25 and 26 are substantially flush with the upper surface 22 </ b> A of the insulating film 22. The other end surfaces 25B, 26B of the through electrodes 25, 26 are substantially flush with the lower surface 21B of the substrate 21. The through electrodes 25 and 26 can be formed by, for example, a plating method. As a material of the through electrodes 25 and 26, for example, Cu can be used.

  The pad 28 is provided on the insulating film 22 formed on the upper surface 21 </ b> A of the substrate 21. The pad 28 is connected to the upper end of the through electrode 25. The pad 28 has a connection surface 28A on which the electronic component 12 is mounted.

  The pad 29 is provided on the insulating film 22 formed on the upper surface 21 </ b> A of the substrate 21. The pad 29 is connected to the upper end of the through electrode 26. The pad 29 has a connection surface 29A on which the electronic component 13 is mounted.

  The wiring 31 is provided on a portion of the insulating film 22 located between the first mounting region where the electronic component 12 is mounted and the second mounting region where the electronic component 13 is mounted. The wiring 31 has one end connected to the pad 28 and the other end connected to the pad 29.

  For example, Cu can be used as the material of the pads 28 and 29 and the wiring 31 configured as described above. The pads 28 and 29 and the wiring 31 can be formed by, for example, a semi-additive method.

  The heat blocking member 32 is provided in the through groove 47. In other words, the heat shielding member 32 is disposed so as to penetrate the portion of the substrate 21 located between the first mounting region where the electronic component 12 is mounted and the second mounting region where the electronic component 13 is mounted. Has been. One end surface 32 </ b> A of the heat shield member 32 is substantially flush with the upper surface 22 </ b> A of the insulating film 22. The other end surface 32 </ b> B of the heat blocking member 32 is substantially flush with the lower surface 21 </ b> B of the substrate 21. When the width A of the through groove 47 is 200 μm, the width B of the heat blocking member 32 can be set to 198 μm, for example.

  The heat blocking member 32 is a material (for example, having a thermal conductivity of 0.1 to 1.0 W / m · K) capable of blocking heat conducted through the substrate 21 (for example, a thermal conductivity of 150 to 170 W / m · K). Material). As a material of the heat shielding member 32, for example, a resin containing a resin or a filler (for example, silica) can be used. For example, a polyimide resin, an epoxy resin, a silicone resin, or the like can be used as the resin constituting the heat blocking member 32. When a resin containing a filler (for example, silica) is used as the heat blocking member 32, the difference in thermal expansion coefficient between the substrate 21 and the heat blocking member 32 can be reduced. For example, when a silicon substrate (thermal expansion coefficient 3 ppm / K) is used as the substrate 21, the content of the filler (silica) contained in the resin can be 50% (the thermal expansion of the heat blocking member 32 at this time). The coefficient is about 40 ppm / K.)

  In this way, by providing the heat blocking member 32 that penetrates the portion of the substrate 21 located between the first mounting region where the electronic component 12 is mounted and the second mounting region where the electronic component 13 is mounted. The heat generated by the electronic component 13 during operation can be blocked by the heat blocking member 32. Thereby, the heat generated from the electronic component 13 during operation can be prevented from being conducted to the electronic component 12 through the portion of the substrate 21 corresponding to the first mounting region.

  The via 33 is provided in the opening 48. The via 33 is connected to the other end of the through electrode 25. As a result, the via 33 is electrically connected to the pad 28 via the through electrode 25.

  The via 34 is provided in the opening 49. The via 34 is connected to the other end of the through electrode 26. As a result, the via 34 is electrically connected to the pad 29 via the through electrode 26.

  For example, Cu can be used as the material of the vias 33 and 34 configured as described above.

  The external connection pad 36 is provided on the lower surface 23 </ b> A of the insulating film 23. The external connection pad 36 is formed integrally with the via 33. The external connection pad 36 is electrically connected to the pad 28 through the via 33 and the through electrode 25. The external connection pad 36 has a connection surface 36A on which the external connection terminal 15 is disposed.

  The external connection pad 37 is provided on the lower surface 23 </ b> A of the insulating film 23. The external connection pad 37 is formed integrally with the via 34. The external connection pad 37 is electrically connected to the pad 29 through the via 34 and the through electrode 26. The external connection pad 37 has a connection surface 37A on which the external connection terminal 16 is disposed.

  The solder resist layer 39 is provided on the upper surface 22 </ b> A of the insulating film 22 and the wiring 31. The solder resist layer 39 has an opening 39A that exposes the connection surface 28A of the pad 28 and an opening 39B that exposes the connection surface 29A of the pad 29.

  The solder resist layer 41 is provided on the lower surface 23 </ b> A of the insulating film 23. The solder resist layer 41 has an opening 41A exposing the connection surface 36A of the external connection pad 36 and an opening 41B exposing the connection surface 37A of the external connection pad 37.

  The electronic component 12 is flip-chip mounted on the pad 28 formed in the first mounting region. An underfill resin 17 is filled in the gap between the electronic component 12 and the wiring board 11. As the electronic component 12, for example, a semiconductor chip (for example, a flash memory) having a heat generation amount of 1 W or less during operation can be used.

  The electronic component 13 is flip-chip mounted on the pad 29 formed in the second mounting region. An underfill resin 18 is filled in the gap between the electronic component 13 and the wiring board 11. The electronic component 13 is an electronic component that generates a larger amount of heat during operation than the electronic component 12. The electronic component 13 is, for example, an electronic component that generates 20 W or more during operation. As the electronic component 13, for example, a semiconductor chip for CPU can be used.

  The external connection terminal 15 is provided on the connection surface 36 </ b> A of the external connection pad 36. The external connection terminal 15 is electrically connected to the electronic component 12. The external connection terminal 15 is a terminal connected to a pad (not shown) provided on a mounting board such as a mother board. As the external connection terminal 15, for example, a solder ball can be used.

  The external connection terminal 16 is provided on the connection surface 37 A of the external connection pad 37. The external connection terminal 16 is electrically connected to the electronic component 13. The external connection terminal 16 is a terminal connected to a pad (not shown) provided on a mounting board such as a mother board. For example, a solder ball can be used as the external connection terminal 16.

  According to the wiring board of the present embodiment, the heat penetrating through the portion of the substrate 21 located between the first mounting area where the electronic component 12 is mounted and the second mounting area where the electronic component 13 is mounted. By providing the blocking member 32, it is possible to block the heat generated from the electronic component 13 during operation by the heat blocking member 32. Thereby, the heat generated from the electronic component 13 during operation can be prevented from being conducted to the electronic component 12 through the portion of the substrate 21 corresponding to the first mounting region.

  According to the semiconductor device of the present embodiment, the provision of the wiring board 11 having the above configuration prevents the electronic component 12 from malfunctioning due to heat generated from the electronic component 13 during operation. Performance can be demonstrated.

  3 to 18 are views showing manufacturing steps of the semiconductor device according to the first embodiment of the present invention. 3 to 18, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.

  A method for manufacturing the semiconductor device 10 according to the first embodiment will be described with reference to FIGS. First, in the step shown in FIG. 3, a base material 55 having a plurality of substrate forming regions C on which the substrate 21 (one of the components of the wiring board 11 described above) is formed is prepared (base material preparation step). ).

  The base material 55 has a cutting region D surrounding the plurality of substrate forming regions C. The cutting region D is a region that is cut when the semiconductor device 10 is separated after the structure corresponding to the semiconductor device 10 is formed in the plurality of substrate forming regions C.

  As the material of the base material 55, the same material as that of the substrate 21 is used. As a material of the base material 55, for example, a semiconductor material (for example, a compound semiconductor such as silicon or GaAs) can be used. At this stage, the base material 55 is thicker than the substrate 21. When the thickness of the substrate 21 made of silicon is 200 μm, the thickness of the base material 55 can be set to 725 μm, for example. In the present embodiment, the following description will be given by taking as an example the case where a silicon wafer is used as the substrate 55.

  Next, in the step shown in FIG. 4, an opening 57 (first opening) corresponding to the formation position of the through electrode 25 is formed on the base 55 from the upper surface 55 </ b> A (first surface of the base 55) side of the base 55. Part), the opening 58 (second opening) corresponding to the formation position of the through electrode 26, and the groove 59 are simultaneously formed (opening and groove forming step).

  At this time, the openings 57 and 58 and the groove 59 are formed so as not to penetrate the base material 55. The openings 57 and 58 and the groove 59 can be formed by, for example, anisotropic etching (for example, dry etching) using a mask. The depths of the openings 57 and 58 and the groove 59 are substantially equal, and can be, for example, 220 μm. The groove 59 is formed in a portion of the base material 55 located between the first mounting area where the electronic component 12 is mounted and the second mounting area where the electronic component 13 is mounted. The width E of the groove 59 can be set to 200 μm, for example.

  The opening 57 is an opening that becomes the through hole 45 shown in FIG. 2 by thinning the substrate 55 in the substrate thinning step shown in FIG. Further, the opening 58 is an opening that becomes the through hole 46 shown in FIG. 2 by thinning the substrate 55 in the substrate thinning step shown in FIG. The groove 59 is a groove that becomes the through groove 47 shown in FIG. 2 by thinning the substrate 55 in the substrate thinning step shown in FIG.

  Thus, by forming the groove 59 serving as the through groove 47 in which the heat blocking member 32 is disposed simultaneously with the openings 57 and 58 serving as the through holes 45 and 46, the groove 59 and the openings 57 and 58 are formed. The manufacturing cost of the wiring board 11 can be reduced as compared with the case where these are formed separately.

  Next, in the process shown in FIG. 5, the surface of the base material 55 on which the openings 57 and 58 and the groove 59 are formed (both surfaces 55 </ b> A and 55 </ b> B of the base material 55 and the portions constituting the openings 57 and 58 and the groove 59. Insulating film 22 is formed to cover (including the surface of base material 55).

As the insulating film 22, for example, a thermal oxide film, an oxide film formed by a CVD method, or the like can be used. Specifically, for example, a SiO ₂ film can be used as the insulating film 22. When a SiO ₂ film is used as the insulating film 22, the thickness of the insulating film 22 can be set to 1 μm, for example.

  Next, in the step shown in FIG. 6, a mask 61 having a through groove 61 </ b> A exposing the groove 59 is formed on the upper surface 22 </ b> A of the insulating film 22. Specifically, for example, a mask 61 is formed by attaching a film resist to the upper surface 22A of the insulating film 22, and then laser processing the formation region of the through groove 61A. The thickness of the mask 61 can be set to 20 μm, for example.

  Next, in the process shown in FIG. 7, the heat shielding member 32 is formed by filling the groove 59 with resin (a base material of the heat shielding member 32) by, for example, squeegee printing. In addition, resin which comprises the heat | fever interruption | blocking member 32 is hardened by heat-processing as needed.

  At this time, since the opening 61A of the mask 61 is also filled with the resin, it is necessary to remove the excess heat blocking member 32 in the process shown in FIG.

  As the resin, for example, a resin capable of interrupting heat (for example, a thermal conductivity of 0.1 to 1.0 W / m · K) can be used. Specifically, as the resin, for example, a polyimide resin, an epoxy resin, a silicone resin, or the like can be used. In addition, you may make a resin contain a filler (for example, silica). When the resin contains a filler (for example, silica), the difference in thermal expansion coefficient between the substrate 21 and the heat blocking member 32 can be reduced. For example, when a silicon substrate (thermal expansion coefficient 3 ppm / K) is used as the substrate 21, the content of the filler (silica) contained in the resin can be 50%.

  Next, in the step shown in FIG. 8, the mask 61 shown in FIG. 7 is removed. Specifically, for example, the mask 61 is removed using an amine-based stripping solution.

  Next, in a step shown in FIG. 9, a conductive member 65 that is a base material of the through electrodes 25 and 26 is formed in the openings 57 and 58 (conductive member forming step). Specifically, for example, a seed layer is formed by a sputtering method, and then a conductive plating member 65 is formed by depositing and growing a Cu plating film by an electroplating method by a semi-additive method, or an opening is formed by a printing method. The conductive member 65 is formed by filling the portions 57 and 58 with a conductive paste (for example, Cu paste, Ag paste, Ni paste, etc.). At this time, the conductive member 65 may protrude from the upper surface 22 </ b> A of the insulating film 22.

  Next, in the step shown in FIG. 10, the conductive member 65 and / or the heat shielding member 32 protruding from the upper surface 22A of the insulating film 22 are removed (conductive member and / or heat shielding member removing step). Specifically, the unnecessary conductive member 65 and / or the heat shielding member 32 protruding from the upper surface 22A of the insulating film 22 are removed by grinding or polishing.

  Thereby, the end surface 25A of the conductive member 65 formed in the first mounting region, the end surface 26A of the conductive member 65 formed in the second mounting region, the end surface 32A of the heat shielding member 32, and the upper surface 22A of the insulating film 22 are formed. Therefore, the pads 28 and 29 and the wiring 31 can be formed on the upper surface side of the structure shown in FIG.

  In the conductive member and / or heat shield member removal step, when the heat shield member 32 is removed, the insulating film 22 formed on the upper surface 55A of the base material 55 may be removed. The following description is given by taking the case where the film 22 remains as an example. In addition, in the conductive member and / or heat shielding member removing step, when the insulating film 22 is lost, it is necessary to form an insulating film separately. In this case, an insulating film is separately formed by performing a process similar to the process shown in FIG. 42 described in a third embodiment to be described later.

  Next, in the step shown in FIG. 11, the pads 28 and 29 and the wiring 31 are simultaneously formed on the upper surface side of the structure shown in FIG. 10 (pad forming step). Specifically, a seed layer is formed by a sputtering method, and then the pads 28 and 29 and the wiring 31 are formed by a semi-additive method. As a material of the pads 28 and 29 and the wiring 31, for example, Cu can be used.

  Next, in a step shown in FIG. 12, a solder resist layer 39 having an opening 39A that exposes the connection surface 28A and an opening 39B that exposes the connection surface 29A is formed on the upper surface 22A of the insulating film 22.

  Next, in the process illustrated in FIG. 13, the base material 55 is exposed from the surface 55 </ b> B (second surface of the base material 55) side of the base material 55 illustrated in FIG. 12 until the lower ends of the conductive member 65 and the heat shielding member 32 are exposed. Is formed to form the heat shielding member 32 that penetrates the thinned base material 55 and the through electrodes 25 and 26 (substrate thinning step).

  Specifically, the substrate 55 is thinned by grinding or polishing. At this time, the insulating film 22 formed on the lower surface 55B side of the substrate 55 is removed, and the end surfaces 25B and 26B of the through electrodes 25 and 26 and the end surface 32B of the heat shielding member 32 and the lower surface 55B of the substrate 55 thinned. Is substantially the same. The thickness of the thinned base material 55 can be set to 200 μm, for example.

  In this way, the heat shield that penetrates the base material 55 in the portion of the base material 55 located between the first mounting region and the second mounting region and blocks heat generated from the electronic component 13 during operation. By forming the member 32, heat generated from the electronic component 13 during operation can be prevented from being conducted to the electronic component 12 through the portion of the substrate 21 corresponding to the first mounting region.

Next, in the step shown in FIG. 14, the lower surface 55B of the base 55 shown in FIG. 13 has an opening 48 that exposes the end surface 25B of the through electrode 25 and an opening 49 that exposes the end surface 26B of the through electrode 26. The insulating film 23 thus formed is formed. As the insulating film 23, for example, an oxide film (for example, SiO ₂ film) formed by a CVD method, an insulating resin layer, or the like can be used. The thickness of the insulating film 22 can be set to 1 μm, for example. The openings 48 and 49 can be formed by, for example, anisotropic etching (for example, dry etching) using a mask or laser processing.

  Next, in the step shown in FIG. 15, vias 33 and 34 and external connection pads 36 and 37 are simultaneously formed on the lower surface side of the structure shown in FIG. 14 (external connection pad forming step).

  Specifically, for example, a seed layer is formed by a sputtering method, and then vias 33 and 34 and external connection pads 36 and 37 are formed by a semi-additive method. As a material for the vias 33 and 34 and the external connection pads 36 and 37, for example, Cu can be used.

  Next, in a step shown in FIG. 16, a solder resist layer 41 having an opening 41A exposing the connection surface 36A and an opening 41B exposing the connection surface 37A is formed on the lower surface 23A of the insulating film 23. Thereby, the wiring substrate 11 is formed in the plurality of substrate forming regions C.

  Next, in the step shown in FIG. 17, the electronic components 12 and 13 are flip-chip mounted on the pads 28 and 29 of the wiring board 11, and then the gap between the electronic component 12 and the wiring board 11 is filled with the underfill resin 17. An underfill resin 18 is filled in the gap between the electronic component 13 and the wiring board 11. Next, the external connection terminals 15 are disposed on the external connection pads 36, and the external connection terminals 16 are disposed on the external connection pads 37. Thereby, the semiconductor device 10 is manufactured in the plurality of substrate formation regions C.

  Next, in the step shown in FIG. 18, the structure shown in FIG. 17 is cut along the cutting region D to singulate a plurality of semiconductor devices 10 (cutting step).

  According to the method for manufacturing the wiring board of the present embodiment, the first and second openings 57 and 58 that do not penetrate through the base material 55 and the electronic component 12 are mounted on the base material 55 from the upper surface 55A side of the base material 55. A heat blocking member that is located between the mounting region and the second mounting region on which the electronic component 13 is mounted and that simultaneously forms a groove 59 that does not penetrate the base material 55, and then blocks heat from the groove 59. 32, and then, the conductive member 65 serving as the base material of the through electrodes 25 and 26 is formed in the openings 57 and 58, and then the pads 28 and 29 are formed. Thereafter, from the lower surface 55B side of the base 55 By forming the through electrodes 25 and 26 by thinning the base material 55 until the conductive member 65 and the heat shielding member 32 are exposed, the portion located between the first mounting region and the second mounting region The substrate 55 penetrates the substrate 55 and operates. Since the heat blocking member 32 that blocks the heat generated from the electronic component 13 is formed in the electronic component 13, the heat generated from the electronic component 13 during operation passes through the portion of the substrate 21 corresponding to the first mounting region. 12 can be prevented from being conducted.

  FIG. 19 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment of the present invention, and FIG. 20 is provided in the semiconductor device according to a modification of the first embodiment of the present invention. It is a figure for demonstrating a penetration groove and a heat insulation member. In FIG. 19, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals. In FIG. 20, F is a first mounting area where the electronic component 12 is mounted (hereinafter referred to as “first mounting area F”), and G is a second mounting area where the electronic component 13 is mounted (hereinafter referred to as “first mounting area F”). , “Second mounting area G”).

  Referring to FIGS. 19 and 20, a semiconductor device 70 according to a modification of the first embodiment is provided with a wiring board 71 instead of the wiring board 11 provided in the semiconductor device 10 of the first embodiment. The configuration is the same as that of the semiconductor device 10 except that is provided.

  The wiring substrate 71 is configured in the same manner as the wiring substrate 11 except that a through groove 73 and a heat blocking member 74 are provided instead of the through groove 47 and the heat blocking member 32 provided in the wiring substrate 11.

  The through groove 73 is formed in the substrate 21 so as to continuously surround the portion of the substrate 21 corresponding to the second mounting region G. The through groove 73 has a frame shape. The width A of the through groove 73 can be set to 200 μm, for example.

  The heat blocking member 74 is provided in the through groove 73. The heat blocking member 74 has the same configuration as the heat blocking member 32 described above except that the shape thereof is a frame shape.

  According to the wiring board according to the modification of the present embodiment, the substrate 21 is formed with the through groove 73 that continuously surrounds the portion of the substrate 21 corresponding to the second mounting region G, and the through groove 73 has a frame shape. By providing the heat blocking member 73, the heat generated from the electronic component 13 during operation is not conducted to a region other than the second mounting region G. Therefore, the heat generated from the electronic component 13 during operation is reduced. It is possible to prevent conduction to the electronic component 12 through the portion of the substrate 21 corresponding to the first mounting region F.

  Note that the wiring board 71 according to the modification of the first embodiment can be manufactured by the same method as the wiring board 11 of the first embodiment described above.

  FIG. 21 is a diagram illustrating an arrangement example of the heat blocking members.

  As shown in FIG. 21, a plurality of the heat shielding members 32 described in FIG. 2 may be arranged so as to surround the second mounting region G. In this case, the same effect as that of the wiring board 71 according to the modification of the first embodiment can be obtained.

(Second Embodiment)
FIG. 22 is a sectional view of a semiconductor device according to the second embodiment of the present invention. In FIG. 22, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.

  Referring to FIG. 22, the semiconductor device 80 according to the second embodiment is the same as the semiconductor device except that a wiring substrate 81 is provided instead of the wiring substrate 11 provided in the semiconductor device according to the first embodiment. 10 is configured in the same manner.

  The wiring substrate 81 is configured in the same manner as the wiring substrate 11 except that the portion of the insulating film 22 formed on the side surface of the through groove 47 provided in the wiring substrate 11 is excluded from the constituent elements. That is, the side surface of the through groove 47 and the side wall of the heat shielding member 32 having insulation properties are in contact with each other.

  The wiring board 81 of the second embodiment configured as described above can obtain the same effects as the wiring board 11 of the first embodiment.

  23 to 32 are views showing manufacturing steps of the semiconductor device according to the second embodiment of the present invention. 23 to 32, the same components as those of the semiconductor device 80 according to the second embodiment are denoted by the same reference numerals.

  A method for manufacturing the semiconductor device 80 according to the second embodiment will be described with reference to FIGS. First, the base material 55 shown in FIG. 3 described in the first embodiment is prepared (base material preparation step). Next, in the step shown in FIG. 23, the first mounting region on which the electronic component 12 is mounted and the electronic component 13 are mounted from the upper surface 55A side of the substrate 55 shown in FIG. 3 described in the first embodiment. A groove 59 that does not penetrate through the base material 55 is formed in a portion of the base material 55 located between the second mounting region (groove forming step).

  The groove 59 is formed by, for example, anisotropic etching (for example, dry etching) using a mask. The groove 59 is a groove that becomes the through groove 47 shown in FIG. 22 by thinning the base material 55 in the base material thinning step shown in FIG. 29 described later. The depth of the groove 59 can be set to 220 μm, for example. The width E of the groove 59 can be set to 200 μm, for example.

  Next, in the process shown in FIG. 24, the same process as the process shown in FIGS. 6 to 8 and 10 described in the first embodiment is sequentially performed, so that the upper surface 55 </ b> A of the base material 55 is formed in the groove 59. The heat shielding member 32 having the end face 32A that is substantially flush is formed (heat shielding member forming step).

  Next, in the step shown in FIG. 25, from the upper surface 55A side of the base material 55, an opening 57 corresponding to the formation position of the through electrode 25 and an opening 58 corresponding to the formation position of the through electrode 26 are formed on the base material 55. Are simultaneously formed (opening forming step).

  At this time, the openings 57 and 58 are formed so as not to penetrate the base material 55. The openings 57 and 58 can be formed by, for example, anisotropic etching (for example, dry etching) using a mask. The depth of the openings 57 and 58 can be set to 220 μm, for example.

  The opening 57 is an opening that becomes the through hole 45 shown in FIG. 22 by thinning the substrate 55 in the substrate thinning step shown in FIG. 29 described later. In addition, the opening 58 is an opening that becomes the through hole 46 shown in FIG. 22 by thinning the base 55 in the substrate thinning step shown in FIG. 29 described later.

Next, in the process shown in FIG. 26, the surface of the base material 55 on which the openings 57 and 58 are formed (specifically, the bases 55A and 55B of the base material 55 and the bases of the portions constituting the openings 57 and 58). The insulating film 22 covering the surface of the material 55 is formed. As the insulating film 22, for example, an oxide film (for example, SiO ₂ film) formed by a CVD method can be used. The thickness of the insulating film 22 can be set to 1 μm, for example.

  Next, in the step shown in FIG. 27, by performing the same process as the step shown in FIG. 9 described in the first embodiment, a conductive member that becomes a base material of the through electrodes 25 and 26 in the openings 57 and 58. 65 is formed (conductive member forming step), and then the portion of the conductive member 65 protruding from the upper surface 22A of the insulating film 22 is removed (conductive member removing step). The portion of the conductive member 65 protruding from the upper surface 22A of the insulating film 22 is removed by polishing, for example. In the step shown in FIG. 27, since the polishing is performed using a polishing liquid capable of removing only the conductive member 65, the insulating film 22 formed on the upper surface 55A of the base 55 is not polished.

  Next, in the step shown in FIG. 28, by performing the same process as the step shown in FIG. 11 described in the first embodiment, the pads 28 and 29 and the wiring 31 are formed on the upper surface side of the structure shown in FIG. Are simultaneously formed (pad forming step), and then a solder resist layer 39 having an opening 39A exposing the connection surface 28A and an opening 39B exposing the connection surface 29A is formed on the upper surface 22A of the insulating film 22. To do.

  Next, in the step shown in FIG. 29, the conductive member 65 and the heat are heated from the surface 55B side of the substrate 55 shown in FIG. 28 by performing the same process as the step shown in FIG. 13 described in the first embodiment. The substrate 55 is thinned until the lower end of the shielding member 32 is exposed, and the heat shielding member 32 that penetrates the thinned substrate 55 and the through electrodes 25 and 26 are formed (substrate thinning step). The thickness of the thinned base material 55 can be set to 200 μm, for example.

  In this way, the heat shield that penetrates the base material 55 in the portion of the base material 55 located between the first mounting region and the second mounting region and blocks heat generated from the electronic component 13 during operation. By forming the member 32, heat generated from the electronic component 13 during operation can be prevented from being conducted to the electronic component 12 through the portion of the substrate 21 corresponding to the first mounting region.

  Next, in the process shown in FIG. 30, an insulating film is obtained by performing the same process as the process shown in FIGS. 14 to 16 (process including the “external connection pad forming process”) described in the first embodiment. 23, vias 33 and 34, external connection pads 36 and 37, and a solder resist layer 41 are formed. Thereby, the wiring substrate 81 is formed in the plurality of substrate forming regions C.

  Next, in the process shown in FIG. 31, the electronic components 12 and 13 are flip-chip mounted on the pads 28 and 29 of the wiring board 81, and then the gap between the electronic component 12 and the wiring board 11 is filled with the underfill resin 17. The underfill resin 18 is filled in the gap between the electronic component 13 and the wiring board 81. Next, the external connection terminals 15 are disposed on the external connection pads 36, and the external connection terminals 16 are disposed on the external connection pads 37. Thereby, the semiconductor device 80 is manufactured in the plurality of substrate formation regions C.

  Next, in the step shown in FIG. 32, the structure shown in FIG. 31 is cut along the cutting region D, thereby dividing the plurality of semiconductor devices 80 into pieces (cutting step).

  According to the method for manufacturing a wiring board of the present embodiment, a portion of the base material 55 located between the first mounting region where the electronic component 12 is mounted and the second mounting region where the electronic component 13 is mounted. Next, a groove 59 that does not penetrate the base material 55 is formed from the upper surface 55A side of the base material 55, and then a heat blocking member 32 that shields heat is formed in the groove 59, and then from the surface 55A side of the base material 55 Openings 57 and 58 that correspond to the formation positions of the through electrodes 25 and 26 and do not penetrate the base material 55 are simultaneously formed in the base material 55, and then the base materials of the through electrodes 25 and 26 are formed in the openings 57 and 58. Then, the pads 28 and 29 are formed, and then the substrate 55 is thinned from the surface 55B side of the substrate 55 until the lower ends of the conductive member 65 and the heat shielding member 32 are exposed. By doing so, the first mounting area and the second actual Since the heat shielding member 32 that penetrates the base material 55 and shields the heat generated from the electronic component 13 during operation is formed in the base material 55 that is located between the electronic component 13 and the region. The generated heat can be prevented from being conducted to the electronic component 12 through the portion of the substrate 21 corresponding to the first mounting region.

  In place of the heat blocking member 32 provided on the wiring board 81 of the present embodiment, the heat blocking member 74 described in FIG. 20 of the first embodiment, or FIG. 21 of the first embodiment. A plurality of the heat shielding members 32 described may be provided.

(Third embodiment)
FIG. 33 is a sectional view of a semiconductor device according to the third embodiment of the present invention. In FIG. 33, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.

  Referring to FIG. 33, the semiconductor device 90 of the third embodiment is similar to the semiconductor device 10 except that a wiring substrate 91 is provided instead of the wiring substrate 11 provided in the semiconductor device 10 of the first embodiment. It is configured in the same way.

  The wiring board 91 is provided with insulating films 93 and 94 instead of the insulating films 22 and 23 provided on the wiring board 11 and vias 96 and 97, thereby forming vias 33 and 34 provided on the wiring board 11. The configuration is the same as that of the wiring substrate 11 except for the elements.

The insulating film 93 is provided on the upper surface 21 </ b> A of the substrate 21, and has an opening 93 </ b> A that exposes the end face 25 </ b> A of the through electrode 25 and an opening 93 </ b> B that exposes the end face 26 </ b> A of the through electrode 26. Pads 28 and 29 and a wiring 31 are formed on the upper surface of the insulating film 93. As the insulating film 93, for example, an oxide film (for example, a SiO ₂ film) formed by a CVD method, a resin layer (for example, a resin layer made of an epoxy resin or a polyimide resin), or the like can be used. The thickness of the insulating film 93 can be set to 1 μm, for example. The openings 93A and 93B can be formed by, for example, anisotropic etching (for example, dry etching) using a mask or laser processing.

The insulating film 94 is provided on the lower surface 21 </ b> B of the substrate 21. The lower surface 94A of the insulating film 94 and the end surfaces 25B and 26B of the through electrodes 25 and 26 are substantially flush with each other. As the insulating film 93, for example, a thermal oxide film or an oxide film (for example, SiO ₂ film) formed by a CVD method can be used. The thickness of the insulating film 94 can be set to 1 μm, for example.

  The via 96 is provided in the opening 93A. The via 96 is formed integrally with the pad 28 formed above the via 96. A lower end portion of the via 96 is connected to the through electrode 25. Thus, the pad 28 is electrically connected to the through electrode 25 through the via 96.

  The via 97 is provided in the opening 93B. The via 97 is formed integrally with a pad 29 formed above the via 97. A lower end portion of the via 97 is connected to the through electrode 26. As a result, the pad 29 is electrically connected to the through electrode 26 via the via 97. As a material of the vias 96 and 97, for example, Cu can be used.

  The external connection pad 36 is connected to the lower end portion of the through electrode 25. The external connection pad 37 is connected to the lower end portion of the through electrode 26.

  The wiring board 91 of the third embodiment having the above configuration can obtain the same effects as the wiring board 11 of the first embodiment.

  In place of the heat blocking member 32 provided in the semiconductor device 90 of the present embodiment, the heat blocking member 74 described in FIG. 20 of the first embodiment, or FIG. 21 of the first embodiment. A plurality of the heat shielding members 32 described may be provided.

  34 to 48 are views showing manufacturing steps of the semiconductor device according to the third embodiment of the present invention. 34 to 48, the same components as those of the semiconductor device 90 according to the third embodiment are denoted by the same reference numerals.

  A manufacturing method of the semiconductor device 90 according to the third embodiment will be described with reference to FIGS. First, in the step shown in FIG. 34, a thinned base material 55 having a plurality of substrate forming regions C on which the substrate 21 is formed is prepared (base material preparation step).

  The base material 55 has a cutting region D surrounding the plurality of substrate forming regions C. The base material 55 shown in FIG. 34 can be formed, for example, by thinning the base material 55 shown in FIG. 3 described in the first embodiment. The thickness of the thinned base material 55 can be set to 220 μm, for example.

  Next, in the step shown in FIG. 35, the through hole 45 (first through hole) corresponding to the formation position of the through electrode 25 and the formation position of the through electrode 26 are formed in the base material 55 from the upper surface 55A side of the base material 55. The through hole 46 (second through hole) corresponding to the above and the through groove 47 are formed simultaneously (through hole and through groove forming step).

  At this time, the through holes 45 and 46 and the through groove 47 are formed so as to penetrate the base material 55. The through holes 45 and 46 and the through groove 47 can be formed by, for example, anisotropic etching (for example, dry etching) using a mask. The depths of the through holes 45 and 46 and the through groove 47 are substantially equal to the thickness of the base material 55, and can be set to 220 μm, for example. The through-groove 47 is formed in a portion of the base material 55 located between the first mounting area where the electronic component 12 is mounted and the second mounting area where the electronic component 13 is mounted. The width A of the through groove 47 can be set to 200 μm, for example.

Next, in the step shown in FIG. 36, the surface of the base material 55 on which the through holes 45 and 46 and the through grooves 47 are formed (both surfaces 55A and 55B of the base material 55 and the through holes 45 and 46 and the through grooves 47 are formed. Insulating film 94 is formed so as to cover the surface of part of the base material 55. As the insulating film 94, for example, a thermal oxide film or an oxide film (for example, SiO ₂ film) formed by a CVD method can be used. The thickness of the insulating film 94 can be set to 1 μm, for example.

  Next, in the step shown in FIG. 37, the mask 61 shown in FIG. 6 of the first embodiment is formed on the upper surface 94B of the insulating film 94, and the through holes 45 and 46 and the through holes are formed on the lower surface 94A of the insulating film 94. A film 101 that closes the groove 47 is attached. As the film 101, for example, a dry film resist can be used. When a dry film resist is used as the film 101, the thickness of the film 101 can be set to 50 μm, for example.

  Next, in the step shown in FIG. 38, the heat blocking member 32 is formed by filling the through groove 47 with resin (base material of the heat blocking member 32) by, for example, squeegee printing (heat blocking member forming step). .

  At this time, the opening 61A of the mask 61 is also filled with resin. As the resin, for example, a resin capable of interrupting heat (for example, a thermal conductivity of 0.1 to 1.0 W / m · K) can be used. Specifically, as the resin, for example, a polyimide resin, an epoxy resin, a silicone resin, or the like can be used. In addition, you may make a resin contain a filler (for example, silica). When the resin contains a filler (for example, silica), the difference in thermal expansion coefficient between the substrate 21 and the heat blocking member 32 can be reduced. For example, when a silicon substrate (thermal expansion coefficient 3 ppm / K) is used as the substrate 21, the content of the filler (silica) contained in the resin can be 50%.

  Next, in the step shown in FIG. 39, the mask 61 and the film 101 shown in FIG. 38 are removed. When a dry film resist is used as the mask 61 and the film 101, for example, the mask 61 and the film 101 are simultaneously removed with an amine-based stripping solution.

  Next, in the step shown in FIG. 40, the same process as the step shown in FIG. 9 described in the first embodiment is performed, so that the conductive member that becomes the base material of the through electrodes 25 and 26 in the through holes 45 and 46 is obtained. 65 is formed. At this time, the conductive member 65 may protrude from the upper surface 94B of the insulating film 94. In the present embodiment, the following description will be given by taking as an example the case where the conductive member 65 protrudes from the upper surface 94B of the insulating film 94.

  Next, in the step shown in FIG. 41, the conductive member 65 and the heat shield member 32 protruding from the upper surface 94B of the insulating film 94 are removed (conductive member and / or heat shield member removal step). Specifically, the unnecessary conductive member 65 and / or the heat shielding member 32 protruding from the upper surface 94B of the insulating film 94 are removed by grinding or polishing.

  Thereby, the heat shielding member 32 penetrating the base material 55 and the through electrodes 25 and 26 are formed (the step shown in FIGS. 40 and 41 corresponds to the “through electrode forming step”). Further, by removing the portions of the conductive member 65 and the heat blocking member 32 protruding from the upper surface 94B of the insulating film 94, the end surface 32A of the heat blocking member 32 and the end surfaces 25A and 26A of the through electrodes 25 and 26 and the base material 55 are removed. The upper surface 55A is substantially flush. The end surface 32B of the heat shield member 32, the end surfaces 25B and 26B of the through electrodes 25 and 26, and the lower surface 94A of the insulating film 94 are substantially flush.

  In this way, the heat shield that penetrates the base material 55 in the portion of the base material 55 located between the first mounting region and the second mounting region and blocks heat generated from the electronic component 13 during operation. By forming the member 32, heat generated from the electronic component 13 during operation can be prevented from being conducted to the electronic component 12 through the portion of the substrate 21 corresponding to the first mounting region.

42, an insulating film 93 having openings 93A and 93B is formed on the upper surface 55A of the base material 55 shown in FIG. As the insulating film 93, for example, an oxide film (for example, SiO ₂ film) formed by a CVD method, an insulating resin layer, or the like can be used. The thickness of the insulating film 93 can be set to 1 μm, for example. The openings 93A and 93B can be formed by, for example, anisotropic etching (for example, dry etching) using a mask or laser processing.

  Next, in the step shown in FIG. 43, vias 96 and 97, pads 28 and 29, and wirings 31 are simultaneously formed on the upper surface side of the structure shown in FIG. 42 (pad forming step). Specifically, for example, a seed layer is formed by a sputtering method, and then vias 96 and 97, pads 28 and 29, and a wiring 31 are simultaneously formed by a semi-additive method. As a material of the vias 96 and 97, the pads 28 and 29, and the wiring 31, for example, Cu can be used.

  Next, in a step shown in FIG. 44, a solder resist layer 39 having an opening 39A exposing the connection surface 28A and an opening 39B exposing the connection surface 29A is formed on the upper surface of the insulating film 93.

  45, external connection pads 36 and 37 are formed on the lower surface 94A of the insulating layer 94 (external connection pad forming step). Specifically, for example, a seed layer is formed by a sputtering method, and then external connection pads 36 and 37 are formed by a semi-additive method. As a material of the external connection pads 36 and 37, for example, Cu can be used.

  46, a solder resist layer 41 having an opening 41A exposing the connection surface 36A and an opening 41B exposing the connection surface 37A is formed on the lower surface 94A of the insulating film 94. Thereby, the wiring substrate 91 is formed in the plurality of substrate forming regions C.

  Next, in the step shown in FIG. 47, the electronic components 12 and 13 are flip-chip mounted on the pads 28 and 29 of the wiring board 91, and then the gap between the electronic component 12 and the wiring board 91 is filled with the underfill resin 17; An underfill resin 18 is filled in a gap between the electronic component 13 and the wiring board 91. Next, the external connection terminals 15 are disposed on the external connection pads 36, and the external connection terminals 16 are disposed on the external connection pads 37. Thereby, the semiconductor device 90 is manufactured in the plurality of substrate formation regions C.

  Next, in the step shown in FIG. 48, the structure shown in FIG. 47 is cut along the cutting region D to singulate a plurality of semiconductor devices 90 (cutting step).

  According to the method for manufacturing a wiring board of the present embodiment, the through-holes 45 and 46 penetrating the base material 55 and the electronic component 12 are mounted on the base material 55 corresponding to the formation positions of the through electrodes 25 and 26. A through-groove 47 that is located between the first mounting area and the second mounting area on which the electronic component 13 is mounted and penetrates the base material 55 is formed at the same time. The heat blocking member 32 for blocking heat is formed, then the through holes 45 and 46 are filled with a conductive member to form the through electrodes 25 and 26, and then the pads 28 and 29 are formed, thereby forming the electronic component 12 Is generated from the electronic component 13 during operation while penetrating through the base material 55 in a portion located between the first mounting region where the electronic component 13 is mounted and the second mounting region where the electronic component 13 is mounted. The heat blocking member 32 that blocks the heat to be formed is formed. Because the heat generated from the electronic component 13 during operation, through the substrate 21 of the portion corresponding to the first mounting area, can be prevented from being conducted to the electronic component 12.

(Fourth embodiment)
FIG. 49 is a sectional view of a semiconductor device according to the fourth embodiment of the present invention. In FIG. 49, the same components as those of the semiconductor device 90 of the third embodiment are denoted by the same reference numerals.

  Referring to FIG. 49, the semiconductor device 110 according to the fourth embodiment is similar to the semiconductor device 90 except that a wiring substrate 111 is provided instead of the wiring substrate 91 provided in the semiconductor device 90 according to the third embodiment. It is configured in the same way.

  The wiring board 111 is provided with insulating films 115 and 116 instead of the insulating films 93 and 94 provided on the wiring board 91, and the vias 96 and 97 provided on the wiring board 91 are removed from the constituent elements, and the through holes 118, 119, and the heat blocking member 32 is further provided between the side surfaces of the through holes 45 and 46 and the through electrodes 25 and 26.

The insulating film 115 is provided on the upper surface 21 </ b> A of the substrate 21. The insulating film 115 covers the side surfaces of the upper end portions of the through electrodes 25 and 26. The upper surface 115A of the insulating film 115 and the end surfaces 25A and 26A of the through electrodes 25 and 26 are substantially flush with each other. Pads 28 and 29, wirings 31, and a solder resist layer 39 are provided on the upper surface 115 </ b> A of the insulating film 115. As the insulating film 115, for example, an oxide film (for example, SiO ₂ film) formed by a CVD method, a resin layer (for example, a resin layer made of an epoxy resin or a polyimide resin), or the like can be used. The thickness of the insulating film 115 can be set to 5 μm to 10 μm, for example.

The insulating film 116 is provided on the lower surface 21 </ b> B of the substrate 21. The insulating film 116 covers the side surfaces of the lower end portions of the through electrodes 25 and 26. The lower surface 116A of the insulating film 116 and the end surfaces 25B and 26B of the through electrodes 25 and 26 are substantially flush with each other. External connection pads 36 and 37 and a solder resist layer 41 are provided on the lower surface 116A of the insulating film 116. As the insulating film 116, for example, an oxide film (for example, SiO ₂ film) formed by a CVD method, a resin layer (for example, a resin layer made of an epoxy resin or a polyimide resin), or the like can be used. The thickness of the insulating film 116 can be set to 5 μm to 10 μm, for example.

  The portion of the heat blocking member 32 provided between the side surfaces of the through holes 45 and 46 and the through electrodes 25 and 26 is for electrically insulating the substrate 21 and the through electrodes 25 and 26. . The portion of the heat blocking member 32 provided between the side surfaces of the through holes 45 and 46 and the through electrodes 25 and 26 is made of the same insulating material as the heat blocking member 32 provided in the through groove 47. ing. The thickness of the heat blocking member 32 at a portion provided between the side surfaces of the through holes 45 and 46 and the through electrodes 25 and 26 can be set to 20 μm, for example.

  The through hole 118 is formed so as to penetrate through the insulating layers 115 and 116 and the heat blocking member 32 at a position where the through electrode 25 is formed. The through hole 118 is a hole for disposing the through electrode 25. When the diameter of the through hole 45 is 100 μm, the diameter of the through hole 118 can be set to 60 μm, for example.

  The through hole 119 is formed so as to penetrate the insulating layers 115 and 116 and the heat blocking member 32 at a portion where the through electrode 26 is formed. The through hole 119 is a hole for disposing the through electrode 26. When the diameter of the through hole 46 is 100 μm, the diameter of the through hole 119 can be set to 60 μm, for example.

  The side surface of the part of the heat blocking member 32 provided in the through groove 47 is in contact with the substrate 21. One end surface 32A of the portion of the heat blocking member 32 provided in the through groove 47 is in contact with the lower surface 115B of the insulating film 115, and the other end surface 32B is in contact with the upper surface 116B of the insulating film 116.

  The wiring board 111 of the fourth embodiment having the above configuration can obtain the same effects as the wiring board 11 of the first embodiment.

  Instead of the heat blocking member 32 provided in the semiconductor device 110 of the present embodiment, the heat blocking member 74 described in FIG. 20 of the first embodiment or the FIG. 21 of the first embodiment. A plurality of the heat shielding members 32 described may be provided.

  50 to 57 are views showing manufacturing steps of the semiconductor device according to the fourth embodiment of the present invention. 50 to 57, the same components as those of the semiconductor device 110 according to the fourth embodiment are denoted by the same reference numerals.

  A method of manufacturing the semiconductor device 110 according to the fourth embodiment will be described with reference to FIGS. First, the base material 55 shown in FIG. 35 is obtained by performing the same process as the step shown in FIGS. 34 and 35 (the base material preparation step and the through hole and through groove forming step) described in the third embodiment. (Specifically, the base material 55 in which the through holes 45 and 46 and the through groove 47 are formed) is formed.

  Next, in the step shown in FIG. 50, the heat blocking member 32 is formed in the through holes 45, 46 and the through groove 47 by filling the through holes 45, 46 and the through groove 47 with insulating resin (heat blocking member filling step). ).

  At this time, the end surface 32A of the heat shielding member 32 and the upper surface 55A of the base material 55 are substantially flush with each other, and the end surface 32B of the heat shielding member 32 and the lower surface 55B of the base material 55 are substantially flush with each other. The heat blocking member 32 is formed. In the heat blocking member filling step, when the insulating resin protrudes from the upper surface 55A and / or the lower surface 55B of the base material 55, for example, the protruding portion of the insulating resin may be removed by polishing.

  As the insulating resin, for example, an epoxy resin, a polyimide resin, a silicone resin, or the like can be used. The insulating resin may contain a filler (for example, silica).

Next, in the process shown in FIG. 51, the insulating film 115 covering the upper surface 55A of the base material 55 and the end surface 32A of the heat shielding member 32, and the insulating film 116 covering the lower surface 55B of the base material 55 and the end surface 32B of the heat shielding member 32, Form. As the insulating films 115 and 116, for example, an oxide film (for example, SiO ₂ film) formed by a CVD method, an insulating resin layer (epoxy resin, polyimide resin, silicone resin, or the like) can be used. The thickness of the insulating films 115 and 116 can be set to 5 μm to 10 μm, for example.

  Next, in the step shown in FIG. 52, through holes 118 penetrating through the portions of the insulating films 115 and 116 corresponding to the positions where the through holes 45 (first through holes) are formed and the heat blocking members 32 formed in the through holes 45. (Third through hole) and through hole 119 penetrating through portions of insulating films 115 and 116 corresponding to the formation position of through hole 46 (second through hole) and heat blocking member 32 formed in through hole 46. (Fourth through-hole) are simultaneously formed (through-hole forming step). Specifically, for example, the through holes 118 and 119 are formed by laser processing the insulating films 115 and 116 and the heat blocking member 32.

  At this time, the through-holes 118, such that the insulating heat blocking member 32 is interposed between the side surface of the through-hole 45 and the through-hole 118 and between the side surface of the through-hole 46 and the through-hole 119. 119 is formed.

  In this way, the through hole 118 is disposed such that the heat shielding member 32 having insulation properties is interposed between the side surface of the through hole 45 and the through hole 118 and between the side surface of the through hole 46 and the through hole 119. , 119 eliminates the need to separately form an insulating film that insulates the through electrodes 25, 26 and the substrate 21, thereby reducing the manufacturing cost of the wiring substrate 111.

  When the diameter of the through holes 45 and 46 is 100 μm, the diameter of the through holes 118 and 119 can be set to 60 μm, for example.

  Next, in the step shown in FIG. 53, the through holes 118 and 119 are filled with a conductive member to form the through electrode 25 in the through hole 118 and the through electrode 26 is formed in the through hole 119 (through electrode forming step). .

  Specifically, the through electrodes 25 and 26 can be formed by, for example, an electrolytic plating method in which a metal foil is disposed so as to be in contact with the lower surface 116A of the insulating film 116 and the metal foil is used as a power feeding layer. . In this case, for example, Cu can be used as the conductive member. The through electrodes 25 and 26 may be formed by filling the through holes 118 and 119 with a conductive member (in this case, a conductive paste) by a printing method. As the conductive paste, for example, Ni paste, Ag paste, Cu paste, or the like can be used.

  In the through electrode forming step, the end surfaces 25A and 26A of the through electrodes 25 and 26 and the upper surface 115A of the insulating film 115 are substantially flush with each other, and the end surfaces 25B and 26B of the through electrodes 25 and 26 and the lower surface 116A of the insulating film 116 are used. The through electrodes 25 and 26 are formed so as to be substantially flush with each other. When the conductive member protrudes from the upper surface 115A of the insulating film 115 and / or the lower surface 116A of the insulating film 116, the conductive member is filled into the through holes 118 and 119, and then, for example, the protruding portion of the conductive member is polished and removed. Thus, the through electrodes 25 and 26 are formed.

  Next, in the step shown in FIG. 54, by performing the same process as the step shown in FIG. 11 described in the first embodiment, the pads 28 and 29 and the wiring 31 are formed on the upper surface side of the structure shown in FIG. After that, the solder resist layer 39 is formed on the upper surface 115A of the insulating film 115 by performing the same process as the process shown in FIG. 12 described in the first embodiment.

  Next, in the step shown in FIG. 55, external connection pads 36 and 37 are formed on the lower surface side of the structure shown in FIG. 54 by performing the same process as the step shown in FIG. 11 described in the first embodiment. Then, the solder resist layer 41 is formed on the lower surface 116A of the insulating film 116 by performing the same process as the process shown in FIG. 12 described in the first embodiment. To do. Thereby, the wiring substrate 111 is formed in the plurality of substrate forming regions C.

  Next, in the step shown in FIG. 56, the electronic components 12 and 13 are flip-chip mounted on the pads 28 and 29 of the wiring board 111, and then the gap between the electronic component 12 and the wiring board 111 is filled with the underfill resin 17; An underfill resin 18 is filled in a gap between the electronic component 13 and the wiring board 111. Next, the external connection terminals 15 are disposed on the external connection pads 36, and the external connection terminals 16 are disposed on the external connection pads 37. Thereby, the semiconductor device 110 is manufactured in the plurality of substrate formation regions C.

  Next, in the step shown in FIG. 57, the structure shown in FIG. 56 is cut along the cutting region D to singulate a plurality of semiconductor devices 110 (cutting step).

  According to the method for manufacturing a wiring board of the present embodiment, through holes 45 and 46, a first mounting region in which electronic component 12 is mounted, and a second mounting in which 13 electronic components are mounted are formed on base 55. The through-groove 47 disposed between the regions is formed at the same time, and then the through-holes 45 and 46 and the through-groove 47 are filled with an insulating resin to form the heat blocking member 32, and then the through-hole 45 A through hole 118 in which the through electrode 25 is disposed is formed in the heat shielding member 32 formed in the above, and a through hole 119 in which the through electrode 26 is disposed in the heat shielding member 32 formed in the through hole 46 is formed. Then, the through holes 118 and 119 are filled with a conductive member, the through electrodes 25 and 26 are formed, and then the pads 28 and 29 are formed, whereby the first mounting region in which the electronic component 12 is mounted is formed. And second mounting on which electronic component 13 is mounted Since the heat shielding member 32 that penetrates the base material 55 and shields the heat generated from the electronic component 13 during operation is formed in the portion of the base material 55 positioned between the electronic component 13 and the electronic component 13 during operation. The generated heat can be prevented from being conducted to the electronic component 12 through the portion of the substrate 21 corresponding to the first mounting region.

  Further, the heat blocking member 32 is formed by filling the through holes 45 and 46 and the through groove 47 with an insulating resin, and in the through hole forming step, between the through hole 45 and the through hole 118 and between the through hole 46 and the through hole. By forming the through-holes 118 and 119 so that the heat blocking member 32 is interposed between them, it is not necessary to separately form an insulating film that insulates the through-electrodes 25 and 26 and the substrate 21. The manufacturing cost of the wiring board 111 can be reduced.

(Fifth embodiment)
FIG. 58 is a sectional view of a semiconductor device according to the fifth embodiment of the present invention. In FIG. 58, the same symbols are affixed to the same constituent portions as those of the semiconductor device 80 of the second embodiment.

  Referring to FIG. 58, the semiconductor device 130 of the fifth embodiment is similar to the semiconductor device 10 except that a wiring board 131 is provided instead of the wiring board 11 provided in the semiconductor device 10 of the first embodiment. It is configured in the same way.

  The wiring board 131 is configured in the same manner as the wiring board 11 except that a groove 133 and a heat blocking member 135 are provided instead of the through groove 47 and the heat blocking member 32 provided in the wiring board 11.

  The groove 133 is formed in the portion of the substrate 21 located between the first mounting region where the electronic component 12 is mounted and the second mounting region where the electronic component 13 is mounted from the lower surface 21B side of the substrate 21. ing. The groove 133 is a groove that does not penetrate the substrate 21. The surface of the substrate 21 in the part constituting the groove 133 is covered with the insulating film 22. The width I of the groove 133 can be set to 200 μm, for example. When the thickness of the substrate 21 is 200 μm, the depth J of the groove 133 can be set to 170 μm, for example.

  The heat blocking member 135 is provided in the groove 133 in which the insulating film 22 is formed. The heat blocking member 135 is configured in the same manner as the heat blocking member 32 except that its shape is different from that of the heat blocking member 32 described in the first embodiment. That is, the heat blocking member 135 is a member that is made of the same material as that of the heat blocking member 32 and can obtain the same effect as the heat blocking member 32. The width K of the heat blocking member 135 can be set to 150 μm, for example.

  According to the semiconductor device of the present embodiment, from the lower surface 21 </ b> B side of the substrate 21, between the mounting region of the electronic component 12 and the mounting region of the second electronic component 13 that generates a larger amount of heat during operation than the electronic component 12. The groove 133 that does not penetrate the substrate 21 is provided in the substrate 21 in the position, and the heat blocking member 135 is provided in the groove 133, whereby the heat generated from the electronic component 13 during operation is blocked by the heat blocking member 135. Is possible. Thereby, the heat generated from the electronic component 13 during operation can be prevented from being conducted to the electronic component 12 through the portion of the substrate 21 corresponding to the first mounting region.

  In addition, you may arrange | position the thermal insulation member 135 provided in the wiring board 131 of this Embodiment so that the 2nd mounting area may be surrounded continuously or discontinuously.

  59 to 69 are views showing a process for manufacturing a semiconductor device according to the fifth embodiment of the invention. 59 to 69, the same components as those of the semiconductor device 130 according to the fifth embodiment are denoted by the same reference numerals.

  With reference to FIGS. 59 to 69, a method of manufacturing the semiconductor device 130 according to the fifth embodiment will be described. First, the base material 55 shown in FIG. 34 is prepared by performing the same processing as the step shown in FIG. 34 described in the third embodiment (base material preparation step).

  Next, in the process shown in FIG. 59, from the surface 55B side of the base material 55, a portion located between the first mounting area where the electronic component 12 is mounted and the second mounting area where the electronic component 13 is mounted. A groove 133 that does not penetrate the base material 55 is formed in the base material 55 (groove forming step).

  Specifically, for example, the groove 133 is formed by etching the base material 55 by anisotropic etching (for example, dry etching) using a mask. The width I of the groove 133 can be set to 200 μm, for example. The depth J of the groove 133 can be set to 170 μm, for example.

  Next, in the step shown in FIG. 60, the through hole 45 that penetrates the portion of the base material 55 corresponding to the formation position of the through electrode 25 and the through hole that penetrates the portion of the base material 55 corresponding to the formation position of the through electrode 26. 46 are simultaneously formed (through-hole forming step).

  Specifically, the through holes 45 and 46 are formed by etching the base material 55 by, for example, anisotropic etching (for example, dry etching) using a mask.

  Next, in the step shown in FIG. 61, the same processing as the step shown in FIG. 5 described in the first embodiment is performed, so that both surfaces 55A and 55B of the base material 55, the through holes 45 and 46, and the groove 133 are formed. An insulating film 22 is formed to cover a portion of the base material 55 that constitutes the portion.

  Next, in the step shown in FIG. 62, the same process as the step shown in FIG. 6 described in the first embodiment is performed, so that the insulating film 22 provided on the lower surface 55B of the base 55 is formed in FIG. A mask 61 shown is formed. At this time, the mask 61 is formed so that the opening 61 </ b> A exposes the groove 133.

  Next, in the process shown in FIG. 63, for example, the heat blocking member 135 is formed by filling the groove 133 with resin (a base material of the heat blocking member 135) by a squeegee printing method (heat blocking member forming process).

  At this time, the opening 61A of the mask 61 is also filled with resin. As the resin, for example, a resin capable of blocking heat (for example, a thermal conductivity of 0.1 to 1.0 W / m · K) can be used. Specifically, as the resin, for example, a polyimide resin, an epoxy resin, a silicone resin, or the like can be used. In addition, you may make a resin contain a filler (for example, silica). When the resin contains a filler (for example, silica), the difference in thermal expansion coefficient between the substrate 21 and the heat blocking member 135 can be reduced. For example, when a silicon substrate (thermal expansion coefficient 3 ppm / K) is used as the substrate 21, the content of the filler (silica) contained in the resin can be 50%.

  Next, in a step shown in FIG. 64, the mask 61 shown in FIG. 63 is removed by performing the same process as the step shown in FIG. 8 described in the first embodiment.

  Next, in a step shown in FIG. 65, a conductive member 65 that is a base material for the through electrodes 25 and 26 is formed in the openings 57 and 58. Specifically, for example, the seed layer is formed by a sputtering method, and then the conductive member 65 is formed by depositing and growing a Cu plating film by a semi-additive method, or the openings 57 and 58 are formed by a printing method. Is filled with a conductive paste (for example, Cu paste, Ag paste, Ni paste, etc.) to form a conductive member 65. At this time, the conductive member 65 may protrude from the insulating film 22 formed on the lower surface 55 </ b> B of the base material 55.

  Next, in the step shown in FIG. 66, the conductive member 65 and / or the heat shielding member 135 in a portion protruding from the insulating film 22 formed on the lower surface 55B of the base material 55 is removed (conductive member and / or heat shielding member removal). Process).

  Specifically, the unnecessary conductive member 65 and / or the heat shielding member 135 in the portion protruding from the insulating film 22 are removed by grinding or polishing. As a result, the through electrodes 25 and 26 are formed (in the case of the present embodiment, the process shown in FIGS. 65 and 66 is the “through electrode forming process”) and the end face 135A (polished or ground) of the heat shielding member 135. And the end faces 25B, 26B of the through electrodes 25, 26 are substantially flush with each other.

  Next, the process shown in FIG. 67 includes the processes shown in FIGS. 11, 12, and 14 to 16 described in the first embodiment (including the “pad forming process” and the “external connection pad forming process”). By sequentially performing the same process as in the step), the pads 28 and 29, the wiring 31, the vias 33 and 34, the external connection pads 36 and 37, and the solder resist layers 39 and 41 are formed. Thereby, the wiring substrate 131 is formed in the plurality of substrate forming regions C.

  Next, in the step shown in FIG. 68, the electronic components 12 and 13 are flip-chip mounted on the pads 28 and 29 of the wiring board 131, and then the gap between the electronic component 12 and the wiring board 131 is filled with the underfill resin 17; An underfill resin 18 is filled in a gap between the electronic component 13 and the wiring board 131. Next, the external connection terminals 15 are disposed on the external connection pads 36, and the external connection terminals 16 are disposed on the external connection pads 37. Thereby, the semiconductor device 130 is manufactured in the plurality of substrate formation regions C.

  Next, in the step shown in FIG. 69, the structure shown in FIG. 68 is cut along the cutting region D to singulate a plurality of semiconductor devices 130 (cutting step).

  According to the method for manufacturing a wiring board of the present embodiment, the first mounting area where the electronic component 12 is mounted and the second mounting area where the electronic component 13 is mounted from the surface 55B side of the base 55. A groove 133 that does not penetrate through the base material 55 is formed in the base material 55 located between them, and then the base material 55 corresponds to the formation position of the through electrodes 25 and 26 and penetrates through the base material 55. The holes 45 and 46 are formed at the same time, and then the heat blocking member 135 for blocking heat is formed in the groove 133, and then the through hole 25 is filled with the conductive member 65 to form the through electrodes 25 and 26. By forming the pads 28 and 29, a portion of the base material 55 located between the first mounting area on which the electronic component 12 is mounted and the second mounting area on which the electronic component 13 is mounted is provided during operation. Thermal shut-off that shuts off heat generated from the electronic component Since wood 135 is formed can prevent the heat generated from the electronic component 13 during operation, through the substrate 21 of the portion corresponding to the first mounting region, it is conducted to the electronic component 12.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

10, 70, 80, 90, 110, 130 Semiconductor device 11, 71, 81, 91, 111, 131 Wiring board 12, 13 Electronic component 15, 16 External connection terminal 17, 18 Underfill resin 21 Substrate 21A, 22A, 55A , 94B, 115A, 116B Upper surface 21B, 23A, 55B, 94A, 115B, 116A Lower surface 22, 23, 93, 94, 115, 116 Insulating film 25, 26 Through electrode 25A, 25B, 26A, 26B, 32A, 32B, 135A End face 28, 29 Pad 28A, 29A, 36A, 37A Connection face 31 Wiring 32, 74, 135 Heat blocking member 33, 34, 96, 97 Via 36, 37 External connection pad 39, 41 Solder resist layer 39A, 39B, 48 , 49, 57, 58, 93A, 93B Openings 45, 46, 18, 119 Through-hole 47, 61A, 73 Through-groove 55 Base material 59, 133 Groove 61 Mask 65 Conductive member 101 Film A, B, E, I, K Width C Substrate formation region D Cutting region F First mounting region G Second mounting area J Depth

Claims (9)

A substrate made of a semiconductor material; a first pad provided on a first surface side of the substrate; on which a first electronic component is mounted; provided on a first surface side of the substrate; A second pad on which a second electronic component that generates a larger amount of heat during operation than the electronic component is mounted;
A first through electrode penetrating the substrate and having one end electrically connected to the first pad;
A wiring substrate having a second through electrode penetrating the substrate and having one end electrically connected to the second pad,
The first surface of the substrate located between the first mounting area where the first electronic component is mounted and the second mounting area where the second electronic component is mounted; A wiring board characterized in that a groove not penetrating the substrate is provided in a portion of the substrate located on the opposite side, and a heat blocking member is provided in the groove. An insulating film is formed on the surface of the substrate and the heat shielding member,
The first pad, the second pad, and a wiring connected to the first pad and the second pad are formed on the substrate through the insulating film. The wiring board according to claim 1.   The wiring board according to claim 2, wherein an inner wall of the groove is covered with the insulating film. The insulating film is formed on an inner surface of a first through-hole penetrating the substrate; the first through-electrode is formed in the first through-hole through the insulating film;
The insulating film is formed on an inner surface of a second through hole penetrating the substrate, and the second through electrode is formed in the second through hole via the insulating film. The wiring board according to claim 2 or 3.   5. The wiring board according to claim 2, wherein the insulating film is made of an oxide film.   The wiring substrate according to claim 1, wherein the groove is formed in a continuous frame shape so as to surround the substrate at a portion corresponding to the second mounting region.   6. The wiring board according to claim 1, wherein a plurality of the grooves are arranged so as to surround the substrate in a portion corresponding to the second mounting region.   The wiring board according to claim 1, wherein a thermal conductivity of the heat blocking member is 0.1 to 1.0 W / m · K.   The wiring board according to claim 1, wherein a material of the heat shielding member is a resin.

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