JP5463423B2 - Charge trap type memory device and method of manufacturing the same - Google Patents

Charge trap type memory device and method of manufacturing the same Download PDF

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JP5463423B2
JP5463423B2 JP2012550729A JP2012550729A JP5463423B2 JP 5463423 B2 JP5463423 B2 JP 5463423B2 JP 2012550729 A JP2012550729 A JP 2012550729A JP 2012550729 A JP2012550729 A JP 2012550729A JP 5463423 B2 JP5463423 B2 JP 5463423B2
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順子 小野
隆史 中川
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Canon Anelva Corp
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    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
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    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
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    • G11INFORMATION STORAGE
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    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]

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Description

本発明は、電極膜を用いた不揮発性半導体記憶装置及びその製造方法に関するものであり、特にチャージトラップ型記憶装置及びその製造方法に関する。   The present invention relates to a nonvolatile semiconductor memory device using an electrode film and a manufacturing method thereof, and more particularly to a charge trap memory device and a manufacturing method thereof.

既存のフローティングゲート型に対し、高密度化、微細化が可能である不揮発性半導体の開発が進められている。例えば、MONOS(Metal Oxide Nitride Oxide Semiconductor)型のチャージトラップ型記憶装置では、酸化膜上に窒化膜と酸化膜を積層し、その上にゲート電極を設置しており、この酸化膜に挟まれた窒化膜中に電荷を蓄積し、記憶を保持する。   Development of non-volatile semiconductors that can be made denser and finer than existing floating gate types is underway. For example, in a MONOS (Metal Oxide Nitride Oxide Semiconductor) type charge trap memory device, a nitride film and an oxide film are stacked on an oxide film, and a gate electrode is provided on the oxide film, and sandwiched between the oxide films. Charges are accumulated in the nitride film and the memory is retained.

図14を用いて従来のチャージトラップ型記憶装置の構成を説明する(特許文献1参照)。従来のチャージトラップ型メモリ装置800は、シリコン基板810上に、トンネル酸化膜811、チャージトラップ膜812、ブロッキング絶縁膜813、ゲート電極814が、下側からこの順で形成された積層構造を有する。   The configuration of a conventional charge trap memory device will be described with reference to FIG. 14 (see Patent Document 1). The conventional charge trap memory device 800 has a stacked structure in which a tunnel oxide film 811, a charge trap film 812, a blocking insulating film 813, and a gate electrode 814 are formed in this order from below on a silicon substrate 810.

上記トンネル酸化膜811は、シリコン酸化膜(SiO膜)を含んでおり、チャージトラップ膜812は、シリコン窒化膜(SiN膜)又はシリコン酸窒化膜(SiONを含んでいる。ブロッキング絶縁膜813は、シリコン酸化膜(SiO膜)又はAl膜、高誘電率膜(High−k膜)、例えば、HfO、ZrO、Ta、Y等を含むことができる。また、ゲート電極814は、ポリシリコン膜、TaN膜、金属膜(W,Pt等)、TiN膜等を含む。The tunnel oxide film 811 includes a silicon oxide film (SiO 2 film), and the charge trap film 812 includes a silicon nitride film (SiN film) or a silicon oxynitride film (SiON). , Silicon oxide film (SiO 2 film) or Al 2 O 3 film, high dielectric constant film (High-k film), for example, HfO 2 , ZrO 2 , Ta 2 O 5 , Y 2 O 3, etc. The gate electrode 814 includes a polysilicon film, a TaN film, a metal film (W, Pt, etc.), a TiN film, and the like.

上記構成のチャージトラップ型メモリ装置800では、書き込み/消去制御回路820から所定電圧、例えば+18Vのパルス電圧をゲート電極814に印加することにより、チャージトラップ膜812にシリコン基板810側から負の電荷(電子)をトラップして書き込み動作を行う。また、書き込み/消去制御回路820から所定電圧、例えば−18V(或いは−20V)のパルス電圧をゲート電極814に印加することにより、チャージトラップ膜812にトラップされている負の電荷(電子)をデトラップして消去動作を行う。   In the charge trap memory device 800 having the above-described configuration, a negative voltage (from the silicon substrate 810 side to the charge trap film 812 is applied to the charge trap film 812 by applying a predetermined voltage, for example, a +18 V pulse voltage from the write / erase control circuit 820. Electrons) are trapped and a write operation is performed. Further, a negative voltage (electrons) trapped in the charge trap film 812 is detrapped by applying a pulse voltage of −18 V (or −20 V), for example, from the write / erase control circuit 820 to the gate electrode 814. Then, erase operation is performed.

図15を用いて従来の別のチャージトラップ型記憶装置の構成を説明する(特許文献2参照)。図15の半導体記憶装置901は、基板911と、第1のゲート絶縁膜921と、電荷蓄積絶縁膜922と、第2のゲート絶縁膜923と、ゲート電極924と、側壁絶縁膜931と、層間絶縁膜941とを備える。基板911はシリコン基板又はSOI(Semiconductor On Insulator)基板を含んでいる。基板911には、ソース拡散層951やドレイン拡散層952が設けられている。第1のゲート絶縁膜921は、トンネル絶縁膜とも呼ばれ、シリコン酸化膜又は第1のシリコン酸化膜とシリコン窒化膜と第2のシリコン酸化膜とを含むONO型の積層膜を含む。第2のゲート絶縁膜923は、ブロッキング絶縁膜とも呼ばれ、Al層、HfAlOX層又はHfO層等のhigh−k絶縁膜を含む。ゲート電極924は、コントロールゲートとも呼ばれ、NiSi層又はCoSi層、TaN層とWN層とW層とを含む積層膜を含む。側壁絶縁膜931はシリコン窒化膜等の窒化膜を含む。層間絶縁膜941はシリコン酸化膜を含む。なお、図15において、S1は電荷蓄積絶縁膜922のビット線方向の側面、S2は第2のゲート絶縁膜923のビット線方向の側面、S3はゲート電極924のビット線方向の側面、W1は電荷蓄積絶縁膜922のビット線方向の幅、W2は第2のゲート絶縁膜923のビット線方向の幅、W3はゲート電極924のビット線方向の幅である。The configuration of another conventional charge trap memory device will be described with reference to FIG. 15 (see Patent Document 2). A semiconductor memory device 901 in FIG. 15 includes a substrate 911, a first gate insulating film 921, a charge storage insulating film 922, a second gate insulating film 923, a gate electrode 924, a sidewall insulating film 931, and an interlayer An insulating film 941. The substrate 911 includes a silicon substrate or an SOI (Semiconductor On Insulator) substrate. A source diffusion layer 951 and a drain diffusion layer 952 are provided on the substrate 911. The first gate insulating film 921 is also called a tunnel insulating film, and includes a silicon oxide film or an ONO-type stacked film including a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The second gate insulating film 923 is also called a blocking insulating film, and includes a high-k insulating film such as an Al 2 O 3 layer, an HfAlOX layer, or an HfO 2 layer. The gate electrode 924 is also called a control gate, and includes a stacked film including a NiSi layer or a CoSi 2 layer, a TaN layer, a WN layer, and a W layer. Sidewall insulating film 931 includes a nitride film such as a silicon nitride film. The interlayer insulating film 941 includes a silicon oxide film. In FIG. 15, S1 is a side surface in the bit line direction of the charge storage insulating film 922, S2 is a side surface in the bit line direction of the second gate insulating film 923, S3 is a side surface in the bit line direction of the gate electrode 924, and W1 is The width of the charge storage insulating film 922 in the bit line direction, W2 is the width of the second gate insulating film 923 in the bit line direction, and W3 is the width of the gate electrode 924 in the bit line direction.

特開2010−192592号公報JP 2010-192592 A 特開2010−27707号公報JP 2010-27707 A

本発明は、このような課題に鑑みてなされたもので、消去時のリーク電流を低減し、信頼性の向上を図ったチャージトラップ型記憶装置及びその製造方法を提供することを目的とするものである。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a charge trap memory device and a manufacturing method thereof in which leakage current during erasure is reduced and reliability is improved. It is.

このような目的を達成するために、本発明の第1の態様は、シリコン基板上に、トンネル酸化膜、チャージトラップ膜、ブロッキング絶縁膜、およびゲート電極がこの順番で形成された積層構造を有し、前記ゲート電極に電圧を印加することによって、前記シリコン基板側から前記チャージトラップ膜に電荷をトラップ及びデトラップして情報の書き込み及び消去を行うるチャージトラップ型記憶装置の製造方法であって、前記トンネル酸化膜、前記チャージトラップ膜、および前記ブロッキング絶縁膜が順に形成された前記シリコン基板を用意する工程と、前記ブロッキング絶縁膜上にWとNとOを含有する金属酸窒化物層を形成する工程と、前記金属酸窒化物層上にWとNを含有する金属窒化物層を形成する工程とを有し、前記金属酸窒化物層及び前記金属窒化物層を形成する工程が、真空容器内で、反応性ガスと不活性ガスの混合雰囲気下において前記金属酸窒化物層及び前記金属窒化物層に含まれる金属からなる金属ターゲットをマグネトロンスパッタする工程であり、前記金属酸窒化物層を形成する工程における前記反応性ガスが酸素及び窒素であり、前記金属窒化物層を形成する工程における前記反応性ガスが窒素であることを特徴とする。

In order to achieve such an object, the first aspect of the present invention has a laminated structure in which a tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode are formed in this order on a silicon substrate. A method for manufacturing a charge trap type memory device that performs writing and erasing of information by trapping and detrapping charges from the silicon substrate side to the charge trap film by applying a voltage to the gate electrode, Preparing the silicon substrate on which the tunnel oxide film, the charge trap film, and the blocking insulating film are sequentially formed; and forming a metal oxynitride layer containing W, N, and O on the blocking insulating film And forming a metal nitride layer containing W and N on the metal oxynitride layer, the metal oxynitride And forming the metal layer and the metal nitride layer in a vacuum vessel in a mixed atmosphere of a reactive gas and an inert gas, the metal comprising the metal contained in the metal oxynitride layer and the metal nitride layer. It is a step of magnetron sputtering a target, the reactive gas in the step of forming the metal oxynitride layer is oxygen and nitrogen, and the reactive gas in the step of forming the metal nitride layer is nitrogen It is characterized by.

本発明によれば、チャージトラップ型記憶装置において、仕事関数の高い、WとNとOとを含有する金属酸窒化物層(例えば、WON膜)をゲート電極に用いることにより消去時のリーク電流を低減し、チャージトラップ型記憶装置の信頼性が向上するという効果がある。更に該効果に加えて、WとNとOとを含有する金属酸窒化物層からなるゲート電極上にWとNとを含有する金属窒化物層(例えば、WN膜)を積層することにより金属の拡散を抑制することができ、耐熱性が向上するという効果がある。   According to the present invention, in a charge trap memory device, a leakage current at the time of erasure is obtained by using a metal oxynitride layer (for example, a WON film) having a high work function and containing W, N, and O as a gate electrode. And the reliability of the charge trap memory device is improved. Further, in addition to the effect, a metal nitride layer (for example, WN film) containing W and N is laminated on a gate electrode made of a metal oxynitride layer containing W, N, and O to form a metal. Diffusion can be suppressed, and heat resistance is improved.

本発明の一実施形態により電極膜を形成したMONOS型のチャージトラップ型装置の断面図である。It is sectional drawing of the MONOS type | mold charge trap type | mold apparatus which formed the electrode film by one Embodiment of this invention. 本発明の一実施形態に係る金属酸窒化物膜の形成工程に用いる処理装置の一例の概略を示した図である。It is the figure which showed the outline of an example of the processing apparatus used for the formation process of the metal oxynitride film | membrane which concerns on one Embodiment of this invention. 本発明の一実施形態に係るWN膜の放電特性をした図である。It is the figure which made the discharge characteristic of the WN film | membrane which concerns on one Embodiment of this invention. 本発明の一実施形態に係るWON膜の放電特性をした図である。It is the figure which made the discharge characteristic of the WON film | membrane which concerns on one Embodiment of this invention. 本発明の一実施形態に係るWN膜の成膜速度を示した図である。It is the figure which showed the film-forming speed | rate of the WN film | membrane which concerns on one Embodiment of this invention. 本発明の一実施形態に係るWO膜およびWON膜の成膜速度を示した図である。It is the figure which showed the film-forming speed | rate of the WO film | membrane and WON film | membrane which concerns on one Embodiment of this invention. 本発明の一実施形態に係るWON膜の成膜時の酸素流量とモル比率O/(O+N+W)の関係を示した図である。It is the figure which showed the relationship between the oxygen flow rate at the time of film-forming of the WON film | membrane which concerns on one Embodiment of this invention, and molar ratio O / (O + N + W). 本発明の一実施形態に係るWON膜のモル比率O/(O+N+W)と比抵抗を示した図である。It is the figure which showed the molar ratio O / (O + N + W) and specific resistance of the WON film | membrane which concerns on one Embodiment of this invention. 本発明の一実施形態に係るWON膜のモル比率O/(O+N+W)と密度を示した図である。It is the figure which showed the molar ratio O / (O + N + W) and density of the WON film | membrane which concern on one Embodiment of this invention. 本発明の一実施形態に係るWON膜のモル比率O/(O+N+W)と仕事関数を示した図である。It is the figure which showed the molar ratio O / (O + N + W) and work function of the WON film | membrane which concerns on one Embodiment of this invention. 本発明の一実施形態に係るWN膜上にTiN膜を積層し、1000℃で焼成した後の膜厚方向の組成を示した図である。It is the figure which showed the composition of the film thickness direction after laminating | stacking a TiN film | membrane on the WN film | membrane which concerns on one Embodiment of this invention, and baking at 1000 degreeC. 本発明の一実施形態に係るWON膜上にTiN膜を積層し、1000℃で焼成した後の膜厚方向の組成を示した図である。It is the figure which showed the composition of the film thickness direction after laminating | stacking a TiN film | membrane on the WON film | membrane which concerns on one Embodiment of this invention, and baking at 1000 degreeC. 本発明の第1の実施例のMISキャパシタの断面図を示す図である。It is a figure which shows sectional drawing of the MIS capacitor of the 1st Example of this invention. 本発明の第2の実施例の半導体装置の製造方法の工程を示す図である。It is a figure which shows the process of the manufacturing method of the semiconductor device of the 2nd Example of this invention. 本発明の第2の実施例の半導体装置の断面図を示す図である。It is a figure which shows sectional drawing of the semiconductor device of the 2nd Example of this invention. 従来(特許文献1)のチャージトラップ型記憶装置の構成を示す図である。It is a figure which shows the structure of the conventional charge trap memory | storage device (patent document 1). 従来(特許文献2)のチャージトラップ型記憶装置の構成を示す図である。It is a figure which shows the structure of the conventional charge trap memory | storage device (patent document 2).

本発明者らは、上記課題を解決すべく検討した結果、特定の組成を有する金属酸窒化物をチャージトラップ型記憶装置のゲート電極として形成すことにより、膜密度と仕事関数が高い電極膜が得られることを見出し、本発明を完成するに至った。
以下、本発明の実施形態を図面に基づき詳細に説明する。
本発明の一実施形態は、表面にシリコン酸化膜を有するシリコン基板上に、トンネル酸化膜、チャージトラップ膜、ブロッキング絶縁膜、ゲート電極がこの順番で形成された積層構造を有し、該ゲート電極に電圧を印加することによって、シリコン基板側からチャージトラップ膜に電荷をトラップ及びデトラップして情報の書き込み及び消去を行うチャージトラップ型記憶装置に指向する。以下では、ゲート電極膜として、構成元素としてWとNとOとを含む金属酸窒化膜(以下WON膜と記述)を形成したMONOS(Metal Oxide Nitride Oxide Semiconductor)型記憶装置を例に取り説明する。
As a result of studying to solve the above problems, the present inventors have formed an electrode film having a high film density and work function by forming a metal oxynitride having a specific composition as a gate electrode of a charge trap memory device. As a result, the present invention was completed.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
One embodiment of the present invention has a stacked structure in which a tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode are formed in this order on a silicon substrate having a silicon oxide film on the surface, and the gate electrode By applying a voltage to the charge trap film, the charge trap film is trapped and detrapped to the charge trap film from the silicon substrate side to be directed to a charge trap type storage device for writing and erasing information. In the following, a MONOS (Metal Oxide Semiconductor Oxide Semiconductor) type memory device in which a metal oxynitride film (hereinafter referred to as WON film) containing W, N, and O as constituent elements is formed as a gate electrode film will be described as an example. .

図1に示すように、表面に膜厚3nm〜5nmの範囲のシリコン酸化膜を有するシリコン基板1にSiO層2とSiN層3とを積層し、誘電体膜4を堆積した後、WON膜であるゲート電極として機能する電極膜5を形成している。SiO層2はトンネル酸化膜、SiN層3はチャージトラップ膜、誘電体膜4はブロッキング絶縁膜である。
なお、ブロッキング絶縁膜としての誘電体膜4は、金属酸化物、金属シリケート、もしくは窒素が導入された、金属酸化物または金属シリケートを含む高誘電率絶縁膜である。
As shown in FIG. 1, after a SiO 2 layer 2 and a SiN layer 3 are stacked on a silicon substrate 1 having a silicon oxide film with a thickness of 3 nm to 5 nm on the surface, a dielectric film 4 is deposited, and then a WON film An electrode film 5 that functions as a gate electrode is formed. The SiO 2 layer 2 is a tunnel oxide film, the SiN layer 3 is a charge trap film, and the dielectric film 4 is a blocking insulating film.
The dielectric film 4 as a blocking insulating film is a high dielectric constant insulating film containing metal oxide, metal silicate, or metal oxide or metal silicate into which nitrogen is introduced.

図2に、WON膜からなるゲート電極の形成工程に用いられる処理装置の一例の概略を示す。成膜処理室100はヒータ101によって所定の温度に加熱できるように構成されている。被処理基板102は、基板支持台103に組み込まれた、サセプタ104を介して、ヒータ105によって所定の温度に加熱される。基板支持台103は、膜厚の均一性の観点から所定の回転数で回転できることが好ましい。   FIG. 2 shows an outline of an example of a processing apparatus used in the process of forming a gate electrode made of a WON film. The film formation chamber 100 is configured to be heated to a predetermined temperature by the heater 101. The substrate to be processed 102 is heated to a predetermined temperature by the heater 105 via the susceptor 104 incorporated in the substrate support base 103. It is preferable that the substrate support 103 can be rotated at a predetermined rotational speed from the viewpoint of film thickness uniformity.

成膜処理室100内には、ターゲット106、126が、被処理基板102を望む位置に設置されている。ターゲット106、126は、Cu等の金属から出来ているバックプレート107、127を介してターゲットホルダー108、128に設置されている。なお、ターゲット106、126とバックプレート107、127を組み合わせたターゲット組立体の外形を1つの部品としてターゲット材料で作成し、これをターゲットとして取り付けても構わない。つまり、ターゲットがターゲットホルダーに設置された構成でも構わない。   In the film formation processing chamber 100, targets 106 and 126 are installed at positions where the target substrate 102 is desired. The targets 106 and 126 are installed on the target holders 108 and 128 via back plates 107 and 127 made of a metal such as Cu. It should be noted that the outer shape of the target assembly in which the targets 106 and 126 and the back plates 107 and 127 are combined may be made of a target material as a single component and attached as a target. That is, a configuration in which the target is installed on the target holder may be used.

Cu等の金属製のターゲットホルダー108、128には、スパッタ放電用電力を印加する直流電源110、130が接続されており、絶縁体109、129により接地電位の成膜処理室100の壁から絶縁されている。   Direct current power sources 110 and 130 for applying sputtering discharge power are connected to the target holders 108 and 128 made of metal such as Cu, and insulated from the wall of the film formation processing chamber 100 at the ground potential by the insulators 109 and 129. Has been.

スパッタ面から見たターゲット106、126の背後には、マグネトロンスパッタリングを実現するためのマグネット111、131が配設されている。マグネット111、131は、マグネットホルダー112、132に保持され、図示しないマグネットホルダー回転機構により回転可能となっている。ターゲットのエロージョンを均一にするため、放電中には、このマグネット111、131は回転している。   Magnets 111 and 131 for realizing magnetron sputtering are disposed behind the targets 106 and 126 as viewed from the sputtering surface. Magnets 111 and 131 are held by magnet holders 112 and 132, and can be rotated by a magnet holder rotating mechanism (not shown). In order to make the erosion of the target uniform, the magnets 111 and 131 rotate during discharge.

ターゲット106、126は、基板102に対して斜め上方のオフセット位置に設置されている。すなわち、ターゲット106、126のスパッタ面の中心点は、基板102の中心点の法線に対して所定の寸法ずれた位置にある。   The targets 106 and 126 are installed at offset positions obliquely above the substrate 102. That is, the center point of the sputtering surface of the targets 106 and 126 is at a position displaced by a predetermined dimension with respect to the normal line of the center point of the substrate 102.

ターゲット106、126と処理基板102の間には、遮蔽板116が設置され、電力が供給されたターゲット106、126から放出されるスパッタ粒子による処理基板102上への成膜を制御している。   A shielding plate 116 is installed between the targets 106 and 126 and the processing substrate 102 to control film formation on the processing substrate 102 by sputtered particles emitted from the targets 106 and 126 to which power is supplied.

本発明の一実施形態では、窒化膜3上にスパッタリング法により膜厚10nmの誘電体膜4を堆積させる。次に、成膜後、アニール処理を施すことにより結晶化させ、誘電体膜4とする。   In one embodiment of the present invention, a dielectric film 4 having a thickness of 10 nm is deposited on the nitride film 3 by sputtering. Next, after the film formation, the dielectric film 4 is obtained by crystallization by annealing.

次に、誘電体膜4上にゲート電極としてのWON電極5を堆積させる。ターゲットは、Wの金属ターゲット106を用いれば良い。電極膜5の堆積は、金属ターゲット106に、直流電源110より、ターゲットホルダー108およびバックプレート107を介して電力を供給することにより実施される。この際、不活性ガスが、不活性ガス源201から、バルブ202、マスフローコントローラ203、バルブ204を介してターゲット付近から処理室100に導入される。また、酸素と窒素とを含む反応性ガスは、それぞれ酸素ガス源205と窒素ガス源209から、バルブ206、210、マスフローコントローラ207、211、バルブ208、212を介して処理室100内の基板付近に導入される。導入された不活性ガスおよび反応性ガスは、コンダクタンスバルブ117を介して、排気ポンプ118によって排気される。   Next, a WON electrode 5 as a gate electrode is deposited on the dielectric film 4. As the target, a W metal target 106 may be used. The electrode film 5 is deposited by supplying electric power to the metal target 106 from the DC power source 110 through the target holder 108 and the back plate 107. At this time, an inert gas is introduced into the processing chamber 100 from the vicinity of the target from the inert gas source 201 through the valve 202, the mass flow controller 203, and the valve 204. A reactive gas containing oxygen and nitrogen is supplied from the oxygen gas source 205 and the nitrogen gas source 209 to the vicinity of the substrate in the processing chamber 100 through valves 206 and 210, mass flow controllers 207 and 211, and valves 208 and 212, respectively. To be introduced. The introduced inert gas and reactive gas are exhausted by the exhaust pump 118 via the conductance valve 117.

本発明の一実施形態では、基板温度30℃、Wのターゲットパワーを500Wに設定し、不活性ガスとしてArを用い、Arの供給量を25sccmとして、反応性ガスである窒素と酸素を供給し、成膜する。このとき、WON膜の酸素のモル比率O/(O+N+W)は、窒素ガス流量を15sccm一定として、酸素ガス流量を0sccm〜20sccmの範囲で変えることにより調節する。尚、本明細書中における「モル比率」とは、物質量の基本単位であるモル数の比率をいう。モル比率は、例えば、X線光電子分光法により物質内にある固有の電子の結合エネルギー、電子のエネルギー準位と量から測定することができる。また、sccm=一分間当たり供給されるガス流量0℃1気圧で表したcm数=1.69×10−3Pa・m/s(0℃において)である。また、酸素ガス流量を20sccm以下としたのは、Wのターゲットの表面が酸化することにより生じるスパッタ率の低下率が最大となるようにするためである。「スパッタ率」とは、スパッタターゲットを衝撃する衝撃イオン1個当たり放出するスパッタ原子数の割合をいう。In an embodiment of the present invention, a substrate temperature of 30 ° C., a target power of W is set to 500 W, Ar is used as an inert gas, Ar is supplied at 25 sccm, and reactive gases such as nitrogen and oxygen are supplied. A film is formed. At this time, the molar ratio O / (O + N + W) of oxygen in the WON film is adjusted by changing the oxygen gas flow rate in the range of 0 sccm to 20 sccm while keeping the nitrogen gas flow rate constant at 15 sccm. In the present specification, the “molar ratio” refers to the ratio of the number of moles, which is the basic unit of the substance amount. The molar ratio can be measured, for example, from X-ray photoelectron spectroscopy, from the binding energy of intrinsic electrons in the substance, the energy level and amount of electrons. Further, sccm = the number of cm 3 expressed at a flow rate of gas supplied per minute of 0 ° C. and 1 atm = 1.69 × 10 −3 Pa · m 3 / s (at 0 ° C.). The reason why the oxygen gas flow rate is set to 20 sccm or less is to maximize the reduction rate of the sputtering rate caused by the oxidation of the surface of the W target. “Sputtering rate” refers to the ratio of the number of sputtered atoms emitted per impact ion that bombards the sputter target.

図3Aに窒素を導入した時のWターゲットの放電特性(WNの放電特性)、図3Bに窒素流量を15sccmに固定して、酸素を0sccm〜50sccm導入した時のWターゲットの放電特性(WONの放電特性)を示す。図3AのWターゲットの放電特性より、窒素流量を増やすと放電電圧は緩やかに増加することが解る。一方図3BのWターゲットの放電特性より、酸素流量を増やすと、酸素流量が30sccm以下の領域では放電電圧が増加するが、30sccmよりさらに酸素流量を増やすと放電電圧は徐々に低下する。この放電電圧の変化は酸素の供給量が増加すると金属ターゲット表面が酸化され、スパッタ率が変化するためである。   FIG. 3A shows the discharge characteristic of the W target when nitrogen is introduced (discharge characteristic of WN), and FIG. 3B shows the discharge characteristic of the W target when the nitrogen flow rate is fixed at 15 sccm and oxygen is introduced at 0 sccm to 50 sccm (WON Discharge characteristics). From the discharge characteristics of the W target in FIG. 3A, it can be seen that the discharge voltage gradually increases when the nitrogen flow rate is increased. On the other hand, from the discharge characteristics of the W target in FIG. 3B, when the oxygen flow rate is increased, the discharge voltage increases in the region where the oxygen flow rate is 30 sccm or less, but when the oxygen flow rate is further increased from 30 sccm, the discharge voltage gradually decreases. This change in the discharge voltage is because the surface of the metal target is oxidized and the sputtering rate is changed when the supply amount of oxygen is increased.

図4AにWN膜の成膜速度に対する窒素流量依存性、図4BにWON膜、WO膜の成膜速度に対する酸素流量依存性を示す。図4A中、黒塗り菱形「◆」のプロットはWN膜の結果を示している。図4B中、黒塗りの丸「●」のプロットはWO膜、黒塗り三角「▲」のプロットはWON膜の結果を示している。図4Aより、WNの成膜速度は、窒素流量が増すに従って減少することが解る。これらの放電電圧の変化は窒素の供給量が増加すると金属ターゲット表面が窒化され、スパッタ率が低下するためである。一方、図4Bにおいて、WO及びWON膜の成膜速度は、酸素流量の増加に従って増加する。本発明の一実施形態における絶縁体膜形成を堆積速度の低下を招くことなく実現するには、少なくともWターゲットの窒化が小さい15sccm以下で行うことが好ましい。   FIG. 4A shows the nitrogen flow rate dependence on the WN film deposition rate, and FIG. 4B shows the oxygen flow rate dependence on the WON film and WO film deposition rates. In FIG. 4A, the plot of the black diamond “♦” indicates the result of the WN film. In FIG. 4B, the black circle “●” plots show the results for the WO film, and the black triangle “▲” plots show the results for the WON film. From FIG. 4A, it can be seen that the deposition rate of WN decreases as the nitrogen flow rate increases. The change in the discharge voltage is because the surface of the metal target is nitrided and the sputtering rate is lowered when the supply amount of nitrogen is increased. On the other hand, in FIG. 4B, the film formation rates of the WO and WON films increase as the oxygen flow rate increases. In order to realize the formation of the insulator film in one embodiment of the present invention without causing a decrease in the deposition rate, it is preferable to perform at least 15 sccm at which the nitriding of the W target is small.

図5に、WON膜の酸素のモル比率O/(O+N+W)と成膜時の酸素ガス流量依存性を示す。組成は、AES(Auger ElectronSpectroscopy オージェ電子分光法)により評価した。該評価の結果から、酸素ガス流量を0sccmから10sccmの範囲で調節することにより、酸素モル比率を0から0.55の範囲で制御することが確認できる。   FIG. 5 shows the oxygen molar ratio O / (O + N + W) of the WON film and the oxygen gas flow rate dependency during the film formation. The composition was evaluated by AES (Auger Electron Spectroscopy Auger Electron Spectroscopy). From the result of the evaluation, it can be confirmed that the oxygen molar ratio is controlled in the range of 0 to 0.55 by adjusting the oxygen gas flow rate in the range of 0 sccm to 10 sccm.

図6にWON膜の比抵抗と酸素のモル比率O/(O+N+W)の関係を示す。WON膜の比抵抗は、酸素のモル比率が増加するに従って増加する。WON膜を電極膜5として用いる場合、電極膜5の比抵抗を6000μΩ・cm以下にすることが望ましい。従って、本発明の一実施形態におけるWON膜の酸素のモル比率を0から0.22の範囲内に設定することが好ましい。   FIG. 6 shows the relationship between the specific resistance of the WON film and the molar ratio O / (O + N + W) of oxygen. The specific resistance of the WON film increases as the molar ratio of oxygen increases. When a WON film is used as the electrode film 5, it is desirable that the specific resistance of the electrode film 5 be 6000 μΩ · cm or less. Therefore, it is preferable to set the molar ratio of oxygen in the WON film in one embodiment of the present invention within the range of 0 to 0.22.

図7にWON膜の密度と酸素のモル比率O/(O+N+W)の関係を示す。図より、WON膜の密度は、酸素モル比率が増えるに従って減少することが解る。WON膜の密度が低下すると絶縁膜や、誘電体膜からの酸素の拡散により、WON膜の酸素モル比率が変化し、比抵抗の制御が困難となる。従って、WON膜の酸素モル比率は、密度を大幅に低下させることのない0から0.3の範囲で制御することが必要であり、10g/cc以上の密度が得られる酸素のモル比率O/(O+N+W)が、0<O/(O+N+W)≦0.22の範囲で制御することが好ましい。なお、密度の測定は、XRR(X−RAY Reflectometer X線反射率法)を用いて行った。   FIG. 7 shows the relationship between the density of the WON film and the molar ratio O / (O + N + W) of oxygen. From the figure, it can be seen that the density of the WON film decreases as the oxygen molar ratio increases. When the density of the WON film decreases, the oxygen molar ratio of the WON film changes due to the diffusion of oxygen from the insulating film or the dielectric film, making it difficult to control the specific resistance. Therefore, it is necessary to control the oxygen molar ratio of the WON film in the range of 0 to 0.3 without greatly reducing the density, and the molar ratio O / of oxygen that can obtain a density of 10 g / cc or more is required. (O + N + W) is preferably controlled in the range of 0 <O / (O + N + W) ≦ 0.22. In addition, the measurement of the density was performed using XRR (X-RAY Reflectometer X-ray reflectivity method).

WN膜及びWON膜の仕事関数を測定する為、SiO基板上に10nm
TiN膜を積層し、更に15nm WN膜若しくは15nm WONを積層し、更に3nm HfOxを積層したスタック構造を形成し、電気特性の測定を行った。尚、本明細書中における「仕事関数」とは、1個の電子をフェルミ準位から真空準位へ取り出すのに必要なエネルギーをいう。仕事関数の測定は、C−V測定器を用いて行った。図8にWONの仕事関数と酸素のモル比率O/(O+N+W)の関係を示す。WON膜の仕事関数は、酸素のモル比率の増加に従って増加するが、極大値を持ち、酸素のモル比率を0.14とすることにより4.9eV得られた。仕事関数が4.75eV以上を実現するには、酸素のモル比率が0から0.3の範囲で制御することが必要であり、好ましくは仕事関数が4.87eV以上である酸素のモル比率が0<O/(O+N+W)≦0.22の範囲を有することが好ましい。
In order to measure the work function of WN film and WON film, 10 nm on SiO 2 substrate
A stack structure was formed by laminating a TiN film, a 15 nm WN film or a 15 nm WON, and a 3 nm HfOx, and the electrical characteristics were measured. Note that the “work function” in this specification refers to the energy required to extract one electron from the Fermi level to the vacuum level. The work function was measured using a CV measuring device. FIG. 8 shows the relationship between the work function of WON and the molar ratio O / (O + N + W) of oxygen. The work function of the WON film increases as the molar ratio of oxygen increases, but has a maximum value, and 4.9 eV was obtained by setting the molar ratio of oxygen to 0.14. In order to realize a work function of 4.75 eV or more, it is necessary to control the molar ratio of oxygen in the range of 0 to 0.3, and preferably the molar ratio of oxygen having a work function of 4.87 eV or more is It preferably has a range of 0 <O / (O + N + W) ≦ 0.22.

次に、大気曝露によるWON膜中のO濃度の変化を防ぐないしは低減する為にTiN膜でCapしてWON膜の組成を測定した。
図9、10にそれぞれTiN膜/WN膜及びTiN膜/WON膜の積層膜を1000℃で熱処理した後の膜厚方向の組成を示す。組成は、SIMS(Secondary ionmass spectrometry 二次イオン質量分析法)により評価した。図9より、TiN/WNの積層膜は、1000℃で熱処理した後もTiN膜とWN膜の各金属は拡散することなく、2層に分離していることが解る。一方、図10より、TiN/WONの積層膜は、1000℃で熱処理することによりTiとWが相互拡散し、TiN/WONの界面が不明瞭となっていることが解る。以上の結果より、WON上に金属膜を積層し、更に熱処理が加わる場合は、WONと金属膜の間にWN膜を挿入することで、Wと金属の相互拡散を抑制出来ることが解る。すなわち、ゲート電極膜としてのWON膜上に、WとNとを含有する金属窒化物層としてのWN膜を形成することによって、WON膜上にTiN層等を形成する場合に、WのTiN層への拡散およびTiのWON膜への拡散を低減することができる。
Next, in order to prevent or reduce the change in O concentration in the WON film due to atmospheric exposure, the TiN film was capned and the composition of the WON film was measured.
FIGS. 9 and 10 show the composition in the film thickness direction after heat treatment of the laminated film of TiN film / WN film and TiN film / WON film at 1000 ° C., respectively. The composition was evaluated by SIMS (Secondary ionmass spectrometry secondary ion mass spectrometry). From FIG. 9, it can be seen that the TiN / WN laminated film is separated into two layers without diffusion of the metals of the TiN film and the WN film even after heat treatment at 1000 ° C. On the other hand, it can be seen from FIG. 10 that the TiN / WON laminated film is subjected to heat treatment at 1000 ° C., whereby Ti and W are interdiffused and the TiN / WON interface is unclear. From the above results, it is understood that when a metal film is laminated on WON and further heat treatment is applied, interdiffusion of W and metal can be suppressed by inserting a WN film between WON and the metal film. That is, when a TiN layer or the like is formed on a WON film by forming a WN film as a metal nitride layer containing W and N on the WON film as a gate electrode film, a TiN layer of W And diffusion of Ti into the WON film can be reduced.

また、金属酸窒化物を形成する工程が、図2に示す真空容器100内で、酸素と窒素の混合ガスからなる反応性ガス205と不活性ガス201の混合雰囲気下において上記金属酸窒化物層を形成するための金属ターゲット106、126をマグネトロンスパッタする工程である。該工程では、堆積速度の低下を抑制するため、反応性ガス205の供給量を金属ターゲット106、126の表面が酸化、窒化または酸窒化することにより生じるスパッタ率の低下率が最大となる供給量以下に設定することが好ましい。更に、形成される電極膜の膜厚均一性を±2.5%以下にするには、成膜中の真空容器100内の圧力を1×10−1Pa以下に設定することが好ましい。
なお、WとNを含有する金属窒化物層を形成する場合は、金属酸窒化物層を形成する工程と、金属窒化物層を形成する工程とを、基板を大気に暴露することなく真空中で連続して実施することが好ましい。
Further, the step of forming the metal oxynitride is performed in the vacuum vessel 100 shown in FIG. 2 in the mixed atmosphere of the reactive gas 205 and the inert gas 201 made of a mixed gas of oxygen and nitrogen. This is a step of magnetron sputtering the metal targets 106 and 126 for forming. In this step, in order to suppress a decrease in the deposition rate, the supply amount of the reactive gas 205 is the supply amount that maximizes the reduction rate of the sputtering rate caused by oxidizing, nitriding or oxynitriding the surfaces of the metal targets 106 and 126. It is preferable to set the following. Further, in order to make the film thickness uniformity of the formed electrode film ± 2.5% or less, it is preferable to set the pressure in the vacuum vessel 100 during film formation to 1 × 10 −1 Pa or less.
In the case of forming a metal nitride layer containing W and N, the step of forming the metal oxynitride layer and the step of forming the metal nitride layer are performed in a vacuum without exposing the substrate to the atmosphere. It is preferable to carry out continuously.

尚、上記の説明では、シリコン酸化膜1上に、SiO層2とSiN層3を積層し、誘電体膜4を堆積した後、電極膜5を形成したチャージトラップ型記憶装置の場合ついて述べたが、これらに限定されるものではない。例えば、TANOS型不揮発メモリにおける電極膜、FG型不揮発メモリ素子における浮遊電極とゲート電極、MOSトランジスタの一部に、本発明のWとNとOとを含有する金属酸窒化物層を適用することで、十分にその効果を得ることができる。
即ち、電極膜を有する半導体装置の製造方法に、本発明の方法(電極層としてWとNとOとを含有する金属酸窒化物層を形成する工程)を適用することができ、例えば、以下の製造方法が挙げられる。
1.上記本発明の方法を、少なくとも表面が半導体層で構成される基板と、該基板上に形成されたゲート電極と、上記基板と上記ゲート電極の間に順次積層された積層型ゲート絶縁膜を有する不揮発性半導体装置の製造方法に適用することができる。すなわち、上記積層型ゲート絶縁膜に含まれる絶縁膜の少なくとも一層を、上記本発明の方法により形成する。
2.また、本発明の一実施形態は、少なくとも表面が半導体層で構成される基板と、該基板上に形成されたゲート電極と、上記基板と上記ゲート電極の間に絶縁膜と浮遊電極と絶縁膜が順次積層された構造を有する不揮発性半導体装置であって、上記ゲート電極と上記浮遊電極の少なくとも一部が、本発明の電極膜(WとNとOとを含有する金属酸窒化物層)である不揮発性半導体装置をも含む。
In the above description, the charge trap type memory device in which the SiO 2 layer 2 and the SiN layer 3 are stacked on the silicon oxide film 1 and the dielectric film 4 is deposited and then the electrode film 5 is formed will be described. However, it is not limited to these. For example, the metal oxynitride layer containing W, N, and O of the present invention is applied to an electrode film in a TANOS type nonvolatile memory, a floating electrode and a gate electrode in an FG type nonvolatile memory element, and a part of a MOS transistor. Thus, the effect can be sufficiently obtained.
That is, the method of the present invention (a step of forming a metal oxynitride layer containing W, N, and O as an electrode layer) can be applied to a method for manufacturing a semiconductor device having an electrode film. The manufacturing method of these is mentioned.
1. The method of the present invention includes a substrate having at least a surface composed of a semiconductor layer, a gate electrode formed on the substrate, and a stacked gate insulating film sequentially stacked between the substrate and the gate electrode. The present invention can be applied to a method for manufacturing a nonvolatile semiconductor device. That is, at least one insulating film included in the stacked gate insulating film is formed by the method of the present invention.
2. In one embodiment of the present invention, a substrate having at least a surface formed of a semiconductor layer, a gate electrode formed on the substrate, an insulating film, a floating electrode, and an insulating film between the substrate and the gate electrode In which the gate electrode and the floating electrode are at least partially formed of the electrode film of the present invention (a metal oxynitride layer containing W, N, and O) The non-volatile semiconductor device is also included.

(第1の実施例:スパッタ法による実施例)
本発明の第1の実施例を、図面を参照しながら詳細に説明する。
(First Example: Example by Sputtering Method)
A first embodiment of the present invention will be described in detail with reference to the drawings.

図11は、誘電体膜303を有するMIS(metal insulator semiconductor)キャパシタを示した図である。表面に膜厚3nm〜5nmのシリコン酸化膜302を有するシリコン基板301に、誘電体膜303として、HfOx膜を堆積した後、電極膜304としてスパッタ法によりWON膜を堆積した。ターゲットとしては、Wの金属ターゲットを用い、スパッタガスとしてアルゴン、および酸素および窒素を用いた。なお、図11において、大気曝露によるWON膜中のO濃度の変化を防ぐないしは低減する為に、WON膜上にTiN膜を積層し熱処理を行う場合には、WON膜とTiN膜の間にWN膜を挿入してもよい。   FIG. 11 shows a MIS (metal insulator semiconductor) capacitor having a dielectric film 303. After a HfOx film was deposited as a dielectric film 303 on a silicon substrate 301 having a silicon oxide film 302 with a thickness of 3 nm to 5 nm on the surface, a WON film was deposited as an electrode film 304 by a sputtering method. A W metal target was used as the target, and argon, oxygen, and nitrogen were used as the sputtering gas. In FIG. 11, in order to prevent or reduce the change in O concentration in the WON film due to atmospheric exposure, when a TiN film is stacked on the WON film and heat treatment is performed, the WN is interposed between the WON film and the TiN film. A membrane may be inserted.

基板温度は27℃〜600℃、ターゲットパワーは50W〜1000W、スパッタガス圧は0.02Pa〜0.1Pa、Arガス流量は1sccm〜200sccm、酸素ガス流量は1sccm〜100sccm、窒素ガス流量は1sccm〜100sccm、の範囲内で適宜決定することができる。   The substrate temperature is 27 ° C. to 600 ° C., the target power is 50 W to 1000 W, the sputtering gas pressure is 0.02 Pa to 0.1 Pa, the Ar gas flow rate is 1 sccm to 200 sccm, the oxygen gas flow rate is 1 sccm to 100 sccm, and the nitrogen gas flow rate is 1 sccm to It can be determined as appropriate within the range of 100 sccm.

ここでは、基板温度30℃、Hfのターゲットパワー500W、スパッタガス圧0.03Pa、Arガス流量25sccm、酸素流量0sccm〜20sccmとして成膜を行った。   Here, the film was formed at a substrate temperature of 30 ° C., a Hf target power of 500 W, a sputtering gas pressure of 0.03 Pa, an Ar gas flow rate of 25 sccm, and an oxygen flow rate of 0 sccm to 20 sccm.

このとき、誘電体膜303の酸素モル比率O/(Hf+O)は、Hfターゲットパワーと酸素流量によって制御することができる。   At this time, the oxygen molar ratio O / (Hf + O) of the dielectric film 303 can be controlled by the Hf target power and the oxygen flow rate.

誘電体膜303として、上述の形成工程を用いた酸素モル比率0≦O/(Hf+O)≦0.50の範囲のHfOx膜としての誘電体膜303を膜厚5nm〜25nmの範囲で成膜した。   As the dielectric film 303, a dielectric film 303 as a HfOx film having an oxygen molar ratio in the range of 0 ≦ O / (Hf + O) ≦ 0.50 using the above-described formation step was formed in a thickness range of 5 nm to 25 nm. .

尚、ここでは誘電体膜303として、HfOx膜を用いたが、Al、HfAlONも適宜、用いることができる。また、これらからなる群のうちから選択される膜を堆積してもよい。Although the HfOx film is used here as the dielectric film 303, Al 2 O 3 and HfAlON can also be used as appropriate. Further, a film selected from the group consisting of these may be deposited.

基板温度30℃、Wのターゲットパワー500W、スパッタガス圧0.03Pa、Arガス流量25sccm、窒素流量15sccm、酸素流量0sccm〜50sccmとして電極膜304の成膜を行った。   The electrode film 304 was formed at a substrate temperature of 30 ° C., a target power of 500 W at W, a sputtering gas pressure of 0.03 Pa, an Ar gas flow rate of 25 sccm, a nitrogen flow rate of 15 sccm, and an oxygen flow rate of 0 sccm to 50 sccm.

このとき、本実施例の電極膜304のモル比率O/(O+N+W)は、WターゲットパワーとO流量とN流量によって制御することができる。図5は、本実施例において形成した電極膜304のモル比率O/(O+N+W)の酸素流量依存性を示す。組成は、AES(AugerElectron
Spectroscopy オージェ電子分光法)による分析により評価した。このように、酸素流量を調節することにより、0〜0.3の範囲でモル比率O/(O+N+W)を制御できることを確認した。
At this time, the molar ratio O / (O + N + W) of the electrode film 304 of the present embodiment can be controlled by the W target power, the O flow rate, and the N flow rate. FIG. 5 shows the oxygen flow rate dependency of the molar ratio O / (O + N + W) of the electrode film 304 formed in this example. The composition is AES (AugerElectron
(Evaluation by spectroscopic Auger electron spectroscopy). Thus, it was confirmed that the molar ratio O / (O + N + W) could be controlled in the range of 0 to 0.3 by adjusting the oxygen flow rate.

次に、窒素雰囲気中で1000℃の温度において10secのアニール処理を行い、誘電体膜303を結晶化させた。尚、ここでは電極膜(WON膜)304を堆積した後、アニール処理を行ったが、電極膜(WON膜)304を堆積する前にアニール処理を行ってもよい。また、ここでは窒素雰囲気中でアニール処理を行ったが、酸素雰囲気、Ar等の不活性ガス雰囲気を適宜、用いることができる。また、これらからなる群のうち選択される雰囲気中でアニールしてもよい。   Next, annealing was performed for 10 seconds at a temperature of 1000 ° C. in a nitrogen atmosphere to crystallize the dielectric film 303. Although the annealing process is performed after the electrode film (WON film) 304 is deposited here, the annealing process may be performed before the electrode film (WON film) 304 is deposited. Further, although the annealing treatment is performed here in a nitrogen atmosphere, an oxygen atmosphere or an inert gas atmosphere such as Ar can be used as appropriate. Moreover, you may anneal in the atmosphere selected from the group which consists of these.

次に、リソグラフィー技術とRIE技術を用いて電極膜(WON膜)304を所望の大きさに加工し、MISキャパシタ構造を形成した。   Next, the electrode film (WON film) 304 was processed into a desired size using a lithography technique and an RIE technique to form a MIS capacitor structure.

以上のように作製した電極膜(WON膜)304の比抵抗を評価した。図6に示した酸素のモル比率とWON膜の比抵抗の関係より、酸素のモル比率0<(O/(O+N+W))≦2.2の範囲で、比抵抗が6000μΩ・cm以下となる。   The specific resistance of the electrode film (WON film) 304 produced as described above was evaluated. From the relationship between the molar ratio of oxygen and the specific resistance of the WON film shown in FIG. 6, the specific resistance is 6000 μΩ · cm or less in the range of the molar ratio of oxygen 0 <(O / (O + N + W)) ≦ 2.2.

図7にWONの密度と酸素のモル比率O/(O+N+W)の関係を示す。図より、WONの密度は、酸素のモル比率が増えるに従って減少することが解る。   FIG. 7 shows the relationship between the density of WON and the molar ratio of oxygen O / (O + N + W). From the figure, it can be seen that the density of WON decreases as the molar ratio of oxygen increases.

図8はWONの仕事関数と酸素のモル比率O/(O+N+W)の関係を示す。WONの仕事関数は、酸素含有量の増加に従って増加するが、極大値を持ち、酸素のモル比率を0.14とすることにより4.9eVが得られた。仕事関数が4.75eV以上を実現するには、酸素のモル比率が0から0.3の範囲で制御することが必要であり、好ましくは仕事関数が4.87eV以上であるモル比率が0から0.22の範囲で制御することが好ましい。   FIG. 8 shows the relationship between the work function of WON and the molar ratio O / (O + N + W) of oxygen. The work function of WON increases as the oxygen content increases, but has a maximum value, and 4.9 eV was obtained by setting the molar ratio of oxygen to 0.14. In order to realize a work function of 4.75 eV or more, it is necessary to control the molar ratio of oxygen in the range of 0 to 0.3, and preferably the molar ratio of work function of 4.87 eV or more is from 0 to 0. It is preferable to control within the range of 0.22.

以上のことからわかるように、本実施例によれば、WとNとOを含有する複合酸窒化物からなる電極膜であって、WとOとNのモル比率O/(O+N+W)が0から0.22の間であり、成膜速度が5nm/min以上であり、膜密度が10g/cm以上である電極膜において、仕事関数が4.9eV以上の高仕事関数が得られることがわかる。As can be seen from the above, according to this example, the electrode film is composed of a composite oxynitride containing W, N, and O, and the molar ratio O / (O + N + W) of W, O, and N is 0. In an electrode film having a film formation rate of 5 nm / min or more and a film density of 10 g / cm 3 or more, a work function of 4.9 eV or more can be obtained. Recognize.

(第2の実施例:不揮発メモリ素子の電極膜に適用した実施例)
図12は本発明の第2の実施例に関わる半導体素子の作製工程を示した断面図である。
(Second Embodiment: Embodiment Applied to Electrode Film of Nonvolatile Memory Element)
FIG. 12 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the second embodiment of the present invention.

まず図12の工程121に示すようにシリコン基板401の表面にSTI(Shallow Trench Isolation)技術を用いて素子分離領域402を形成した。   First, as shown in Step 121 of FIG. 12, an element isolation region 402 was formed on the surface of the silicon substrate 401 by using STI (Shallow Trench Isolation) technology.

続いて、素子分離されたシリコン基板401表面に、第1の絶縁膜403としてシリコン酸化膜を熱酸化膜法により30Å〜100Å形成した。続いて、第2の絶縁膜404としてシリコン窒化膜をLPCVD(Low Pressure Chemical Vapor Deposition)法により30Å〜100Å形成した。続いて、第3の絶縁膜405として、酸化アルミニウム膜を5Å〜50Å形成した。酸化アルミニウム膜は、MOCVD法、ALD(Atomic Layer Deposition)法、PVD(Physical Vapor Deposition)法を用いてもよい。続いて、第4の絶縁膜406として、HfAlON膜を膜厚5nm〜20nmの範囲で形成した。続いて、第5の絶縁膜407として、酸化アルミニウム膜を5Å〜50Å形成した。形成方法は、MOCVD法、ALD法、PVD法を用いて形成した。   Subsequently, a silicon oxide film was formed as a first insulating film 403 on the surface of the isolated silicon substrate 401 by a thermal oxide film method by 30 to 100 mm. Subsequently, a silicon nitride film was formed as the second insulating film 404 by 30 to 100 by LPCVD (Low Pressure Chemical Vapor Deposition). Subsequently, an aluminum oxide film having a thickness of 5 to 50 mm was formed as the third insulating film 405. The aluminum oxide film may be formed by MOCVD, ALD (Atomic Layer Deposition), or PVD (Physical Vapor Deposition). Subsequently, an HfAlON film having a thickness of 5 nm to 20 nm was formed as the fourth insulating film 406. Subsequently, an aluminum oxide film having a thickness of 5 to 50 mm was formed as the fifth insulating film 407. As a forming method, MOCVD method, ALD method, and PVD method were used.

次に、ゲート電極408として厚さ10nmのWON膜を形成した。WON膜はPVD法を用いて作成した。ゲート電極の作製後、図12の工程122に示すように、リソグラフィー技術およびRIE(Reactive Ion Etching)技術を用いてゲート電極に加工し、引き続きイオン注入を行い、エクステンション領域409を、ゲート電極をマスクとして自己整合的に形成した。さらに、図12の工程123に示すように、シリコン窒化膜とシリコン酸化膜を順次堆積し、その後エッチバックすることによってゲート側壁410を形成した。この状態で再度イオン注入を行い、活性化アニールを経てソース・ドレイン領域411を形成した。なお、図12において、大気曝露によるWON膜中のO濃度の変化を防ぐないしは低減する為に、WON膜上にTiN膜を積層し熱処理を行う場合には、WON膜とTiN膜の間にWN膜を挿入してもよい。   Next, a WON film having a thickness of 10 nm was formed as the gate electrode 408. The WON film was created using the PVD method. After the fabrication of the gate electrode, as shown in Step 122 of FIG. 12, the gate electrode is processed using lithography technology and RIE (Reactive Ion Etching) technology, and then ion implantation is performed, and the extension region 409 is masked with the gate electrode. As self-aligned. Furthermore, as shown in step 123 of FIG. 12, a gate sidewall 410 is formed by sequentially depositing a silicon nitride film and a silicon oxide film and then etching back. In this state, ion implantation was performed again, and source / drain regions 411 were formed through activation annealing. In FIG. 12, in order to prevent or reduce the change in O concentration in the WON film due to exposure to the atmosphere, when a TiN film is stacked on the WON film and heat treatment is performed, the WN is interposed between the WON film and the TiN film. A membrane may be inserted.

以上のように作製した電極膜408の仕事関数と半導体素子の信頼性を評価した。   The work function of the electrode film 408 manufactured as described above and the reliability of the semiconductor element were evaluated.

図8に示したWONの仕事関数と酸素のモル比率O/(O+N+W)の関係より、WONの仕事関数は、酸素のモル比率の増加に従って増加するが、極大値を持ち、酸素のモル比率を0.14とすることにより4.9eV得られた。   From the relationship between the work function of WON and the molar ratio of oxygen O / (O + N + W) shown in FIG. 8, the work function of WON increases as the molar ratio of oxygen increases, but has a maximum value, and the molar ratio of oxygen increases. By setting it to 0.14, 4.9 eV was obtained.

下記表1に様々な上部電極膜に対するリーク電流及び信頼性の関係を示す。なお、下記表1の「Top electrode」はゲート電極、「ProgramΔVfb」は書き込み時と消去時の電圧差、「Retention% Vfb change」は信頼性、「CET」は電気的酸化膜換算膜厚、「J at」は印加電圧を示す。   Table 1 below shows the relationship between leakage current and reliability for various upper electrode films. In Table 1 below, “Top electrode” is the gate electrode, “Program ΔVfb” is the voltage difference between writing and erasing, “Retention% Vfb change” is reliability, “CET” is the equivalent oxide film thickness, “J at” indicates an applied voltage.

Figure 0005463423
Figure 0005463423

上記表1より、WON膜をゲート電極とした場合、印加電圧20V(J at 20V)におけるリーク電流(0.00019)は、TiN電極のリーク電流(0.0003)やWN電極のリーク電流(0.00027)よりも低く、酸素のモル比率を増加すると更にリーク電流は低減することが解った。又、仕事関数が最大となった酸素のモル比率が0.14のWON膜を電極とした場合、信頼性は向上し、Vfbchange比率が5.41%とTiN膜を用いた場合の2倍以上の改善が観られた。   From Table 1 above, when the WON film is a gate electrode, the leakage current (0.00019) at an applied voltage of 20 V (J at 20 V) is the leakage current of the TiN electrode (0.0003) or the leakage current of the WN electrode (0 It is found that the leakage current is further reduced when the molar ratio of oxygen is increased. In addition, when the WON film having a molar ratio of oxygen having a maximum work function of 0.14 is used as an electrode, the reliability is improved, and the Vfbchange ratio is 5.41%, which is more than double that when a TiN film is used. The improvement was seen.

このように、本実施例によれば、WON(酸素のモル比率0<(O/(O+N+W)≦0.3)で表され、スパッタ実施することにより仕事関数が4.9eV以上であり、かつリーク電流値の低減し、信頼性を向上することができる電極膜が得られることを確認した。なお、図13は実施例2の半導体装置の断面図であり、601はpoly−Siを示す。   Thus, according to this example, WON (molar ratio of oxygen 0 <(O / (O + N + W) ≦ 0.3) is represented, and the work function is 4.9 eV or more by performing sputtering, and It was confirmed that an electrode film capable of reducing the leakage current value and improving the reliability was obtained, wherein Fig. 13 is a cross-sectional view of the semiconductor device of Example 2, and 601 represents poly-Si.

(第3の実施例:スタックトゲート型メモリセルの電極膜に適用した実施例)
本発明の電極膜は、公知のスタックトゲート型メモリセルの浮遊ゲートFG又は制御ゲートCGにも適用可能である。本発明の電極膜を浮遊ゲートFG又は制御ゲートCGに適用することにより、仕事関数が4.9eV以上であり、かつリーク電流値の低減し、信頼性を向上することができる浮遊ゲートFG又は制御ゲートCGが得られることを確認した。
(Third embodiment: an embodiment applied to an electrode film of a stacked gate type memory cell)
The electrode film of the present invention can also be applied to a floating gate FG or a control gate CG of a known stacked gate type memory cell. By applying the electrode film of the present invention to the floating gate FG or the control gate CG, the work function is 4.9 eV or more, the leakage current value is reduced, and the reliability can be improved. It was confirmed that a gate CG was obtained.

Claims (3)

シリコン基板上に、トンネル酸化膜、チャージトラップ膜、ブロッキング絶縁膜、およびゲート電極がこの順番で形成された積層構造を有し、前記ゲート電極に電圧を印加することによって、前記シリコン基板側から前記チャージトラップ膜に電荷をトラップ及びデトラップして情報の書き込み及び消去を行うチャージトラップ型記憶装置の製造方法であって、
前記トンネル酸化膜、前記チャージトラップ膜、および前記ブロッキング絶縁膜が順に形成された前記シリコン基板を用意する工程と、
前記ブロッキング絶縁膜上にWとNとOを含有する金属酸窒化物層を形成する工程と、
前記金属酸窒化物層上にWとNを含有する金属窒化物層を形成する工程とを有し、
前記金属酸窒化物層及び前記金属窒化物層を形成する工程が、
真空容器内で、反応性ガスと不活性ガスの混合雰囲気下において前記金属酸窒化物層及び前記金属窒化物層に含まれる金属からなる金属ターゲットをマグネトロンスパッタする工程であり、
前記金属酸窒化物層を形成する工程における前記反応性ガスが酸素及び窒素であり、
前記金属窒化物層を形成する工程における前記反応性ガスが窒素であることを特徴とするチャージトラップ型記憶装置の製造方法。
On the silicon substrate, a tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode have a laminated structure formed in this order, and by applying a voltage to the gate electrode, the silicon substrate side A charge trap memory device manufacturing method for writing and erasing information by trapping and detrapping charges in a charge trap film,
Preparing the silicon substrate on which the tunnel oxide film, the charge trap film, and the blocking insulating film are sequentially formed;
Forming a metal oxynitride layer containing W, N and O on the blocking insulating film;
Forming a metal nitride layer containing W and N on the metal oxynitride layer,
Forming the metal oxynitride layer and the metal nitride layer,
In a vacuum vessel, magnetron sputtering a metal target made of metal contained in the metal oxynitride layer and the metal nitride layer in a mixed atmosphere of a reactive gas and an inert gas,
The reactive gas in the step of forming the metal oxynitride layer is oxygen and nitrogen;
A method for manufacturing a charge trap memory device, wherein the reactive gas in the step of forming the metal nitride layer is nitrogen.
前記マグネトロンスパッタする工程は、前記金属ターゲットの表面が酸化、窒化または酸窒化することにより生じるスパッタ率の低下率が最大となる供給量以下に、前記反応性ガス又は不活性ガスの供給量を設定することを特徴とする請求項1に記載のチャージトラップ型記憶装置の製造方法。   The magnetron sputtering step sets the supply amount of the reactive gas or the inert gas below the supply amount that maximizes the reduction rate of the sputtering rate caused by oxidation, nitridation, or oxynitridation of the surface of the metal target. The method of manufacturing a charge trap memory device according to claim 1. 前記真空容器内の圧力を1×10−1Pa以下に設定することを特徴とする請求項1に記載のチャージトラップ型記憶装置の製造方法。 2. The method for manufacturing a charge trap memory device according to claim 1, wherein the pressure in the vacuum vessel is set to 1 × 10 −1 Pa or less.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173796A (en) * 2005-12-19 2007-07-05 Internatl Business Mach Corp <Ibm> SEMICONDUCTOR STRUCTURE USING METAL OXYNITRIDE ACTING AS pFET MATERIAL AND ITS MANUFACTURING METHOD
JP2008244163A (en) * 2007-03-27 2008-10-09 Toshiba Corp Memory cell of nonvolatile semiconductor memory
JP2009081203A (en) * 2007-09-25 2009-04-16 Toshiba Corp Nonvolatile semiconductor memory, and manufacturing method thereof
JP2010045395A (en) * 2009-11-16 2010-02-25 Toshiba Corp Non-volatile semiconductor storage device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173796A (en) * 2005-12-19 2007-07-05 Internatl Business Mach Corp <Ibm> SEMICONDUCTOR STRUCTURE USING METAL OXYNITRIDE ACTING AS pFET MATERIAL AND ITS MANUFACTURING METHOD
JP2008244163A (en) * 2007-03-27 2008-10-09 Toshiba Corp Memory cell of nonvolatile semiconductor memory
JP2009081203A (en) * 2007-09-25 2009-04-16 Toshiba Corp Nonvolatile semiconductor memory, and manufacturing method thereof
JP2010045395A (en) * 2009-11-16 2010-02-25 Toshiba Corp Non-volatile semiconductor storage device

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