JP5460023B2 - Wafer pattern inspection method and apparatus - Google Patents

Description

  The present invention relates to a pattern inspection method and apparatus for inspecting a wafer pattern.

Conventionally, for example, as shown in claim 1 of Patent Document 1, a means for inputting a wafer inspection image, a means for comparing the input inspection image with a pre-stored master image, and the difference between the comparison images Means for determining whether or not the wafer is good, means for storing the inputted inspection image as a new master image when the difference amount is equal to or smaller than a predetermined value, and means for outputting the result of good or bad judgment. A wafer pattern inspection apparatus is known.
Japanese Patent Laid-Open No. 5-281151

  However, the conventional pattern matching inspection cannot be performed if the patterns are greatly different. This is because the difference amount is too large and the determination result may always be negative.

  On the other hand, at present, wafers having different patterns depending on the manufacturing process, that is, wafers having different pattern deviations, color irregularities, and the like may be subject to inspection.

  Also, depending on the product, the difference in pattern may not be a problem in quality and performance. Such products could not be properly inspected by wafer pattern matching inspection.

  On the other hand, in the case of wafers having different patterns, the inspection can be performed to some extent if the learning process and the inspection sensitivity for the difference are reduced.

  However, if the difference learning process and the detection sensitivity are made too sweet, the detectability deteriorates.

  In addition, when the learning process is automatically performed, it is difficult to ensure desired detectability.

An object of the present invention is to provide a wafer pattern inspection method and apparatus that enable an automatic learning function that can reduce (decrease) the detection sensitivity of wafers having different patterns depending on the product .

  Examples of the solving means of the present invention for solving the above-described problems are a wafer pattern inspection method and apparatus described in each of the claims.

  Even if there is a pattern or chip with greatly different pattern deviation or color unevenness from the original reference, it is judged whether it is a non-defective wafer as a product that does not cause a problem in product performance. Can maintain the non-defective rate.

  The best mode for carrying out the present invention will be described below.

  (1) If a large amount of over-detection occurs during the inspection (when the yield rate is extremely reduced), the learning process is performed again. More specifically, after learning the pattern by the learning process, a uniform pattern is searched. If it is a uniform pattern portion, the wafer is inspected by an inspection other than the pattern inspection such as a pitch inspection.

  (2) The pattern inspection and the pitch inspection are simultaneously performed on the uniform pattern portion, and the sensitivity of the pattern inspection is determined from the result of the pitch inspection.

  (3) The pattern or chip on the entire wafer surface is inspected with the sensitivity determined as described above.

  By doing so, it is possible to determine a non-defective product as a wafer that does not cause a problem in product performance even when the patterns are greatly different, and to maintain the work efficiency of inspection and the maintenance of the original non-defective product rate.

  When the non-defective product rate is extremely reduced to be equal to or less than a predetermined threshold, the learning process is performed again. The predetermined threshold can be arbitrarily set by the user of the apparatus (for example, a non-defective product between 90 and 95%). rate). However, the predetermined threshold value may be fixed to only one desired value, or only the lowest value may be fixed, and the desired value may be made variable and adjusted as necessary. Also good. For example, the lowest value may be fixed at 90%, and an arbitrary threshold value (for example, 95%) higher than that may be set. In particular, it is preferable to be able to adjust to a desired threshold according to the inspection object.

  The present invention includes a step of inputting an inspection image of a wafer pattern or chip, comparing the input inspection image with a pre-stored reference image, and determining whether the wafer is good or bad based on a difference amount of the comparison image. The pattern inspection method and apparatus are improved.

  In the present invention, when the non-defective product rate is extremely decreased during inspection and becomes a predetermined value (for example, 90%, 95%, or other values), the pattern or chip image under inspection is learned as a reference image. Perform the process again or search for a uniform pattern after learning the pattern in the learning process, and if it is a uniform pattern part, inspect the wafer by an inspection other than the pattern inspection such as pitch inspection, or uniform pattern part The pattern inspection and the pitch inspection are performed simultaneously to determine the sensitivity of the pattern inspection, and the pattern or chip on the entire wafer surface is inspected with the determined sensitivity.

  A preferred embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows an appearance inspection apparatus 10 suitable for carrying out a wafer pattern (appearance) inspection method according to the present invention.

  In FIG. 1A, an appearance inspection apparatus 10 has each circuit pattern formed on a large number of semiconductor chips 11a formed in alignment on a semiconductor wafer 11 as shown in FIG. Used to determine if the defect is acceptable. Hereinafter, the present invention will be described along an example in which the present invention is applied to an inspection of a semiconductor chip 11 a formed on a semiconductor wafer 11.

  As shown in FIG. 1A, the appearance inspection apparatus 10 controls the operation of the optical imaging mechanism 10a and the optical imaging mechanism, and performs arithmetic processing on the image information obtained by the optical imaging mechanism 10a. And a control calculation means 10b.

  The optical imaging mechanism 10a moves the moving unit 12 provided with the stage 12a for holding the semiconductor wafer 11 and the stage 12a of the moving unit in the X-axis direction and the Y-axis direction on the XY plane, and moves around the Z-axis. And an imaging unit 15 for capturing a surface image of a desired semiconductor chip 11a formed on the semiconductor wafer 11 on the stage 12a under illumination by the illumination unit 14. As is well known in the art, the imaging unit 15 is constituted by, for example, a CCD imaging device and its optical system.

  The control arithmetic means (arithmetic processing unit) 10 b includes an arithmetic processing circuit 16, and the arithmetic processing circuit 16 can be configured by a central processing unit (CPU) that operates in accordance with a program stored in the memory 17, for example. . The arithmetic processing circuit 16 controls the operations of the driver 13, the illumination unit 14, and the imaging unit 15 of the optical imaging mechanism 10a via the control circuit 18, and is obtained by the imaging unit 15 according to the information stored in the memory 17. The detected image is subjected to defect detection processing.

  The arithmetic processing circuit 16 includes an area setting unit 16a for dividing the inspection region of the image obtained by the imaging unit 15 into a plurality of areas, and a defect by comparing the inspection region of the image with a template for inspection. A defect extraction unit 16b for extracting a part, a determination unit 16c for determining whether or not the defect part extracted by the defect extraction part is within an allowable range, and a pattern that is within the allowable range but has no problem in product performance. When there is a deviation, a learning function unit 16d is provided that learns the image of the shifted pattern, the image of the chip, or the average image thereof as a reference image (reference image or reference image).

  The arithmetic processing circuit 16 is connected to a monitor 19 having a display unit composed of, for example, a liquid crystal or a CRT, and an input unit 20 composed of, for example, a keyboard and a mouse. The monitor 19 can display an image captured by the imaging unit 15 and an image processed by the arithmetic processing circuit 16, and can display information necessary for operating the optical imaging mechanism 10a. Based on the information displayed on the monitor 19, a command necessary for operating the appearance inspection apparatus 10 can be appropriately input from the input unit 20.

  The imaging unit 15 captures a reference image (reference image or standard image) and an image for the object to be inspected. A desired inspection region is cut out from the surface image of the semiconductor chip 11 a photographed by the imaging unit 15 and displayed on the monitor 19.

  In FIG. 2, the image on the left is an example of the display screen 21A for the examination area cut out as described above. This display screen 21A shows an example in which the semiconductor chip 11a is a memory chip.

  FIG. 6 shows a pattern image and a chip image. In the surface image, a defective portion is observed at a position indicated by a star, that is, a star. The observed defect is a defect such as adhesion of a foreign substance to the circuit pattern or a partial defect of the circuit pattern.

  In the reference image (reference image), the surface image (21A) of the highest quality semiconductor chip 11a with few defects such as defects and foreign matters among the surface images 21A obtained from the respective semiconductor chips 11a of the semiconductor wafer 11; Alternatively, an average image is selected and used as a reference image (reference image). This reference image (reference image) and the surface image 21A of the other semiconductor chip 11a that is the inspection object, that is, the inspection object, are compared by the arithmetic processing circuit 16 for defect extraction.

  As is well known in the art, the arithmetic processing circuit 16 compares a reference image (reference image) with an image of the semiconductor chip 11a of the object to be inspected. For the entire pattern image or a part of the chip image in the pattern image, the sensitivity adjustment is performed for the reference image (reference image) and the entire pattern or chip of the object to be inspected.

  At that time, as preprocessing, shading processing for removing illumination unevenness by the illumination unit 14, multi-value processing for promoting the clarification of edges, and reducing the influence of pattern density and image shading upon edge detection For example, color tone conversion processing for color recognition, chromaticity conversion for facilitating pattern recognition, or expansion / contraction processing using an expansion / contraction filter for removing noise is performed. These processes can be performed by a well-known method. These can be appropriately selected and combined.

  The arithmetic processing circuit 16 compares the reference image (reference image) with the image subjected to the image preprocessing of the object to be inspected, and uses the reference image (reference image) based on pattern density, image density, chromaticity, and the like. Adjust the detection sensitivity.

  Hereinafter, an example of the optimal inspection procedure will be described.

  As shown in FIG. 2, in the pattern inspection, an image to be compared is registered in advance.

  First, a reference image (reference image) as a reference for inspection is created (recipe creation). In this case, the reference image (reference image) is, for example, one chip. However, a plurality of chip images may be set as a reference image.

  The reference image (reference image) is stored in a storage unit (memory) provided separately from the arithmetic processing unit of the apparatus, and is learned through the learning function of the arithmetic processing unit. After learning, the average image is stored in the storage unit as a reference image (reference image).

  As a result, as shown in FIG. 3, since the left pattern matches the reference image (reference image), it is determined to be inspected, but the right pattern is different from the reference image (reference image). , It is determined that the inspection is NG.

  However, in this case, since the pattern is misaligned, the pattern (or chip) of the wafer to be inspected becomes NG, but some products do not cause any pattern misalignment. Therefore, when the non-defective product ratio (ratio of non-defective products with a small difference from the reference image) falls below a predetermined value, a reference image (reference image) is automatically recreated. For example, if the non-defective product rate suddenly drops to 95% while continuing the pattern inspection operation at a good product rate of approximately 97%, if the threshold is set to 95%, the reference image (reference image) is automatically set there. ) And restart pattern inspection at the non-defective rate.

  As shown in FIG. 4, although the non-defective product rate has decreased to 95%, for example, a reference image is re-created using a wafer pattern (or chip) with a shift that does not cause a problem in the product as a reference image. The average image is changed, the reference image (reference image) is relearned, and the wafer pattern or chip inspection is restarted based on the reference image (reference image).

  As shown in FIG. 5, when the reference image (reference image) is corrected, the inspection result is OK even if the pattern is different from the pattern before the reference image correction.

  According to the present invention, for example, when the non-defective product rate is lower than the minimum 90%, for example, 85%, or another predetermined value, the re-learning process is immediately performed, and the reference image (reference image) is obtained. It is desirable to make it again.

  Note that the present invention is not limited to a fixed fixed product rate (95% or other set values), and the operator can achieve a predetermined minimum product rate (for example, 90%, but not limited to this). The learning function can be adjusted to re-learn freely at any threshold within the range.

  Preferably, the arithmetic control unit has a function of automatically adjusting the detection sensitivity in combination with the pattern inspection based on the reference image (reference image). Here, the automatic adjustment of sensitivity refers to a function of automatically determining sensitivity by comparing the detectability of pattern inspection and pitch inspection.

  As shown in FIG. 6, in the pattern inspection, the entire chip is usually compared with the entire reference image (reference image) to check whether or not they match, but only the pitch that is a uniform pattern portion of the pattern is checked. It is preferable to perform the pitch inspection to be performed at the same time.

  Preferably, the pattern inspection sensitivity is adjusted so that the same defect can be detected by comparing the pattern inspection result with the pitch inspection result. The detection sensitivity of the pattern inspection is adjusted so that the reflected light detection sensitivity and the like in the pattern inspection are substantially the same in the pattern inspection and the pitch inspection.

  The pattern inspection can inspect the entire chip, but the pitch inspection can usually inspect only the uniform pattern portion.

  FIG. 7 shows a flowchart.

  In this illustrated example, a recipe is created with the first wafer and wafer inspection is performed. When the non-defective product rate is lower than a set value (for example, 90%), the learning process is performed on the wafer under inspection. The inspection is performed again based on the re-learned reference image (reference image). The inspection result of the re-learned reference image (reference image) is stored as the wafer inspection result, and the inspection is terminated.

  It is preferable to deal with the following in response to a chip whose pattern has shifted.

  Even if there is a shift in the pattern for each lot or for each wafer, it is possible to make it non-defective. If the pattern is misaligned, the generated wafer is subjected to the learning process again and inspected.

  Although it is not easy for the apparatus to automatically determine whether the cause of the decrease in the non-defective product rate is a pattern shift, it is preferable to perform the learning process again when the non-defective product rate falls below a predetermined threshold.

  In a preferred aspect of the present invention, the learning process is performed again when the yield rate falls below a predetermined threshold.

  In the experimental example, when the non-defective product rate was reduced and the inspection was performed again, the inspection was able to greatly suppress the excessive detection of pattern deviation.

  Depending on the wafer, the detection performance may be reduced by learning. For example, the deterioration in detection performance is noticeable in wafers with severe color irregularities and wafers with continuous defects at the same position, but these wafers can also be used together with pitch inspection and by adjusting detection sensitivity. It is possible to determine a pattern or chip that does not cause a problem in performance as a non-defective product, and to maintain the inspection work efficiency and the original good product rate.

The figure which shows the outline of the pattern inspection apparatus of the wafer which concerns on this invention. The figure for demonstrating recipe (reference) creation. The figure for demonstrating the test | inspection based on a recipe (reference). The figure for demonstrating recipe creation after re-learning. The figure for demonstrating the test | inspection after re-learning. The figure for demonstrating the difference of a pattern test | inspection and a pitch test | inspection. The figure which shows a flowchart.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Appearance inspection apparatus 11 Semiconductor wafer 12 Moving part 13 Driver 14 Illumination part 15 Imaging part 16 Arithmetic processing circuit 17 Memory 19 Monitor 20 Input part

Claims (2)

The inspection image of the wafer pattern or chip to be inspected is input, the input inspection image is compared with the pre-stored reference image to check whether they match, and the quality of the wafer is determined by the difference in the comparison image. A wafer pattern inspection method comprising a step of determining,
If non-defective rate during the test drops below a predetermined threshold value, to automatically re-create the reference image, again performs a learning process using the pattern or chip image under examination as a reference image, in which the pattern is deviation and is re-learned by using the pattern of the wafer is shifted to not a performance problem in products as a reference image,
Perform pattern inspection and pitch inspection based on the re-learned reference image ,
A wafer pattern inspection method comprising: determining a pattern inspection sensitivity from a pattern inspection result and a pitch inspection result, and inspecting a pattern or a chip on the entire wafer surface with the determined sensitivity. A means for inputting an inspection image of a wafer pattern or chip to be inspected, a means for comparing the input inspection image with a pre-stored reference image and inspecting whether or not they match, and a wafer based on the comparison result A wafer pattern inspection apparatus comprising: an arithmetic processing unit having a determination unit that determines whether the quality is good or bad;
If non-defective rate during the test drops below a predetermined threshold value, to automatically re-create the reference image, again performs a learning process using the pattern or chip image under examination as a reference image, in which the pattern is deviation and is re-learned by using the pattern of the wafer is shifted to not a performance problem in products as a reference image,
Perform pattern inspection and pitch inspection based on the re-learned reference image ,
A wafer pattern inspection apparatus characterized by determining a pattern inspection sensitivity from a pattern inspection result and a pitch inspection result, and inspecting a pattern or a chip on the entire surface of the wafer with the determined sensitivity.

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