JP5457104B2 - Cross compiler - Google Patents

Description

  The present invention relates to a cross compiler for generating an object program intended to operate in a specific target system environment.

  Conventionally, an electronic circuit provided with a shared bus that is shared by a sound source that accesses waveform data stored in a storage means and a CPU that accesses a program / data stored in the storage means and is used alternately in a time-sharing manner. In the sound generator, the program development of the CPU has been performed so as to simply convert the program language into machine language instructions.

  However, when the program is developed as described above, it is necessary to separate the access timing between the sound source and the CPU at the time of program execution, and the sound source uses the bus even when an instruction that does not use the bus is executed by the CPU. During this period, there is a problem that the CPU must wait for the execution of the CPU, resulting in a problem that the processing speed decreases. Especially when pipeline processing is executed, the problem is remarkably reflected.

  The present invention was devised in view of the above problems, and is a cross compiler for generating an object program intended to operate in the electronic sound generator environment, and operates in the environment. It is intended to provide a cross compiler that can increase the execution speed of the CPU included therein.

The configuration of the present invention is as follows:
Storage means for storing at least a program and data, a sound source for accessing waveform data stored in the storage means, a CPU for accessing programs and data stored in the storage means, and a shared connection of the storage means A cross compiler that generates an object program intended to operate in a target system environment including a bus and a bus controller that controls the sound source and the CPU to alternately access the shared bus in a time-division manner,
First detection means for detecting an instruction for the CPU to use a shared bus;
Second detection means for detecting whether or not the timing at which the instruction detected by the first detection means is executed is a timing at which the CPU should use the shared bus;
When the second detection means detects that the instruction that the CPU uses the shared bus detected by the first detection means is executed at a timing when the sound source should use the shared bus, Determining means for determining whether or not the CPU can be replaced with an instruction next to an instruction executed by the CPU using a shared bus before the instruction;
Based on the determination result, if the instruction can be exchanged for the next instruction, the instruction is exchanged for the instruction. On the other hand, if the instruction cannot be exchanged for the next instruction, the instruction to pause the shared bus until the next use of the CPU is issued. An operation means for inserting,
The basic feature is that the CPU generates an object program that operates to access other than the shared bus at the timing when the sound source uses the shared bus.

  According to the above configuration, the second detection unit detects that the instruction for the CPU to use the shared bus detected by the first detection unit is executed at a timing at which the sound source should use the shared bus. When it is detected, it is determined by the determination means whether or not the CPU can be replaced with an instruction next to the instruction executed by the CPU using the shared bus before the instruction. In the determination result, If the instruction can be exchanged for the next instruction, the instruction is exchanged for the instruction by the operation means, and conversely, if the instruction cannot be exchanged for the next instruction, the operation means pauses the shared bus until the next use of the CPU. (The object program generated by the compiler has a cycle in which the shared bus access instruction of the CPU and the sound source timing collide with each other.) If the instruction that does not use the bus is executed, the instruction is issued to suspend the use of the CPU bus until the next use timing). While the sound source uses the bus, the CPU can execute the instruction as it is without waiting, and as a result, the execution speed of the CPU can be increased.

  According to the configuration of the present invention as described above, the object program generated by the compiler is replaced with the next instruction that can be exchanged by detecting a cycle in which the shared bus access instruction of the CPU and the sound source timing collide, or Since the instruction to pause the use of the CPU bus is output until the use timing of the CPU, if the instruction that the CPU does not use the bus is executed, the CPU does not wait while the sound source uses the bus. The instruction can be executed as it is, and as a result, an excellent effect can be obtained that the execution speed of the CPU can be increased.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

  The cross compiler of this embodiment is a cross compiler that generates an object program developed in a program development environment as shown in FIG. 1 for the purpose of operating in another target system environment called an electronic keyboard instrument.

  First, FIG. 1 shows a functional block diagram of a workstation of another system for creating the compiler of the present invention.

  The workstation is connected to a CPU block 1004, a direct memory access controller 1006, an interface 1008 for connecting to an external device, a memory block 1010, a disk I / O unit 1012, and a hard disk drive 1014 via a system bus 1000. Also connected to the I / O bus 1002 via the interface 1008. The I / O bus 1002 is further connected to a typing keyboard, a mouse, and an external device in addition to the GPU 1016. The GPU 1016 controls the screen of the video monitor 1018 that hits the external display.

  Here, a development environment for an object program generated by the present cross compiler, in which a configuration constructed by each functional unit described later is generated on the CPU 10 of a target system configured by an electronic keyboard instrument to be described later. Will be provided.

  FIG. 2 is a flowchart showing the processing flow of the compiler. First, preprocessing is performed for all source codes (step S100). Pre-processing is processing that is performed prior to actual compilation. For example, a macro is expanded into a normal instruction.

  Then, label extraction processing for all jump instructions (branch) and subroutine call instructions is performed (step S102).

  These instructions are encoded (step S104), the instruction counter i is set to 0 (step S106), and thereafter, the process is executed one instruction at a time until step S122.

  That is, the i-th instruction (in order from 0 to the total number of instructions −1) to be processed by the CPU 40 is acquired (step S108), and the first detection unit 1 in FIG. It is checked whether or not bus 40 access is requested (step S110). When the instruction does not make an external bus 40 access request (step S110; N), the process proceeds to step S120 described later.

  On the contrary, when the first detection unit 1 detects that the instruction makes an external bus 40 access request (step S110; Y), the address is a multiple of 8 [8n (n = 0, 1,... ]] Is checked by the second detection unit 2 which will be described later (step S112). This is because the CPU 10 executes one instruction at one clock as a whole, but an instruction placed at a multiple of 8 is fetched by the CPU 10 at an even clock, and after three clocks (ie, an odd clock), if necessary, an external bus This is because the tone generator 20 accesses the external bus 40 to odd clocks. By these two checks, it is checked whether or not the CPU 10 has violated access.

  If the address is not a multiple of 8 (the instruction length is a fixed length of 4 bytes, that is, a multiple of 8 + 4) (step S112; N), the process proceeds to step S120 described later.

  On the other hand, when the address is a multiple of 8 (step S112; Y), the determination unit 3 which will be described later checks whether or not it can be exchanged with the next instruction (step S114).

  If it can be exchanged for the next command (step S114; Y), the command is exchanged by the operation unit 4 which will be described later (step S116). On the other hand, if it cannot be exchanged for the next instruction (step S114; N), a NOP instruction (pause instruction) is inserted at the timing by the operation unit 4 described later (step S118).

  After any step S116 or S118, the instruction counter i is incremented (step S120).

  It is checked whether or not the instruction counter i has reached the total number of codes (step S122). If not reached (step S122; N), the process returns to step S106, and the above processing is repeated over all source codes. .

  When the instruction counter i reaches the total number of codes (step S122; Y), label position correction is performed (step S124). In other words, in the label position correction, a process is performed in which all jump (branch) instructions and subroutine call instruction jump labels (addresses) are multiples of 8, and the addresses of the instructions at the jump source are multiples of 8 +4. It will be. If the address of the instruction at the jump source is a multiple of 8, a NOP is inserted so that it becomes a multiple of 8 + 4. As a result, the compiler can arrange all instructions so that there is no access violation without connecting to the target.

  This completes the compiler processing flow.

  FIG. 3 is a flowchart showing a procedure for developing an object program intended to operate on an electronic keyboard instrument as a target system environment by using a cross compiler while using the workstation.

  First, the editor provided in the workstation is activated, and the source code of the flow shown in FIG. 2 is created (step S200). Alternatively, in step S200, the existing source code may be corrected. Similarly, a compiler provided in the workstation is activated, and the generated source code is converted into a machine language target program by the compiler (step S202).

  Then, it is checked whether or not there is an error in the program (step S204). If there is an error (step S204; Y), the process returns to step S200, and the source code is corrected.

  On the other hand, if there is no error (step S204; N), from the external device terminal connected to the I / O bus 1002 of the workstation, the interface 1008 and the electronic keyboard instrument which is the target system shown in FIG. Similarly, the created target program is transferred through the interface 66 (step S206). Operation confirmation is performed with the electronic keyboard instrument (step S208), and it is checked whether there is any abnormality (step S210). If there is an abnormality (step S210; N), the process returns to step S200 and the above processing is repeated. On the other hand, if there is no abnormality (step S210; Y), the interfaces 1008 and 66 are disconnected, the workstation is disconnected from the electronic keyboard instrument of the target system, and the electronic keyboard instrument is completed.

  FIG. 4 is a schematic block diagram of the configuration of the electronic keyboard instrument of the target system. The electronic keyboard instrument includes a CPU 10 (data input / output is performed via this bus), a sound generator (ToneGenerator) 20, a bus controller 30 via a data internal bus 70 incorporated in one LSI. Further, the CPU 10 (instructions are input / output via this bus) and the memory controller 62 are connected via an instruction internal bus 60. The memory controller 62 is connected to a flash memory 64 that stores a program, and the flash memory 64 stores a target program via the interface 66 and the memory controller 62 as described above. The CPU 10 issues an instruction at the same time as the power is turned on, reads out the target program stored in the flash memory 64 via the instruction internal bus 60 and the memory controller 62, and thereafter processes the CPU 10 according to the target program. Will be made.

  The CPU 10 is a RISC CPU that has, for example, a 24-bit address space and a 32-bit data bus width, and performs five-stage pipeline processing, as will be described later. The memory controller 62 connects the flash memory 64 to the workstation while transferring the target program from the electronic keyboard instrument as the target system, and connects the flash memory 64 to the CPU 10 after the transfer is completed.

  On the other hand, the CPU 10 and the sound source 20 are connected to an external bus 40 outside the LSI via a bus controller 30 and are connected to the bus and store data ROM (here, timbre data). CPU 10 stores programs and data between a memory 50 storing waveform data and a RAM 50 (in which calculation results of the CPU 10 are written) 50 and a memory 52 storing waveform data. The sound source 20 is configured to access the waveform data alternately in a time division manner. Therefore, the external bus 40 is a shared bus between the CPU 10 and the sound source 20.

  The sound source 20 from which the waveform data has been read out generates a musical sound waveform there, and the DSP 22 connected to the data internal bus 70 is added with an acoustic effect mainly centered on the delay, and the sound described later outside the LSI. Output to the system. The DSP 22 adds various acoustic effects to the musical sound waveform from the sound source 20 based on the instruction from the CPU 10 and the output of the coefficients. When the delay effect is added, the DSP 22 is connected via the DSP bus 22b outside the LSI. The sound effect is added to the musical sound waveform while using the delay memory 22a.

  The musical sound waveform output from the DSP 22 is converted into an analog signal by a digital / analog converter (DAC) 24, amplified by an amplifier 26, and emitted to the outside through a speaker 28.

  Furthermore, performance information such as MIDI is taken into the LSI data internal bus 70 from the outside via the interface 72.

  As described above, in the electronic keyboard instrument as the target system, the ROM / RAM 50 and the waveform data memory 52 as storage means for storing various data (including calculation results), and the waveform data stored in the waveform data memory 52 are stored. The sound source 20 to be accessed, the CPU 10 that accesses data stored in the ROM / RAM 50, the external bus 40 that is a shared bus to which the storage means is connected, and the sound source 20 and the CPU 10 are time-shared with respect to the external bus 40. And a bus controller 30 that performs control to alternately access.

  FIG. 5 is a functional block diagram of a configuration that is formed on the CPU 10 when the target program read from the flash memory 64 is executed by the CPU 10.

  As shown in the drawing, an object program generated by converting a source program by a cross compiler used in the workstation for the purpose of operating with an electronic keyboard instrument as a target system environment is a CPU 10. The first detection unit 1 (which can be detected by the instruction code) that detects all the instructions and uses the external bus 40 among them is input to the CPU 10. The timing at which the instruction detected by the 1 detector 1 is executed is the timing at which the CPU 10 should use the external bus 40 (the bus access timing of the CPU 10 is an odd clock as in step S112 described above). CPU detected by the second detector 2 and the first detector 1 The second detection unit is configured such that an instruction for 0 to use the external bus 40 is executed at a timing at which the sound source 20 should use the external bus 40 (the sound source 20 accesses the external bus 40 when the clock is an odd number). 2, a determination unit 3 that determines whether or not the CPU 10 can be replaced with an instruction next to an instruction executed by the CPU 10 using the external bus 40 before the instruction, and a result of the determination. If the instruction can be exchanged for the next instruction, the instruction is exchanged for the next instruction. On the other hand, if the instruction cannot be exchanged for the next instruction, the instruction to pause the external bus 40 until the next use of the CPU 10 is inserted. The operation unit 4 is constructed on the CPU 10 of the electronic keyboard instrument.

  As described above, the CPU 10 and the sound source 20 are connected to the external bus 40 outside the LSI via the bus controller 30, and the ROM and RAM 50 that are connected to the bus and store data. And the memory 52 storing the waveform data, the CPU 10 accesses the data and the like, and the sound source 20 alternately accesses the waveform data in a time division manner (as described above, the CPU 10 originally has an odd address timing). In this case, the external bus 40 is accessed and the sound source 20 accesses the external bus 40 at even address timing). Therefore, the external bus 40 is a shared bus between the CPU 10 and the sound source 20. ing.

  As described above, the timing at which the sound source 20 should use the external bus 40 is an odd-numbered clock. As shown in steps S110 to S118 of the flowchart of FIG. 1, when the CPU 10 detects an instruction using the external bus 40, the second detection unit 2 detects whether the bus access timing is an odd clock, that is, whether the instruction address is a multiple of 8. . When the bus access timing is an odd clock, the determination unit 3 determines whether or not the CPU 10 can be replaced with an instruction next to an instruction executed without using the external bus 40. If the next instruction can be exchanged without using the external bus 40, the operation unit 4 exchanges the next instruction with the next instruction, and the CPU 10 executes the instruction. On the other hand, if it is not possible to exchange the next instruction, the operation unit 4 inserts a NOP instruction that pauses until the CPU 10 uses the external bus 40 next time.

  FIG. 6 is a functional block diagram showing an internal configuration of the CPU 10 of the electronic keyboard instrument. The CPU 10 is a RISC type CPU that performs pipeline processing as described above, and has an internal configuration as shown in FIG. That is, the CPU 10 has a clock generation unit 190, which receives an operation clock (MCK) used on the LSI, generates an inversion operation clock (XMCK), and outputs the inversion operation clock (XMCK). The operation clock (MCK) is used inside the CPU 10.

  In the figure, PR is a pipeline register, p1 to p4 are the number of corresponding pipeline stages, and the processing result of each stage is stored. The final stage (fifth stage) of the pipeline does not have a pipeline register because the processing is completed and it is not necessary to store the processing result. Each internal part forms each stage of the pipeline. Each reads data from the preceding pipeline register, performs the operation of each unit as will be described later during one cycle of the operation clock (MCK), and stores the data in the corresponding pipeline register PR.

  More specifically, in the CPU 10, there is an instruction fetch unit 100 connected to an instruction internal bus 60 for inputting a target program, and instruction fetch (InstructionFetch) of the program is performed. Then, the fetched instruction (Instruction) is temporarily stored in the pipeline register (PRp1) 110 of the pipeline 1. At the next stage, the instruction (Instruction) is transferred to the instruction decoding unit 120, and the instruction decoding unit 120 refers to a register file 192 (see FIG. 7 described later) to decode the instruction (Instruction). The The decoding result is temporarily stored in the pipeline register (PRp2) 130 of the pipeline 2. Further, in the next stage, the decoding result is transferred to the operation unit 140 where the operation is performed, and the operation result is temporarily stored in the pipeline register (PRp3) 150 of the pipeline 3.

  Then, the memory access unit 160 connected to the data internal bus 70 connected to the bus controller 30 is accessed to the data ROM / RAM 50 connected to the external bus 40 via the bus controller 30 in the next stage. The necessary data is loaded from there, or the calculation result is output (written). The calculation result is temporarily stored in the pipeline register (PRp3) 170 of the pipeline 3.

  Further, in the next stage, the write-back unit 180 writes reference data necessary for a register file 192 (refer to register groups r0 to rf in FIG. 7 described later).

  The above instruction fetch, instruction decode, operation, memory access, and write back units operate in parallel.

  FIG. 7 shows a register configuration of the register file 192 of the CPU 10. This is a general-purpose register having a 32-bit length from r0 to re. Only the register rf is a status register, 8 bits is a stack pointer of the data RAM in the ROM / RAM 50 for storing data.

  FIG. 8 is a schematic diagram of the configuration of the instruction fetch unit 100 (and the pipeline register PR110 of the first stage pipeline) of the CPU 10 internal configuration. In the figure, an instruction fetch unit 100 has an instruction pointer IP and an adder 104.

  The value of the instruction pointer IP102, which is a 24-bit wide register, is output to the instruction internal bus 60 as an address.

  At the same time, the value of the instruction pointer IP102 is added to the fixed value 4 by the adder 104, and stored as the next instruction address predicted value NIEX in the area NA of the first-stage pipeline register PR110. Since the instruction address is always a multiple of 4, the instruction pointer IP102 may be 22 bits wide by omitting the least significant 2 bits.

  The current instruction code RICD is read from the data bus of the instruction internal bus 60 and stored in the area IC of the first-stage pipeline register PR110.

  The next instruction address NIAD given from the memory access unit 160 of FIG. 11 described later is overwritten on the instruction pointer IP102 at the end of one cycle of the operation clock MCK.

  The instruction fetch unit 100 repeats the above processing for each operation clock MCK.

  FIG. 9 is a schematic diagram of the configuration of the instruction decode unit 120 (and the pipeline registers PR110 and 130 of the first and second pipelines before and after). In the figure, the instruction decode unit 120 has an instruction separator ID 121, an operand separator OD122, a temporary storage register X1 (123), a temporary storage register X2 (124), and a selector S1 (125). ing.

  The next instruction address predicted value NIEX in the area NA of the first-stage pipeline register PR110 is stored as it is in the area NA of the second-stage pipeline register PR130 as the next instruction address predicted value NIEX.

  The current instruction code RICD is read from the area IC of the pipeline register PR110 at the first stage and separated into the instruction type ITYP and the operand data OP by the instruction separator ID 121 of the instruction decoding unit 120, and the instruction type ITYP is set to 2 It is stored in the area IT of the pipeline register 130 at the stage. Hereinafter, the operation will be described separately for a branch instruction, a transfer instruction, an arithmetic instruction, and a NOP instruction.

(For branch instructions)
Operand data OP is input to the operand separator OD122, the first operand pointer or immediate value O1 is retrieved by referring to the instruction type ITYP, stored in the area O1 of the second-stage pipeline register PR130, and the second operand pointer A fixed value 15 is set as OPT2 and stored in the area O2 of the second-stage pipeline register PR130.

  The first operand pointer or immediate value O1 sends the lower 4 bits to the register file 192, obtains the register value V1 corresponding thereto, and the timing of the end of the first half cycle of the operation clock MCK (up edge of the operation clock MCK). Then, it is stored in the temporary storage register X1 (123).

  At the same time, the second operand pointer OPT2 is sent to the register file 192, the register value V2 corresponding to this is obtained, and the temporary storage register is obtained at the end of the first half of the operation clock MCK (up edge of the operation clock MCK). Store in X2 (124).

  The selector S1 (125) refers to the IM bit (bit 30 in the branch instruction) of the instruction type ITYP. If this is 1, the first operand value or immediate value (immediate value in this case) 24 bits, otherwise V1 Is stored as the first operand value OPV1 in the area V1 of the second-stage pipeline register PR130.

  At the same time, V2 is stored in the area V2 of the second-stage pipeline register PR130 as the second operand value OPV2.

(For transfer instructions)
The operand data OP is input to the operand separator OD122, the instruction type ITYP is referred to, the first operand pointer or immediate value O1 is taken out, stored in the area O1 of the second-stage pipeline register PR130, and the second operand pointer OPT2 is taken out and stored in the area O2 of the second-stage pipeline register PR130.

  The first operand pointer or immediate value O1 sends the lower 4 bits to the register file 192, obtains the register value V1 corresponding thereto, and the timing of the end of the first half cycle of the operation clock MCK (up edge of the operation clock MCK). Then, it is stored in the temporary storage register X1 (123).

  At the same time, the second operand pointer OPT2 is sent to the register file 192, the register value V2 corresponding to this is obtained, and the temporary storage register is obtained at the end of the first half of the operation clock MCK (up edge of the operation clock MCK). Store in X2 (124).

  The selector S1 (125) refers to the TRMD signal (bits 28 to 29) of the instruction type ITYP. If this is not 0, the first operand value or immediate value (immediate value in this case) 24 bits, and if 0, V1 is set. The first operand value OPV1 is stored in the area V1 of the second-stage pipeline register PR130.

  At the same time, V2 is stored in the area V2 of the second-stage pipeline register PR130 as the second operand value OPV2.

(In the case of operation instructions)
The operand data OP is input to the operand separator OD122, the instruction type ITYP is referred to, the first operand pointer O1 is fetched, stored in the area O1 of the second-stage pipeline register PR130, and the second operand pointer OPT2 is stored. The data is taken out and stored in the area O2 of the second-stage pipeline register PR130.

  The first operand pointer O1 is sent to the register file 192, the register value V1 corresponding to this is obtained, and the temporary storage register is obtained at the end of the first half of the operation clock MCK (up edge of the operation clock MCK). Store in X1 (123).

  At the same time, the second operand pointer OPT2 is sent to the register file 192, the register value V2 corresponding to this is obtained, and temporarily stored at the end of the first half cycle of the operation clock MCK (up edge of the operation clock MCK). Store in the register X2 (124).

  The selector S1 (125) always stores V1 as the first operand value OPV1 in the area V1 of the second-stage pipeline register PR130.

  At the same time, V2 is stored in the area V2 of the second-stage pipeline register PR130 as the second operand value OPV2.

(NOP instruction)
Works like a transfer instruction, but no value is used.

  The instruction decode unit 120 repeats the operation described above in detail for each cycle of the operation clock MCK.

  FIG. 10 is a schematic diagram of the configuration of the arithmetic unit 140 (and pipeline registers PR 130 and 150 in the second and third pipelines before and after). In the figure, the calculation unit 140 has a calculation unit CU141.

  The next instruction address predicted value NIEX in the area NA of the second-stage pipeline register PR130 is stored as it is in the area NA of the third-stage pipeline register PR150 as the next instruction address predicted value NIEX.

  The instruction type ITYP in the area IT of the second-stage pipeline register PR130 is stored as it is as the instruction type ITYP in the area IT of the third-stage pipeline register PR150.

  The first operand pointer OPT1 in the area O1 of the second-stage pipeline register PR130 is stored as it is in the area O1 of the third-stage pipeline register PR150 as the first operand pointer OPT1.

  The second operand pointer OPT2 in the area O2 of the second-stage pipeline register PR130 is stored as it is as the second operand pointer OPT2 in the area O2 of the third-stage pipeline register PR150.

  The second operand value OPV2 in the area V2 of the second-stage pipeline register PR130 is stored as it is in the area V2 of the third-stage pipeline register PR150 as the second operand value OPV2.

  The first operand value OPV1 and the second operand value OPV2 in the areas V1 and V2 of the second-stage pipeline register PR130 are input to the arithmetic unit CU141.

  Hereinafter, the operation will be described separately for a branch instruction (a jump instruction and a call / return instruction), a transfer instruction, and an arithmetic instruction and a NOP instruction.

(Branch instruction: Jump instruction)
The first operand value OPV1 is output as it is as the operation result CR.

  The upper 4 bits of the second operand value OPV2 are output as they are as the operation status ST.

  The calculation result CR is stored as the calculation result CRSL in the area CR of the third-stage pipeline register PR150, and the calculation status ST is stored as the calculation status CRST in the area ST of the third-stage pipeline register PR150.

(For branch instructions: call / return instructions)
-4 (call) or +4 (return) is calculated on the lower 24 bits of the second operand value OPV2, and the lower 24 bits of the operation result are output as the operation result CR.

  The upper 4 bits of the second operand value OPV2 are output as they are as the operation status ST.

  The calculation result CR is stored as the calculation result CRSL in the area CR of the third-stage pipeline register PR150, and the calculation status ST is stored as the calculation status CRST in the area ST of the third-stage pipeline register PR150.

(For transfer instructions)
The first operand value OPV1 is output as it is as the operation result CR.

  The calculation status ST output may be indefinite.

  The calculation result CR is stored as the calculation result CRSL in the area CR of the third-stage pipeline register PR150, and the calculation status ST is stored as the calculation status CRST in the area ST of the third-stage pipeline register PR150.

(In the case of operation instructions)
The first operand value OPV1 and the second operand value OPV2 are calculated according to the instruction type ITYP, and the calculation result is output as CR.

  The calculation status ST changed according to the calculation is output.

  The calculation result CR is stored as the calculation result CRSL in the area CR of the third-stage pipeline register PR150, and the calculation status ST is stored as the calculation status CRST in the area ST of the third-stage pipeline register PR150.

(NOP instruction)
Works like the transfer instruction above, but the value is not used after all.

  The calculation result CR is stored as the calculation result CRSL in the area CR of the third-stage pipeline register PR150, and the calculation status ST is stored as the calculation status CRST in the area ST of the third-stage pipeline register PR150.

  The arithmetic unit 140 repeats the operation described above in detail for each cycle of the operation clock MCK.

  FIG. 11 is a schematic diagram of a configuration of the memory access unit 160 (and pipeline registers PR150 and 170 of the third and fourth pipelines before and after). In the figure, the memory access unit 160 includes an address gate AG161, a condition discriminator DM162, a selector S2 (163), a selector S3 (164), and a bus transceiver TR165.

  The instruction type ITYP in the area IT of the third-stage pipeline register PR150 is stored as it is in the area IT of the fourth-stage pipeline register PR170 as the instruction type ITYP.

  The first operand pointer OPT1 in the area O1 of the third-stage pipeline register PR150 is stored as it is in the area O1 of the fourth-stage pipeline register PR170 as the first operand pointer OPT1.

  The second operand pointer OPT2 in the area O2 of the third-stage pipeline register PR150 is stored as it is as the second operand pointer OPT2 in the area O2 of the fourth-stage pipeline register PR170.

  The following operations are divided into branch instructions (jump instructions and call / return instructions), transfer instructions (other than register-to-register transfers and register-to-register transfers), arithmetic instructions and NOP instructions. Explain.

(Branch instruction: Jump instruction)
The address gate AG161 is closed by the instruction type ITYP and is not connected to the data internal bus 70.

  The condition identifier DM162 refers to the instruction type ITYP and the operation status CRST, and when branching (when unconditional jump or when a condition is satisfied by conditional jump), 1 is set, and when not branching, 0 is set. The selector S2 (163) outputs the calculation result CRSL to the selector S3 (164) when the condition discriminator DM162 outputs 1, and the next instruction address predicted value NIEX to the selector S3 (164). Is a jump instruction, the selector S2 (163) output is selected and output to the instruction fetch unit 100 of FIG. 8 as the next instruction address NIAD.

  The calculation result CRSL in the area CR of the third-stage pipeline register PR150 is stored as the calculation result CRSL in the area CR of the fourth-stage pipeline register PR170.

  The operation status CRST in the area ST of the third-stage pipeline register PR150 is stored as it is in the area ST of the fourth-stage pipeline register PR170 as the operation status CRST.

  By the instruction type ITYP, the bus transceiver TR165 is closed and not connected to the data internal bus 70.

(For branch instructions: call / return instructions)
The address gate AG161 is opened according to the instruction type ITYP, and the second operand value OPV2 is output to the data internal bus 70.

  Depending on the instruction type ITYP, the selector S3 (164) selects the output of the transceiver TR165 and outputs it to the instruction fetch unit 100 of FIG. 8 as the next instruction address NIAD. The calculation result CRSL in the area CR of the third-stage pipeline register PR150 is stored as the calculation result CRSL in the area CR of the fourth-stage pipeline register PR170.

  The operation status CRST in the area ST of the third-stage pipeline register PR150 is stored as it is in the area ST of the fourth-stage pipeline register PR170 as the operation status CRST.

  In response to the instruction type ITYP, the bus transceiver TR165 is opened by reading and output to the selector S3 (164), and is stored as load data LDAT in the area LD of the pipeline register PR170 at the fourth stage.

(For transfer instructions other than register-to-register transfers)
The address gate AG161 is opened according to the instruction type ITYP, and the operation result CRSL is output to the data internal bus 70.

  The instruction type ITYP and the condition discriminator DM162 cause the selectors S2 (163) / S2 (164) to select the next instruction address predicted value NIEX and output it to the instruction fetch unit 100 in FIG. 8 as the next instruction address NIAD.

  The calculation result CRSL in the area CR of the third-stage pipeline register PR150 is stored as the calculation result CRSL in the area CR of the fourth-stage pipeline register PR170.

  The operation status CRST in the area ST of the third-stage pipeline register PR150 is stored as it is in the area ST of the fourth-stage pipeline register PR170 as the operation status CRST.

  In the case of a load data (ld) instruction, the bus transceiver TR165 is read by the instruction type ITYP, and stored as load data LDAT in the area LD of the pipeline register PR170 at the fourth stage. In the case of the load status (st) instruction, the bus transceiver TR165 is opened by writing according to the instruction type ITYP, and the second operand value OPV2 is output.

(Transfer instruction: Transfer between registers)
The address gate AG161 is closed by the instruction type ITYP and is not connected to the data internal bus 70.

  The instruction type ITYP and the condition discriminator DM162 cause the selectors S2 (163) / S3 (164) to select the next instruction address predicted value NIEX and output it to the instruction fetch unit 100 in FIG. 8 as the next instruction address NIAD.

  The calculation result CRSL in the area CR of the third-stage pipeline register PR150 is stored as the calculation result CRSL in the area CR of the fourth-stage pipeline register PR170.

  The operation status CRST in the area ST of the third-stage pipeline register PR150 is stored as it is in the area ST of the fourth-stage pipeline register PR170 as the operation status CRST.

  By the instruction type ITYP, the bus transceiver TR165 is closed and not connected to the data internal bus 70.

(Calculation instruction)
The address gate AG161 is closed by the instruction type ITYP and is not connected to the data internal bus 70.

  Depending on the instruction type ITYP, the selector TR3 (164) selects the output of the transceiver TR165 and outputs it to the instruction fetch unit 100 in FIG. 8 as the next instruction address NIAD.

  The calculation result CRSL in the area CR of the third-stage pipeline register PR150 is stored as the calculation result CRSL in the area CR of the fourth-stage pipeline register PR170.

  The operation status CRST in the area ST of the third-stage pipeline register PR150 is stored as it is in the area ST of the fourth-stage pipeline register PR170 as the operation status CRST.

  By the instruction type ITYP, the bus transceiver TR165 is closed and not connected to the data internal bus 70.

(NOP instruction)
Operates in the same way as the above arithmetic instruction, but the value is not used after all.

  The memory access unit 160 repeats the operation described above in detail for each cycle of the operation clock MCK.

  FIG. 12 is a schematic diagram of the configuration of the write-back unit 180 (and the pipeline register PR170 of the previous fourth-stage pipeline). In the figure, the write back unit 180 has a selector S4 (181) and a selector S5 (182).

  Here, since the access to the register file 192 is performed in the second half cycle of the operation clock MCK, it does not collide with the access of the instruction decoding unit 100.

  Hereinafter, in the case of branch instructions (in the case of jump instructions and call / return instructions), in the case of transfer instructions [in cases other than register-to-register transfer with load data (ld) instruction and between registers with load data (ld) instruction And the case of a transfer instruction of a load status (st) instruction], the operation of the write back unit 180 will be described separately for an arithmetic instruction and a NOP instruction.

(Branch instruction: Jump instruction)
The selector S4181 does not send any signal of the first operand pointer OPT1 / second operand pointer OPT2 to the register file 192, and does not select any register of the register file 192.

  The selector S5182 may select either the operation result CRSL or the load data LDAT as the registration data, but nothing is written because no pointer signal is transmitted.

  The status (the upper 4 bits of the register rf in FIG. 7) is not rewritten.

In the case of a branch instruction (call / return instruction) The selector S4 (181) sends a first operand pointer OPT1 (register rf = pointing to the stack pointer) as a pointer signal to the register file 192.

  The selector S5 (182) selects the calculation result CRSL as the registration data and sends it to the register file 192 as write data.

  The status (the upper 4 bits of the register rf in FIG. 7) is not rewritten.

In the case of a transfer instruction [other than register-to-register transfer by load data (ld) instruction] The selector S4 (181) sends the second operand pointer OPT2 as a pointer signal to the register file 192.

  The selector S5 (182) selects the load data LDAT as the registration data and sends it to the register file 192 as write data.

  The status (the upper 4 bits of the register rf in FIG. 7) is not rewritten.

In the case of a transfer instruction [transfer between registers by load data (ld) instruction] The selector S4 (181) sends the second operand pointer OPT2 to the register file 192 as a pointer signal.

  The selector S5 (182) selects the calculation result CRSL as the registration data and sends it to the register file 192 as write data.

  The status (the upper 4 bits of the register rf in FIG. 7) is not rewritten.

In the case of a transfer instruction [load status (st) instruction] The selector S4 (181) does not send any signal of the first operand pointer OPT1 / second operand pointer OPT2 to the register file 192, and selects any register of the register file 192. do not do.

  The selector S5 (182) may select either the operation result CRSL or the load data LDAT as the registration data, but nothing is written because no pointer signal is transmitted.

  The status (the upper 4 bits of the register rf in FIG. 7) is not rewritten.

(In the case of operation instructions)
The selector S4 (181) sends the second operand pointer OPT2 as a pointer signal to the register file 192.

  The selector S5 (182) selects the calculation result CRSL as the registration data and sends it to the register file 192 as write data.

  Of the statuses (the upper 4 bits of the register rf in FIG. 7), the bits that have been changed by the operation are rewritten according to the operation status CRST.

(NOP instruction)
The selector S4 (181) does not send any signal of the first operand pointer OPT1 / second operand pointer OPT2 to the register file 192, and does not select any register of the register file 192.

  The selector S5 (182) may select either the operation result CRSL or the load data LDAT as the registration data, but nothing is written because no pointer signal is transmitted.

  The status (the upper 4 bits of the register rf in FIG. 7) is not rewritten.

  The write back unit 180 repeats the operation described above in detail for each cycle of the operation clock MCK.

  FIG. 13 is a flowchart showing a main flow when the processing flow of the target program is executed by the CPU 10 in the electronic keyboard instrument as the target system.

  First, initialization of the entire electronic keyboard instrument is executed (step S300). Then, it is checked whether there is any event as an electronic keyboard instrument (for example, a key pressing event, a panel event, a MIDI event, etc.) (step S302).

  If there is no such event (step S302; N), the process proceeds to step S306 described later. Conversely, if there is an event (step S302; Y), the event processing shown in FIG. 14 is performed (step S304).

  Thereafter, non-event processing shown in FIG. 15 is performed (step S306).

  FIG. 14 is a flowchart showing the process flow of the event process in step S304 in FIG.

  First, it is checked whether or not there is a key pressing event (step S400). If there is a key pressing event (step S400; Y), a key pressing process is executed (step S402).

  If there is no key pressing event (step S400; N), it is checked whether there is a panel event (step S404). If there is a panel event (step S404; Y), panel processing is executed (step S406). .

  If there is no panel event (step S404; N), it is checked whether there is a MIDI event (step S408). If there is a MIDI event (step S408; Y), MIDI event processing is executed (step S410). .

  If there is no MIDI event (step S410; N), other event processing is performed (step S412). Then return to the main flow.

  FIG. 15 is a flowchart showing the process flow of the non-event process in step S306 in FIG.

  First, an elapsed time acquisition process is performed (step S500). This is because it is necessary to know the elapsed time in order to reset the T of the interval timer described later and advance the UpDate of the transmitter LFO described later.

  Next, envelope EV phase processing is performed (step S502). This is because it is necessary for the CPU 10 to notify the sound source 20 that the envelope phase has arrived and to proceed to the next phase.

  Further, the step of the transmitter LFO, that is, the LFO UpDate process is executed (step S504). That is, processing for updating the value of the LFO module is performed.

  Thus, automatic performance processing is performed (step S506). After this processing, the process returns to step S302 in FIG.

  FIG. 16 is a flowchart showing a processing flow of interval timer interrupt processing. This is simply an increment of time T (step S600).

  FIG. 17 is a flowchart showing a processing flow of reception interrupt processing from a serial interface such as MIDI or USB.

  These serial reception RC interrupts are first stored in the buffer (step S700). Then, it is checked whether or not the command is completed (step S702). If the command is not completed (step S702; N), this processing flow ends.

  On the contrary, if the command is completed (step S702; Y), an event generation process is performed (step S704), and then the buffer clear process is performed (step S706).

  FIG. 18 is a timing chart showing operation timings of the CPU 10, the sound source 20, and the internal bus / external bus.

  The operation clock MCK is inverted to generate an inverted operation clock XMCK, and the operation clock MCK is divided by two to generate CK1. The CK1 represents the usage status of the external bus. That is, when the CK1 is true, the sound source 20 is in a state where the CPU 10 can access the external bus when the CK1 is false.

  A sound source clock CKTG is generated from the CK1 and the operation clock MCK. The sound source 20 operates from the down edge of the sound source clock CKTG.

  In addition, the I / E of the CPU 10 indicates that the CPU 10 can access either the internal bus or the external bus. Indicates access to the internal bus. On the other hand, (NC) of the sound source 20 indicates that it is not connected by NotConnect, and ACTV indicates that a musical sound waveform is output from the sound source 20.

  As shown in the figure, when CK1 is false, the CPU 10 accesses either the internal bus or the external bus, but when CK1 is true, it accesses only the internal bus. On the other hand, when CK1 is true and the sound source clock CKTG is down edge, the sound source 20 becomes active and remains active until CK1 changes to false. At the same time as CK1 becomes false, the sound source 20 stops reading the musical sound waveform.

  FIG. 19 is a timing chart showing various operation timings when the CPU 10 performs pipeline processing.

  In this timing chart, the operation timing is as follows during a system cycle (0 to 8 are shown in the figure). Note that the operation timings of the operation clocks MCK, CK1, CPU 10, and sound source 20 are the same as those in FIG.

  In the system cycle 0, the instruction IC-0 is fetched (IF) from the program flash memory 64 to the instruction fetch unit 100 in the first-stage pipeline.

  At the time of system cycle 1, the instruction decode unit 120 performs decode processing of the previously fetched instruction and register operand fetch (RF) in the second-stage pipeline. At the same time, in the first-stage pipeline, the instruction IC-1 is fetched (IF) from the program flash memory 64 to the instruction fetch unit 100.

  In the system cycle 2, in the third-stage pipeline, the instruction execution (EX) is performed by the arithmetic unit 140, and in the second-stage pipeline, the instruction fetch unit 120 Decoding processing and register operand fetch (RF) are performed. At the same time, in the first stage pipeline, the instruction IC-2 is fetched (IF) from the program flash memory 64 to the instruction fetch unit 100.

  In system cycle 3, in the fourth stage pipeline, the memory access unit 170 performs memory access (MA) to the data internal bus 70, and in the third stage pipeline, the arithmetic unit 140 Execution (EX) is performed. In the second-stage pipeline, the instruction decoding unit 120 performs a decoding process on the previously fetched instruction and a register operand fetch (RF). At the same time, in the first stage pipeline, the instruction IC-3 is fetched (IF) from the program flash memory 64 to the instruction fetch unit 100.

  In the system cycle 4, in the fifth-stage pipeline, the write-back processing (WB) to the register file 192 is performed by the write-back unit 180, and the processing of the instruction IC-0 is completed. In the fourth stage pipeline, the memory access unit 170 performs memory access (MA) to the data internal bus 70, and in the third stage pipeline, the operation unit 140 performs instruction execution (EX). Made. In the second-stage pipeline, the instruction decoding unit 120 performs a decoding process on the previously fetched instruction and a register operand fetch (RF). At the same time, in the first stage pipeline, the instruction IC-4 is fetched (IF) from the program flash memory 64 to the instruction fetch unit 100.

  In the system cycle 5, in the fifth-stage pipeline, the write-back processing (WB) to the register file 192 is performed by the write-back unit 180, and the processing of the instruction IC-1 is completed. In the fourth stage pipeline, the memory access unit 170 performs memory access (MA) to the data internal bus 70 or the external bus 40, and in the third stage pipeline, the arithmetic unit 140 executes instructions. (EX) is made. In the second-stage pipeline, the instruction decoding unit 120 performs a decoding process on the previously fetched instruction and a register operand fetch (RF). At the same time, in the first stage pipeline, the instruction IC-5 (not shown) is fetched (IF) from the program flash memory 64 to the instruction fetch unit 100. Thereafter, instructions are sequentially executed.

  The timing chart shown at the bottom of the figure shows whether or not the instruction of the CPU 10 uses the external bus 40, and the external bus 40 is not used until the system cycles 0 to 2. It is not in use and is in a high-impedance state. Thereafter, from the system cycle 3 onward, the instruction of the CPU 10 uses the external bus 40 and the data internal bus 70 alternately. However, it is allowed to use the data internal bus 70 at the timing of using the external bus 40. Therefore, the compiler does not exclude combinations of addresses and instructions that perform such operations.

  According to the configuration of the embodiment described in detail above, the object program generated by the cross compiler of the present invention detects the cycle in which the external bus 40 access instruction of the CPU 10 and the sound source timing collide with each other and can be replaced with the next instruction. Since the instruction for stopping the use of the external bus 40 of the CPU 10 is output until the next use timing, the sound source 20 is connected to the external bus 40 when the instruction that the CPU 10 does not use the external bus 40 is executed. While using the CPU 10, the CPU 10 can execute the instruction as it is without waiting, and as a result, the CPU 10 can increase the execution speed.

  That is, the second detection unit 2 detects that the instruction that the CPU 10 uses the external bus 40 detected by the first detection unit 1 is executed at a timing when the sound source 20 should use the external bus 40. In this case, before the instruction, the determination unit 3 determines whether or not the CPU 10 can be replaced with an instruction next to an instruction executed by the CPU 10 using the external bus 40. In the determination result, If it can be exchanged for the next instruction, it is exchanged for that instruction by the operation unit 4, and conversely, if it is not exchangeable for the next instruction, the operation unit 4 will use the external bus 40 next time by the CPU 10 Instruction that pauses until the object program is inserted (the object program generated by the compiler This is because a cycle in which the 10 external bus 40 access instructions and the sound source timing collide is detected and exchanged with the next exchangeable instruction, or an instruction to stop using the external bus 40 of the CPU 10 is output until the next use timing) When the instruction that the CPU 10 does not use the external bus 40 is executed, the CPU 10 can execute the instruction as it is without waiting while the sound source 20 uses the external bus 40. As a result, the CPU 10 The execution speed of can be increased.

  The compiler according to the present invention is not limited to the illustrated example described above, and it is needless to say that various changes can be made without departing from the gist of the present invention.

  It goes without saying that the cross compiler of the present invention can be widely applied to electronic musical instruments.

It is a functional block diagram of a workstation showing a program development environment in which a cross compiler for generating an object program is used for the purpose of operating in another target system environment called an electronic keyboard instrument. It is a flowchart which shows the processing flow of a cross compiler. It is a flowchart which shows the development work procedure of the object program aiming to operate | move with an electronic keyboard instrument. It is an outline block diagram of composition of an electronic keyboard instrument. FIG. 3 is a functional block diagram of a configuration that is formed on a CPU 10 when a target program is executed by the CPU 10. It is a functional block diagram which shows the internal structure of CPU10 of an electronic keyboard instrument. 3 is an explanatory diagram illustrating a register configuration of a register file 192 of a CPU 10. FIG. It is a schematic diagram of the structure of the instruction fetch part 100 of CPU10 internal structure. 3 is a schematic diagram of a configuration of an instruction decoding unit 120. FIG. 3 is a schematic diagram of a configuration of a calculation unit 140. FIG. 3 is a schematic diagram of a configuration of a memory access unit 160. FIG. 3 is a schematic diagram of a configuration of a write back unit 180. FIG. It is a flowchart which shows the main flow at the time of the process flow of this program being performed when the target program is performed by CPU10 in an electronic keyboard instrument. It is a flowchart which shows the processing flow of the event process of step S304 in FIG. It is a flowchart which shows the processing flow of the non-event process of step S306 in FIG. It is a flowchart which shows the processing flow of an interval timer interruption process. It is a flowchart which shows the processing flow of the reception interruption process from a serial interface. It is a timing chart which shows the operation timing of CPU10, the sound source 20, and an internal bus and an external bus. It is a timing chart which shows various operation timings when CPU10 performs a pipeline process.

DESCRIPTION OF SYMBOLS 1 1st detection part 2 2nd detection part 3 Judgment part 4 Operation part 10 CPU
20 sound source 22 DSP
22a DSP memory 22b DSP bus 24 DAC
26 Amplifier 28 Speaker 30 Bus controller 40 External bus 50 Data ROM / RAM
52 Waveform Data Memory 60 Instruction Internal Bus 62 Memory Controller 64 Flash Memory 66 Interface 70 Data Internal Bus 72 Interface 100 Instruction Fetch Unit 102 Instruction Pointer IP
104 Adder 110, 130, 150, 170 Pipeline register 120 Instruction decode unit 121 Instruction separator ID
122 Operand separator OD
123 Temporary storage register X1
124 Temporary storage register X2
125 selector S1
140 Arithmetic Unit 141 Arithmetic Unit CU
160 Memory Access Unit 161 Address Gate AG
162 Condition identifier DM
163 Selector S2
164 Selector S3
165 Bus transceiver TR
180 Write-back unit 181 Selector S4
182 Selector S5
190 Clock generation unit 192 Register file 1000 System bus 1002 I / O bus 1004 CPU block 1006 DMA
1008 Interface 1010 Memory block 1012 Disk I / O unit 1014 Hard disk drive 1016 GPU
1018 Video monitor

Claims (1)

Storage means for storing at least a program and data, a sound source for accessing waveform data stored in the storage means, a CPU for accessing programs and data stored in the storage means, and a shared connection of the storage means A cross compiler that generates an object program intended to operate in a target system environment including a bus and a bus controller that controls the sound source and the CPU to alternately access the shared bus in a time-division manner,
First detection means for detecting an instruction for the CPU to use a shared bus;
Second detection means for detecting whether or not the timing at which the instruction detected by the first detection means is executed is a timing at which the CPU should use the shared bus;
When the second detection means detects that the instruction that the CPU uses the shared bus detected by the first detection means is executed at a timing when the sound source should use the shared bus, Determining means for determining whether or not the CPU can be replaced with an instruction next to an instruction executed by the CPU using a shared bus before the instruction;
Based on the determination result, if the instruction can be exchanged for the next instruction, the instruction is exchanged for the instruction. On the other hand, if the instruction cannot be exchanged for the next instruction, the instruction to pause the shared bus until the next use of the CPU is issued. An operation means for inserting,
A cross compiler that generates an object program that operates so that the CPU accesses a bus other than the shared bus at a timing when the sound source uses the shared bus.

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