JP5454618B2 - Memory device, memory controller and memory system - Google Patents

Description

  The present invention relates to a memory device that records two-dimensional array data such as digital image data, a memory controller of the memory device, and a memory system, and more particularly, effectively reduces the bandwidth that means the number of data that can be processed per unit time. The present invention relates to a memory device, a memory controller, and a memory system.

  Memory devices that record two-dimensionally arranged data such as digital image data are becoming an increasingly large market with the spread of digital broadcasting and video distribution via the Internet. The digital image data is a data group in which pixel gradation information is composed of a plurality of bits (for example, 8 bits, 256 gradations). For example, image data for high-definition broadcasting is image data of 1920 × 1040 pixels per frame. Consists of. The image data in units of frames is arranged in the address space in the image memory according to a predetermined mapping method.

  This memory mapping is determined so that the most efficient access is possible based on the memory configuration and operation of a synchronous DRAM (SDRAM) that is currently popular. For example, an SDRAM has a plurality of banks, each bank has a plurality of word lines and bit lines, a plurality of memory cells at intersections thereof, and a sense amplifier corresponding to the bit lines, and the plurality of banks are independent. Thus, the active operation can be executed. The active operation in the SDRAM is a series of operations for selecting the word line based on the row address and activating the sense amplifier. The SDRAM read operation is a series of operations for outputting the bit line potential amplified by the sense amplifier based on the column address to the input / output terminal as read data. The write operation is input from the input / output terminal. This is a series of operations for inputting the selected write data to the bit line selected based on the column address.

  The address space in the memory in the SDRAM is composed of a plurality of page areas selectable by bank address and row address, and each page area has a bit group or byte group selectable by a column address. The byte group (or bit group) selected by this column address is input / output via a plurality of input / output terminals.

  According to a general mapping method, a pixel of digital image data is associated with each byte (or bit) of a byte group (or bit group) that can be selected by a column address in the page area. Furthermore, according to this mapping method, each bank of the SDRAM can independently execute an active operation and a read or write operation, so that a plurality of page regions associated with the pixel arrangement of the digital image data are The page areas adjacent to the top, bottom, left, and right on the image are arranged so as to correspond to different bank addresses. For example, when the SDRAM has a 4-bank configuration, page areas with bank addresses BA = 0 and 1 are alternately arranged in odd rows, and page areas with bank addresses BA = 2 and 3 are alternately arranged in even rows. . With this arrangement, when reading or writing one frame of image data, it is possible to execute active operation and read or write operation by alternately and temporally overlapping different banks, and unit time The bandwidth, which is the number of pixels that can be processed per hit, can be dramatically increased.

  Patent Documents 1 and 2 describe that in a semiconductor memory that stores image data, a plurality of rows can be accessed simultaneously to improve access efficiency.

  Further, in Patent Document 3, when a DRAM is used for image decompression processing, data must be read across pages, and in order to solve the problem that reading time becomes long and power consumption increases, input row address There is described a memory device provided with a sub-array selection circuit for controlling the sub-array allocated to 1 and the sub-array allocated to the next higher row address to be activated simultaneously. However, Patent Document 3 aims to increase the efficiency of horizontal access that continues in the row direction of an image, and does not describe rectangular access.

  Furthermore, in Patent Document 4, an address active command is issued in response to an access instruction from the data processing unit to a storage area different from the storage area being accessed by the bus control unit in burst mode, and an access address can be set in advance. A data processing system is described. That is, it is described that the memory controller activates one bank and accesses the other bank to issue an active command to perform an active operation in advance, thereby realizing a high-speed read / write operation. .

  In Patent Document 5, column addresses are continuously generated while accessing an image memory and an arbitrary bank so that an arbitrary address in the same page can be continuously accessed and accessed thereafter. There is disclosed an image processing apparatus including controller means for controlling a bank so that it can be accessed immediately even if the bank to be accessed is switched by making the row active in advance. That is, it is described that the memory controller has an address order prediction circuit, predicts a bank to be accessed next, and issues an active command to the memory.

  In Patent Document 6, a volatile memory is provided in a plurality of banks, a refresh target bank is specified by an auto-refresh command, and during a refresh operation in the refresh target bank, in response to a normal memory operation command except for the refresh target bank A memory system that performs normal memory operations is described. However, there is no description of performing refresh control by setting a plurality of refresh times in advance.

  Patent Document 7 describes a memory device in which a dual-port DRAM is divided into a plurality of banks, and a data read transfer cycle for one bank and a refresh cycle for other banks are performed simultaneously.

  In Patent Document 8, a memory controller performs a write or read by controlling access to an SDRAM having two banks, and issues an active command and a precharge command to a bank different from the bank being accessed to perform a refresh operation. It is described to do.

  In Patent Document 9, in a DRAM having two blocks, when an access and a refresh occur simultaneously, or when an access has already occurred in one block, the arbiter performs a refresh operation on the other block, It is described that the block performs an access operation.

JP 2001-312885 A Japanese Patent Laid-Open No. 08-180675 JP 09-231745 A JP 2002-132777 A JP-A-10-105367 US Patent Publication US2005 / 0265104A1 Japanese Patent Laid-Open No. 08-115594 Japanese Patent Laid-Open No. 09-129881 Japanese Patent Laid-Open No. 10-11348

  An image memory that stores digital image data requires horizontal access for writing and reading image data in the order of arrangement of matrix-like pixels and rectangular access for partial rectangular areas of matrix-like pixels. Become. The horizontal access corresponds to, for example, a raster scan operation in which one frame of image data is written or read by repeating horizontal scanning. In addition, the rectangular access is, for example, an operation of reading out image data of a small rectangular block in an encoding operation such as MPEG to obtain a motion vector, or of reading out image data of a block in image reproduction in a decoding operation. Corresponds to the operation to write.

  However, since the pixel image data is stored in the address space of the memory by the memory mapping described above, there is a problem of effective bandwidth reduction in rectangular access. First, in a page area selected by a bank address and a row address, a byte group, that is, a plurality of bytes (or a plurality of bits) are simultaneously accessed by a column address. However, if the rectangular image area to be accessed in the rectangular access and the plurality of bytes (or a plurality of bits) selected by the column address do not match, useless input / output data is generated in the access by one column address. Secondly, when the rectangular image area to be accessed in the rectangular access and the page area in the address space do not match, it is required to access a plurality of page areas across the boundary of the page area. Control is required.

  The first and second problems are that if the rectangular image area to be accessed does not match the page area and does not match the multiple bytes (or multiple bits) selected by the column address, the memory control is further performed. It becomes complex and causes a reduction in effective bandwidth.

  Effective bandwidth reduction occurs not only in rectangular access. In general synchronous DRAM (SDRAM), in response to an auto-refresh command issued by the memory controller, a refresh operation is performed in parallel in all banks based on the refresh address of a refresh address counter provided in the memory in common. I do. For this reason, once the refresh operation starts, neither horizontal access nor rectangular access can be executed, and it is necessary to wait for the access operation until the refresh operation is completed. As a result, the effective bandwidth is reduced.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a memory device, a memory controller of the memory device, and a memory system in which the effective bandwidth reduction caused by the refresh operation of the memory device is solved.

  In order to achieve the above object, according to a first aspect of the present invention, a plurality of banks each having a memory core including a memory cell array and selected by a bank address, a background refresh command, and refresh burst length information And a control circuit that causes the memory core in the refresh target bank to continuously execute the refresh operation corresponding to the refresh burst length information.

  To achieve the above object, according to a second aspect of the present invention, in a memory device that operates in response to a command from a memory controller, each memory core including a memory cell array is selected by a bank address. In response to a background refresh command, the memory cores in the refresh target bank set by the memory controller are continuously refreshed for the number of refresh burst lengths set by the memory controller. In response to a normal operation command while the memory core in the refresh target bank is executing the refresh operation, the memory core in the bank other than the refresh target bank and selected by the bank address is executed. In addition, the normal operation command Usually correspond to command and a control circuit for executing the memory operations.

  In the second aspect of the present invention, according to the first preferred embodiment, the memory device further includes a refresh target address in a bank corresponding to each of the plurality of banks or each of the plurality of sets of the plurality of banks. Has a refresh address counter. The control circuit includes a background refresh control unit that outputs a refresh control signal to the set refresh target bank in response to the background refresh command, and a refresh burst length register in which the refresh burst length is set. Provided in each of the plurality of banks and in response to the background refresh control signal, the memory core is refreshed for the address of the refresh address counter by the number of times of the refresh burst length set in the refresh burst length register. A core controller for executing the operation.

  In the second aspect of the present invention, according to the second preferred embodiment, a refresh block number indicating the number of memory blocks simultaneously activated in one refresh cycle is set by the memory controller, and the control circuit is In response to the background refresh command, a refresh operation for simultaneously activating the number of refresh blocks is executed in the refresh target bank for the set number of refresh burst lengths. The number of refresh blocks is preset in the mode register. Alternatively, the refresh block number is input and set together with the background refresh command.

  In the second aspect of the present invention, according to the third preferred embodiment, the refresh burst length and the number of refresh blocks are input simultaneously with the background refresh command. Alternatively, the refresh burst length and the number of refresh blocks are input simultaneously with the mode register setting command. In the former case, the refresh burst length register is provided corresponding to the bank, and the input refresh burst length is set in the refresh burst length register in the refresh target bank. Further, a refresh block number register is provided, and the inputted refresh block number is set in the refresh block number register. In the latter case, the refresh burst length register is provided in the mode register, and the input refresh burst length is set in the mode register. Similarly, a refresh block number register is provided in the mode register, and the input refresh block number is set in the mode register.

  In the second aspect of the present invention, in the third preferred embodiment, the core controller performs the refresh operation in response to a newly input background refresh command during the refresh operation for the number of times of the refresh burst length. The refresh operation is continuously performed by the memory core in the refresh target bank by the number obtained by adding the refresh burst length to the remaining number of times.

  Alternatively, the core controller responds to a newly input background refresh command during the refresh burst length refresh operation, regardless of the remaining refresh operation count, the refresh burst length count, The refresh operation is continuously executed by the memory cores in the refresh target bank.

  Further, in response to the refresh all command, the core controller causes the memory cores in the refresh target bank to repeatedly perform a refresh operation from the address in the refresh address counter to the remaining addresses.

  In the second aspect of the present invention, according to the fourth preferred embodiment, the core controller responds to a background refresh stop command in the refresh target bank during the refresh operation of the number of refresh burst lengths. The refresh operation is stopped in the memory core. This stop control of the refresh operation is performed so that the memory core in the refresh target bank does not start the next refresh operation after the refresh operation being executed is terminated.

  In the second aspect of the present invention, according to the fifth preferred embodiment, the background refresh control unit is input in response to a normal memory operation command based on the setting of the active refresh interlock flag in the mode register. The background refresh control signal is supplied to banks other than the access target bank corresponding to the bank address to be accessed. Thus, the memory controller can execute a refresh operation in a bank other than the bank to be accessed by issuing a normal memory operation command without issuing a background refresh command.

  In order to achieve the above object, according to a third aspect of the present invention, a memory device includes a memory cell array and a memory core including a decoder, each having a plurality of banks selected by bank addresses, and a memory logic Based on memory mapping in which a space has a plurality of page areas selected by the bank address and row address, the plurality of page areas are arranged in a matrix, and adjacent page areas are associated with different bank addresses, The plurality of banks store two-dimensional array data. Then, the memory device responds to the normal operation command during the horizontal access period in which the two-dimensional array data is accessed in the horizontal direction, and sends the normal operation command to the memory core in the bank selected by the bank address. A control circuit for executing a corresponding normal memory operation and causing a memory core in a refresh target bank other than the horizontal access target bank to execute a refresh operation in response to a background refresh command. Further, the control circuit, in a rectangular access period for accessing the two-dimensional array data to an arbitrary rectangular area, responds to the normal operation command and the bank selected by the bank address and the selected bank The memory core in the bank adjacent to the memory core is caused to execute the normal memory operation, and the refresh operation is prohibited during the normal memory operation.

  According to the third aspect, the memory device repeats normal memory operation in a specific bank during a horizontal access period. Therefore, the memory device performs normal memory operation in the selected bank and refreshes other than the horizontal access target bank. A refresh operation is performed in the target bank. However, during the rectangular access period, the memory access target bank cannot be predicted, so the refresh operation performed together with the normal memory operation is prohibited. As a result, horizontal access can be continued even during the background refresh operation, and the effective bandwidth can be increased.

  To achieve the above object, according to a fourth aspect of the present invention, a memory system includes the memory device according to the first or second aspect and a memory controller that supplies a command to the memory device. .

  In order to achieve the above object, according to a fifth aspect of the present invention, a memory controller includes a command, a refresh bank information, a refresh burst length, and a refresh block number in the memory device of the first or second aspect. Supply.

  According to the present invention, since the memory core performs the refresh operation for the number of refresh times set in the refresh target bank, the normal memory operation is started for the refresh target bank in a short time after the background refresh operation is completed. It is possible to suppress the decrease in effective bandwidth.

  According to the present invention, while another memory bank is executing a normal memory operation, the memory core is caused to execute a refresh operation by a plurality of refresh times set in the set refresh target bank. The operation can be executed in parallel, and the reduction in effective bandwidth in the normal memory operation due to the refresh operation can be suppressed. Moreover, since the number of background refresh operations during normal memory operation is set in advance, normal memory operation can be started for the refresh target bank in a short time after the background refresh operation is completed. A decrease in bandwidth can be suppressed.

It is a figure which shows the memory mapping of the image memory in this Embodiment. It is a figure which shows two accesses in an image memory. It is a figure which shows the subject of a horizontal access. It is a figure which shows the 1st subject of a rectangular access. It is a figure which shows the 2nd subject of a rectangular access. It is a figure which shows the whole operation | movement of this Embodiment. It is a figure which shows another example of the whole operation | movement of this Embodiment. It is a block diagram of the image processing system in this Embodiment. It is a block diagram of the image memory in this Embodiment. It is a figure explaining a byte boundary function. It is a figure which shows the timing chart in a byte boundary function. It is a figure explaining the byte boundary function with respect to different mapping. It is a figure explaining the big endian and little endian of FIG. It is a figure explaining the byte boundary function in special memory mapping. It is a figure explaining the special memory mapping of FIG. It is a timing chart figure which shows the byte boundary function in rectangular access. It is a block diagram of the image processing system for implement | achieving a byte boundary function. It is a figure which shows a byte boundary function. 1 is a configuration diagram of an image processing system that realizes a simplified byte boundary function. FIG. It is a figure explaining the image processing system which implement | achieves the simplified byte boundary function of FIG. It is a figure which shows the concept of the memory structure which has a byte boundary function. It is a figure which shows the 1st example of the image memory which has a byte boundary function. It is a figure explaining the operation | movement of FIG. FIG. 24 is a diagram illustrating a second example of an image memory having a byte boundary function. It is a figure explaining the operation | movement of FIG. It is a figure which shows operation | movement of the modification (1) of the 2nd example of the image memory which has a byte boundary function. It is a figure which shows operation | movement of the modification (2) of the 2nd example of the image memory which has a byte boundary function. It is a figure which shows operation | movement of the modification (3) of the 2nd example of the image memory which has a byte boundary function. It is a figure which shows the 3rd example of the image memory which has a byte boundary function. It is a figure explaining the operation | movement of FIG. It is a figure which shows a corresponding means with the input-output terminal of the image memory which has a byte boundary function. It is a figure which shows the operation | movement of FIG. It is a figure which shows a corresponding means with the input-output terminal of the image memory which has a byte boundary function. It is a figure which shows the operation | movement of FIG. It is a block diagram (1) of the image memory which has a byte boundary function, and can respond to an endian. It is a block diagram (2) of the image memory which has a byte boundary function, and can respond to an endian. It is a block diagram (3) of the image memory which has a byte boundary function, and can respond to an endian. FIG. 38 is an operation timing chart of the up mode in the DDR memory of FIG. 37. FIG. 38 is an operation timing chart of the down mode in the DDR memory of FIG. 37. It is a figure explaining the specification method of the boundary in a byte boundary function. It is a figure which shows the conversion circuit of start byte SB and shift value SV. It is a figure explaining the automatic rectangular access using a byte boundary function. It is a timing chart figure in automatic rectangular access. It is a block diagram of an internal column address calculator required for automatic rectangular access. It is a figure which shows the example of a memory operation | movement when the access by a byte boundary function reaches the end of a page area. It is a figure which shows another example of the memory operation | movement when the access by a byte boundary function reaches the end of a page area. It is a figure which shows another example of the memory operation | movement when the access by a byte boundary function reaches the end of a page area. It is a figure explaining the other use of a byte boundary function. It is a figure explaining the other use of a byte boundary function. It is a figure explaining the other use of a byte boundary function. 1 is a configuration diagram of an image processing system. It is a figure which shows the input and output signal of a memory control part (memory controller). It is a figure explaining the reference image area | region of reading object in a frame image. It is a detailed block diagram of a memory control part. It is a figure explaining the calculation of the arithmetic process part 515 in the reference image read-out control part 514. FIG. It is a figure which shows the example of a calculation of the arithmetic process part 515 in the reference image read-out control part 514. It is a figure which shows the example of memory mapping. 3 is a diagram illustrating a configuration of a page area 14 in the memory mapping 12. FIG. FIG. 57 is a diagram showing an arrangement of a reference image area in FIG. 56 on a memory map. It is a figure which shows another example of arrangement | positioning on the memory map of a reference image area | region. It is a timing chart figure in a memory controller with respect to the memory which does not have a byte boundary function. It is a timing chart figure in a memory controller with respect to the memory which has a byte boundary function. FIG. 10 is a timing chart in a memory controller for a memory that does not have a byte boundary function and a multi-bank access function. FIG. 4 is a timing chart in a memory controller for a memory having a multi-bank access function and a byte boundary function. It is a flowchart figure of control operation of a memory controller. It is a flowchart figure of control operation of a memory controller. It is a schematic explanatory drawing about the multibank access in this Embodiment. It is a figure explaining the multibank access in this Embodiment. It is a timing chart figure in case multibank information SA 'is bank number information (= 4). FIG. 11 is a timing chart when the multi-bank information SA ′ is rectangular area size information (W = 8 bytes, H = 8 rows). It is a block diagram of a memory device having a multi-bank access function. 6 is a diagram illustrating a first example of a multi-bank activation control unit 88. FIG. 6 is a diagram illustrating a first example of a multi-bank activation control unit 88. FIG. 6 is a diagram illustrating a second example of a multi-bank activation control unit 88. FIG. 6 is a diagram illustrating a second example of a multi-bank activation control unit 88. FIG. FIG. 10 is a diagram illustrating a third example of the multi-bank activation control unit 88. FIG. 10 is a diagram illustrating a third example of the multi-bank activation control unit 88. It is a figure which shows the example 1 of a bank activation timing. It is a figure which shows the example 2 of a bank activation timing. It is a figure explaining the logic of the bank activation timing control of the activation bank control circuit 88C. It is a figure which shows the example 3 of a bank activation timing. It is a figure explaining row address generation in multi-bank access in this embodiment. It is a figure which shows Example 1 of the row address calculating part in this Embodiment. It is a figure which shows Example 2 of the row address calculating part in this Embodiment. It is a figure which shows two memory mapping examples. It is a figure which shows the bank address switching circuit 861 with respect to two types of memory mapping. It is a figure which shows the timing chart when multibank access and byte boundary generate | occur | produce. 1 is a configuration diagram of a memory device having multi-bank access and a byte boundary function. FIG. It is a figure which shows an example of memory mapping. It is a block diagram of the memory controller in this Embodiment. It is a figure which shows the signal between an access origin block and an interface. It is a figure explaining the data of an access object area | region. It is a timing chart figure of the signal between an access origin block and an interface. It is a figure which shows the operation | movement outline | summary of a memory controller. It is a block diagram of sequencer SEQ. It is a figure for demonstrating the computing equation which produces | generates an intermediate parameter. It is an operation | movement flowchart in a command / address generation part. It is a timing chart figure between a memory controller and a memory device. It is a schematic explanatory drawing of the background refresh in this Embodiment. It is a schematic explanatory drawing of the memory system which performs background refresh in this Embodiment. It is an operation | movement flowchart figure of the memory controller which controls background refresh. It is a figure which shows the relationship between the background refresh and horizontal access in this Embodiment. It is a figure which shows the relationship between the background refresh in this Embodiment, a horizontal access, and a rectangular access. It is a figure explaining the frequency | count of background refresh and the number of blocks in this Embodiment. FIG. 10 is an operation timing chart of background refresh in the present embodiment. It is a figure explaining the refresh burst length in this Embodiment. It is a figure explaining the refresh burst length in this Embodiment. 1 is an overall configuration diagram of a memory device having a background refresh function. It is a bank block diagram of a memory device having a background refresh function. It is a bank block diagram of a memory device having a background refresh function. It is another bank block diagram of a memory device. It is a figure explaining the background refresh operation | movement in this Embodiment. It is a figure which shows the circuit of the 1st, 2nd refresh bank decoder. It is a figure which shows the circuit of the 3rd refresh bank decoder. It is a figure which shows the circuit of a 4th refresh bank decoder. It is a figure which shows the circuit of the 5th refresh bank decoder. It is a figure which shows the circuit of a 6th refresh bank decoder. It is a figure which shows the circuit of the 7th refresh bank decoder. It is a block diagram of a core control circuit. It is a timing chart figure which shows operation | movement of a core control circuit. It is a figure which shows the structure and operation | movement of an address latch circuit. It is a timing chart figure which shows refresh burst operation. It is a block diagram of the core control circuit which controls refresh burst operation. It is another block diagram of the core control circuit which controls refresh burst operation. FIG. 11 is a detailed circuit diagram of a timing control circuit 1190 and a refresh control circuit 1191 in the core control circuit. FIG. 10 is another detailed circuit diagram of the timing control circuit 1190 and the refresh control circuit 1191 in the core control circuit. 12 is a configuration diagram of a refresh burst length counter 1230, a refresh burst length register 1231, and a refresh burst end detection circuit 1232. FIG. It is a block diagram of an address latch circuit. It is a timing chart figure of refresh burst operation. It is a figure which shows the outline of refresh burst stop operation | movement. It is a block diagram of a core control circuit having a refresh burst stop function. It is a circuit diagram of a refresh state control circuit. 3 is a circuit diagram of a timing control circuit 1190 and a refresh control circuit 1191 of a core control circuit. FIG. FIG. 10 is another circuit diagram of the timing control circuit 1190 and the refresh control circuit 1191 of the core control circuit. It is a timing chart figure which shows the operation | movement of FIG. It is a circuit diagram of the command decoder which implement | achieves a refresh stop function. It is a block diagram of the core control circuit 1085 which performs countdown type refresh burst control. 10 is a truth table showing the correspondence between the refresh burst length set in the refresh burst length register 1231 and the address terminals A <3: 0>. It is another block diagram of the core control circuit 1085 which performs countdown type refresh burst control. 3 is a circuit diagram of a timing control circuit 1190 and a refresh control circuit 1191 in a core control circuit 1085. FIG. 12 is a circuit diagram of a refresh burst length register 1231 and a refresh burst length counter 1230. FIG. 12 is a circuit diagram of a refresh burst length register 1231 and a refresh burst length counter 1230. FIG. 10 is a circuit diagram of a refresh address counter 1083 and a refresh address comparison circuit 1370. FIG. FIG. 6 is a timing chart when the countdown type core control circuit has RBL = 3. 6 is a timing chart of a refresh stop operation of a countdown type core control circuit. FIG. 6 is a timing chart of a refresh stop operation of a countdown type core control circuit. FIG. FIG. 6 is a timing chart illustrating a refresh all operation of a countdown type core control circuit. FIG. 10 is a timing chart illustrating an operation for resetting a refresh command of a countdown type core control circuit. FIG. 10 is a timing chart illustrating an operation for resetting a refresh command of a countdown type core control circuit. It is a timing chart figure which shows active and refresh interlocking control. It is a circuit diagram of a refresh bank decoder in active and refresh interlocking control. It is a circuit diagram of the core control circuit in active and refresh interlocking control. It is a circuit diagram of an address latch circuit in active and refresh interlocking control. It is a block diagram of a bank circuit. It is a figure which shows control of the memory block in a core according to the number of refresh blocks. It is a circuit diagram of an address latch circuit. It is a circuit diagram of a predecoder circuit in a row decoder. It is a block diagram of a memory system having a background refresh function. It is a figure which shows the example of memory mapping. It is a figure which shows the head pixel address and size information in horizontal access and rectangular access. It is a block diagram of a memory controller. It is an operation | movement timing chart figure of a memory controller. 6 is a chart for explaining a decoder DEC0 and a selector SEL0 of an active bank number generation unit. 12 is a chart for explaining the meaning of values 000b to 111b that can be set in ACTBA of a register 543. It is a figure which shows the conversion table of decoder DEC1. It is a chart which shows the conversion operation | movement of the decoder DEC1 corresponding to the 1st example of a register setting value. It is a chart which shows the conversion operation | movement of the decoder DEC1 corresponding to the 2nd example of a register setting value. 7 is a chart showing an operation of a selector SEL1. It is a chart which shows the conversion table of decoder DEC2. It is a figure which shows operation | movement of the decoder DEC2 in the case of a 1st register setting value. It is a figure which shows operation | movement of the decoder DEC2 in the case of a 2nd register setting value. It is a figure which shows operation | movement of the decoder DEC2 in the case of a 3rd register setting value. It is a figure which shows operation | movement of the decoder DEC2 in the case of a 4th register setting value. It is a figure which shows the start byte signal SB in a byte boundary. It is a figure which shows the relationship between the 2nd information BMR of byte combination data, and 1st information SB (start byte). It is a figure which shows row address step RS. It is a figure which shows the memory mapping information AR. It is a figure which shows refresh burst length RBL and refresh block number RBC in background refresh. It is a figure which shows the structure of the exclusive input terminal in a memory device, its input buffer, and a mode register. It is a figure which shows the structure of the exclusive input terminal in a memory device, its input buffer, and a mode register. It is a figure which shows an example of a mode register. It is a figure which shows an example of an enable signal generation circuit. It is a figure which shows the input method in a single data rate (SDR). It is a figure which shows the input method in a double data rate (DDR). It is a figure which shows the input method in an ADQ multiplex input system. It is a figure which shows the input method in an address multiplex input system. It is a figure which shows the input method in an address multiplex system by a double data rate (DDR). It is a figure which shows the input method in an address multiplex system by a double data rate (DDR).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

[Memory mapping and problems of image memory]
FIG. 1 is a diagram showing memory mapping of the image memory in the present embodiment. In FIG. 1, display image data in an image processing system including the display device 10 is stored in an image memory 15. The display image data is composed of data such as a luminance signal Y and color difference signals Cb and Cr of each pixel and an RGB gradation signal of each pixel, and each signal is composed of, for example, 8-bit (1 byte) data.

  On the other hand, the image memory 15 is generally composed of a large-capacity and high-speed semiconductor memory device in which an integrated circuit is formed on a semiconductor substrate such as SDRAM. Such an image memory is composed of a plurality of banks Bank 0 to 3 (four banks in FIG. 1), each bank Bank 0 has a plurality of blocks BLK-0, and each block has a plurality of word lines WL and bit lines. It has BL and memory cell MC at the intersection. Although not shown, the memory cell includes a MOS transistor having a gate connected to a word line and a capacitor connected to the transistor. In the example of FIG. 1, four banks are associated with bank addresses BA0-BA3, word lines are associated with row addresses RA0-RA7, and bit lines are associated with column addresses CA0-CA127. A word line in the bank which is a combination of the bank address BA and the row address RA is selected, and a bit line is selected by the column address CA. The 4-byte data BY0-3 is accessed by the bank address BA, row address RA, and column address CA. Since one byte is composed of 8 bits, data of 4 bytes, that is, 4 × 8 = 32 bits, is read or written in association with the input / output terminal of the memory in one access. In general, the 1-byte data (8-bit data) corresponds to a pixel signal. By inputting / outputting 4-byte data in one access, the bandwidth, which means the number of pixels that can be processed per unit time for the image memory, can be increased.

  According to the memory mapping 12 for the display image data, the page area 14 specified by the bank address BA and the row address RA is arranged in a matrix. One page area 14 has 128 memory unit areas specified by column addresses CA0-127 as shown in the enlarged area 14E, and each memory unit area stores 4-byte data BY0-3. . The 4-byte data BY0-3 is input / output via a total of 32 input / output terminals, ie, memory input / output terminals DQ0-7, DQ8-15, DQ16-23, and DQ24-31. The 8-bit data of each byte corresponds to the pixel signal data.

  The memory mapping 12 is suitable for operating the image memory 15 such as SDRAM having a plurality of banks at high speed. The SDRAM drives the selected word line in the selected bank in response to an active command given together with the bank address BA and the row address RA, reads the memory cell data to the bit line, and associates it with the bit line. An active operation for activating the sense amplifier and amplifying the bit line potential is performed, and then a read operation for reading data from the selected bit line is performed in response to a read command given together with the column address CA. Alternatively, the SDRAM performs a write operation for writing the write data to the selected bit line in response to a write command given together with the column address CA and the write data after the active operation. After the read operation or write operation, a precharge operation by a precharge command is performed, and the active operation, read operation, or write operation is performed again. As described above, in the SDRAM, each bank can independently perform an active operation, a read operation, and a write operation.

  According to the memory mapping 12 of FIG. 1, different bank addresses BA0-3 are associated with page areas 14 that are adjacent vertically and horizontally. That is, bank addresses BA0, 1 are alternately arranged in odd rows of the memory mapping 12, and bank addresses BA2, 3 are alternately arranged in even rows. Further, in the raster direction (row direction) of the memory mapping 12, the row address RA0-7 is incremented while being repeated two by two, and each row of the memory mapping 12 is folded at four row addresses RA0-3 and RA4-7. Yes.

  In this way, if memory mapping is used in which the page area on the image is allocated so that the page area of the same bank is not adjacent in either the row direction or the column direction on the memory, a typical access to the image memory is possible. In a certain horizontal access, that is, an access in which the page area 14 is moved and selected in the row direction, the access can be performed while simultaneously executing the active operation and the read / write operation in two banks, and the access efficiency can be improved. . The same applies to access in the vertical direction.

  FIG. 2 is a diagram showing two accesses in the image memory. The horizontal access shown in FIG. 2A is an access that frequently occurs when inputting and outputting a video frame image, and corresponds to a raster scan in which the image is accessed in the horizontal direction 20 from the upper left to the lower right. On the other hand, the rectangular access in FIG. 2B is an access that frequently occurs in image compression and decompression processing such as MPEG, and is accessed as indicated by the arrow 24 from the upper left to the lower right in the rectangle 22 having an arbitrary aspect ratio. It corresponds to the operation. The rectangular area 22 corresponds to an MPEG motion vector extraction target block or the like.

  In general, in an image system using an image memory, the transfer rate of the image memory, which is a frame memory, is set faster than the screen display operation, and image data read out by horizontal access of the image memory is displayed on the screen. New frame data is created by rectangular access, and frame data can be created and output without interruption. For this reason, in an actual image system, horizontal access and rectangular access are mixed.

  In the horizontal access, since scanning is performed in the horizontal direction 20, memory access can be efficiently performed while simultaneously activating adjacent banks. On the other hand, in the rectangular access, the bank address BA and the row address RA are obtained by preventing the position of the accessed rectangular area 22 from exceeding a single bank and further from exceeding the page area in the bank. Since the data in the rectangular area 22 can be accessed by one designated active operation, efficient memory access can be performed in the same way as horizontal access.

  FIG. 3 is a diagram illustrating a problem of horizontal access. A horizontal access timing chart 30 for accessing the horizontal direction 20 in the memory map 12 is shown. In this timing chart, when the page area (BA0 / RA4, BA1 / RA4, BA0 / RA5, BA1 / RA5) in the fourth row of the memory map 12 is accessed horizontally (20 in the figure), the automatic refresh command AREF is It has occurred. The timing chart 30 shows a command CMD, a clock CLK, a bank address BA, a row address RA, a column address CA, and an input / output terminal DQ.

  As a premise, the burst length BL is set to 4. When the page area of BA0 / RA4 is activated by the active command ACT32 and reading of BA0 / CA0 is instructed by the read command RD33, four sets of 32-bit data are input / output after a predetermined latency (4 clocks in the figure). It is continuously output from the terminal DQ in 4 clock cycles. That is, four sets of 32-bit data at column addresses CA0 to CA3 in the page area BA0 / RA4 are continuously output in four steps. This burst operation is an operation in which SDRAM is required by the standard. This means that each 4-byte (32-bit) data of the column addresses CA0 to CA3 in the enlarged page area 14E in FIG.

  Next, 4-byte data of the page area BA1 / RA4 is output by the active command ACT34 and the read command RD35. Similarly, 4-byte data of page area BA0 / RA5 is output by active command ACT36 and read command RD37, and 4-byte data of page area BA1 / RA5 is output by active command ACT38 and read command RD39, respectively.

  At this time, when an automatic refresh command AREF 40 for designating the row address RA6 is generated, the SDRAM memory constituting the image memory executes the refresh operation in parallel in all the built-in banks, the four banks BA0-3. That is, the word lines of the row address RA6 in the four banks are simultaneously driven, the sense amplifier is activated, rewriting is performed, and a precharge operation is performed. This refresh operation means that the four page areas 31 in the memory map 12 in FIG. 3 are performed. Therefore, the horizontal access (arrow 20) is temporarily stopped during the refresh operation period tREF. Then, after the refresh operation period tREF, the horizontal access is resumed by accessing the next page area BA0 / RA6 again with the active command ACT41 and the read command RD (not shown).

  Since the refresh operation by the automatic refresh command AREF is performed at the same time for four banks, if a refresh command is generated during horizontal access, the horizontal access is temporarily interrupted and the effective bandwidth is narrowed. This is a problem in horizontal access.

  FIG. 4 is a diagram illustrating a first problem of rectangular access. FIG. 4A shows an example of horizontal access, and FIG. 4B shows an example of rectangular access. In either case, the access exceeds the boundary of the memory unit area (4-byte area) 45 selected by the column address CA. As described above, according to a general memory map, the page area 14 specified by the bank address BA and the row address RA is divided into a plurality of memory unit areas 45 selected by the column addresses CA0-127. Data of 4 bytes BY0-3 are simultaneously accessed by two column addresses CA. The 8-bit data of each byte corresponds to the pixel signal.

  For this reason, access is performed with relatively little waste in horizontal access, but wasteful data input / output occurs in rectangular access, and the effective bandwidth is reduced.

  In the horizontal access shown in FIG. 4A, when the area 22A is accessed, four read commands RD are issued for the column address CA0-3 following the active command ACT designating the page area BA0 / RA0, and the column address CA0. -3, 4-byte data BY0-3 is input / output continuously. In this case, since the area 22A includes the bytes BY2 and 3 of the column address CA0 to the bytes BY0 and 1 of the column address CA3, the data of the bytes BY0 and 1 of the 4-byte input / output DQ corresponding to the column address CA0. Is not required, and the data of bytes BY2 and 3 among the 4-byte input / output DQ corresponding to the column address CA3 is not required. Therefore, the valid output data is 12 bytes / 16 bytes.

  On the other hand, in the rectangular access shown in FIG. 4B, when the rectangular area 22B is accessed, the six read commands RD are added to the column addresses CA0, 1, following the active command ACT specifying the page area BA0 / RA0. 4, 5, 8, 9 are issued, and 4-byte data BY 0-3 of the column addresses CA 0, 1, 4, 5, 8, 9 is input / output continuously. However, since the rectangular area 22B does not coincide with the boundary of the memory unit area (4-byte area) 45 selected by the column address and exceeds the boundary of the 4-byte area, each of the 4-byte data BY0-3 is half. Becomes unnecessary data. That is, valid output data is 12 bytes / 24 bytes. FIG. 4B shows the worst case.

  As described above, even in the case of data of the same number of bytes, the above rectangular access needs to input / output 24 bytes of data by six read commands RD, but in horizontal access, four read commands RD. Therefore, 16 bytes of data may be input / output. Therefore, an effective bandwidth decreases when accessing a rectangular area exceeding the boundary of the 4-byte area (memory unit area) 45 selected by one column address. This is the first problem of rectangular access.

  FIG. 5 is a diagram illustrating a second problem of rectangular access. The rectangular access is an access to an arbitrary rectangular area, and the rectangular area may exceed the boundary 14BOU of the adjacent page area 14. In FIG. 5, the rectangular area 22 (A) is a 16-byte area in the same page area BA1 / RA6, and the rectangular area 22 (B) is four adjacent page areas BA3 / RA2, BA2 / RA3, BA1 /. A case of a 16-byte area extending over RA6, BA0 / RA7 is shown.

  In the case of the rectangular area 22 (A), as shown in the timing chart, one active command ACT (50 in the figure) for the page area BA1 / RA6 and four times for the column addresses CA6, 7, 10, 11 are shown. 16 bytes of data can be input / output by issuing a read command RD (52 in the figure).

  On the other hand, in the case of the rectangular area 22 (B), as shown in the timing chart, four active commands ACT (54 in the figure) for the page areas BA3 / RA2, BA2 / RA3, BA1 / RA6, BA0 / RA7 and 16-byte data cannot be input / output unless four read commands RD (56 in the figure) are issued for column addresses CA127 (BA3), CA124 (BA2), CA3 (BA1), and CA0 (BA0). That is, when the rectangular area 22 includes adjacent page areas, the active command ACT is issued a plurality of times to activate different banks, and the read RD or write command WR is issued with the column address in each bank. Must. Therefore, the amount of data that can be accessed per unit time is reduced, and the effective bandwidth is reduced.

  When the rectangular area 22 (B) in FIG. 5 is partitioned in the middle of the memory unit area (4-byte area) selected by the column address, the first problem shown in FIG. In addition to requiring multiple active commands (second problem), unnecessary data is included in the input / output data DQ for the read command (first problem). Resulting in lower bandwidth.

  As described above, when memory mapping utilizing the structural characteristics of the SDRAM is adopted in the image memory, the first problem is that access is interrupted by the occurrence of a refresh command during horizontal access, and the second is that the rectangular access area is a column. The problem that input / output data is wasted when the boundary of the memory unit area (4-byte area) selected by the address is exceeded. Third, when the rectangular access area exceeds the boundary of the page area specified by the bank address There is a problem that it is necessary to issue a plurality of bank active commands.

[Overview of this embodiment]
Below, the structure and operation | movement which solves those subjects are demonstrated roughly.

  In this embodiment, access interruption caused by refresh operation and access efficiency decrease due to rectangular access are solved. First, refresh operation can be performed in the background in parallel with access operation during horizontal access. Second, it enables a function to efficiently access an area shifted from the memory unit area (4-byte area) selected by the column address at the time of rectangular access or an area exceeding the memory unit area. This enables a function for efficiently accessing a rectangular area including a plurality of page areas across the boundary of the page area at the time of rectangular access.

  FIG. 6 is a diagram showing the overall operation in the present embodiment. As described above, in an image system using an image memory, horizontal access and rectangular access to the image memory occur together. In the example of FIG. 6, the horizontal access 20-1 for the page area of the bank address BA0, BA1 in the first row of the memory map 12, the rectangular access 22 for the page area BA2 / RA2 in the second row, and the bank in the second row. This is an example in which horizontal access 20-2 to the page areas of addresses BA2 and BA3 occurs in order. In the rectangular access 22, an access is made to a rectangular area that exceeds the boundary of the memory unit area (4-byte area) 45 in one page area BA2 / RA2.

  In this case, in the rectangular access, an access is made to an arbitrary bank of the memory, but in the horizontal access, the access is made only to a predetermined bank for a certain period. For example, during the horizontal access of the first row in the memory map 12, only the bank BA0, 1 is accessed, and the bank BA2, 3 of the second row is not accessed. Conversely, during horizontal access on the second row, access occurs only in the banks BA2 and BA3, and access does not occur in the banks BA0 and BA1 on the first row.

  Therefore, in the horizontal access 20-1, before entering the memory access, a background refresh command BREN for designating a bank that will not be accessed for a while will be issued, and bank information SA = 2/3 that will not be accessed is stored in the memory. Notify That is, a subsequent automatic refresh operation is permitted to the bank SA designated by the background refresh command BREN. Therefore, normal access to the banks SA = 2 and 3 designated for the refresh operation is prohibited.

  In the horizontal access 20-1 in FIG. 6, refresh bank information SA (61 in the figure) for permitting the subsequent refresh operation is issued together with the background refresh command BREN (60 in the figure), and then the page area by the active command ACT. BA0 / RA0 is activated and 4-byte data BY0-3 of column address CA0 is output to input / output terminal DQ by read command RD (BA0, CA0). Similarly, page area BA1 / RA0 is activated by active command ACT, and 4-byte data BY0-3 of column address CA0 is output to input / output terminal DQ by read command RD (BA1, CA0). However, in FIG. 6, the output of four sets of 4-byte data corresponding to BL = 4 is omitted.

  When an automatic refresh request (not shown) activated by a background refresh command BREN is issued in the image memory during the horizontal access 20-1, the refresh operation for the banks BA2 and BA3 is started. However, the horizontal access only causes access to the banks BA0 and BA1, and different banks can be independently activated in the SDRAM, so the horizontal access is disturbed and interrupted by the refresh operation in the banks BA2 and BA3. There is nothing.

  Next, in the rectangular access of FIG. 6, the rectangular area 22 is in the same page area BA2 / RA2, and the latter two bytes BY2, 3 in the column address CA0 and the first two bytes BY0, 1 in the column address CA1. Including. In this case, according to a general read command of SDRAM, it is necessary to issue two read commands RD to the column addresses CA0, CA1.

  However, in this embodiment, by issuing a read command RD (62 in the figure) for the column address CA0 (63 in the figure) and supplying byte combination information SB (64 in the figure) for the access, the byte combination Four bytes corresponding to the information SB can be automatically associated with the input / output terminal DQ. In the above example, by specifying byte shift information SB = 2 to be shifted by 2 bytes as the byte combination information SB, among the 4 byte data of the column address CA0, the data of bytes BY2 and 3 shifted by 2 bytes and the adjacent data Of the 4-byte data at the column address CA1, the first 2-byte bytes BY0, 1 are automatically output.

  In the rectangular access in FIG. 6, following the active command ACT for the page area BA2 / RA2, a read command RD62 designating BA2 / CA0 (63 in the figure) is issued together with the byte combination information SB = 2 (64 in the figure). . This byte combination information SB = 2 means a combination of 4-byte data from the byte BY2 shifted by 2 bytes in the 4-byte area. Alternatively, this byte combination information SB = 2 means that the first byte position (start byte) in the 4-byte area is BY2. In response to this, the image memory stores the data of the bytes BY2 and 3 shifted by 2 bytes (or from the start byte BY2) and the byte data BY0 and 1 of the column address CA1 among the 4-byte data of the column address CA0. Data is output in correspondence with the 4-byte input / output terminal DQ. The memory controller does not need to issue the read command RD for the column addresses CA0, CA twice. Moreover, only necessary data is output to the 4-byte input / output terminals DQ, and unnecessary data is not output, resulting in high access efficiency.

  Further, when the read command RD for specifying BA2 / CA4 is issued together with the combination information SB = 2, the image memory outputs 4-byte data consisting of 2 bytes in the column addresses CA4 and 5 and specifies BA2 / CA8. When the read command RD to be issued is issued together with the combination information SB = 2, 4-byte data consisting of 2 bytes each in the column addresses CA8 and 9 is output, and the read command RD for specifying BA2 / CA12 is output together with the combination information SB = 2 When issued, 4-byte data consisting of 2 bytes each in the column addresses CA12 and CA13 is output.

  As a result, even if the rectangular access area 22 includes the memory unit areas (4-byte areas) of the eight column addresses CA0, 1, 4, 5, 8, 9, 12, and 13, the read command RD receives the column address CA0. , 4, 8, and 12 are only required to be issued four times, and there is no unnecessary data output at the input / output terminals, and the access efficiency can be doubled.

  Since the horizontal access 20-2 after the rectangular access is an access to the page area of the second row of the memory map 12, the normal access to the banks BA0 and BA1 does not occur for the time being. Therefore, similarly to the above, SA = 0/1 is designated as the bank information SA (66 in the figure) permitting the refresh operation together with the background refresh command BREN (65 in the figure), and the subsequent bank BA2 and 3 are transferred to the banks BA2 and BA3. In parallel with the normal access, an automatic refresh operation to the banks BA0 and BA1 is permitted.

  As described above, in the horizontal accesses 20-1 and 20-2, automatic refresh in the background is permitted during normal access, and in the rectangular access, automatic refresh in the background is not permitted. As a result, in the horizontal access 20-1, a normal access operation in the banks BA0, 1 and a refresh operation in the banks BA2, 3 are possible in parallel, and in the horizontal access 20-2, a normal access operation in the banks BA2, 3. Refresh operations can be performed in parallel in banks BA0 and BA1. As a result, horizontal access disturbance due to the refresh operation can be avoided, and an effective reduction in bandwidth can be suppressed.

  In rectangular access, the background refresh operation is prohibited. Thereby, rectangular access to an arbitrary area can be prevented from being interrupted by the refresh operation. Therefore, a decrease in total effective bandwidth can be suppressed.

  In the rectangular access, the byte combination information SB is specified together with the read command, and the combined byte data is input to the 4-byte input / output terminal DQ with any byte combination starting from the column address CA of the read command. Can be output. The byte combination information SB can be specified together with a command for setting the mode register prior to the active command.

  FIG. 7 is a diagram showing another example of the overall operation in the present embodiment. In this example, horizontal access 20-1 to the page area of the first row of the memory map, rectangular access 22, and horizontal access 20-2 to the page area of the second row of the memory map are sequentially performed. is there. In the rectangular access 22, the rectangular area 22 exceeds the page area boundary 14BOU, and is divided into four page areas BA3 / RA2, BA2 / RA3, BA1 / RA6. Includes BA0 / RA7.

  In the horizontal accesses 20-1 and 20-2, as in FIG. 6, by issuing the refresh bank information SA together with the background refresh command BREN, the subsequent automatic refresh operation to the bank is permitted, and the horizontal access is performed. Is prevented from being disturbed by the refresh operation. In a rectangular access to a rectangular area 22 including a plurality of page areas, that is, a plurality of banks, multi-bank information SA ′ is issued together with an active command ACT as bank information to be simultaneously activated. In response to this, the image memory simultaneously performs an active operation on the page areas of a plurality of banks designated by the multi-bank information SA ′ with the address information BA and RA issued together with the active command ACT as the upper left. As a result, in response to one active command ACT, a plurality of banks can be activated simultaneously, and thereafter, a read command RD for each bank is issued together with a bank address BA and a column address CA, whereby each bank 4 bank data of the memory unit area (4 bank area) selected by the column address CA can be output to the input / output terminal DQ.

  In the example of rectangular access in FIG. 7, address information BA3 and RA2 (71 in the figure) specifying the upper left page area are issued together with the active command ACT (70 in the figure), and at the same time, the multibank information SA ′ = 0− 3 (72 in the figure) is also issued. In response to this, the image memory simultaneously activates the four banks BA3, BA2, BA1, BA0 designated by the multibank information SA ′ with the bank BA3 in the upper left page area as the head, and the subsequent four The 4-byte data of the bank BA / column address CA specified by the read command RD is output in order. The same applies to the write command. In the figure, BA3 / CA127, BA2 / CA124, BA1 / CA3, BA0 / CA0 are supplied to four read commands RD, and 4-byte data of each is output.

  If the multi-bank information SA ′ is “2 banks in the horizontal direction”, the bank on the right of the upper left bank corresponding to the bank address BA supplied by the active command ACT is also activated at the same time. If so, the banks below the upper left bank are simultaneously activated. Similarly, if the multi-bank information SA 'is "4 banks vertically and horizontally", the four banks adjacent to the right, bottom, and bottom right of the upper left bank are simultaneously activated. Therefore, in order to automatically activate the multibank, how the row address RA of each row of the memory map is arranged, specifically, in what unit the row address RA is folded back to each row It is preferable to set information (row address step information) in a register or the like in advance.

  In the rectangular access of FIG. 7, when the byte combination information SB described in FIG. 6 is specified together with the read command RD in addition to the multi-bank information SA ′ at the time of the active command ACT, the boundary 14BOU of the page area 14 is exceeded, In addition, some byte combinations in the memory unit area (four bank area) selected by the column address CA can be automatically associated with the input / output terminal DQ.

  FIG. 8 is a configuration diagram of the image processing system in the present embodiment. The image processing system includes an image processing chip 80 corresponding to a memory controller and an image memory chip 86 that stores image data to be processed. The image processing chip 80 and the memory chip 86 are semiconductor chips, and an integrated circuit is formed on each single semiconductor substrate.

  The image processing chip 80 responds to a memory access request including an image processing control unit 81 that performs image processing, such as an encoder and a decoder corresponding to MPEG image compression and decompression, and an image area designation from the image processing control unit 81. And a memory control unit 82 for controlling access to the image memory chip 86. The memory control unit 82 includes a background refresh control unit 84 that controls the background refresh operation in horizontal access, and a byte boundary that controls access to any combination of bytes in the memory unit area (4-byte area) through rectangular access. It has a control unit 85 and a multi-bank activation control unit 83 that controls access including a plurality of page areas by rectangular access. With these controls, commands and bank addresses, row addresses, column addresses, byte combination information SB, refresh bank information SA, multi-bank information SA ′, and the like necessary for each operation are issued to the image memory 86.

  The image memory 86 has a plurality of banks Bank 0 to 3 in the memory core 92, and controls the row control unit 87 that mainly controls the active operation and the read and write operations for these memory cores 92. A column control unit 90 to perform and a background refresh control unit 89 are provided. The row controller 87 has a multi-bank activation controller 88, and the column controller 90 has a byte boundary controller 91. Each bank Bank0-3 includes a row decoder RowDec, a column decoder ColDec, a memory array MA, a sense amplifier group SA, an input / output unit 93 for associating the memory array MA and an input / output terminal DQ. It is.

  FIG. 9 is a configuration diagram of the image memory in the present embodiment. In the image memory chip 86, the external terminal group 93 includes a command terminal including RAS, CAS, WE, and CS, bank address terminals BA0 and BA1, refresh bank information terminals SA0 and SA1, and a plurality of addresses in addition to the clock CLK. A terminal Add, a byte combination information terminal SB having a predetermined number of bits, a data input / output terminal DQ having a predetermined number of bits, a multi-bank information terminal SA ′ not shown, and the like are included.

  Note that the terminals SB, SA ', and SA required for the aforementioned byte boundary function, multi-bank access function, and background refresh function can also be realized by a common special pin. Since such information is supplied together with different commands, the special pin input data may be set in the corresponding register in accordance with the supplied command.

  Further, these terminals SB, SA ', and SA can be realized by unused terminals. For example, in the read operation, if the row address is input at the address terminals Add0 to 12 and the column address is input at the address terminals Add0 to 9, the address terminals Add10 to 12 are not used when the column address is input. . Therefore, the control data SB, SA ′, SA can be input from the address terminals Add10 to 12 that are not used when the column address is input.

  Each of these external terminal groups 93 is connected to an internal circuit via a buffer 94. The command group is input to the command control unit 95, and a control signal corresponding to the command is supplied to the internal circuit. In response to the mode register set command, the command control unit 95 sets a predetermined setting value in the mode register 96 based on the setting data supplied to the address pin Add. The setting information set in the mode register 96 is supplied to the internal circuit. The row control unit 87 includes a multi-bank activation control unit 88, and further includes a row address calculation unit 97 necessary for multi-bank activation. From the multi-bank activation control unit 88, an active pulse is supplied to the bank to be activated. The row address calculation unit 97 supplies a row address to be activated to each bank. In the bank Bank, a refresh row address instructing unit 98 for instructing a row address to be refreshed in the bank is provided. The refresh row address instruction unit 98 has a refresh counter, for example, and generates a row address necessary when an automatic refresh command is generated. The configuration in the bank is as described above.

Hereinafter, the details of the image memory and the memory controller will be described in order for the byte boundary function, the multi-bank active function, and the background refresh function described with reference to FIGS.
《Byte Boundary》
FIG. 10 is a diagram for explaining the byte boundary functions. This figure shows a byte group (or bit group) selected by a row address RA and a column address CA in a certain bank. As described above, also in this example, a 4-byte data area (memory unit area) is selected by the row address RA and the column address CA, and is associated with the 32-bit input / output terminals DQ0-31. Therefore, “0123” at the intersection of the row address RA and the column address CA means the bytes BY0, BY1, BY2, and BY3, respectively. Alternatively, 4 bits may be used instead of 4 bytes. In this case, a 4-bit data area (memory unit area) is selected by the row address RA and the column address CA, and is associated with the 4-bit input / output terminals DQ0-3. The following is an example of 4 bytes for simplicity.

  FIG. 10A corresponds to the conventional example, and a 4-byte data area is uniquely determined by the row address RA and the column address CA, and 32 bits of the 4-byte area (memory unit area) 100 and 101 are always input / output. Associated with terminals DQ0-31.

  On the other hand, FIG. 10B corresponds to the present embodiment, and the input / output terminals DQ0-31 are combined with arbitrary bytes, starting with a 4-byte area specified by the row address RA and the column address CA. Can be associated with In the figure, all 4-byte areas 100 selected when RA = 0 and CA = 0 are directly associated with the input / output terminals DQ0-31. On the other hand, the 4-byte area 102 continuous from the third byte shifted by 2 bytes in the 4-byte area selected by RA = 2 and CA = 1 is associated with the input / output terminals DQ0-31. In this case, the first information (start byte) indicating which byte in the 4-byte area selected by RA = 2 and CA = 1 is the head, and whether 4 bytes are continuous or down from the head byte. Second information (big endian or little endian) such as whether 4 bytes are continuous in the direction, every other one in the up direction or every other one in the down direction is given together with the read command and the write command.

  Based on the byte combination information consisting of the first and second information, the input / output unit of the image memory extracts a total of 4 bytes from the byte data corresponding to different column addresses CA in the page, Associated with input / output terminals DQ0-31. Then, necessary 4-byte data is input / output from the 32-bit input / output terminal DQ at a time.

  FIG. 11 is a diagram showing a timing chart in the byte boundary function. In this example, 4 bytes 102 in the memory map 12 are accessed. First, the bank address BA = 0 and the row address RA = 2 are given together with the active command ACT (110 in the figure), the corresponding page area is activated, and the bank address BA = 0 along with the read command RD (111 in the figure). And column address CA = 1 (112 in the figure), and further, as the byte combination information 113, the first information SB = 2 (114 in the figure) indicating the byte shift amount or the start byte and the combination pattern are shown. Second information BMR = UP (115 in the figure) is given.

  Based on the byte combination information SB = 2 and BMR = UP, the image memory uses the latter half of the 4-byte area selected by the column address CA = 1 (BY2, 3) and the column address CA = 2. The first half of the selected 4-byte area (BY0, 1) is associated with the input / output terminals DQ16-23, DQ24-31, DQ0-7, and DQ8-15 as shown in the figure. This association is performed in the input / output unit 93 by the byte boundary control unit 91 of FIG. Therefore, in spite of the data of different column addresses, any combination of 4-byte data can be associated with the input / output terminal DQ by giving the read command RD once. The same applies to the write command.

  In FIG. 11, the same byte boundary function can be applied even if the 4-byte area selected by the row address RA and the column address CA is a 4-bit area. In this case, 4-bit data in a 4-bit area is associated with the input / output terminals DQ0-3.

  FIG. 12 is a diagram for explaining the byte boundary functions for different mappings. In FIG. 12, for the sake of simplicity, the memory unit area selected by the row address RA and the column address CA is composed of 4 bits. In the left side of FIG. 12, memory mappings 12-1 and 12-2 indicating the correspondence between image pixels and memory spaces are shown, in the center are memory logical spaces 15-1 and 15-2, and on the right side are memory mappings 12-1 and 15-2. A timing chart corresponding to is shown.

  In the central memory logical spaces 15-1 and 15-2, "0-3" indicating 4 bits in the 4-bit area selected by the row address RA and the column address CA is shown, and the input / output terminal DQ0 -3. Also in the left memory mappings 12-1 and 12-2, “0-3” indicating 4 bits in the memory logical space corresponding to the image pixels is shown. That is, the memory mapping shows how each pixel of the image is associated with the input / output terminals DQ0-3 of the memory.

  In the image system, it is up to the system designer to associate the image pixels with any of the 4-bit input / output terminals DQ0-3 that are simultaneously accessed at a certain address BA, RA, CA. Mapping 12-1 is an example of mapping four pixels from left to right in the figure to input / output terminals DQ0-3 in the same direction as the address moving direction (left to right), and is called big endian. On the other hand, the mapping 12-2 is an example in which four pixels are mapped to the input / output terminals DQ3-0 in the direction opposite to the address traveling direction, and is called little endian.

  In both mappings 12-1 and 12-2, rectangular access occurs in the four pixels 123 and 127 from 6 pixels to 9 pixels from the upper left corner of the image. However, since these mappings are mapped in the opposite direction to the 4 bits in the memory, different accesses are required. That is, in the case of the mapping 12-1, as indicated by the arrow 120, for the pixels from the left to the right of the image, DQ1, CA = 1, DQ2, CA = 1, DQ2, CA = 1, DQ3, CA = It is necessary to input / output data in the order of DQ0 in 2. On the other hand, in the case of the mapping 12-2, as indicated by an arrow 124, DQ 2 in CA = 1, DQ 1 in CA = 1, DQ 0 in CA = 1, CA = It is necessary to input / output data in the order of DQ3 in 2.

  Bit combination information SB and BMR are used to cope with such different mappings. That is, in the case of the mapping 12-1, as shown at 121 in the figure, the read command RD and the head address consisting of BA = 0 and CA = 1 and the bit combination information consisting of SB = 1 and BMR = UP are issued. In response, as shown at 122 in the figure, CA = 1 3-bit DQ1, 2, 3 and CA = 2 DQ0 are output simultaneously.

  On the other hand, in the case of mapping 12-2, as shown by 125 in the figure, a read command RD and a head address consisting of BA = 0, CA = 1 and bit combination information consisting of SB = 1, BMR = DOWN are issued. In response to this, 3 bits DQ0, 1, 2 with CA = 1 and DQ3 with CA = 2 are output at the same time as 126 in the figure.

  Thus, by specifying the bit combination information SB and BMR corresponding to different memory mappings of big endian and little endian, the image memory can input and output 4 bits simultaneously corresponding to the memory mapping on the system side. it can. By increasing the types of bit combination information, flexible 4-bit access can be realized for various mappings.

  FIG. 13 is a diagram for explaining the big endian and the little endian in FIG. 12. FIG. 13 shows an image processing system that uses a memory with an input / output bit width of 4 bits on both the left and right sides. The right is a little endian system that handles the direction from DQ3 to DQ0 of the memory DQ as the forward direction.

  The pixel positions (X0 to X11) on the screen both indicate physical positions on the same screen. The “pixel information” at each pixel position is the same “A” to “L” in both systems, which means that both systems display the same image. ing.

  In big-endian systems, pixel positions X0 to X3 are assigned to DQ0 to DQ3 at memory address CA0, pixel positions X4 to X7 are assigned to DQ0 to DQ3 at memory address CA1, and pixel positions X8 to X11 are assigned to DQ0 at memory address CA2. It corresponds to ~ DQ3.

  On the other hand, in the little endian system, pixel positions X0 to X3 are assigned to DQ3 to DQ0 of memory address CA0, pixel positions X4 to X7 are assigned to DQ3 to DQ0 of memory address CA1, and pixel positions X8 to X11 are assigned to memory address CA2. It corresponds to DQ3-DQ0.

  That is, when both systems are compared, the correspondence between the pixels X0 to X3 and the input / output terminals T0 to T3 in the image processing system is opposite between big endian and little endian. Therefore, the pixel information “A” at the pixel position X0 is stored in different physical positions (DQ0 of CA0 and DQ3 of CA0) in the big-endian system and the little-endian system.

  Here, when the image processing system generates a rectangular access (130 in the figure) for the pixel information “FGHI” at the pixel positions X5 to X8, the memory is a physical memory of different memory cells in the big endian system and the little endian system. Locations 132 and 134 must be accessed. Therefore, the minimum information that needs to be supplied to the memory is information BMR indicating whether the system is big-endian (Up) or little-endian (Down), the address CA containing the starting bit, and the starting bit. Of the location information SB in the address of.

  The big endian and the little endian are the same when the memory unit area accessed by the addresses RA and CA is a 4-byte area (byte group).

  FIG. 14 is a diagram for explaining a byte boundary function in special memory mapping. FIG. 14 also shows the memory mapping 12 on the left side, the memory logical space 15 on the center, and the corresponding timing chart on the right side as in FIG.

  In the figure, the memory mapping 12 on the left shows the state of which bits of the memory are assigned to each pixel in the frame image. In this example, one pixel is composed of 2-bit information. For example, even bits hold data representing luminance and odd bits hold data representing color difference.

Therefore, Grouping-1 is a rectangular access that collects only luminance information (even bits) in the second to fifth pixels in the upper left corner, and Grouping-2 is color difference information (odd numbers) in the second to fifth pixels in the upper left corner. Means a rectangular access that only collects bits). In this case, both Grouping-1 / 2 are rectangular accesses from the second pixel to the fifth pixel in the upper left corner of the image, but the luminance (even bit) as indicated by arrow 140 and the color difference (odd bit) as indicated by arrow 144 Due to the difference, as shown in the timing chart, the access from the image processing system to the memory and the input / output terminal DQ are as follows.
Grouping-1: For CA = 0 / SB = 2 and access of BMR = AL (designation of collecting 4 bits every other bit) (141 in the figure), CA = 1 is applied to the input / output terminals DQ0-3. DQ0, CA = 2 DQ0, CA = 0 DQ2, and CA = 1 DQ2 are associated (142 in the figure).
Grouping-2: For CA = 0 / SB = 3 and BMR = AL (designation to collect 4 bits every other bit) (145 in the figure), CA = 2 for I / O terminals DQ0-3 DQ1, CA = 1 DQ1, 3 and CA = 0 DQ3 are associated (146 in the figure).

  In this way, since the same DQ (for example, DQ0 and DQ2 in Grouping-1) is accessed simultaneously in the 4-bit area of different column addresses, some data is transferred to the input / output terminal DQ. For, it is necessary to replace the terminals, that is, to use another DQ data bus.

  FIG. 15 is a diagram for explaining the special memory mapping of FIG. FIG. 15 shows an image processing system using a memory having an input / output bit width of 4 bits. In particular, an image processing system using even DQ of the memory for luminance information of each pixel and odd DQ for color difference information of each pixel. It is. FIG. 15A shows a case where only luminance information is accessed, and FIG. 15B shows a case where only color difference information is accessed.

  The pixel positions (X0 to X5) on the screen indicate the physical positions on the same screen on the left and right. Each pixel position holds “A, C, E, G, I, K” as “luminance information” and “B, D, F, H, J, L” as “color difference information”.

  Here, when the image processing system generates the rectangular access 151 for the luminance information “CEGI” at the pixel positions X1-X4, the memory accesses only the even DQ as shown in FIG. 15A (153 in the figure). When the rectangular access 152 for the color difference information “DFHJ” is generated, the memory must access only the odd DQ (154 in the figure) as shown in FIG.

  For this reason, the minimum information that the memory needs to receive is information indicating whether the system uses a method that maintains luminance information in even DQ and color difference information in odd DQ (whether access is required every 1 DQ) (BMR = AL), an address (CA) including a bit as a starting point, and position information (SB) of a bit as a starting point in the 4-bit area of the address. These column address CA and bit combination information SB and BMR have already been described with reference to FIG.

  In this case, the same DQ (for example, DQ0 or DQ2 in Grouping-1) is accessed at different addresses at the same time, so the data is transferred to the input / output terminals. It is necessary to replace the terminals to use the data bus. For this purpose, a plurality of switches indicated by white and black circles are provided in the memory, and these switches are controlled based on the information SB and MBR.

  FIG. 16 is a timing chart showing a byte boundary function in rectangular access. This rectangular access is an example of accessing the rectangular area 22 in FIG. As described above, in rectangular access, any combination of byte data (bit data) from any byte position (or bit position) in the memory unit area (4-byte area or 4-bit area) selected by the column address CA. Are read out, the first information SB and the second information BMR are required as the first column address CA and the byte combination information 166.

  FIG. 16A shows an example in which these byte combination information SB and BMR are supplied together with the read command RD. The bank address BA = 2 and the row address RA = 2 are supplied by the active command ACT (161 in the figure), and the head byte is sent together with the bank address BA = 2 and the column address CA = 0 by the subsequent read command RD (162 in the figure). First information SB = 2 ((163 in the figure) indicating the (first bit) position and second information BMR = V (165 in the figure) indicating a combination of bytes (bits) are supplied. 6, the first 4 bytes (4 bits) of the rectangular area 22 are output to the input / output terminal DQ, and the remaining three sets of 4 bytes (4 bits) of the rectangular area 22 are also the same bank address BA and column address. It is specified by CA and byte combination information SB and BMR.

  In FIG. 16B, of the byte combination information SB and BMR, the second information BMR (165 in the figure) is the mode register set command EMRS (in the figure) in the register access mode before the active command ACT is issued. 167) and the second information BMR is recorded in a mode register in the memory. In the subsequent rectangular access, column access is performed based on the second information BMR. The active command ACT (161 in the figure) and the read command RD (162 in the figure) in the rectangular access are the same as those in FIG. 16A except for the second information BMR.

  The second information BMR = V is various in big endian (V = UP), little endian (V = DOWN), when luminance information is stored in even DQ, and color difference information is stored in odd DQ (V = AL). Can have a lot of information.

  The image system can realize a byte boundary function in rectangular access by any of the systems shown in FIGS.

  FIG. 17 is a configuration diagram of an image processing system for realizing the byte boundary functions. Similarly to FIG. 8, a memory control unit 82 for controlling the image memory 86 is provided. The memory control unit 82 provides address information BA, RA, CA, and a 4-byte area (or selected by the address information). Byte combination information (bit combination information) 166 including first information SB indicating the first byte (first bit) in the 4-bit area) and second information BMR indicating a combination of bytes, and operation commands ACT, RD , EMRS are supplied to the image memory 86.

  As described above, in the timing chart (A), the byte combination information SB and BMR (166 in the figure) are supplied simultaneously with the read command RD or the write command WT (not shown). In the timing chart (B), the second information BMR is supplied simultaneously with the mode register set command EMRS (167 in the figure), and the first information SB is supplied simultaneously with the read command RD or the write command WT (not shown).

  FIG. 18 is a diagram showing a byte boundary function. This figure is the same as the rectangular access in FIG. In FIG. 10 and subsequent figures, the case where the memory unit area selected by the column address CA is a 4-bit area has been described as an example. However, as described above, when the memory unit area is a 4-byte area, rectangular access is possible by the byte boundary function. FIG. 18 shows this again.

  In the example of FIG. 18, in order to efficiently access the rectangular area 22 in the page area 14 (BA = 0, RA = 0), together with the read command RD (167 in the figure), the bank address BA, the column address CA and , Byte combination information 166 composed of the first information SB and the second information BMR is issued. In response to this, 4-byte data BY0-3 in the rectangular area 22 is simultaneously output to the input / output terminal DQ. A similar operation is performed in the case of the write command WT. That is, the four 4-byte terminals BY0-3 of the input / output terminal DQ are associated with the byte data in CA1, CA1, CA0, CA0 corresponding to the first read command RD, and the next read command RD. Corresponding to each byte data in CA5, CA5, CA4 and CA4. The correspondence between the column addresses corresponding to the remaining read commands RD and the input / output terminals is as shown in the figure.

  In this manner, the bit boundary and byte boundary functions can be realized in the same manner regardless of whether the input / output terminal DQ is 4 bits wide or 32 bits (4 bytes) wide.

  FIG. 19 is a configuration diagram of an image processing system that realizes a simplified byte boundary function. As described above, one of two types of memory mapping, big endian and little endian, can be selected in system design. Correspondingly, in the above-described embodiment, byte-shifted rectangular access is specified by specifying BMR = UP for big endian and BMR = DOWN for little endian in the second information BMR of the byte combination information. Even so, the pixel on the image can be associated with the byte position in the memory space.

  In the example of FIG. 19, when the memory mapping 12 is designed to support little endian, the image memory 86 and the memory control unit 82 can be used even if only the byte boundary function corresponding to big endian can be supported in the memory space 15. By providing the input / output terminal group switching means 190 between the two, the whole system can realize a byte boundary function corresponding to little endian.

  That is, when the memory mapping on the system side is little endian, the switching means 190 is provided to replace 0 and 3 of both input / output terminal groups from 3 to 0. As a result, since the system side can be regarded as supporting big endian when viewed from the image memory, a little endian byte boundary function can be realized even with a memory configuration corresponding only to the second information BMR = UP.

  FIG. 20 is a diagram illustrating an image processing system that implements the simplified byte boundary function of FIG. FIG. 20 (1) is an example in which the image processing system 80 and the image memory 86 are connected by the connection unit 200 that is connected without replacing the input / output terminals T0 to T3. FIG. This is an example in which the connection unit 190 is connected. In any case, the image memory 86 has only a bit boundary function corresponding to big endian, and the image processing system 80 uses the 4-bit data of the input / output bit width as the pixel position X0-X3 and the input / output terminal T3- It is a little endian type corresponding to T1.

  In FIG. 20 (1), when the address unit is accessed (A), the pixel position (X0-X7) on the screen and the address (CA) on the memory side are one-to-one (X0-X3 and CA = 0, X4-X7 and CA = 1), so there is no problem. However, when the signal SB is designated to perform bit-by-bit access (B), in a memory having only a bit boundary function (only BMR = UP) corresponding to big endian, the pixel position shift (X1-X4 ( BCDE), 200 in the figure, and the shift of the physical position of the memory cell (CBAH, 201 in the figure) do not match, and erroneous data CBAH is transferred. In this case, if there is a bit boundary function (BMR = DOWN) corresponding to little endian, BCDE on the memory cell can be output. However, providing the memory with a bit boundary function that can handle both big endian and little endian causes an increase in cost.

  Therefore, as shown in FIG. 20 (2), a connection unit 190 for connecting the input / output terminals on the system side and the memory side is provided, so that the pixels X0-X3 on the image correspond to DQ0-DQ3 also on the memory cells. By doing so, the little-endian image processing system 80 appears to be a big-endian system from the memory 86, so that the relationship between the pixel position shift 200 and the memory cell physical position shift 202 is one. Therefore, normal data BCDE can be transferred even if bit-shifted access corresponding to big endian is performed.

  As described above, by using the connection unit 190 that can be switched and connected by replacement, even a memory having only a bit boundary (or byte boundary) function supporting big endian can be used for an image processing system supporting little endian. Thus, a bit boundary (or byte boundary) function can be realized. In addition, in the case of a memory having a bit boundary (or byte boundary) function corresponding to both big endian and little endian, the memory and the system may be connected by the connection unit 200 that is not switched and connected.

  FIG. 21 is a diagram showing a concept of a memory configuration having a byte boundary function. This memory comprises a bit group with an arbitrary number (Nb) of 1 or more, and has an input / output terminal (Nb x N) of multiples (N) of 2 or more of the arbitrary number (Nb) of bits. The entire storage area (Nb × Ng) is configured by a plurality of bit groups (Ng) greater than a predetermined multiple (N), and any one of the plurality of bit groups (Ng) is synchronized with the first operation code. Address information that can be selected, and select the same number of bit groups as multiples (N) according to a predetermined rule starting from any one bit group selected by the address information. The plurality of bits (Nb x N) to which they belong simultaneously transfers the stored information through the input / output terminals (Nb x N).

  The arbitrary number of bits (Nb) is a concept including both a bit unit and a byte unit, and Nb = 8 (1 byte) according to the above-described embodiment. The multiple (N) expresses how many times the arbitrary number of bits (Nb) is accessed from one address, and Nb × N corresponds to the number of input / output terminals. According to the above embodiment, N = 4 and the number of input / output terminals for 4 bytes. That is, more precisely, the number of input / output terminals is Nb × N, and the number of input / output terminals = 32 (= 8 × 4).

  Ng of multiple (Ng) bit groups is the number of all bits or bytes in the memory (Nb bit bit groups), and is the number obtained by dividing the capacity of the entire storage area by Nb. Is equivalent. Usually, the number is much larger than a multiple (N) that is the number of bit groups input / output at a time. For example, in a 64-Mbit memory, Ng = 64M if Nb = 1 and Ng = 8M if Nb = 8. If we consider a 64Mbit memory according to previous examples, Nb = 8 and Ng = 8M.

  According to the examples so far, address information that can select any one bit group is information (SB) indicating an address (BA, RA, CA) and a starting bit, and the address (BA, RA , CA), the data narrowed down to 4 bytes is further limited to the starting byte by the information (SB) indicating the starting byte.

  Selecting the same number of bits as multiples (N) according to the rule means that according to the previous examples, selecting multiple bytes according to the information (BMR) on the combination of bytes accessed simultaneously with the starting byte, Since N = 4, if BMR = Up, four consecutive bytes in the Up direction are accessed simultaneously from any given byte.

  This is a combination of information (BA, RA, CA) that can select any one bit group (1 byte according to the previous examples) and bytes that are accessed at the same time as the starting byte information (SB). The 4 bytes selected by the information (BMR) are accessed to the image processing system via a 32-bit (= NbxN) input / output terminal.

  The memory device shown in FIG. 21 has a memory capacity of 64 bits. Therefore, there are Ng = 8 groups of bits consisting of Nb = 8 bits. The address (BA, RA, CA) and the start byte SB are composed of a total of 3 bits, and thus one bit group is selected from the bit group of Ng = 8. Further, N = 4 bit groups that are accessed simultaneously are determined by combination information (BMR). Accordingly, in the example of FIG. 21, the second group is selected by the address (BA, RA, CA) and the start byte SB, and the four groups (2 to 5 groups) that are continuous from the second group by the combination information BMR = UP. Are simultaneously accessed from the input / output terminals.

  If the memory capacity is the same 64 bits and the address increases by 1 bit, there are Ng = 16 groups of bits in units of Nb = 4 bits, and the input / output terminals are still Nb × N = 32. Multiple N = 8, and the other seven bit groups are selected by combination information BMR.

[Memory with byte boundary functions]
Next, the configuration of an image memory having a byte boundary function will be described in detail. The byte boundary function enables access to 4-byte data across the boundary of a memory unit area (4-byte area) selectable by a column address. Therefore, a function for inputting / outputting necessary 4-byte data in the memory is added. In the following description, for the sake of simplicity, a case where only the first information SB (referred to as a start byte or a start bit) is given as byte combination information will be described as an example. The second information BMR is an example of fixed UP.

[Internal column control example]
First, some specific examples of column control in the memory will be described.

  FIG. 22 is a diagram illustrating a first example of an image memory having a byte boundary function. FIG. 23 is a diagram for explaining the operation of FIG.

  In FIG. 22, the same reference number is assigned to the same component as the image memory of FIG. The address signal A is input in a multiple manner, the row address RA is latched in the row address buffer 94R, and the column address CA is latched in the column address buffer 94C. The row control unit 87 supplies the row address RA to the row decoder 223 of the selected memory bank 92. The column address CA in the column buffer 94C is also supplied to the column decoder 222 in the selected memory bank.

  The memory bank 92 is divided into four memory blocks, byte areas Byte0-3. Each byte area includes a memory cell array 224, a second amplifier 225, a pair of data latches 226, 227, and a data bus switch 228. 1 byte (8 bits) of data is input / output in one access. A total of 32 bits (4 bytes) of data are input / output to / from the input / output bus I / Obus from the four byte areas. The input / output bus I / Obus is connected to 32-bit input / output terminals DQ0-31 via a buffer. In FIG. 22, only one memory bank 92 is shown, and the remaining three memory banks are omitted.

  The column control unit 90 includes a column timing controller 220 that controls the operation timing of the column decoder 222, a data latch circuit 226, 227, and a data latch selector 221 that controls the data bus switch 228. The data latch selector 221 controls the data latch circuits 226 and 227 and the data bus switch 228 in each byte area Byte0-3 according to the column address CA and the start byte signal SB.

  As shown in FIG. 23, it is assumed that 4-byte data from the second byte of the column address CA0 to the first byte of the column address CA1 is accessed in the page area of the row address RA0. Therefore, the start byte signal SB = 1.

  The memory chip 86 in FIG. 23 shows the relationship between the memory space and the input / output terminals DQ. In FIG. 23, 4-byte data of the memory unit area selected at one time by the column address CA is indicated by Q00 to Q15. That is, the 4-byte data Q00-03 is selected by the column address CA0, and the 4-byte data Q04-07 is selected by the column address CA1.

  A timing chart is shown on the right side of FIG. First, along with the active command ACT, a row address RA0 is given together with a bank address (not shown), the word line in the corresponding bank is driven, and the sense amplifier is activated. Thereafter, the column address CA0 and the start byte signal SB = 1 are given as bank combination information together with the read command RD. In response to this, the column decoder 222 in the selected memory bank 92 time-divides the internal decode signal 222D corresponding to the column address CA0 and the code signal 222D internally corresponding to CA1 obtained by incrementing CA0 by +1. The data is output to four byte areas Byte0-3. In each byte area, two sets of 1-byte data corresponding to CA0 and CA1 are cached in the data latch circuits 226 and 227. Then, the data bus switch 228 outputs 1-byte data selected according to the combination of CA0 and SB1 in each byte area from one of the data latch circuits 226 and 227 to the input / output bus I / Obus. That is, CA0 data Q01, Q02, Q03 and CA1 data Q04 are output to the I / O bus I / Obus. During a write operation, 1-byte data is input from the input / output bus to one of the data latch circuits.

  That is, the column decoder selects a column line (bit line) for one byte in each byte area in one access. In the read operation, one byte of data is selected from the memory cell array 224 in each byte area, amplified by the second amplifier 225, and cached in the data latch circuits 226 and 227. At this time, in each byte area, a memory cell mapped to the same column address CA is accessed. In order to realize byte boundary access that crosses the boundary of the memory unit area (4-byte area) that can be selected by the column address, the column decoder 222 selects the column line again after the first access is completed. The address of this column line is CA1, which is one address ahead of the previous address CA0. The 1-byte data read from the memory cell array 224 is amplified by the second amplifier and cached in the data latch circuit 227 different from the first access.

  Therefore, since the data latch circuits 226 and 227 have 8 bytes of data, which is twice the 4 bytes required by the input / output terminal DQ in one access, the data bus switch 228 has data in each byte area. One half of the data is selected from the two bytes of data cached in the latch circuit and transferred to the input / output bus I / Obus. The data latch selector 221 controls the cache operation to the data latch circuits 226 and 227 in each byte area and the switch operation at the data bus switch 228 according to the column address CA0 and the start byte signal SB = 1. Thus, byte data corresponding to different column addresses CA0 and CA1 can be transferred from each byte area to the input / output bus I / Obus.

  As a result, as shown in FIG. 23, 4-byte data Q04, Q01, Q02, and Q03 are transferred to the input / output terminal DQ via the input / output bus I / Obus. As described above, the input / output unit 93 is configured by the second amplifier 225, the data latch circuits 226 and 227, and the data bus switch 228.

  FIG. 24 is a diagram illustrating a second example of an image memory having a byte boundary function. FIG. 25 is a diagram for explaining the operation of FIG.

  In FIG. 24, the configuration different from that in FIG. 22 is that the memory cell array is divided into two arrays 224-0 and 224-1 in each byte area Byte0-3 in the memory bank 92. Circuits 226 and 227 are provided. In the pair of memory cell arrays 224-0 and 224-1, the column address CA corresponds to an even number (CA [0] = 0) and an odd number (CA [0] = 1). The column decoder 222 does not output the decode signals of CA0 and CA1 from the given column address CA0 in a time division manner, but a pair of memory cell arrays 224 obtained by dividing the two decode signals 222D0 and 222D1 simultaneously. Output to -0, 224-1. In response to this, the pair of memory cell arrays output 1-byte data to the data latch circuits 226 and 227, respectively. As a result, each byte area simultaneously caches the supplied column address CA and 2-byte data of the column address incremented by +1. Then, the data latch selector 221 controls switching of the data bus switch 228 according to the column address CA and the start byte signal SB, and transfers necessary 1-byte data to the input / output bus. Each of the four byte areas outputs 1 byte of data, and a total of 4 bytes of data is output from the input / output terminal DQ.

  In the case of a write command, the 4-byte data supplied to the input / output terminal DQ is transferred to the two data latch circuits 226 via the data bus switch 228 whose switching is controlled according to the column address CA and the start byte signal SB. , 227 and written to the two memory cell arrays 224-0 and 224-1.

  FIG. 25 shows the operation when the start byte signal SB = 1 and the burst length BL = 4. Assuming that the column address CA0 and the start byte signal SB = 1 are supplied simultaneously with the read command RD and the burst length BL = 4 is set in the mode register, the column decoder 222 has the column address CA0 and CA1 obtained by incrementing it by +1. Are simultaneously supplied to the byte areas Byte0-3. In response to this, the pair of memory cell arrays 224-0 and 224-1 in each byte area outputs 1-byte data to the data latch circuits 226 and 227 via the second amplifier 225, respectively. As a result, 2-byte data is cached from each byte area. Then, based on the column data CA and the start byte signal SB, the data latch selector 221 controls which data latch circuit data is selected in each byte area (total of 4 bits in 4 byte areas, one bit at a time). Bit) is supplied to the data bus switch 228 to control the switch operation in the data bus switch. As a result, in the first cycle, 4-byte data Q04 and Q01-03 are transferred to the input / output bus I / Obus.

  In FIG. 25, since the burst length BL = 4, the column decoder 222 issues decode signals 222D0 and 222D1 corresponding to the column addresses CA2 and CA3 under the control of the column timing controller 220, and further outputs 8-byte data. The data latch circuits 22 and 227 are cached. Since the data latch circuits 226 and 227 need to hold 8-byte data of CA0 and CA1, each data latch circuit is configured to hold 2 bytes of data. As a result, 8-byte data Q08-Q15 are newly latched in the data latch circuit. Then, 4-byte data Q05-Q08 is transferred to the input / output bus by data bus switch 228 from 8-byte data Q00-Q15 held in the previous clock cycle and 8-byte data Q08-A15 held in the current clock cycle. . Therefore, the select signal S221 of the data latch selector 221 in this case is composed of 8 bits (2 bits in each byte area).

  In the next clock cycle, the column decoder 222 issues decode signals 222D0 and 222D1 corresponding to the column addresses CA4 and CA5, and caches 8-byte data Q16 to Q23 in the data latch circuit. Data bus switch 228 transfers 4-byte data Q09-Q12. In the next clock cycle, the data bus switch 228 transfers the 4-byte data Q13-Q16 to the input / output bus. At this time, it is not necessary to cache new 8-byte data from the memory cell array.

  The write operation is the same as described above. When the burst length BL = 4, 4 bytes of data are supplied to the input / output terminal DQ in 4 cycles and stored in the data latch circuits 226 and 227 via the data bus switch 228. The In response to the decode signals of column addresses CA0, 1, CA2, 3, CA4, and 5 from the column decoder 222, a total of 16 byte data is written into the memory cell array in three cycles.

  FIG. 26 is a diagram illustrating an operation of the modification (1) of the second example of the image memory having the byte boundary functions. In the example of FIG. 25, each byte area Byte0-3 caches 2 bytes of data in the pair of data latch circuits 226 and 227 simultaneously. On the other hand, in the modified example of FIG. 26, in the first column control after the read command RD, the column decoder 222 issues the internal decode signals 222D0 and 222D1 of the column addresses CA0 and CA1 simultaneously, and 2 bytes in each byte area. Are simultaneously cached in a pair of data latch circuits. In the subsequent cache operation, the column decoder 222 alternately issues the internal decode signal 222D0 on the even side (CA2, CA4) and the internal decode signal 222D1 on the odd side (CA3), and each byte area has 1 byte. Data is alternately cached in a pair of data latch circuits 226 and 227.

  That is, the 8-byte data Q00-Q07 is first cached, and the 4-byte data Q08-Q11, Q12-Q15, Q16-Q19 are cached in the data latch circuit from the next. Then, the data bus switch 228 sequentially transfers the 4-byte data DQ1-DQ4, Q05-Q08, Q09-Q12, Q13-Q16 to be transferred to the input / output bus. Also in this case, the select signal S221 of the data latch selector 221 is composed of 8 bits (2 bits in each byte area). As described above, in the read operation, the cache operation of the data from the memory cell array to the data latch circuit by the decode signal of the column address is performed in 4 cycles, and the data transfer operation from the data latch circuit to the input / output bus is also performed in 4 cycles. Done in

  Also in the case of the write operation, 4 bytes of data are supplied to the input / output terminal DQ in 4 cycles, and stored in the data latch circuits 226 and 227 via the data bus switch 228 in 4 cycles. Then, in response to the decode signals of column addresses CA0 / 1, CA2, CA3, and CA4 from the column decoder 222, a total of 16 byte data is written into the memory cell array in 4 cycles.

  FIG. 27 is a diagram illustrating the operation of the modification (2) of the second example of the image memory having the byte boundary functions. This example is an example applied to DDR (Double Data Rate). The DDR SDRAM inputs and outputs data from the DQ terminal at both the rising and falling edges of the clock CLK. That is, 4-byte data Q05-Q08 is input / output at the rising edge, and 4-byte data Q09-Q12 is input / output at the falling edge.

  Since the input / output rate is doubled in this way, it is necessary to double the amount of data cached in the memory. In the example of FIG. 27, 16 bytes of data Q00-Q03, Q04-Q07, Q08-Q11, Q12-Q15 are simultaneously cached in the data latch circuit in the first cache cycle after the read command RD, and 4 bytes from the 16-byte data. Byte data Q05-Q08 is transferred to the I / O bus at the rising edge of the clock, and the next 4-byte data Q09-Q12 is transferred to the I / O bus at the falling edge of the clock.

  In order to enable batch cache of 16-byte data as shown in FIG. 27, the memory is divided into four memory cell arrays in the byte area Byte0-3 in FIG. 24, and a second amplifier and a data latch circuit are respectively provided. Provided. In each byte area, the column decoder 222 supplies the internal decode signal of the column address CA0-3 corresponding to the head column address CA1 to the four memory cell arrays, and the 4-byte data is cached in the four data latch circuits. Is done. Then, 1-byte data of the data latch circuit selected by the data bus switch 228 by the data latch select signal S221 is transferred from the four data latch circuits to the input / output bus. In the figure, a core bus Corebus corresponds to an input / output bus of a memory cell array, and those data are cached in a data latch circuit.

  In the example of FIG. 27, the LSB (CA [0]) of the input column address CA is ignored, and the input column addresses CA0 and CA1 always correspond to the column addresses CA0-3. Data is accessed. In other words, the paired column address is fixed regardless of whether the input column address is odd or even.

  Further, in the next clock cycle, the column decoder 222 issues an internal decode signal of the column address CA4-7 to the four memory cell arrays, and further caches 4-byte data in the four data latch circuits. As a result, the 16-byte data Q16 to Q31 are latched by the data latch circuit, and the 4-byte data Q13 to Q16 and the 4-byte data Q17 to Q20 selected from the latches are generated at the rising and falling edges of the clock. Each is output.

  In the write operation, write data is written in the memory cell array from the input / output terminal DQ through the data latch circuit in the reverse direction.

  In the case of FIG. 27 as well, the data latch select signal S221 is a control signal of 8 bits in total for 2 bits in each byte area. Such a data latch select signal is generated by the data latch selector 220 in the column controller 90 according to the column address CA and the start byte signal SB.

  FIG. 28 is a diagram illustrating the operation of the modification (3) of the second example of the image memory having the byte boundary functions. This is also an example of an operation corresponding to DDR as in FIG. 27. The difference from FIG. 27 is that the combination of addresses accessed simultaneously is different depending on whether the input column address CA is odd or even. That is, the data corresponding to the input column address CA and the +1, +2, +3 CA are simultaneously accessed. That is, in the case of the input column address CA1, the data of CA1, CA2, CA3, CA4 are accessed. That is, the column decoder monitors the LSB (CA [0]) of the input column address CA and determines the column address to be accessed simultaneously.

  As shown in FIG. 28, for the input column address CA1, the column decoder generates an internal decode signal 222D0-3 of CA1-CA4, and 4 bytes data in each byte area, a total of 16 bytes data is a data latch circuit. Cached. In the next clock cycle, internal decode signals 222D0-3 of CA5-CA8 are generated, and 16-byte data is cached. Therefore, the cached 16-byte data is shifted by 4 bytes from FIG.

  Therefore, the read operation and the write operation of FIG. 28 can be realized with the same memory configuration as that of FIG.

  FIG. 29 is a diagram illustrating a third example of an image memory having a byte boundary function. FIG. 30 is a diagram for explaining the operation of FIG. In the third example, 4-byte data Q01-Q04 input / output by the byte boundary function is accessed by one column access to each byte area Byte0-3 and transferred to the input / output bus. That is, in order to access 4-byte data to the memory unit area of the adjacent column address as in the first and second examples described above, a larger number of 8-byte data or 16-byte data is stored in a plurality of memory units of the adjacent column address. Do not cache from the region.

  As shown in FIG. 29, the column control unit 90 includes a column address controller 290, and determines whether or not the column address CA should be shifted +1 to the column shifter circuit 291 in each byte area Byte 0-3 in the memory bank 92. The shift control signal S290 is supplied. Each byte area includes a column shifter 291, a column decoder 222 that decodes the output, a memory cell array 224 that inputs and outputs 1-byte data by an internal decode signal 222D, a second amplifier, a data latch circuit 226, a data bus And a switch circuit 228. In response to the shift control signal S290, the column shifter 291 in each byte area outputs the column address to the column decoder 222 with or without shifting the column address CA by +1. The data latch circuit 226 only needs to hold 1-byte data. Therefore, the data bus switch circuit 228 always selects 1-byte data in the data latch circuit 226 and transfers it to the input / output bus I / Obus.

  Referring to FIG. 30, the column address controller 290 generates CA1 by shifting the column address CA0 by +1 to the column shifter 291 in the byte area Byte0 in accordance with the input column address CA0 and the start byte signal SB. Control is performed so that the column shifters of other byte areas Byte1-3 do not shift by +1. As a result, in the byte area Byte0, 1-byte data Q04 is accessed based on the internal decode signal 222D corresponding to the column address CA1, and is latched by the data latch circuit 226. In the other byte areas Byte1-3, the 1-byte data Q01, Q02, Q03 are accessed based on the internal decode signal 222D corresponding to the column address CA0 and latched by the data latch circuit 226.

  As described above, in the third example of FIGS. 29 and 30, since the column address is generated in the memory in correspondence with the 4-byte data to be accessed, the column decoder side has a complicated structure. Since it is possible to eliminate the cache operation of byte data having more than 4 bytes, the configuration of the input / output unit 93 is simplified and the power consumption in the memory bank can be reduced.

  In the read operation, 1-byte data corresponding to the column address from the column decoder 222 is output to the data latch circuit 226 in each byte area, and transferred to the input / output terminal DQ via the data bus switch 228. In the write operation, 4-byte data input to the input / output terminal DQ is latched by the data latch circuit 226 via the data bus switch 228 in each byte area. Then, the latched data is written in the memory corresponding to the column address from the column decoder 222 in each byte area.

  The four byte areas in the bank shown in FIGS. 22 to 31 are four bit areas when the memory unit area selected by the column address is composed of four bits. One bit unit of data is accessed as a plurality of sets or a single set.

[Control with input / output terminals]
Next, an example of correspondence control between the input / output terminal DQ in the image memory and the bus or data latch circuit in the memory cell array will be described.

  FIG. 31 is a diagram showing a correspondence means with an input / output terminal of an image memory having a byte boundary function. FIG. 32 is a diagram illustrating the operation of FIG. In the means for correspondence with the input / output terminals, as shown in FIG. 32, 4-byte data corresponding to the column address CA in the memory space is always the same input / output terminal group DQ [7: 0] to DQ [31:24 ], And the correspondence relationship is not dynamically changed. That is, the correspondence (assignment relationship) between the input / output terminal DQ and the bus in the memory (input / output bus of the memory cell array 224) is always fixed without being affected by the start byte signal SB. Therefore, even if the start byte signal SB is different between writing and reading, the input / output terminal DQ input during writing and the input / output terminal DQ output during reading are the same terminal.

  FIG. 31 shows a connection method with the DQ terminal in the case of performing 4-byte access across the boundary of the 4-byte area selected by the column address CA. This figure assumes a read operation (SB = 1) from Byte1 (Q01) in the 4-byte area in the column address CA0.

  When the input / output terminal DQ is not exchanged, the data stored as Byte1 data is always output to the DQ terminal corresponding to Byte1 without depending on the start byte signal SB. Therefore, the connection between the memory cell array 224 and the input / output buffer 94 I / O is always fixedly assigned. Therefore, the designation of the start byte signal SB is simply used to determine which column address CA bus of the memory cell array 224 should be connected to the input / output buffer 94 I / O.

  The example of FIG. 31 is a configuration example corresponding to the first example of FIG. 22 and the second example of FIG. 24, and each byte area Byte0-3 is a pair of areas (odd column address, CA [0] = 0 and even column address, CA [0] = 1). That is, as in FIG. 24, there are two memory cell areas with odd and even column addresses CA, which are further divided into four byte areas. The byte areas Byte0 Area to Byte3 Area include from the column decoder to the data latch circuit. In the case of a read operation, twice the data required for one access is output from the Byte Area, and half of the 4-byte data is input / output by the switch group of the data bus switch 228 (eight squares in the figure). Connected to buffer 94 I / O.

  When the input / output terminal DQ is not replaced in this way, the data Q01 output from the Byte1 Area of the memory cell is always connected to the input / output terminal DQ [15: 8] corresponding to Byte1 of the input / output buffer 94I / O. The Therefore, the control of the data bus switch 228 using the byte start signal SB is control of which data latch circuit in the area corresponding to the two column addresses CA is connected to the input / output buffer 94 I / O.

  The data bus switches 228 in the four byte areas Byte0-3 in FIG. 24 are collectively shown as the data bus switch 228 in FIG. Therefore, the data bus switch 228 in each byte area is composed of a pair of switches corresponding to the same input / output terminal DQ in FIG.

  FIG. 33 is a diagram showing a correspondence means with an input / output terminal of an image memory having a byte boundary function. FIG. 34 is a diagram illustrating the operation of FIG. In the means corresponding to the input / output terminals, as shown in FIG. 34, the 4-byte data corresponding to the column address CA in the memory space is sequentially input / output terminal group DQ [ 7: 0] to DQ [31:24], and the correspondence relationship is dynamically switched between the memory cell array 224 and the input / output terminal group DQ. That is, the correspondence relationship (allocation relationship) between the input / output terminal group DQ and the bus in the memory changes dynamically under the influence of the start byte signal SB. Therefore, if the start byte signal SB is different between writing and reading, the input / output terminal group DQ input during writing and the input / output terminal group DQ output during reading become different terminals.

  As is clear from FIG. 34, when the start byte signal SB = 1, the data Q01-Q04 in the memory are associated with the input / output terminal groups DQ [7: 0] to DQ [31:24]. That is, the correspondence between the bus or data latch circuit in the memory cell array and the input / output terminal group according to the start byte signal SB, the first byte data at the input / output terminal DQ [7: 0], and the remaining 3 byte data at Corresponding to the remaining input / output terminals DQ sequentially. For this purpose, the data bus switch 228 of FIG. 33 is provided with switches at all intersections between the input / output bus group I / Obus and the bus or data latch circuit of the memory cell array 224. The above-described dynamic association can be realized by controlling on / off of these switch groups by the data latch select signal S221 from the data latch selector 221.

  In this way, the input / output terminal DQ is switched for the bus or data latch circuit in the memory cell array in accordance with the start byte signal SB. Specifically, the byte data Q01 output from the byte area Byte1 in the memory cell array is connected to DQ [7: 0] corresponding to Byte0 of the input / output buffer 94I / O when SB = "1". , SB = "0", connected to DQ [15: 8]. The byte data Q05 in the byte area Byte1 is connected to DQ [23:16] when SB = "3", and is connected to DQ [31:24] when SB = "2". That is, the positions of the four switches in the closed state in FIG. 33 are shifted to the right according to the start byte signal SB.

  Next, the correspondence control between big endian and little endian in correspondence control with input / output terminals will be described.

  FIG. 35 is a configuration diagram (1) of an image memory having a byte boundary function and capable of corresponding to endian. In this example, as in the image memory described with reference to FIGS. 19 and 20, the configuration in the memory core 350 is compatible only with big endian (up mode). That is, in the byte boundary operation, only the function of accessing the 4-byte data in the up mode from the byte position corresponding to the start byte signal SB. Even in such a case, by controlling the switch group of the data bus switch 228, it is possible to realize correct data input / output with both a big endian compatible image system and a little endian compatible image system.

  In the figure, the mode register 96 is given second information BMR of byte combination information indicating the up mode or the down mode, and is set to one of the modes. However, the memory core 350 including the column decoder, the memory cell array, and the second amplifier shown in FIG. 29 is compatible only with the up mode control. That is, the column control circuit has only the up mode controller 351 and does not have the down mode controller.

  FIG. 35A shows the data bus switch 228 in the up mode. That is, in the up mode that is big endian, the memory core 350 is controlled to the up mode by the up mode controller 351. Therefore, the data bus switch 228 connects the 4-byte data bytes 0-3 of the data latch circuit 226 to the input / output buffer 94I / O as they are. That is, the core data buses cdb00z to cdb31z of the memory core 350 are directly connected to the I / O data buses pdb00z to pdb31z.

  On the other hand, FIG. 35B shows the data bus switch 228 when the down mode is set. In other words, in the case of the down mode which is little endian, the memory core 350 is controlled to the up mode by the up mode controller 351, but the data bus switch 228 stores the 4-byte data Byte 0, 1, 2 and 3 of the data latch circuit 226. , And correspond to the 4-byte bytes 3, 2, 1, 0 of the input / output buffer 94 I / O. In this case, the core bus cdbxxz and the I / O bus pdbxxz are switched in byte units.

  The data bus switch 228 shown in FIG. 35B is an example in which the same one as the input / output terminal group switching means 190 shown in FIGS. As described above, the configuration of the memory core can be adapted to either big endian or little endian, and the data bus switch 228 as described above is provided, and the switch is switched according to the down mode or the up mode. , Both endian can be supported.

  FIG. 36 is a configuration diagram (2) of an image memory having a byte boundary function and capable of corresponding to endian. Similar to FIG. 35, this image memory has a memory core configuration that can only handle up mode control, and the data bus switch 228 is set in accordance with the second information BMR = UP / DOWN set in the mode register 96. By switching, any mode can be supported. 35, the data exchange by the data bus switch 228 is performed so that the MSB (DQ31) and the LSB (DQ00) are exchanged. That is, in addition to the replacement of 4 bytes, the 8-bit data of each byte is also replaced.

  FIG. 37 is a configuration diagram (3) of an image memory having a byte boundary function and capable of corresponding to endian. This image memory corresponds to the image memory of FIG. 29, controls the change of the combination of column addresses in the four byte areas in the memory core 350 corresponding to the operation mode, and starts from the byte corresponding to the start byte signal SB. 4-byte data in the up direction or down direction is input / output from the four memory arrays.

  For example, as shown in FIG. 30, when the column address CA0 and the start byte signal SB = 1, the internal column addresses of the four byte areas Byte0-3 are CA1, CA0, CA0, CA0 in the up mode, Data Q04, Q01, Q02, and Q03 are input / output from the 4-byte input / output terminal DQ. On the other hand, in the down mode, they are CA0, CA0, CA1, CA1, and data Q00, Q01, Q06, Q07 are input / output from the 4-byte input / output terminal DQ.

  In this way, the column shifter 291 switches column data to be given to the four byte areas Byte0-3 in the memory core between the up mode and the down mode. A combination of column addresses uniquely determined by the start byte signal SB and the mode signal BMR is supplied to each byte area in the memory core 350 via the column shifter 291. The column shifter 291 selects one of the four column addresses caby0z-caby3z from the column address control unit 90A that needs to be switched according to the up mode / down mode Up / Down. In other words, in the byte area Byte0, either caby0z or caby3z is selected, in the byte area Byte1, either caby1z or caby2z is selected, in the byte area Byte2, either caby1z or caby2z is selected, and the byte In the area Byte3, either caby0z or caby3z is selected.

  In the case of a single data rate (SDR), it is sufficient that 4-byte data can be input / output in one access. Therefore, as described with reference to FIG. 29, 1-byte data held in the data latch circuit corresponding to each byte area is used as it is. Transfer to the input / output bus.

  On the other hand, in the case of double data rate (DDR), it is necessary to input / output 8 bytes of data 4 bytes at a time in one access. Therefore, in the configuration of FIG. 29, each byte area Byte0-3 has a block of even column address (CA [0] = 0) and a block of odd column address (CA [0] = 1). The column data of the combination uniquely determined by the start byte signal SB and the mode signal BMR is supplied from the column shifter 291 to the pair of blocks, and the necessary 4-byte data is selected by the data bus switch 228 to the input / output bus I / Obus. Forward. In this case, each switch in the data bus switch 228 selects even-numbered block or odd-numbered block data according to the control signal dabyaz-dabydz from the data latch selector 221 and transfers it to the input / output bus I / Obus. For this reason, the data latch selector 221 is supplied with the data bus column address daby0z-daby3z from the column address control unit 90B, and the data latch selector 221 has four byte areas according to the up / down mode Up / Down. Select one of the two that needs to be switched. This combination of switching candidates is the same as that of the column shifter 291 described above.

  As shown in FIG. 37, the number of switches in the switch group of the data bus switch 228 can be reduced by controlling the combination of column addresses. That is, in the data bus switch shown in FIGS. 35 and 36, if the number of input / output terminals DQ is N bytes, 2N * 8 switches are required. However, by controlling the combination of column addresses as shown in FIG. 37, 2N switches are required for the column shifter 291 and the data bus switch 228, respectively, and a total of 4N switches are required. Therefore, the number of switches can be reduced to ¼ as compared with FIGS.

  FIG. 38 is an operation timing chart of an up mode in the DDR memory of FIGS. 38 and 37. This example is an example of the column address CA1 and the start byte signal SB = 1, and is an example of reading data DQ05 to DQ08 stored in the memory 86 with big endian. That is, the relationship between the data Q00 to Q19 and the input / output terminal DQ with respect to the column address in the memory 86 is as illustrated.

  As described above, in the case of the DDR memory, each byte area in the memory cell array has an even column address block (CA [0] = 0) and an odd column address block (CA [0] = 1). The controlled combination column address caby is supplied to these blocks, and the controlled data bus switching column address daby is supplied to the data bus switch 228.

  That is, CA1 is input as the column address CA serving as the base point. Accordingly, the column address CA supplied to the even number block (CA [0] = "0") and the odd number block (CA [0] = "1") in each byte area Byte0-3 is controlled. In the block (CA [0] = "0") area, the column line of the column address CA2 is activated, and in the odd block (CA [0] = "1"), the byte area Byte 0 has the column address CA3. The column line is activated, and the column line of the column address CA1 is activated in the byte areas Byte1, 2, and 3.

  As a result, data Q05 to Q12 are output to the core bus of the memory core. That is, data Q08-Q11 is output to the even-numbered core bus, and data Q5-Q7, Q12 is output to the odd-numbered core bus.

  In DDR memory, it is necessary to transfer 4-byte data from this 8-byte data to the I / O bus. Therefore, the data bus switch selects the data of the even block (CA [0] = "0") only in the byte area Byte0 based on the start byte signal SB and the column address CA, and inputs the data Q05 to Q08 as a result. Can be output to the output terminal DQ.

  Here, in each of the even and odd areas (CA [0] = "0" / "1"), the internal column address cabyaz selects caby0z, the internal column address cabybz selects caby1z, cabycz selects caby2z, and cabydz Each caby3z is selected. Similarly, column address dabyaz for the data bus selects daby0z in each of the even and odd areas (CA [0] = "0" / "1"). Similarly, dabybz selects daby1z, dabycz selects daby2z, dabydz has selected daby3z respectively.

  FIG. 39 is an operation timing chart of the down mode in the DDR memory of FIG. This example is an example of the column address CA1 and the start byte signal SB = 2, and is an example of reading data DQ05 to DQ08 stored in the memory 86 in little endian. That is, the relationship between the data Q00 to Q19 and the input / output terminal DQ with respect to the column address in the memory 86 is as illustrated. The relationship between the 4-byte data and the input / output terminal DQ is opposite to that in FIG.

  In this case, CA1 is input as the column address CA serving as the base point. Accordingly, the column address CA supplied to the even number block (CA [0] = "0") and the odd number block (CA [0] = "1") in each byte area Byte0-3 is controlled. In the block (CA [0] = "0"), the column line of the column address CA2 is activated, and in the odd block (CA [0] = "1"), the byte area Byte 3 has the column line of the column address CA3. When activated, the column line of the column address CA1 is activated in each of the byte areas Byte2, 1,0.

  As a result, data Q05 to Q12 are output to the core bus of the memory core. That is, data Q08-Q11 is output to the even-numbered core bus, and data Q5-Q7, Q12 is output to the odd-numbered core bus.

  In DDR memory, it is necessary to transfer 4-byte data from this 8-byte data to the I / O bus. Therefore, the data bus switch selects the data Q08 of the even block (CA [0] = "0") only in the byte area Byte3 based on the start byte signal SB and the column address CA, and the rest is the data Q05 from the odd block. -07 can be selected and 4-byte data Q05 to Q08 can be output to the I / O terminal DQ.

  Here, in each of the even and odd areas (CA [0] = "0" / "1"), the internal column address cabyaz selects caby3z, the internal column address cabybz selects caby2z, cabycz selects caby1z, and cabydz Each caby0z is selected. Similarly, the column address dabyaz for the data bus selects daby3z in each of the even and odd areas (CA [0] = "0" / "1"). Similarly, dabybz selects daby2z, dabycz sets daby1z, dabydz selects daby0z.

  As described above, compared with the up mode of Fig. 38, by replacing cabyz and dabyz with byte areas Byte0 and Byte3, and further replacing byte areas Byte1 and Byte2, correspondence between two types of byte data, big endian and little endian. can do.

  FIG. 40 is a diagram for explaining a boundary designation method in the byte boundary function. In the figure, in the byte boundary function in which the column address CA [7: 0] is accessed beyond the boundary between the adjacent 4-byte areas of #n and # n + 1, the boundary specification method is shifted by the start byte SB. The case of value SV is considered. The start byte SB means that 4 bytes are accessed from the byte N, and the shift value SV means that 4 bytes are accessed from a position shifted N bytes from the boundary of the 4-byte area of the column address.

  In this case, the correspondence between the start byte SB and the shift value SV is different between the up mode and the down mode, corresponding to the two endian modes. In other words, in the up mode, since the byte data array is Byte0-3, SB and SV are equivalent. However, in the down mode, since the byte data array is Byte 3-0, SB and SV are not equivalent and have an inverse relationship.

  Therefore, when the image memory has only the terminal of the start byte signal SB and the internal structure is controlled according to the shift value SV, the start byte signal SB is non-inverted or inverted according to the up mode or the down mode. Thus, it is necessary to convert to shift value SV. The same applies when the image memory has only the shift value SV terminal and the internal structure is controlled according to the start byte SB.

  FIG. 41 is a diagram showing a conversion circuit between the start byte SB and the shift value SV. The conversion circuit 410 has a 2-bit configuration 410 [0], 410 [1], and includes CMOS transfer gates 412 and 413 and inverters 414 and 415, and counts indicating whether the input start byte SB is in the up mode or the down mode. Depending on the type signal, it is non-inverted or inverted and converted to a shift value SV. As shown in the truth table 411 of the conversion circuit 410, in the up mode, SB is not inverted and becomes SV, but in the down mode, SB is inverted and becomes SV.

[Column address control for rectangular access]
As shown in FIG. 1, in the memory mapping 12, 14E that associates the memory space of the image memory with the pixels of the image, in the page area 14 selected by the bank address BA and the row address RA, the matrix pixels of the image Corresponding to the arrangement, the memory unit area (4-byte area) selected by the column address CA is mapped so as to be folded with a predetermined folding width (CA Wrap). In the example of FIG. 1, the column address CA is folded back by 4 units in the page area 14. That is, the column address folding width CA Wrap is 4. This column address folding width is also referred to as a column address step.

  By mapping the memory unit area selected by the column address with a predetermined folding width, it is possible to increase the access efficiency of the rectangular access frequently performed in the image memory. In other words, while a page area is activated by an active command, a read command and a column address corresponding to the rectangular area to be accessed are repeatedly issued to access a rectangular area within the same page area. it can. Since a rectangular area within the same page area can be accessed with a single active operation, efficient access is possible.

  As shown in FIG. 16, in such rectangular access, it is necessary to repeatedly issue a read command RD, a bank address BA, a column address CA, and a start byte signal SB. However, if the mapping information of the memory, in particular, the wrapping width (CA Wrap) of the column address CA in the page area is known in advance, the image memory can be obtained by giving the first column address CA, rectangular width, and rectangular size of the rectangular area. Can access image data in a rectangular area by automatically issuing a column address to be accessed internally. In that case, the read command and the column address need only be issued once, and there is no need to issue multiple times as shown in FIG.

  FIG. 42 is a diagram for explaining automatic rectangular access using the byte boundary function. In this example, the data area accessed by the memory mapping 421 is indicated by an arrow. In this memory mapping, the column address CA is folded back to 8 within the page area. That is, the column address folding width CAWrap is 8. Therefore, the column address CA at the right end of the page area 14 has # 07, # 0F, # 17, # 1F (hexadecimal number) and the folding width CAWrap = 8. The start address of the rectangular area to be accessed is CA = # 0B, the start byte signal SB = 2, the width of the rectangular area Rwidth = 2 clocks (4 bytes × 2 clocks = 8 bytes), and the size of the rectangular area is burst. The length BL = 8 (4 × 8 = 32 bytes). Therefore, the height of the rectangular area is BL / Rwidth = 4.

  FIG. 43 is a timing chart for automatic rectangular access. FIG. 44 is a block diagram of an internal column address calculator required for automatic rectangular access. In order to perform the rectangular access as shown in FIG. 42, the column addresses CA = # 0B / # 0C, # 0C / # 0D, # 13 / in the memory according to the supply column addresses CA = # 0B and SB = 2. # 14, # 14 / # 15, # 1B / # 1C, # 1C / # 1D, # 23 / # 24, # 24 / # 25 should be issued. That is, in the first access, Byte 2 and 3 access CA = # 0B, and Byte 0 and 1 access CA = # 0C. In the second access, the column address CA advances by 1, and Byte2, 3 = # 0C, and Byte0,1 access CA = # 0D. In this example, since the rectangular width RWidth = 2, the next access for the third time is not the position where the column address CA has advanced by 1, but the folded column addresses CA = # 13 and # 14. Therefore, it is necessary to obtain the third column address by calculation from the column address folding width CAWrap and the rectangular width Rwidth. Considering this third address in Bytes 2 and 3, based on the current column address CA = # 0C (= 12 (decimal number)), CA Wrap = 8, RWidth = 2, the expression (CA + CAWrap−Rwidth + 1) in FIG. ), The CA for the third access is obtained as CA = 12 + 8−2 + 1 = 19 (decimal number) = # 13 (hexadecimal number).

  FIG. 44 shows a column address calculator in the column controller 90. This computing unit includes a column address counter 440 that increments the column address CA supplied from the outside, the column address CA (Wrap) when folded back by +1 in synchronization with the internal clock pclenz synchronized with the clock timing, and a column address counter. CA Rwap is added to the count value and the Rwidth is subtracted, the calculation unit 441, the switch 442 for selecting the output of the calculation unit 441 when the rectangular area is folded, and the synchronous clock pclenz are counted, and the horizontal count during access A rectangular width counter 444 that counts the value, and a comparator 445 that detects that the horizontal count value widthz of the rectangular width counter 444 matches the rectangular width Rwidth and generates a switching signal wrapz in the switch 442.

  This will be described with reference to the timing chart of FIG. First, it is assumed that the rectangular area size is set in the mode register as the burst length BL = 8, and the column address folding width CAWrap = 8 in the page area is also set in the mode register. Then, along with the read command following the active command, the leading column address CA = # 0B, the start byte signal SB = 2, and the rectangular width Rwidth = 2 to be accessed are supplied. In response to this, the timing clock pclenz is generated in synchronization with the clock, the rectangular width counter 444 counts up the horizontal count value widthz being accessed, and the column address counter 440 starts from the top column address CA = # 0B. Count up.

  The internal column address caz [7: 0] issued for the first access is CA = # 0B / # 0C as shown in FIG. In the second access, # 0C / # 0D is output corresponding to the column address caz [7: 0] = # 0C incremented by +1 by the column address counter 440. In the third access, it is necessary to return the rectangle width, the operation value of the arithmetic unit 441 is selected by the switch 442, the column address caz [7: 0] = # 03 is output, and the corresponding result after the return is obtained. Column address CA = # 13 / # 14 is generated. In the fourth, # 14 / # 15 is generated, and in the fifth, the rectangular area is folded and # 1B / # 1C is generated. After that, # 1C / # 1D, # 23 / # 24, # 24 / # 25 are generated in the same way.

  The configuration of the image memory corresponding to this automatic rectangular access is, for example, as shown in FIG. 29, and a combination of four column addresses corresponding to the byte boundary functions is supplied to the four byte areas Byte0-3. That is, the combination of the column addresses of the internal column address caz in FIG. 43 is supplied to the column decoder in each byte area. As a result, the data of these column addresses are output from the four byte areas, respectively.

  In the above example, the rectangular width Rwidth of the rectangular access is supplied together with the read command, but it may be set in the mode register in advance by the mode register set command. Alternatively, the rectangular size BL and the rectangular width Rwidth may be supplied together with the read command. The column address folding width CAWrap is set in advance by the image system, so it is desirable to set it using the mode register set command.

  In this way, when the column address CA, the rectangle width Rwidth, and the rectangle size (BL) as the starting point are given in the rectangular access, the access should be made based on the preset column address folding width CAWrap. An internal column address can be generated automatically. Therefore, rectangular access can be performed by issuing a single read command.

[Byte boundary function of page area boundary]
The byte boundary function can efficiently access data of a predetermined byte (4 bytes) across the boundary of the memory unit area (4 byte area) selected by the column address. However, when performing rectangular access beyond the page area boundary, it is necessary to activate the adjacent page area again with another active command.

  FIG. 45 is a diagram illustrating an example of a memory operation when access by the byte boundary function reaches the end of the page area. In this figure, the page area is composed of column addresses CA [7: 0] = # 00 to #FF, and the right end is an example of CA = # FF. In this case, if 4-byte data indicated by the arrow in the figure is accessed using the byte boundary function, 4-byte data can be output at SB = 0 in the up mode, but SB = 1, 2, In 3, it wraps around the right end of the page area and accesses the byte data on the left end. In other words, this is an example in which return access is performed within the same page area without performing a new active operation. In the down mode, conversely, when SB = 0, 1, 2, it is necessary to wrap from the left end to the right end (Wrap), but only SB = 3 does not require wrapping.

  When the above access is performed, only useless data is output. In order to access the next page area from the end of the page area, it is necessary to activate a neighboring page area by issuing a new active command.

  FIG. 46 is a diagram illustrating another example of the memory operation when the access by the byte boundary function reaches the end of the page area. In this example, the burst length BL is set to 8. When BL = 8 is set, the burst counter in each bank repeats counting of the internal column address with the count width of BL = 8. That is, in the example of FIG. 46, the internal column address generated by the burst counter has a width 8 of CA = # k8 to #kF (16-bit notation). Even in the case of a memory in which the access area is divided into rectangular areas based on the burst length BL by such a counter, the byte boundary function is used at the right end of the burst length area CA = # k8 to #kF as in FIG. Attempting to do so causes the same problem as in FIG. In the example of FIG. 46, folding occurs in SB = 1, 2, 3 in the up mode, and folding occurs in SB = 0, 1, 2 in the down mode. In this case, useless data is output.

  FIG. 47 is a diagram illustrating another example of the memory operation when the access by the byte boundary function reaches the end of the page area. In this example, the byte boundary operation is realized by using the multi-bank access function in the rectangular access described with reference to FIG. That is, when the row address RA = # n is specified by the active command ACT and the column address CA of the starting point is CA = # FF at the right end of the page area by the read command RD, it exceeds the boundary PB of the page area as indicated by an arrow. Access.

  That is, in the up mode, when SB = 1, 2, 3, the byte data of CA = # FF in the page area of RA = # n and the byte data of CA = # 00 in the page area of RA = # n + 1. And are accessed. In the down mode, when SB = 0, 1, and 2, the CA = # FF byte data in the RA = # n page area and the CA = # 00 byte data in the RA # n + 1 page area are accessed. Is done. In this case, since access to the adjacent page area is necessary, the page area of the row address RA = # n given together with the active command ACT is activated, and the column address CA = # FF supplied along with the read command RD In response to the start byte signal SB = 2, the page area of the adjacent row address RA = # n + 1 is activated. That is, it means that word lines in a plurality of banks are activated in response to one active command ACT.

  Thus, if control is performed so that a plurality of banks are activated in parallel, even if a byte boundary function is requested at the end of the page area, data in the necessary area can be input / output without waste.

[Other uses of byte boundary functions]
The byte boundary function enables efficient data input / output when image data is stored in a memory and data corresponding to an arbitrary pixel is accessed. The byte boundary function has the same merit in applications other than such image memory.

  48 to 50 are diagrams for explaining other uses of the byte boundary function. 48 and 49 correspond to the conventional example, and FIG. 50 corresponds to the present embodiment. As a memory configuration, a plurality of byte areas are allocated to the same column address CA, and a plurality of bytes of data allocated to the same column address CA are accessed by one access. In such a structure, access to the memory can be efficiently performed for processing of data of a fixed byte size (word configuration) allocated to the same column address CA.

  However, the size of data to be processed by the system may be less than the memory word configuration. As a coping method in such a case, there is a method of performing padding so that data of a word configuration size or less does not extend over a plurality of column address CA areas. In the example of FIG. 48, the word configuration of the memory is 4 bytes (see 483 in the figure), the data size unit to be processed is 1 byte (format A of 280 in the figure), 2 bytes (same format B), 4 bytes (same as above) Format C). For this reason, 4-byte size data can be stored so that it does not cross the column address CA by storing Byte0 as a base point. In the case of 2-byte data, it is stored at the position where Byte0 and Byte2 are the base points. 1-byte size data can be based on any position of Byte0, Byte1, Byte2, Byte3.

  Now, suppose that data 0 to 5 having a size of 2 bytes, 4 bytes, 1 byte, 2 bytes, 2 bytes, and 1 byte are continuously stored in the memory as in the write data 482 in the figure. In this case, if a write operation is performed as indicated by reference numeral 481 in the figure, padding is performed in several byte areas in the memory as indicated by reference numeral 483 in the figure, and a total of four bytes area is used for storing valid data. Not used. This means that the memory capacity is not used effectively. However, if data is output in units of 4 bytes by the column address CA, each data can be read by one column address access, so that the reading speed is increased.

  However, in order to eliminate the above-mentioned waste of storage capacity, data may be stored continuously in each byte area of the memory without padding. For example, data can be stored in a byte area in the memory as indicated by 493 in FIG. 49 by writing with a write command WR of 3 cycles as indicated by 491 in FIG.

  If data is written as shown in FIG. 49, the storage capacity of the memory can be used effectively. However, when data is stored across different column address areas, such as 2-byte data B03, B13 of data 3 or 4-byte data C01-C31 of data 1, the conventional In the memory, reading / writing cannot be executed by one column access, and two accesses are required. As indicated by reference numeral 491 in the figure, the read command RD must be issued twice for reading the data 4, and the access efficiency decreases.

  Therefore, as indicated by reference numeral 500 in FIG. 50, by using the byte boundary function, issuing a single read command RD and specifying the start byte signal SB = 3 allows different column address areas to be assigned. Data 3 (03, B13) that spans can be accessed. Therefore, a memory having a byte boundary function can improve the memory utilization rate without causing a decrease in access performance.

[Memory controller that supports byte boundary functions]
Next, a memory controller corresponding to the byte boundary function will be described. Although the image processing system has been described with reference to FIG. 8, an image processing control unit 81 and a memory control unit (memory controller) 82 are included in an image processing chip 80 in the image processing system.

  FIG. 51 is a block diagram of an image processing system. As in FIG. 8, the image processing control unit 81, the memory control unit 82, and the image memory 86 are configured. The image processing control unit 81 is configured to perform MPEG decoding processing as an example. The image processing unit 81 includes an entropy decoding processing unit 510 to which encoded and compressed stream data STM is input, an inverse quantization and IDCT processing unit 511 that performs data processing based on the DCT coefficient DCT-F, A prediction unit 512, an inter prediction unit 513 that reads a reference image to the memory control unit 82 based on the motion vector MV and the microblock division information MBdiv, and a process selection unit 515 are included. The memory control unit 82 performs memory control including issuance of commands and addresses between the image processing control unit 81 and the image memory 86. The decoded image data D-IMG output from the process selection unit 515 is stored in the image memory 86 by the memory control unit 82. In addition, the reference image read control unit 514 of the inter prediction unit 513 acquires the data of the reference image R-IMG from the image memory 86 via the memory control unit 82 and supplies the data to the process selection unit 515.

  The MPEG decoder decodes the current image data based on the reference image R-IMG in the past image or the future image read from the memory based on the motion vector and the difference data between the reference image. Accordingly, an operation of reading a rectangular reference image at the position of the motion vector from the image once stored in the image memory 86 is frequently performed. In this rectangular access control, the access efficiency can be improved by using the image memory 86 having the byte boundary function and the memory control unit 82 corresponding thereto.

  FIG. 52 is a diagram illustrating input and output signals of the memory control unit (memory controller). FIG. 53 is a diagram for explaining a reference image area to be read in a frame image. In the frame image FM-IMG, the upper left is the origin (0, 0) of the pixel coordinates, and in order to specify the area of the rectangular reference image RIMG, the upper left coordinates of the rectangle (POSX, POSY) and the vertical and horizontal sizes SIZEY and SIZEX are required. Therefore, the reference image read control unit 514 in the image processing unit supplies the above-described information (POSX, POSY), SIZEY, and SIZEEX specifying the region of the reference image RIMG to the memory controller 82. Further, a direct memory access control signal DMA-CON is input / output between the reference image read control unit 514 and the memory controller 82.

  On the other hand, the memory controller 82 calculates an address Add (bank address, row address, column address) in the memory space based on the information (POSX, POSY), SIZEY, and SIZEX specifying the reference image area, CMD, address Add, multi-bank access information SA ′, start byte signal SB, write data Data, etc. are supplied to the memory 86. In addition, read data Data read from the memory 86 is received.

  FIG. 54 is a detailed configuration diagram of the memory control unit. The memory control unit 82, from the access request source blocks 81-1 to 81-N that request access to the memory, as in the image processing control unit described above, provides information POSX, POSY, SIZEX, SIZEY of the image area to be accessed. The interface control units 541-1 to 541 -N that receive the write data Data, and the address command generation units 542-1 to 542 -N that receive the image area information and generate addresses and commands via these interface units. The interface control unit and the address command generation unit are arbitrated by the arbitration circuit 540 to determine which should be activated. The address command generation unit 542 selected and activated by the arbitration circuit 540 sends a command CMD, an address Add (bank address, row address, column address), multi-bank access information SA ′, start byte via the selector SEL. The signal SB and the like are issued to the memory 86. Thereby, the memory control unit 82 performs access control to the memory 86 and performs data writing or data reading for the access request source block selected by the arbitration. The memory control unit 82 also makes a refresh request to the memory at a necessary frequency.

  The command CMD issued by the memory control unit 82 includes commands necessary for a normal SDRAM such as a mode register set command, an active command, a read command, a write command, a precharge command, and a refresh command. In addition, the setting register 543 in the memory control unit 82 is set with the address of the upper left pixel of the frame image FM-IMG, memory mapping information, and information about the function of the memory 86. The functions possessed by the memory are, for example, a multi-bank access function and a data array switching function corresponding to endian as described later, and the presence / absence of the function possessed by the memory to be controlled is set in this setting register 543. .

  FIG. 55 is a diagram for explaining the calculation of the inter prediction unit 513 in the reference image read control unit 514. In the case of MPEG, the macro block MB is used as a processing unit. The macro block MB is composed of 16 × 16 pixel luminance data and 8 × 8 pixel color difference (Cb, Cr) data (in the case of Y: U: V = 4: 2: 0). A quarter macroblock QMB including luminance data of 8 × 8 pixels obtained by equally dividing the macroblock MB into four is a processing unit of the motion vector MV and the reference image RIMG. If the upper left coordinate of the macro block MB currently being processed is (MBaddrx, MBaddry), and the macro block division information is Mbdivx, Mbdivy, and the motion vector MV = (MVx, MVy), the arithmetic processing unit 515 is illustrated. The upper left coordinates (POSX, POSY), the horizontal width SIZEX, and the height SIZEEY of the reference image RIMG are calculated by the calculation of the arithmetic expression. This horizontal width SIZEX is set to a multiple of the number of bytes input / output in one access of the memory, and the height SIZEY is set to the number of pixels in the vertical direction.

  The reference image specifying information (POSX, POSY), SIZEY, and SIZEX calculated as described above is output from the reference image read control unit 514 to the memory controller 82, and the command address generation unit 542 in the memory controller 82 receives the above information. Based on the reference image specifying information, the memory mapping information in the setting register 543, the upper left address of the frame area, and the like, an address of the memory space necessary for rectangular access is generated.

FIG. 56 is a diagram illustrating a calculation example of the inter prediction unit 513 in the reference image read control unit 514. It is a specific example of FIG. First, the upper left coordinate of the macro block MB is (MBaddrx, MBaddry) = (0, 0), the macro block division information is Mbdivx, Mbdivy = 8, and the motion vector MV = (MVx, Mvy) = (13, 4). , The upper left coordinates (POSX, POSY), the horizontal width SIZEX and the height SIZEEY of the reference image RIMG are obtained by the following calculation.
POSX = 0 + 8 + 13 = 21
POSY = 0 + 8 + 4 = 12
SIZEX = 8, SIZEY = 8
The rectangular area of the reference image RIMG is not consistent with the unit of the 4-byte area selected by the column address. In order to match the unit of the 4-byte area, it is necessary to access an area having upper left coordinates (20, 12), a horizontal width of 12, and a height of 8, like the enlarged area E-RIMG in FIG. However, by using the byte boundary function, it becomes possible to access in units of bytes beyond the boundary of units of 4 bytes. As described above, in the access of reference image data such as MPEG, the byte boundary function contributes to improvement of access efficiency.

  FIG. 57 is a diagram illustrating an example of memory mapping. Similar to the memory mapping 12 shown in FIG. 1, the image pixels and the page area 14 in the memory space are associated like the memory mapping 12, and the adjacent page areas are arranged to have different bank addresses BA. Has been. The page area 14 is an area selected by the bank address BA and the row address RA, and each page area 14 is composed of a plurality of memory unit areas (4-byte areas) selected by the column address. In the example of FIG. 57, the page area 14 is a unit for storing image data of 64 pixels × 16 pixels.

  FIG. 58 is a diagram showing the configuration of the page area 14 in the memory mapping 12. The page area 14 specified by the row address RA0 in the bank BANK0 has memory unit areas of column addresses CA0 to CA255, 4 bytes are selected by each column address, and the folding width (step width) of the column address CA is 16. Therefore, the page area 14 has a configuration in which the width is 64 (= 4 × 16) bytes and the height is 16 (= 256/16) bytes.

  FIG. 59 is a diagram showing the arrangement of the reference image area in FIG. 56 on the memory map. As shown in FIG. 59, the reference image area RIMG has upper left coordinates (21, 12), a width of 8, and a height of 8. Therefore, the column address CA5 is set as the head address, the byte BY1 is 8 bytes, and the height is 8 bytes. Corresponds to the memory area. That is, the left end 591 of the rectangular access area is shifted by 1 byte (592 in the figure) from the boundary 590 by the column address CA. Therefore, for the memory having the above-described byte boundary function, the bank address BA0 and the row address RA0 are issued together with the active command ACT, and the head column addresses CA5, CA6 to CA117, CA118 together with the read command RD (or write command WR). And the start byte signal SB = 1 may be issued continuously. Alternatively, for the memory having the automatic internal column address generation function shown in FIGS. 42 to 44, the column address folding width CAWrap = 16 is set, and the leading column address CA5 is set together with the read command RD (or write command WR). And a start byte signal SB = 1, a rectangular width Rwidth = 2, and a burst length BL = 16.

  FIG. 60 is a diagram showing another arrangement example of the reference image area on the memory map. In this figure, the reference image area RIMG spans adjacent page areas 14-0 and 14-1. That is, it exceeds the boundary 600 of the page area. In this case, if the memory has the multi-bank access function described with reference to FIG. 7, it can be accessed by a single active command by issuing the multi-bank access information SA '. If the memory does not have a multi-bank access function, it must be accessed by issuing a plurality of active commands for the banks BANK0,1. Therefore, the memory controller needs to set in the register whether or not the image memory to be controlled has a multi-bank access function, and change access control to the image memory in accordance with the setting information.

  FIG. 61 is a timing chart in the memory controller for a memory having no byte boundary function. 60 is an access example of the reference image RIMG of FIG. 59. A conventional SDRAM does not have a byte boundary function. In that case, the memory controller must perform control as shown in FIG.

  In FIG. 61, a signal 610 between the reference image read control unit and the memory controller and a signal 611 between the memory controller and the image memory are shown. As described above, the reference image read control unit 514 transmits the information on the upper left coordinates POSX, POSY, the width SIZEX, and the height SIZEEY of the reference image area together with the access request REQ to the memory controller, and the memory controller responds with the acknowledge signal. ACK is returned. It is assumed that the memory mapping information and the address of the upper left origin of the frame image are set in advance in the setting register.

  In response to this access request REQ, the memory controller issues an active command ACT, a bank address BA = 0, and a row address RA = 0 to the image memory to cause the memory to perform an active operation. Thereafter, in synchronization with the clock CLK, the memory controller issues a read command RD, a bank address BA = 0, a column address CA = 5, 6, 7 to 117, 118, 119 (24 times) to obtain 4-byte data Is received 24 times. Thereafter, the memory controller sets the strobe signal STB to H level and transmits the received data to the read control unit.

  FIG. 62 is a timing chart in the memory controller for a memory having a byte boundary function. This figure is an example of access to the reference image RIMG of FIG. 59, and is control when the memory has a byte boundary function. In the figure, a signal 620 between the reference image reading control unit and the memory controller and a signal 621 between the memory controller and the image memory are shown.

  In this case, the same signal as in FIG. 61 is transmitted from the reference image read control unit to the memory controller. The memory controller issues an active command ACT, a bank address BA = 0, and a row address RA = 0 to the image memory to cause the memory to perform an active operation. Thereafter, the memory controller performs a read command RD, a bank address Address BA = 0, column address CA = 5, 6 to 117, 118 (16 times) and start byte signal SB = 01 are issued, and 4-byte data is received 16 times. Further, the memory controller sets the strobe signal STB to the H level and transmits the received 64-byte data to the read control unit. Since the memory has a byte boundary function, the read command may be issued 16 times, resulting in high access efficiency.

  Although not shown, the column address folding width CAWrap = 16 is set for the memory having the automatic internal column address generation function shown in FIGS. 42 to 44, and the head column address CA5 is set together with the read command RD. And a start byte signal SB = 01, a rectangular width Rwidth = 2, and a burst length BL = 16. In response to this, the image memory automatically generates a column address internally and outputs the 4-byte data in the rectangular area in 16 cycles, and the memory controller continuously receives the 4-byte data 16 times.

  FIG. 63 is a timing chart of the memory controller for a memory that does not have a byte boundary function and a multi-bank access function. This example is an example of accessing the reference image RIMG of FIG. 60, and is an example of control for an image memory having no multi-bank access function. In the figure, a signal 630 between the reference image reading control unit and the memory controller and a signal 631 between the memory controller and the image memory are shown.

  As shown in FIG. 45, a memory that does not have a multi-bank access function cannot access an area that crosses a bank boundary. Therefore, in this case, the memory controller issues an active command ACT and BA = 0, RA = 0 to activate the page area 14-0, and together with the read command RD, the bank address BA = 0, column address CA = 15. ~ 127 are issued to receive 8-byte data. Further, the memory controller issues an active command ACT and BA = 1, RA = 0 to activate the page area 14-1, and together with the read command RD, the bank address BA = 1, the column address CA = 0, 1-112. , 113 is issued to receive 16-byte data. Then, the memory controller transmits the received 24-byte data to the reference image read control unit.

  FIG. 64 is a timing chart in the memory controller for a memory having a multi-bank access function and a byte boundary function. This is also an example of accessing the reference image RIMG of FIG. In the figure, a signal 640 between the reference image reading control unit and the memory controller and a signal 641 between the memory controller and the image memory are shown.

  The memory controller issues a bank address BA = 0, a row address RA = 0, and multi-bank access information SA ′ = 10 (indicating access of two banks adjacent in the horizontal direction) together with the active command ACT. In response to this, the image memory activates the bank with bank BA = 0. Then, the memory controller sequentially issues a start byte signal SB = 01, a bank address BA, and a column address CA together with the read command RD. In response to this column address CA = 15, the image memory also activates the bank with BA = 1. The memory controller receives 16 bytes of data in response to 16 read commands RD. Further, the memory controller transmits the received 16-byte data to the reference image read control unit.

  As described above, the memory controller may issue a single active command to a memory having a multi-bank access function, even if the data extends over different bank areas.

  FIG. 65 is a flowchart of the control operation of the memory controller. First, the host CPU sets ON / OFF of the multi-bank active function in the setting register in the memory controller (S1). The reference image read control unit calculates the coordinates (POSX, POSY) and size (SIZEX, SIZEY) of the reference image block from the motion vector information, macroblock division information, and target macroblock information (S2), and requests for rectangular access Are issued to the memory controller together with the rectangle parameters (S3).

  The memory controller uses the rectangular parameters (POSX, POSY) (SIZEX, SIZEY), the memory map information set in the setting register, and the address information of the frame image to issue BA, RA, CA, SB and SA ′ are calculated (S4). When the multi-bank active function is ON (YES in S5), the memory controller issues BA, RA, SA ′ together with the active command ACT, and further issues BA, CA, SB together with the read command RD, Read data is received (S6, S7, S8). In the case of a write operation, write data is output while sequentially issuing BA, CA, and SB together with a write command WR instead of a read command.

  If the multi-bank active function is OFF (NO in S5), the memory controller checks whether the requested rectangle crosses the page area, that is, the bank (S9), and if not (S9). NO) issues BA and RA together with the active command ACT, and further receives BA, CA and SB along with the read command RD while receiving read data (10, 11, 12). In the case of a write operation, write data is output while sequentially issuing BA, CA, and SB together with a write command WR instead of a read command.

  Further, when straddling banks (YES in S9), since the byte boundary function cannot be used, the memory controller calculates the coordinates POSX and the width SIZEX of the enlarged rectangular area E-RIMG shown in FIG. 56, and the corresponding upper left coordinates. Addresses BA, RA, and CA are calculated (S13). For the enlarged rectangular area, issue the BA and RA together with the active command ACT, and receive the read data while sequentially issuing BA and CA together with the read command RD (S15, 16, 17). When the reading in the upper left coordinate bank is completed (YES in S17, YES in S14), a precharge command is once generated, then an active command is generated for the next bank, and BA, Read data is received while sequentially issuing CAs (S19, S16, 17). When all the data in the bank is received (YES in S17), and when all the data is read (S18), the memory control is terminated.

  If the setting register of the memory controller is set to turn off the byte boundary function, the memory controller issues an active command, a read command, and a necessary address as shown in FIG. 61 by the configuration S13 to S18 of FIG. To do.

  In this way, the memory controller can set the byte boundary function ON / OFF and the multi-bank active function ON / OFF in the built-in setting register, and the necessary commands can be selected according to the function of the image memory to be controlled. And byte combination information such as address, multi-bank information, start byte information, up mode, down mode, and alternative are issued as appropriate.

  FIG. 66 is a flowchart of the control operation of the memory controller. In this example, it is possible to set in the memory controller whether or not the image memory to be controlled has an input / output data switching function corresponding to the endian shown in FIGS. First, the host CPU sets the presence / absence of the output data rearrangement function in the image memory in the setting register of the memory controller (S20). Then, the reference image read control unit calculates the coordinates (POSX, POSY) and size (SIZEX, SIZEY) of the reference image block from the motion vector information, macroblock division information, and target macroblock information (S21), and rectangular access. Is issued to the memory controller together with the rectangular parameters (S22).

  Next, the memory controller uses the rectangular parameters (POSX, POSY) (SIZE, SIZEY), the memory map information set in the setting register, and the address information of the frame image to issue BA, RA to be issued by rectangular access. , CA, SB, SA ′ are calculated (S23). If the output data rearrangement function is set to ON (YES in S24), the memory controller issues a bank address BA, a row address RA, and multi-bank information SA ′ together with an active command, and further a read command At the same time, a bank address BA, a column address CA, and start byte information SB are issued (S25). Thereafter, the read command, BA, CA, and SB are repeatedly issued until reading of all data is completed (S26, S27).

  On the other hand, when the output data rearrangement function is set to OFF (NO in S24), the memory controller issues a bank address BA, a row address RA, and multi-bank information SA ′ together with an active command, and further a read command At the same time, a bank address BA, a column address CA, and start byte information SB are issued (S25). Thereafter, until the reading of all data is completed, the read command, BA, CA, and SB are repeatedly issued, and rearrangement is performed so that the received data is in the order of the original image data (S28, S29, S30).

  The above FIG. 65 and FIG. 66 can be appropriately combined depending on the setting items of the setting register.

  In the above embodiment, the image memory that stores digital image data in which image data of a plurality of pixels is two-dimensionally arranged has been described as an example. However, the present invention is not limited to an image memory that stores image data, and can be applied to a memory device that stores two-dimensionally arranged data other than image data based on a predetermined mapping rule. If the stored data is two-dimensionally arranged data, it may be required to access the data across a plurality of memory unit areas when accessing an arbitrary rectangular area in the two-dimensionally arranged data. In this case, the present invention can be applied.

《Multi-bank access》
Next, multi-bank access for preventing a decrease in access efficiency when a rectangular area including a plurality of page areas is accessed will be described as one of the problems of rectangular access. The multi-bank access function at the time of rectangular access has already been described with reference to FIG.

  FIG. 67 is a schematic explanatory diagram of multibank access in the present embodiment. Access to the rectangular area for the image memory occurs at an arbitrary location. Therefore, as shown in FIG. 67, the rectangular access area 22 in the memory map 12 may exceed the boundary of the page area. In the example of FIG. 67, the rectangular access area 22 includes four page areas (a page area for BA3, RA0, a page area for BA2, RA1, a page area for BA1, RA4, and a page area for BA0, RA5).

  According to the memory mapping 12, page areas adjacent vertically and horizontally are assigned to different banks. Therefore, in order to access the rectangular area 22 in FIG. 67, the four banks Bank0-3 in the memory device 86 must be accessed in the order of Bank3, 2, 1, 0. In the SDRAM, when an active command is supplied by designating a bank address BA and a row address RA, a word line (page area) in the bank is activated. Thereafter, the memory unit area in the activated page area is accessed in response to a read command or a write command specifying the bank address BA and the column address CA. Therefore, in order to access the rectangular access area 22, the memory controller must issue four active commands for four banks to the memory device. Such memory control causes a decrease in access efficiency.

  Therefore, in the present embodiment, as shown in the timing chart of FIG. 67, the memory device responds to the extended mode register set command EMRS (670 in the figure) and step information RS of the row address supplied together with the command. = 4 (671 in the figure) is set in the built-in mode register. The row address step information RS is the number of row addresses RA folded in the row direction in the memory mapping 12, and in the example of FIG. 67, it is folded by RA0-RA3 and RA4-RA7, so RS = 4. It is. Since the memory mapping 12 is not frequently changed in a normal image system, it is desirable to set the row address step information RS in a mode register in the memory device when the image system is activated.

  When a rectangular access occurs, the memory device is supplied with an active command ACT (672 in the figure), bank address BA = 3, row address RA = 0, and multi-bank information SA ′ = 4 (673 in the figure). . That is, in response to a rectangular access request from the image processing unit, the memory controller detects that the rectangular area to be accessed extends over four page areas on the memory map, that is, access to four banks is required. Then, the access target bank number “4” is supplied to the image memory device as the multi-bank information SA ′.

  In response to the active command ACT and the multi-bank information SA ′, the memory device starts with the bank of BA3, the bank of BA2 adjacent in the row direction, the bank of BA1 adjacent in the column direction, and the lower right. Activate the adjacent bank of BA0. In that case, the row control unit in the image memory has the bank address BA = 3, the row address RA = 0, the multi-bank information SA ′ = 4 supplied together with the active command ACT, and the row address stored in the mode register. Based on the step information RS = 4, a bank activation signal for a plurality of banks is generated, and a row address of an active operation target in each bank is generated. According to the memory mapping 12 in the figure, the four row addresses targeted for active operation are RA, RA + 1, RA + RS, and RA + RS + 1 with respect to the supplied row address RA. These four row addresses are supplied to the corresponding four banks according to the supply bank address BA. A plurality of banks in the memory device perform an active operation according to the internally generated bank activation signal and row address.

  Thus, in the example of FIG. 67, in response to one active command ACT, a total of four page areas of BA3, RA0, BA2, RA1, BA1, RA4, and BA0, RA5 page areas. The page area is activated. In a specific activation operation, the word line WL is raised, the sense amplifier is activated, and the potential of the bit line corresponding to the data in the memory cell is amplified.

  The memory device is repeatedly supplied with a read command RD (674 in the figure) together with a bank address BA and a column address CA, and in response to each read command, a memory unit area designated by the bank address BA and the column address CA. Read the data. In the case of a write command, data is written into the memory unit area corresponding to the bank address BA and the column address CA supplied together with the write command. In the example of FIG. 67, bank addresses BA = 3, 2, 1, 0 are supplied together with four read commands RD, and column access to four banks is continuously performed.

  As described above, according to the multi-bank access function of the present embodiment, the memory device responds to one active command (first operation command) and supplies the bank address BA, row address RA, and multi-bank supplied. Based on the information SA ′ and the step information RS of the row address set in advance, the page areas of the plurality of banks to be accessed are activated in advance. Therefore, in the subsequent column access, the bank address BA and the column address CA are appropriately supplied together with the read command or the write command, and the rectangular access is performed.

  In the example of FIG. 67, the memory device calculates the row addresses of a plurality of banks on the basis of the row address step information RS = 4 in the memory mapping 12. Therefore, if the memory mapping 12 is different, the arithmetic expression of the row address is also different correspondingly. Therefore, the memory mapping information can also be set by the extended mode register set command EMRS. Alternatively, the bank address bits may be exchanged according to the memory mapping information, and the row address calculation corresponding to a predetermined memory mapping may be performed in the memory device.

  In the example of FIG. 67, multi-bank information SA ′ = 4, but SA ′ = 2 meaning two banks in the horizontal direction, and SA ′ = 3 meaning two banks in the vertical direction. When the meaning SA ′ = 1 is supplied, the corresponding bank is activated. The multi-bank information SA ′ indicating the above four types is composed of 2 bits.

  FIG. 68 is a diagram for explaining multi-bank access in the present embodiment. In FIG. 68, a rectangular area 22 is an access target area, and this rectangular access area 22 includes four page areas, that is, four banks 14-0, 1, 2, 3, and memory units BA3, RA2, and CA127. Starting from the area, the horizontal direction is a rectangular area with a width of 2 clocks (8 bytes) and a vertical direction with a height of 8 lines. Therefore, the multi-bank information SA ′ for specifying the rectangular access area 22 includes a) size information (= width W, height H) of the rectangular area, or b) bank number information (= 4) in the figure. Either is fine.

  Hereinafter, the operation of the memory device corresponding to the two types of multi-bank information SA ′ will be described with reference to FIGS. 69 and 70.

  FIG. 69 is a timing chart when the multi-bank information SA ′ is bank number information (= 4). In addition to the timing chart of FIG. 67, FIG. 69 shows the column address CA (691 in the figure) of the output data for the 4-byte BY0-3 of the input / output terminal DQ and the access state (activated state) of the banks Bank0-3 (FIG. Middle 690) is shown.

  First, the memory device sets the step number data RS = 4 of the row address of the memory mapping in the mode register by the extended mode register set command EMRS. Next, in response to the bank address BA3 and row address RA2 specifying the top page area supplied together with the active command ACT and the multi-bank information SA ′ = 4 (673 in the figure), the memory device The row addresses RA7, 6, 3 in the banks Bank0-3 are generated, and the page area corresponding to the four row addresses is actively operated together with the supply row address RA2 (690 in the figure). As a result, in the memory device, four banks are in an active state, and the memory can be accessed.

  Thereafter, along with 16 read commands RD (674 in the figure), addresses BA3 / CA127, BA2 / CA124, BA1 / CA3, BA0 / CA0. . . In response, the memory device outputs 4-byte data from the corresponding bank to the input / output terminal DQ after a predetermined latency.

  If SA ′ = 4 is supplied as the multi-bank information SA ′, it is found that the access is to the 2 × 2 page area, so that the memory device responds to the active command ACT and activates the four banks. The action can be performed. If the row address RA of the first bank is supplied, the row addresses of the remaining banks can be obtained by calculation based on the row address step information RS.

  FIG. 70 is a timing chart when the multi-bank information SA ′ is size information (W = 8 bytes, H = 8 rows) of a rectangular area. This timing chart also shows the access states of the input / output terminals DQ and the four banks Bank0-3.

  The extended mode register set command EMRS sets the row address step number data RS = 4 (671 in the figure) and the column address step number data CST = 128 (677 in the figure) in the mode register. Along with the active command ACT, a bank address BA3 and a row address RA2 are supplied (672 in the figure), and further, as multi-bank information SA ′ (675 in the figure), size information 8 × 8 (676 in the figure) of the rectangular access area. ) Is supplied. In response to this active command, the memory device actively operates the page area of the supply addresses BA3 and RA2 (700 in the figure). The memory device then determines the remaining number to be accessed based on the step number data CST = 128 set in the mode register, the column address CA127 supplied together with the first read command RD, and the rectangular size information 8 × 8. Banks 0, 1, and 2 and their row addresses RA7, 6, 3 are obtained, and the page area of those banks is activated (701 in the figure).

  Thereafter, in response to 16 read commands (674 in the figure), the memory device outputs 4-byte data from the corresponding bank to the input / output terminal DQ (702 in the figure).

  In this way, when a rectangular size is supplied as the multi-bank information SA ′, the memory device determines whether or not the access extends over a plurality of banks based on the supplied column address and memory mapping (column address step number CST). The activation signal of the bank subject to the active operation and the row address of each bank are generated, and the active operation is sequentially performed. Therefore, the activation operation of the banks Bank0, 1, 2 is performed after the leading column address CA = 127 is supplied.

  FIG. 71 is a configuration diagram of a memory device having a multi-bank access function. This is equivalent to the configuration diagram of the memory device of FIG. In order to realize the multi-bank access function, the memory device 86 includes a multi-bank activation control unit 88 that generates a pulse-like bank activation signal actpz0-3 to be supplied to a bank to be activated by the row control unit 87, and And a row address calculation unit 97 for generating a row address RA to be activated in the bank. The memory device also has special terminals SP0 and SP1 for supplying multibank information SA '.

  The command control unit 95 decodes a command supplied from a combination of signals RAS, CAS, WE, and CS that specify the command. Along with the extended mode register set command EMRS, the step number data RS of the row address of the memory mapping is input from the address terminal Add and set in the mode register 96. In this case, the type of data set by the bank address BA is designated, and the step number data RS is set in the register area corresponding to the bank address BA.

  In response to the active command ACT, the command control unit 95 generates an active pulse actpz that commands the start of the low-side operation. The multi-bank activation control unit 88 distributes the active pulse actpz to the activation target bank obtained from the supply bank address BA and the multi-bank number data SA ′. This distributed pulse signal is a bank activation signal actpz0-3. The multi-bank information SA 'is input from the special terminals SP0 and SP1 when the active command ACT is issued. The row address RA is input from the address terminal Add.

  Further, the row address calculation unit 97 generates four row addresses RA, RA + 1, based on the supplied bank address BA and row address RA, step number data RS set in the mode register 96, and memory mapping. RA + RS and RA + RS + 1 are generated. These four row addresses are supplied to a 2 × 2 bank group with the bank of the supply bank address BA at the upper left.

  Each bank has a memory core including a memory array MA and a decoder Dec, and a core control unit (not shown) for controlling the memory core. The core control unit responds to the bank activation signals actpz0-3. Then, activation control of the memory core in the bank is performed. In that case, the bank address BA is supplied to each row decoder, the corresponding word line is driven, and then the sense amplifier group is activated. This is the activation operation (active operation) in the bank.

  Hereinafter, specific description will be given of the bank selection operation to be activated in the memory device, the bank activation timing control, the row address generation operation, and the memory mapping bank allocation setting operation as functions required for multi-bank access. To do.

[Bank selection]
72 and 73 are diagrams showing a first example of the multi-bank activation control unit 88. FIG. FIG. 72 shows the configuration of the multi-bank activation control unit 88 and a timing chart. In the first example, 2-bit bank number data is supplied as the multi-bank information SA ′.

  The timing chart is the same as in the above example. Along with the extended mode register set command EMRS, the register setting data V is input to the bank address terminal BA, the step number data RS is input to the address terminal ADD, and the mode register is set. Along with ACT, a bank address BA, a row address RA, and multi-bank information SA ′ are input.

  The memory device latches the multi-bank information SA′0,1 and the bank address BA0,1 input to each input buffer 94 in the latch circuit 720 in synchronization with the clock CLK. The multi-bank activation control unit 88 distributes the active pulse actpz in accordance with the bank decoder 88A that generates the four bank selection signals bnkz <3: 0> by decoding the bank addresses BA0 and BA1, and the bank selection signal bnkz <3: 0>. A bank active pulse output circuit 88B for generating a bank activation signal actpz <3: 0>.

  FIG. 73 shows the logical state of the bank decoder 88A corresponding to the rectangular area to be accessed. FIG. 73A shows four types of rectangular areas, and multi-bank information SA ′ (00, 01, 10, 11) corresponding to the four types of rectangular areas. FIG. 73B is a chart showing the logic processing of the bank decoder. As shown in these figures, when SA '= 00, the number of activated banks is 1, and the bank decoder 88A decodes the bank addresses BA0 and BA1. As a result, the bank decoder 88A sets only the bank selection signal bnkz <3: 0> of one bank selected by the supply bank address BA0, 1 to the H level. Accordingly, the bank activation signal actpz <3: 0> is generated only in the selected bank.

  When SA ′ = 01, the number of activated banks is two in the horizontal direction. Therefore, the bank decoder 88A degenerates (ignores) the bank address BA0 and selects two banks selected only by the bank address BA1. The signal bnkz <3: 0> is set to H level. Accordingly, a bank activation signal actpz <3: 0> between the bank selected by the supply bank address and the bank adjacent in the row direction is generated.

  When SA ′ = 10, since the number of activated banks is two in the vertical direction, the bank decoder 88A degenerates (ignores) the bank address BA1, and selects two banks selected only by the bank address BA0. The signal bnkz <3: 0> is set to H level. Accordingly, a bank activation signal actpz <3: 0> between the bank selected by the supply bank address and the bank adjacent in the column direction is generated.

  When SA ′ = 11, the number of activated banks is four in the horizontal and vertical directions. Therefore, the bank decoder 88A degenerates (ignores) the bank addresses BA0 and BA1, and the bank selection signals bnkz <3 for the four banks. : 0> are all set to H level. Accordingly, bank activation signals actpz <3: 0> of four banks adjacent to the bank selected by the supply bank address in the matrix direction are generated.

  The degeneration of the bank address in the bank decoder is a control for setting both the corresponding bank address BA and its inverted signal / BA to the H level. As a result, the bank decoder 88A ignores the bank address and performs bank selection based on the remaining bank address.

  74 and 75 are diagrams illustrating a second example of the multi-bank activation control unit 88. FIG. FIG. 74 shows a configuration of the multi-bank activation control unit 88 and a timing chart. In the second example, 3-bit simultaneous activation bank data SA'0-2 is supplied as multi-bank information SA '.

  FIG. 75 (A) shows the relationship between the memory mapping 12 and the bank addresses BA0 and BA1. That is, with respect to the supply bank address BA0, 1, the right bank can be selected by inverting and decoding the bank address BA0, and the lower bank can be selected by inverting and decoding the bank address BA1. Can be selected by inverting both bank addresses BA0 and BA1 and decoding them.

  FIG. 75B shows simultaneous activation bank data SA'0-2, a bank to be selected, and logical processing in a bank decoder. That is, when SA'0 = H, the bank decoder inverts and inputs BA0 in order to select the right bank in addition to the bank selected by the supply bank address. When SA'1 = H, the bank decoder inverts and inputs BA1 in order to select the lower bank in addition to the bank selected by the supply bank address. When SA'2 = H, the bank decoder inverts and inputs BA0 and BA1 to select the lower right bank in addition to the bank selected by the supply bank address.

  Returning to FIG. 74, the multi-bank activation control unit 88 includes four bank decoders 88A0-3, an OR circuit 88C that performs an OR operation on these four decode signals, and a bank active pulse output circuit 88B. The active pulse output circuit 88B is the same as that in FIG. Also, the four bank decoders 88A0-3, in order from the bottom, decode the supply bank addresses BA0, BA1 to select the upper left bank, invert BA0 to select the right bank, and invert BA1. And a decoder that selects the lower right bank by inverting both BA0 and BA1. Therefore, the three bank decoders from the top are activated in accordance with the simultaneously activated bank data SA'0-2 and output the corresponding bank selection signals bnkz <3: 0>.

  According to the second example above, the top left top bank is selected by the supplied bank address, and the right, bottom, and bottom right banks are appropriately selected by the 3-bit simultaneous activation bank data SA'0-2. Is done. Accordingly, two banks can be simultaneously activated in an oblique direction, or three banks can be simultaneously activated, and the combination of banks to be simultaneously activated can be flexibly changed. Therefore, it is possible to handle access to special areas.

  76 and 77 are diagrams showing a third example of the multi-bank activation control unit 88. FIG. FIG. 76 shows a configuration of the multi-bank activation control unit 88 and a timing chart. In the third example, rectangular size information W and H are input as multi-bank information from the special input terminal SP. Therefore, the multi-bank activation control unit 88 is provided with an activation bank determination circuit 88D. The activation bank determination circuit 88D includes step number data CST for column addresses in the page area, rectangular size information W and H, and The bank to be activated simultaneously is determined from the column address CA.

  As shown in the timing chart of FIG. 76, the memory device inputs the row number step number RS in the memory mapping and the column number step number data CST in the page area together with the extended mode register set command EMRS. Set to. Next, the memory device inputs the bank address BA, the row address RA, and the rectangular area size data W and H together with the active command ACT. At this time, if the address of the memory device is input non-multiple, the column address CA is also input together with the active command ACT. Since a general SDRAM inputs an address in multiples, a column address CA is input together with a read command and a write command as shown in FIG.

  The activation bank determination circuit 88D in the multi-bank activation control unit 88 determines banks to be activated simultaneously from the step number data CST, the rectangular size information W and H, and the column address CA. The determination algorithm is shown in FIG.

FIG. 77A shows information in the page area of the memory mapping. That is, according to the generalized memory mapping, when the column address is M bits, CA [M−1: 0], and the number of steps is CST = 2 ^S , the horizontal direction in the page area 14 is the lower column address CA. Mapping is performed with [S-1: 0], and the vertical direction is mapped with the upper column address CA [M-1: S]. That is, from the input column address CA, the horizontal position of the page area 14 can be determined by the lower S bits of the column address CA, and the vertical position can be determined by the upper MS bits. Therefore, if the difference between the horizontal position in the page area and the column address step number 2 ^S is smaller than the width W of the rectangular area, the rectangular area will straddle the horizontal bank, and the vertical position and page if the difference between the height 2 ^MS region is smaller than the height H of the rectangular area, so that the rectangular area straddles the vertical banks.

As shown in the activation bank determination algorithm in FIG. 77 (B), for the input column address CA, (1) the conditions for straddling the bank (page area) in the horizontal direction are:
2S-CA [S-1: 0] <W, and (2) The conditions for straddling banks (page areas) in the vertical direction are:
2M-S-CA [M-1: S] <H.

  Referring to the example of FIG. 77C, the page area 14X has 128 memory unit areas selected by the 7-bit column address CA [6: 0], and the number of steps in the row direction is CST = 16. is there. For such a page area 14X, when the input column address CA = 77 (decimal number), the rectangular size W = 8 (8 clocks, 32 bytes), and H = 8, the lower address CA [3: 0] = 13. Since the upper address CA [6: 4] = 4, it is determined that both the horizontal direction and the vertical direction straddle based on the above conditional expression.

  By the determination algorithm as described above, the activation bank determination circuit 88D determines which bank should be activated at the same time. As a result, the activation bank determination circuit 88D outputs a bank address degeneration signal 88E to the bank decoder 88A. That is, the bank address BA0 is degenerated when straddling a horizontal bank, and the bank address BA1 is degenerated when straddling a vertical bank. This degeneration signal 88E is equivalent to the multi-bank information SA'0, 1 in FIG.

  That is, the third example is an example in which the activation bank determination function performed by the memory controller in the first and second examples is provided in the memory device. If the above activation bank determination algorithm is provided in the memory controller, the multi-bank information SA'0, 1 of FIG. 72 is supplied from the memory controller to the memory device.

  As described above, in order to realize the multi-bank activation function, the multi-bank activation control unit 88 in the row control unit generates the bank selection signal bnkz <3: 0> to be activated based on the input data, Based on this, the bank activation signal actpz <3: 0> is generated to control the activation operation of the bank to be activated.

[Bank activation timing]
The multi-bank activation control unit 88 supplies a bank activation signal actpz <3: 0> to a bank to be activated, and each bank starts an activation operation of a page area in response to the bank activation signal. . In that case, it is desirable to control the timing for activating a plurality of banks. For example, a control for activating the plurality of banks at the same timing and a control for activating the plurality of banks at different timings can be considered. In the former case, there is no restriction on the timing of subsequent read commands and write commands. On the other hand, in the latter case, since the activation operation is not performed in a plurality of banks at the same time, it is possible to avoid an instantaneous increase in current consumption.

  FIG. 78 shows a first example of bank activation timing. In this example, a plurality of banks are activated simultaneously. As described above, the multi-bank activation control unit 88 selects the active pulse actpz from the command control unit 95 based on the bank decoder 88A for selecting the activation bank and the activation bank selection signal bnk <3: 0>. And a bank active pulse output circuit 88B that distributes to the banks. As shown in the timing chart in the figure, the bank active pulse output circuit 88B is composed of four AND gates and outputs the bank activation signal actpz <3: 0> at the same timing.

  Each bank bank 0-3 has a memory core 781 including a memory cell array and a core control circuit 780 for controlling the memory core. In response to the bank activation signal actpz <3: 0>, each core control circuit 780 Activates the row decoder in the memory core 780, drives the word line corresponding to the row address, and activates the sense amplifier row.

  In Example 1 of FIG. 78, since a plurality of banks to be activated in response to the active command ACT are simultaneously activated, it is possible to access the plurality of banks by sequentially inputting subsequent read commands or write commands.

  FIG. 79 is a diagram illustrating a second example of bank activation timing. In this example, a plurality of banks are activated by sequentially shifting the timing. The command control unit 95 includes three delay circuits 791, 792, and 793 in addition to the command decoder 95A and the pulse generation circuit 95B. The three delay circuits are activated in response to the activation bank number signal 790, and delay the active pulse actpz0 generated by the pulse generation circuit 95B by a predetermined time to generate three delayed active pulses actpz1-3. . The active pulse actpz0 and the delayed active pulse actpz1-3 are respectively supplied to the four selectors SEL of the bank active pulse output circuit 88B.

  The multi-bank activation control unit 88 includes an activation bank control circuit 88C and a bank active pulse output circuit 88B. The activation bank control unit 88C incorporates the function of the bank decoder described above, and supplies a bank address BA [1 : 0] and the multi-bank data SA ′ [1: 0], the activation order is determined for the bank to be activated, and the selection signal 795 is supplied to the selector SEL. This selection signal 795 is composed of 8 bits, a 2-bit selection signal is supplied to each selector, and each selector outputs a bank activation signal actpz <3: 0> to the bank to be activated in response to the selection signal 795. To do.

  Note that the delay circuits 791 to 793 generate necessary delay active pulses actpz1-3 according to the activation bank number data 790, thereby enabling power saving.

  FIG. 80 is a diagram for explaining the logic of the bank activation timing control of the activation bank control circuit 88C. FIG. 80 shows tables 800, 801, and 802 of order data (2-bit binary display) for activating four banks in the case of multi-bank data SA ′ [1: 0] = 11, 01, 10. It is shown.

  When the multi-bank data SA ′ [1: 0] = 11, all four banks are activated, and as shown in the activation order data table 800, according to the supply bank address BA [1: 0] The activation order data (00, 01, 10, 11) are different. For example, when the supply bank address BA [1: 0] = 00, activation control is performed in the order of the banks Bank0, 1, 2, and 3. The activation order data (8 bits of 00, 01, 10, 11) shown in the table 800 corresponds to the 8-bit selection signal 795 generated by the activation bank control circuit 88C shown in FIG. That is, the four selectors SEL select the active pulse actpz0 and the three delayed active pulses actpz1, actpz2, actpz3, respectively. As a result, the bank activation signals actpz <0> to <3> are generated in order.

  When the supply bank address BA [1: 0] = 01, activation control is performed in the order of the banks Bank1, 0, 3, and 2. The bank activation signals actpz <0> to <3> in this case are shown in the timing chart of FIG. The activation order data (8 bits of 01, 00, 11, and 10) shown in the table 800 is supplied to the selector as the selection signal 795, and the four selectors SEL are sequentially supplied with the delayed active pulse actpz1 and the active pulse from the top. Select actpz0 and delayed active pulses actpz3 and actpz2, respectively. As a result, as shown in the timing chart, the bank activation signals actpz <1>, <0>, <3>, <2> are generated in this order.

  Similarly, when the multi-bank data SA ′ [1: 0] = 01, two banks in the horizontal direction are activated, and as shown in the activation order data table 801, the supply bank address BA [1 : 0], two activation order data (00, 01) are generated.

  Similarly, when the multi-bank data SA ′ [1: 0] = 10, two banks in the vertical direction are activated, and as shown in the activation order data table 802, the supply bank address BA [1 : 0], two activation order data (00, 10) are generated. According to this table 802, since it is shared with the table 800, a bank activation signal is generated using the active pulse actpz0 and the delayed active pulse actpz2 in order to activate the two banks. That is, as shown in the timing chart 803 below the table 802, in response to the supplied active command ACT, the internal active command ACT is generated at the timing of the active pulse actpz0 and the delayed active pulse actpz2.

  Therefore, when the multi-bank data SA ′ [1: 0] = 10, activation order data (00, 01) as shown in the table 804 may be generated instead of the table 802. In this case, as shown in the timing chart 805 below the table 804, in response to the supplied active command ACT, the internal active command ACT is generated at the timing of the active pulse actpz0 and the delayed active pulse actpz1. That is, two banks activated simultaneously are activated successively while shifting the timing.

  FIG. 81 shows a third example of bank activation timing. In this example, a plurality of banks are activated by sequentially shifting the timing. In FIG. 81, flip-flop circuits 810 to 812 that operate in synchronization with the clock CLK are provided instead of the delay circuits 791 to 793 of FIG. The other configuration is the same as FIG. The activation bank control circuit 88C is also as described with reference to FIGS.

  According to the third example, since the delay circuit is the flip-flop circuits 810 to 812 synchronized with the clock CLK, three delayed active pulses actpz1-3 are generated from the active pulse actpz0 with a delay timing synchronized with the clock CLK. That is, as shown in the timing chart of FIG. 81, the bank activation signals actpz <0> to <3> are sequentially output in synchronization with the clock CLK. As a result, when the clock CLK is speeded up, the bank activation signals actpz <0> to <3> are also sequentially generated at high speed, and when the speed is decreased, they are sequentially generated at low speed. Therefore, clock synchronous operation is possible.

[Generate row address]
In the multi-bank access function in the present embodiment, in response to one active command ACT and the bank address and row address, activation control is performed for all the page areas of the bank that need access. Therefore, it is necessary to generate a row address for specifying a page area that needs to be activated in addition to determining a bank that needs to be activated from the supplied bank address and row address.

  FIG. 82 is a diagram for explaining row address generation in multibank access in the present embodiment. In the figure, a memory mapping 12, a supply bank address BA0, 1 corresponding to the rectangular access area RC0-3, and a logical value table 820 showing the activation target row address RA of each bank are shown. The memory mapping 12 is the same as described above. In the page area arranged in the matrix direction, the banks of the page areas adjacent to each other in the upper and lower sides are different, and the row address is set for each of the four banks Bank0-3 vertically adjacent to each other. It is incremented by +1.

  According to this memory mapping 12, in the case of the rectangular area RC0 to be accessed, the address of the page area to be activated simultaneously from the supply bank address BA = BA0 (= 00) and the supply row address RA = RA0 is It can be understood that they are BA0 / RA0, BA1 / RA0, BA2 / RA0, and BA3 / RA0. In the case of the rectangular area RC1, from the supplied bank address BA = BA1 (= 01) and row address RA = RA0, the addresses of page areas to be activated simultaneously are BA1 / RA0, BA0 / RA1, BA3 / RA0, In the case of BA2 / RA1 and the rectangular area RC2, the address of the page area to be activated at the same time from the supplied bank address BA = BA2 (= 10) and the row address RA = RA0 is BA2 / RA0, BA3 / RA0, BA0 / RA (0 + RS), BA2 / RA (0 + RS). In the case of the rectangular area RC3, the bank address BA = BA3 (= 11) and the row address RA = RA0 to be simultaneously activated should be activated. The page area addresses are BA3 / RA0, BA2 / RA (0 + 1), BA1 / RA (0 + RS), B Is a 2 / RA (0 + RS + 1).

Generalizing the above, when the supply row address is RA and the number of steps of the row address of the memory mapping 12 is RS, the row address to be generated in each bank Bank0-3 is a logical value according to the supply bank address BA0, BA1. As shown in Table 820. That is, it is as follows.
BA = 00: RA, RA, RA, RA
BA = 01: RA + 1, RA, RA + 1, RA
BA = 10: RA + RS, RA + RS, RA, RA
BA = 11: RA + RS + 1, RA + RS, RA + 1, RA
Therefore, the row address calculation unit 97 in FIG. 71 generates the row address shown in the logical value table 820 in each of the banks Bank0-3 according to the supplied bank address BA and row address RA.

  FIG. 83 is a diagram illustrating Example 1 of the row address calculation unit in the present embodiment. The row address calculation unit 97 selects one of the address adders 831 to 834 for adding 0, 1, RS, and RS + 1 to the supplied row address RA, and the output of these address adders. And a row address control circuit 830 for supplying a selection signal 835 to the selector SEL. The row address control circuit 830 generates a selection signal (2 bits each, 8 bits in total) shown in the logical value table 821 of FIG. 82 according to the supplied bank address BA. Further, the step number data RS and RS + 1 of the row address are supplied from the mode register 96 to the address adders 833 and 834, respectively, and the fixed values “0” and “1” are supplied to the address adders 831 and 832, respectively. . Therefore, the adder 831 outputs the supply row address RA as it is.

  For example, when the supply bank address BA = 01, the row address control circuit 832 generates “01, 00, 01, 00” as the selection signal 835, and accordingly, each selector SEL sequentially receives RA + 1 from the top. , RA, RA + 1, RA are selected and supplied to the address decoder 836 of each bank. In each bank, in response to the bank activation signal actpz <3: 0>, the address decoder 836 of the selected bank is activated, and the activated address decoder becomes the row address RA + 1, RA, RA + 1. , RA are decoded, and the corresponding word line is activated.

  FIG. 84 is a diagram illustrating Example 2 of the row address calculation unit in the present embodiment. In this example, the row address calculation unit 97 selects four address adders 841 to 844 that add the constants 0, 1, RS, and RS + 1 selected by the selector SEL to the supplied row address RA, and the selector SEL. And a row address control circuit 830 for supplying a signal 835. The row address control circuit 830 is the same as FIG. Then, according to the selection signal of the row address control circuit 830, each selector SEL selects one of the four constants 0, 1, RS, and RS + 1 and outputs it to the address adder. That is, the row address calculator 97 selects the constants 0, 1, RS, and RS + 1 to be added to the supplied row address RA with the selector, and gives the selected constant to the address adder. The row address calculator 97 in FIG. 83 selects the outputs of the four address adders with a selector, but the row address calculator 97 in FIG. 84 selects four constants with the selector. The only difference is in this respect.

  As described above, the row address calculator 97 generates necessary four row addresses from the supplied row address RA. Therefore, if a memory device inputs a row address with one active command, it can generate four necessary row addresses internally, and can activate a plurality of banks.

[Memory mapping settings]
In order to realize the multi-bank activation function, it is necessary to set memory mapping information in the memory device. For example, as described with reference to FIG. 82, banks to be activated are selected in the four types of rectangular access areas RC0-3 based on the memory mapping 12, and row addresses to be generated are calculated. Therefore, if the memory mapping in the higher system is different, the memory device is required to change the determination process of the page area to be activated accordingly.

  FIG. 85 is a diagram showing two memory mapping examples. The memory mapping 12A is the same as the memory mapping described above, with the banks Bank0, 1 being arranged in the odd rows, the banks Bank2, 3 being arranged in the even rows, and the row address RA being arranged as shown. In the memory mapping 12B, even-numbered banks Bank0, 2 are arranged in odd rows, odd-numbered banks Bank1, 3 are arranged in even rows, and the row address RA is the same as 12A.

  FIG. 86 is a diagram showing a bank address switching circuit 861 for the above two types of memory mapping. In the configuration diagram of FIG. 86B, an input buffer 94 is provided for each of the clock terminal CLK, the special input terminal SP0, and the bank address terminals BA0 and BA1, and the respective signals are latched in synchronization with the clock CLK. A latch circuit 860 is provided.

  As shown in the timing chart of FIG. 86 (A), the setting data V from the bank address terminal BA, the memory mapping information AR from the special terminal SP0, and the number of steps from the address terminal ADD to the row address together with the extended mode register set command EMRS. Each data RS is input. The setting data V, the memory mapping information AR, and the step number data RS are set in the mode register 96.

  In accordance with the memory mapping information AR set in the mode register 96, the selector SEL in the bank address switching circuit 861 selects one of the 2-bit bank addresses BA0 and BA1, and generates internal bank addresses ba0z and ba1z. To do. As shown in the figure, when the memory mapping information AR = L, the internal bank address is set to ba0z = BA0 and ba1z = BA1, and when the memory mapping information AR = H, the internal bank address is set to ba0z = BA1. , Ba1z = BA0.

  Thus, by switching the bank addresses BA0 and BA1 based on the memory mapping information AR at the input unit, the bank selection function and the row address generation function inside the memory device can be configured based on the common memory mapping 12A. it can.

  In the above embodiment, multi-bank information (SA ′), simultaneous activation bank data (SA′0-2), rectangular area size data (W, H), and the like are input from the special input terminal SP. However, this can be realized with terminals that are not used. For example, in the read operation, if the row address is input at the address terminals Add0 to 12 and the column address is input at the address terminals Add0 to 9, the address terminals Add10 to 12 are not used when the column address is input. . Therefore, the control data SA ', W, H, etc. can be input from the address terminals Add10 to 12 which are not used when the column address is input. In this case, the present invention can be applied.

  Further, the various information set in the mode register by the extended mode register set command EMRS is not limited to the above embodiment, but is also applied from the address terminal.

《Multi-bank access and byte boundary》
It has been described that the memory device has a byte boundary function in response to a rectangular access exceeding the memory unit area selected by the bank address and the column address. It has also been described that the memory device has a multi-bank access function corresponding to the case of rectangular access exceeding the page area selected by the bank address and row address. Therefore, when the rectangular access area exceeds the page area and exceeds the memory unit area, both functions can be accessed with one active command and useless data output can be eliminated. This will be specifically described below.

  FIG. 87 is a diagram showing a timing chart when a multi-bank access and a byte boundary occur. As shown in the figure, the rectangular access area 22 extends over a plurality of banks BA3, BA2, BA1, and BA0 beyond the page area, and column access is required beyond the memory unit area. In this example, the multi-bank information SA ′ = 4 (= 11) and the start byte signal SB = 2.

  FIG. 88 is a configuration diagram of a memory device having a multi-bank access function and a byte boundary function. In this memory device 86, only two banks Bank2 and 3 are shown for simplicity, but in addition to this, two banks Bank0 and 1 (not shown) are provided. In the mode register 96, row number step number data RS and column address step number data CST in memory mapping are preset.

  The row control unit includes a multi-bank activation control unit 88 that generates a bank activation signal actpz <3: 0> to a bank to be activated from the bank address BA and the multi-bank information SA ′, and a bank address BA and a row. Row address calculation units 97-2 and 97-3 for calculating the row address of each bank from the address RA and the step number data RS of the row address are provided. The row address calculation units 97-2 and 97-3 are a part of the configuration described with reference to FIGS. As described with reference to FIG. 78, the bank activation signal actpz is supplied to the core control unit in each bank. However, the core control unit is omitted in FIG.

  The column controller 90 generates internal column addresses I-CA-2 and 3 for each bank from the supplied column address CA and bank address BA, start byte signal SB and column address step number data CST. Column address controllers 290-2 and 290-3 are provided. This column address controller 290 is equivalent to the column address generator shown in FIG. 44, and by adding a bank address BA to this, it is possible to generate a column address necessary for byte boundary across the bank boundary. To do. The step number data CST is the same as the column address return data CAWrap of FIG.

  Further, the column controller 90 generates a control signal S221 for selecting data of the byte areas Byte0-3 in each bank based on the supplied bank address BA, column address CA, and start byte signal SB. By this control signal S221, the data latch circuits in the four byte areas Byte0-3 of each bank are selected and connected to the input / output bus I / Obus. The configuration and operation of the byte areas Byte0-3 in each bank are the same as those described with reference to FIGS. Since there are four byte areas in each bank, the control signal S221 is a selection signal of 4 × 4 = 16 bits.

  Next, the operation when the rectangular area 22 in FIG. 87 is accessed will be described. As shown in the timing chart of FIG. 87, column mode step number data CST = 4 (871 in the figure) and row address step number data RS = 4 (872 in the figure) are input together with the extended mode register set command EMRS. And set in the mode register 96.

  Next, together with the active command ACT (876 in the figure), the bank address BA and row address RA of the page area including the upper left pixel of the rectangular access area, and multi-bank information SA ′ = 4 (873 in the figure) are input. . In SA '= 4, 2 × 2 = 4 banks are requested to be activated simultaneously. In response to this, the multi-bank activation control unit 88 outputs bank activation signals actpz <3: 0> to the four banks. In addition, the row address calculation units 97-2 and 97 calculate the row address of each bank. The row decoders in the four banks decode the calculated row address, drive the corresponding word line, and activate the bank.

  Simultaneously with the read command RD (877 in the figure), the bank address BA = 3, the column address CA = 126, the start byte signal SB = 2 (874 in the figure), and the second information BMR = UP (byte figure). Middle 875). The column address controller 290-3 of the bank Bank3 corresponding to the bank address BA generates a column address CA = 127 based on the supplied column address CA = 126 and the start byte signal SB = 2, and the internal column address I− Output as CA-3. As a result, the bank Bank3 outputs the data at the column addresses 126 and 127 to the byte areas Byte0-3. In response to the control signal S221 from the data latch selector 221, the byte areas Byte2 and 3 receive the data at the column address CA = 126, the byte areas Byte0 and 1 receive the data at the column address CA = 127 and the input / output bus I / Obus. Output to.

  Next, the bank address BA = 3, the column address CA = 127, SB = 2, and BMR = UP are input together with the read command RD. In response to this, the column address controller 290-3 generates an internal column address I-CA-3 = 127, and the bank Bank3 outputs 4-byte data of the column address 127. On the other hand, the column address controller 290-2 detects the necessity of reading data from the bank Bank2 from the bank address BA = 3, the column address CA = 127, and the start byte signal SB = 2, and determines the step number data CST of the column address. Referring to column bank CA2, column address CA = 124 is output as internal column address I-CA-2. As a result, the bank Bank2 reads 4-byte data at the column address CA = 124. Then, the data latch selector 221 generates the control signal S221 based on the bank address BA = 3, the column address CA = 127, and the start byte signal SB = 2, and the data of the byte areas Byte2 and 3 from the bank Bank3. The data in the byte areas Byte 0 and 1 are output from the bank Bank 2 to the input / output bus I / Obus.

  Hereinafter, along with the read command RD, the column address CA = 2, 3, 6, 7,. . . Similarly, the column address controller 290 generates the necessary column address, the data latch selector 221 generates the necessary control signal S221, and the 4-byte data from the position corresponding to the start byte signal SB = 2 is Output from within the same bank or from within an adjacent bank.

  The operation of the read command has been described above, but the same column access control is performed for the write command.

  According to this embodiment, an arbitrary byte (or bit) in the memory unit area is also obtained based on the start byte signal SB and the byte combination information BMR even for a rectangular access extending over a plurality of banks beyond the page area. Can access 4-byte data (or 4-bit data).

[Memory controller supporting multi-bank access]
Next, a memory controller that controls a memory device having a multi-bank access function will be described. As described with reference to FIGS. 69 and 70, the memory controller sets the row address step number data RS and the memory mapping information AR in the mode register in the memory device in advance, and makes a rectangular access request from the memory access source. In response, the bank address BA, row address RA, and multi-bank information SA ′ are issued to the memory device together with the active command ACT, and the bank address BA and column address CA are issued together with the read command RD or the write command WR. Therefore, the memory controller needs to generate the above address and data necessary for the multi-bank access function in response to the memory access request. The configuration and operation of this memory controller will be described.

  FIG. 89 is a diagram illustrating an example of memory mapping. The memory mapping 12 corresponds to a frame image. In the memory mapping 12, as described above, bank addresses BA0, 1 are assigned to odd rows of the page area 14 arranged in a matrix, bank addresses BA2, 3 are assigned to even rows, and row addresses RA are sequentially assigned to each row. Incremented, the step number RS of the row address is RS = 4. The page area 14 is composed of 16 pixels × 32 rows, and a memory unit area consisting of 4-pixel data (4-byte data) is specified by one column address. Therefore, one page area 14 has 512/4 = 128 column address areas (memory unit areas).

  In this memory mapping 12, an 8-page area is arranged in the horizontal direction and a 4-page area is arranged in the vertical direction. Therefore, in the memory mapping 12, the number of pixels in the horizontal direction is 128 (= 16 pixels × 8 page region), and the number of pixels in the vertical direction is also 128 (= 32 rows × 4 page region). Hereinafter, various operations will be described on the premise of this memory mapping.

  FIG. 90 is a configuration diagram of the memory controller in the present embodiment. Similarly to FIG. 54, the memory controller 82 receives a memory access request from the plurality of access source blocks 81-1 to 81-n, and accesses the memory device 86 in response to the memory access request permitted by the arbitration circuit 540. Take control. That is, the memory controller 82 includes interfaces IF_1 to n corresponding to the access source blocks 81-1 to 81-n, and further includes sequencers SEQ_1 to n that generate addresses and commands in response to access requests.

  Therefore, the interfaces IF_1 to n exchange data with the access request source block 81. There are two types of access from the access source block: horizontal access and rectangular access. The arbitration circuit 540 arbitrates an access request from the interface and outputs an access instruction to the sequencer SEQ_n that has acquired the access right. The selector SEL selects a command and address from one of the sequencers SEQ_1 to n in response to the selection signal S540 from the arbitration circuit 540, and outputs it to the memory device 86. In addition, the selector SEL selects the data line Data of any of the interfaces IF_1 to n in response to the selection signal S540.

  Various parameters are set in the register 543 from the host CPU. The parameters include functional data such as whether or not the memory device 86 has a byte boundary function and a multi-bank access function. In addition, the setting parameters include the row address ROW_BASE_ADR of the upper left pixel of the frame image, the number of pixels PICTURE_MAX_XSIZE in the horizontal direction of the frame image, and the like.

  The memory device 86 is an image memory having the above-described byte boundary function and multi-bank access function. The memory controller 82 and the memory device 86 in FIG. 90 constitute an image processing system.

  FIG. 91 is a diagram showing signals between the access source block and the interface. FIG. 91A shows a signal during rectangular access, and FIG. 91B shows a signal during horizontal access. The access source block 81-n outputs data in the access target area together with the access request signal REQ. Signal transmission and reception during both accesses will be described in detail later.

  FIG. 92 is a diagram for explaining data in the access target area. The frame image FM-IMG data is stored in the logical address space S86 of the memory device. As described above, the row address ROW_BASE_ADR of the upper left pixel of the frame image FM-IMG and the number of pixels PICTURE_MAX_XSIZE in the horizontal direction of the frame image are set in the register 543. When the rectangular area RIMG in this frame image is the access target area, the pixel coordinates (X_POS, Y_POS) in the upper left frame and the horizontal size X_SIZE and vertical size Y_SIZE of the rectangular area are the access source block 81. -N to the interface IF_n in the memory controller.

  The frame image FM-IMG matches the memory mapping 12 in FIG. That is, the upper left pixel of the frame image FM-IMG corresponds to the upper left pixel in the page area of the bank address BA = 0 and the local row address RA = 0. Therefore, the row address in the logical address space of the memory can be obtained from the row address ROW_BASE_ADR of the upper left pixel of the frame image FM-IMG and the local row address RA in the frame.

  FIG. 93 is a timing chart of signals between the access source block and the interface. In the rectangular access (when reading) in FIG. 93A, the access source block 81-n sets the read / write instruction signal RXW to the H level (read) and asserts the access request REQ, while accessing the access target area data X / Y_POS, X / Y_SIZE is output. In response to this, the memory controller returns an acknowledge ACK, performs access control to the memory device through a predetermined arbitration process, and acquires read data. The interface IF_n of the memory controller outputs the read data RDATA (Data (A0-A7)) while asserting the enable signal EN. The enable signal EN is asserted one clock cycle before and negated one clock cycle before.

  On the other hand, in the rectangular access (during writing) in FIG. 93B, the access source block 81-n sets the read / write instruction signal RXW to L level (write) and asserts the access request REQ, while accessing the access target area data. X / Y_POS and X / Y_SIZE are output. In response to this, the memory controller returns an acknowledge ACK, controls access to the memory device through a predetermined arbitration process, and receives the write data WDATA (Data (A0-A7)) while asserting the enable signal EN. . This enable signal EN is also asserted one clock cycle before and negated one clock cycle before.

  The same applies to horizontal access. The access source block supplies the horizontal access start address ADR and horizontal access size SIZE, receives read data RDATA if read, and outputs write data RDATA if write. To do. That is, as shown in FIG. 91, the access source block supplies the horizontal access head address ADR, the horizontal access size SIZE, and the read / write instruction signal RXW while asserting the access request REQ. In response, the interface returns an acknowledge signal ACK. Then, the memory controller executes memory access and outputs read data RDATA while asserting an enable signal. At the time of writing, the memory controller receives the write data WDATA while asserting the enable signal EN before accessing the memory.

  FIG. 94 is a diagram showing an outline of the operation of the memory controller. Each operation step is executed in the order of numbers 1 to 4. First, when the access request source block 81-n issues an access request REQ, the interface IF_n transfers the access request to the arbitration circuit 540 in response to the access request REQ. Next, the arbitration circuit 540 returns an acknowledge signal ACK to the interface IF_n and sends a command issuance start instruction START to the sequencer SEQ_n if the memory device 86 is accessible and the access request source has the highest priority. Output. In response to this command issuance start instruction START, the sequencer SEQ_n receives various parameters X / Y_POS and X / Y_SIZE required for command issuance from the interface IF_n.

  The sequencer SEQ_n issues a command based on the above parameters and the parameters set in the register, and starts accessing the memory device 86. The sequencer SEQ_n issues an enable signal EN corresponding to the amount of data according to the command issue status, and the enable signal EN is transmitted to the access request source 81_n via the interface IF_n. In the case of reading, the read data from the memory device 86 is transmitted to the access request source 81_n via the interface IF_n in response to the enable signal EN. In the case of writing, write data from the access request source 81_n is transferred to the memory device 86 via the interface IF_n in response to the enable signal EN.

  In this way, during access control by issuing a command to the memory device 86, the sequencer SEQ_n asserts an active signal ACTIVE indicating to the arbitration circuit 540 that data is being accessed. When the access to the memory is completed, the active signal ACTIVE is negated.

  FIG. 95 is a block diagram of the sequencer SEQ. The sequencer SEQ includes a control unit 940 that performs overall control inside the sequencer, access target area data X / Y_POS and X / Y_SIZE transferred from the interface IF_n, and an upper left pixel of the frame image FM-IMG set in the register 543 An intermediate parameter generation unit 941 that generates an intermediate parameter from the row address ROW_BASE_ADR of the frame and the number of pixels PICTURE_MAX_XSIZE in the horizontal direction of the frame image; Part 942.

FIG. 96 is a diagram for explaining an arithmetic expression for generating an intermediate parameter. In this example, as shown in FIG. 96A, the rectangular area RIMG in the frame image FM-IMG is accessed, and each data is as follows.
PICTURE_MAX_XSIZE = 128
ROW_BASE_ADR = 0
(X_POS, Y_POS) = (28,94)
(X_SIZE, Y_SIZE) = (8,4)
FIG. 96B shows the horizontal pixel numbers and vertical pixel numbers (row numbers) in the four page areas BA1 / RA4, BA0 / RA5, BA3 / RA4, BA2 / RA5 in the vicinity of the rectangular area RIMG. Is shown. These pieces of information are generated as intermediate parameters as follows.

  The intermediate parameter generation unit 941 generates intermediate parameters by the following calculation.

(1) The upper left bank address BA when the rectangular data RIMG spans four page areas is obtained as follows. First, as shown below, the pixel coordinates (X_POS, Y_POS) in the upper left of the rectangular data RIMG in the frame image FM-IMG are respectively divided by the horizontal pixel number 16 and the vertical pixel number 32 in the page area, The bank X address BA_X_ADR and the bank Y address BA_Y_ADR are obtained. The above division rounds down the remainder.
BA_X_ADR = X_POS / 16
BA_Y_ADR = Y_POS / 32
The bank X address BA_X_ADR and the bank Y address BA_Y_ADR correspond to the horizontal page number area in the memory mapping 12 and the vertical page number area in the memory mapping 12. However, the upper left of the memory mapping 12 is the 0th page area in the horizontal direction and the 0th page area in the vertical direction.

Then, depending on whether the obtained bank X address BA_X_ADR and bank Y address BA_Y_ADR are odd or even, the bank address BA [1: 0] is obtained as follows.
If BA_X_ADR is even and BA_Y_ADR is even, upper left BA = 0
If BA_X_ADR is odd and BA_Y_ADR is even, upper left BA = 1
If BA_X_ADR is even and BA_Y_ADR is odd, upper left BA = 2
If BA_X_ADR is odd and BA_Y_ADR is odd, upper left BA = 3
(2) The right bank address BA, the lower bank address BA, and the lower right bank address BA are obtained as follows. That is, according to the memory mapping 12, from the upper left BA [1: 0] obtained in the above (1), the right BA, the lower BA, and the lower right BA are as follows. “~” Means inversion.
Right BA = [Upper left BA [1], ~ Upper left BA [0]]
Lower BA = [~ Upper left BA [1], Upper left BA [0]]
Lower right BA = [~ Upper left BA [1], ~ Upper left BA [0]]
According to the example of FIG. 96, (X_POS, Y_POS) = (28, 94).
For the upper left bank address BA:
BA_X_ADR = X_POS / 16 = 28/16 = 1
BA_Y_ADR = Y_POS / 32 = 94/32 = 2
Therefore, since BA_X_ADR = 1 is an odd number and BA_Y_ADR = 2 is an even number, the upper left bank address BA [1: 0] = 01. That is, BA1 is obtained.
Furthermore, right BA, lower BA, and lower right BA are from upper left BA = 2'b01 to right BA = [upper left BA [1], ~ upper left BA [0]] = [00] = 0
Lower BA = [~ Upper left BA [1], Upper left BA [0]] = [11] = 3
Lower right BA = [~ Upper left BA [1], ~ Upper left BA [0]] = [10] = 2
And BA0, BA3, and BA2 are obtained.

(3) The access start row address ROW_ADR in the logical address space S86 of the memory is as follows.
ROW_ADR = ROW_BASE_ADR + [PICTURE_MAX_XSIZE / (16 * 2)] * [Y_POS / (32 * 2)] + X_POS / (16 * 2)
That is, ROW_BASE_ADR is the row address of the upper left pixel of the frame image, PICTURE_MAX_XSIZE / (16 * 2) is the number of row address steps in the horizontal direction in the frame, and Y_POS / (32 * 2) is the upper left pixel of the rectangular area RIMG. In the vertical direction (reference number 961 in FIG. 96), and X_POS / (16 * 2) indicates the number of horizontal pairs in the frame in the upper left pixel of the rectangular area RIMG (see FIG. 96).

According to the example in FIG. 96, PICTURE_MAX_XSIZE = 128, ROW_BASE_ADR = 0, (X_POS, Y_POS) = (28,94)
ROW_ADR = ROW_BASE_ADR + [PICTURE_MAX_XSIZE / (16 * 2)] * [Y_POS / (32 * 2)] + X_POS / (16 * 2)
= 0 + (128/32) * (94 / (32 * 2)) + 28 / (16 * 2)
= 4
It is.

(4) The access start column address COL_ADR in the logical address space S86 of the memory is a column address in the page and is as follows.
COL_ADR = 4 * Y_POS% 32 + (X_POS / 4)% 4
Here, “%” means the remainder. That is, as shown in FIG. 89, the number of column address steps in the page area is 4, the number of horizontal columns in the page area is 4, and the number of vertical rows is 32. This means the number of rows in the areas BA1 and RA4, and (X_POS / 4)% 4 means the number of columns in the page area.

According to the example of FIG.
COL_ADR = 4 * Y_POS% 32 + (X_POS / 4)% 4
= 4 * 94% 32 + (28/4)% 4 = 120 + 3
= 123
Is required.

(5) Next, since the in-bank X coordinate (BA_X_POS) and Y coordinate (BA_Y_POS) have 16 horizontal pixels in the page area and 32 vertical rows,
BA_X_POS = X_POS% 16
BA_Y_POS = Y_POS% 32
Is required. This corresponds to the coordinates (BA_X_POS, BA_Y_POS) of the upper left pixel of the rectangular area RIMG in the upper right bank (BA1 / RA4) shown in FIG.

(6) The X-direction BANK crossing flag and Y-direction BANK crossing flag indicating whether or not the rectangular area RIMG crosses the bank (page area) are the X and Y coordinates BA_X_POS and BA_Y_POS in the bank obtained in (5). From the horizontal and vertical sizes X / Y_SIZE of the region RIMG, it can be calculated as follows.
If BA_X_POS + X_SIZE> 15, X direction BANK crossing flag = 1
If BA_Y_POS + Y_SIZE> 31, the Y-direction BANK crossing flag = 1
That is, as shown in FIG. 96C, the value obtained by adding the size X / Y_SIZE of the rectangular area to the coordinates (BA_X_POS, BA_Y_POS) of the upper left pixel of the rectangular area RIMG is the horizontal size 15 and vertical size of the page area. If it exceeds 31, it means that the bank will be crossed.

The above (5) and (6) will be described with reference to the example of FIG.
The X and Y coordinates in the bank are
BA_X_POS = X_POS% 16 = 28% 16 = 12
BA_Y_POS = Y_POS% 32 = 94% 32 = 30
The X direction BANK crossing flag and the Y direction BANK crossing flag are
BA_X_POS + X_SIZE = 12 + 8 = 20 and above 15, so X direction BANK crossing flag = 1
BA_Y_POS + Y_SIZE = 30 + 4 = 34 and above 31, so Y direction BANK crossing flag = 1
Thus, both banks in the X and Y directions will be crossed.

(7) Next, the sizes of the rectangular areas in the four banks in the X and Y directions, 1ST_X_SIZE, 2ND_X_SIZE, 1ST_Y_SIZE, and 2ND_Y_SIZE are calculated as follows.
As shown in Fig. 96 (C), when straddling BANK in the X direction, X_SIZE at the left BANK is 1ST_X_SIZE, right is 2ND_X_SIZE, and when straddling BANK in the Y direction, Y_SIZE at the top BANK is 1ST_Y_SIZE, and the bottom is 2ND_Y_SIZE. If the bank is not crossed, only 1STX_SIZE and 1ST_Y_SIZE are valid.
Therefore,
When the X direction BANK crossing flag = 1,
1ST_X_SIZE = 16 − BA_X_POS
2ND_X_SIZE = X_SIZE − 1ST_X_SIZE
If the X direction BANK crossing flag is 0,
1ST_X_SIZE = X_SIZE
If the Y-direction bank crossing flag = 1,
1ST_Y_SIZE = 32 − BA_Y_POS
2ND_Y_SIZE = Y_SIZE − 1ST_Y_SIZE
If the Y-direction bank crossing flag is 0,
1ST_Y_SIZE = Y_SIZE
It becomes.

When the example of FIG. 96 is applied,
Since the X direction BANK crossing flag = 1
1ST_X_SIZE = 16 − BA_X_POS = 16 −12 = 4
2ND_X_SIZE = X_SIZE − 1ST_X_SIZE = 8 −4 = 4
Y direction BANK crossing flag = 1
1ST_Y_SIZE = 32 − BA_Y_POS = 32 −30 = 2
2ND_Y_SIZE = Y_SIZE − 1ST_Y_SIZE = 4 − 2 = 2
Is required.

(8) Finally, the row address step information RS is a number indicating how many row addresses increase when scanning from the left end to the right end in the X direction in the frame image 12 (FM-IMG). It is obtained by the following calculation.
RS = PICTURE_MAX_XSIZE / (16 * 2)
In the example of FIG. 96, RS = PICTURE_MAX_XSIZE / (16 * 2) = 128/32 = 4 is obtained.

  As described above, the intermediate parameter generation unit 94 obtains the intermediate parameters (1) to (8) by the above arithmetic expressions and outputs them to the command / address generation unit 942. Then, the command / address generation unit 942 generates a command to be supplied to the memory 86, a bank address BA, a row address RA, a column address CA, row address step information RS, and multibank information SA ′ based on the intermediate parameters.

  FIG. 97 is an operation flowchart in the command / address generation unit. In the figure, the generated command is indicated by an ellipse. First, the memory controller issues a normal mode register set command MRS and performs various initial settings on the mode register in the memory device (S40). This initial setting is a setting performed in a normal SDRAM. And it will be in a standby state (S41). Eventually, when an access request is received from the access source block 81, the intermediate parameter generation unit 941 receives the access target area data X / Y_POS and X / Y_SIZE received from the access source block and the frame image set in the register 543. The above-mentioned intermediate parameter is generated from the row address ROW_BASE_ADR of the upper left pixel and the number of pixels in the horizontal direction PICTURE_MAX_XSIZE (S42).

  Whether or not the memory device to be controlled has a multi-bank access function is set in the register 543, and is checked (S43). If the multi-bank access function is not set, the active command ACT and the read command RD (or write command) are repeatedly issued by the number of banks by a normal control operation (S44).

When the multi-bank access function is set, the command / address generation unit 942 determines the number of banks based on the bank crossing flag Flag [X: Y] (S46). As a result, the command / address generator 942 generates the multi-bank information SA ′ [1: 0] from the bank crossing flag Flag [X: Y]. The relationship between the two is as follows.
Flag [X: Y] = 00 SA ′ [1: 0] = 00 (activate one bank)
Flag [X: Y] = 10 SA ′ [1: 0] = 01 (2 banks are active in the X direction)
Flag [X: Y] = 01 SA ′ [1: 0] = 10 (2 banks are active in the Y direction)
Flag [X: Y] = 11 SA ′ [1: 0] = 11 (4 banks are active)
Therefore, the command / address generation unit 942 issues the active command ACT, the first bank address BA, the first row address RA, and the multi-bank information SA ′ (S80, S70, S60, S50).

  When simultaneously activating four banks, the command / address generation unit 942 in the memory controller issues multi-bank information SA ′ = 11 together with the active command ACT and the row address RA (S50). Then, the command / address generator 942 issues a read command or a write command together with the column address CA in the upper left bank (S51). This read or write command is repeatedly issued while incrementing the column address for 1ST_X_SIZE = N times which is the access size in the X direction in the upper left bank. Further, a read command or a write command is issued together with the column address CA in the right bank (S52). This read or write command is repeatedly issued while incrementing the column address over 2ND_X_SIZE = N times which is the access size in the X direction in the right bank. Then, the line number line is incremented by +1 (S53), and steps S51, S52, and S53 are repeated until the line number line exceeds 1ST_Y_SIZE, which is the access size in the Y direction in the upper left bank (S54).

  Next, the command / address generator 942 issues a read command or a write command together with the column address CA in the lower bank (S55). This read or write command is repeatedly issued while incrementing the column address over 1ST_X_SIZE = N times which is the access size in the X direction in the lower bank. Further, a read command or a write command is issued together with the column address CA in the lower right bank (S56). This read or write command is repeatedly issued while incrementing the column address over 2ND_X_SIZE = N times which is the access size in the X direction in the right bank. Then, the line number line is incremented by +1 (S57), and steps S55, S56 and S58 are repeated until the line number line exceeds 2ND_Y_SIZE which is the access size in the Y direction in the lower bank (S58).

  The command / address generation unit 942 obtains a column address to be issued together with the read or write command from the top column address COL_ADR = 123 and the column address step number data CST = 4 based on the memory map.

  When simultaneously activating two banks in the X direction, the command / address generator 942 in the memory controller issues multi-bank information SA ′ = 01 together with the active command ACT and the row address RA (S60). Then, a read or write command and column address for the upper left bank are issued N times (S61), and a read or write command and column address for the right bank are issued N times (S62). These steps S61, S62, S63 are repeated until the number of lines exceeds 1ST_Y_SIZE (S64).

  When simultaneously activating two banks in the Y direction, the command / address generator 942 in the memory controller issues multi-bank information SA ′ = 10 together with the active command ACT and the row address RA (S70). Then, a read or write command to the upper left bank and a column address are issued N times (S71), and these steps S71 and S72 are repeated until the number of lines exceeds 1ST_Y_SIZE (S73). Similarly, a read or write command to the lower bank and a column address are issued in the same manner (S74, S75, S76).

  Finally, when only one bank is activated, the command / address generation unit 942 in the memory controller issues multi-bank information SA ′ = 00 together with the active command ACT and the row address RA (S80). Then, a read or write command to the upper left bank and a column address are issued N times (S81), and these steps S81 and S82 are repeated until the number of lines exceeds 1ST_Y_SIZE (S83).

  As described above, when the memory controller 82 receives the access target area data X / Y_POS, X / Y_SIZE together with the access request REQ from the access source block, the row address ROW_BASE_ADR of the frame area in the register 543 and the number of horizontal pixels PICTURE_MAX_XSIZE Then, an intermediate parameter is generated, the number of banks to be activated at the same time is determined, and multi-bank information SA ′ corresponding to the determination result is issued to simultaneously activate the banks in the memory device. Thus, a plurality of banks can be activated by issuing an active command once, and memory access can be performed efficiently.

  FIG. 98 is a timing chart between the memory controller and the memory device. This is a timing chart when accessing the rectangular area RIMG across the four banks of FIG. First, the memory controller issues row address step information RS4 together with the extended mode register set command EMRS, and sets the row address step information RS in the register in the memory device. Next, the memory controller issues an upper left bank address BA1, a head row address RA4, and multibank information SA '(1, 1) together with the active command ACT. In response to this, four banks are simultaneously activated in the memory device.

  In the example of FIG. 98, the multi-bank information SA ′ is input from the column address terminal CA. However, when the memory device adopts an address multiplex configuration in which the row address RA and the column address CA are input from a common address terminal, as shown in FIG. 72, the multibank information SA ′ is stored in the special terminal SP. It is necessary to input from.

  Further, the memory controller repeatedly issues a bank address BA and a column address CA together with the read command RD. As shown in FIG. 96B, the bank address BA and the column address CA are (BA, CA) = (1,123), (0,120), (1,127), (0,124), ( 3,3), (2,0), (3,7), (2,4). Correspondingly, 4-byte data of pixel coordinates (X_POS, Y_POS) shown in FIG. 98 is output from the 4-byte input / output terminals BY0-3 of the memory, and the memory controller receives them. Thus, the active command ACT is issued only once.

  When the memory controller uses the multi-bank access function to activate multiple banks with a single active command, it uses the byte boundary function to access image data from the middle of the 4-byte area. 87, start byte information SB and memory map information BMR are issued in addition to the bank address BA and column address CA together with the read or write command. As a result, the memory controller can reduce the number of times of issuing read or write commands, and can receive or output valid data to all the data buses in one access.

  In the above embodiment, the image memory that stores digital image data in which image data of a plurality of pixels is two-dimensionally arranged has been described as an example. However, the present invention is not limited to an image memory that stores image data, and can be applied to a memory device that stores two-dimensionally arranged data other than image data based on a predetermined mapping rule. If the stored data is two-dimensionally arranged data, it may be required to access data in a plurality of page areas when accessing an arbitrary rectangular area in the two-dimensionally arranged data. In this case, the present invention can be applied.

《Background Refresh》
In FIG. 6, the outline of the background refresh has been described. That is, when the memory controller causes the memory device to continuously perform an access operation to a specific bank such as horizontal access over a predetermined period, the memory controller issues a background refresh command specifying a bank that is not accessed, The memory device is caused to execute a refresh operation in the designated bank. Then, the memory controller issues a normal operation command during the refresh operation, thereby causing the memory device to execute a normal access operation in a bank that is not performing the refresh operation.

  FIG. 99 is a schematic explanatory diagram of background refresh in the present embodiment. FIG. 99A shows the background refresh operation, and FIG. 99B shows the structure of the memory device. The memory device 86 has a first area 991 and a second area 992 in the memory cell area 990. The first and second regions 991 and 992 correspond to bank regions, and can perform an active operation, a read operation, a write operation, and a precharge operation, respectively. Further, the memory device 86 includes an input circuit 995 that inputs operation codes 993 and 994 from the memory controller 82, and one of the first and second regions 991 and 992 in the memory cell region in response to the operation code. A control circuit 996 is provided for causing one to perform a refresh operation and the other to perform a normal memory operation. The operation code is, for example, a command issued by the memory controller. Alternatively, it is a combination of a command and a signal value of a specific input terminal.

  As shown in FIG. 99A, in response to the first operation code 993, the control circuit 996 starts a refresh operation 997 in the first area 991 in the memory. The first operation code 993 corresponds to the background refresh command BREN in FIG. A refresh target area (first area) is set in synchronization with or before the first operation code 993, and the number of refreshes to be executed in response to one background refresh command (refresh (Burst length) and the number of memory blocks to be simultaneously refreshed in one refresh cycle (the number of refresh blocks) are also set. In response to these settings, the control circuit 996 causes the refresh target area (first area) to execute the refresh operation 997.

  The background refresh is performed only on a part of the memory device (first region). Therefore, normal memory operations can be performed in parallel in areas other than the refresh target area. Therefore, in response to the second operation code from the memory controller, the control circuit 996 executes the normal memory operation 998 corresponding to the second operation code 994 in the selected second area 992. The second operation code 994 is, for example, an active command or a read / write command. That is, the control circuit 996 causes the second area 992 to execute the normal memory operation 998 in response to the second operation code 994 even before the refresh operation 997 in the first area 991 is completed. Conversely, the control circuit 996 causes the first region 991 to execute the refresh operation 997 in response to the first operation code 993 even before the normal memory operation 998 in the second region 992 is completed.

  As described above, in the background refresh according to the present embodiment, the refresh operation in the first area and the normal memory operation in the second area can be executed without completing the mutual operation. As a result, by executing the refresh operation in all the areas in the memory device, the normal memory operation is interrupted during the refresh period, and the effective access efficiency is suppressed from decreasing.

  FIG. 100 is a schematic explanatory diagram of a memory system that performs background refresh in the present embodiment. The memory system 1000 includes a memory controller 82 and a memory device 86. The memory device 86 is the same as that shown in FIG. 99, and the memory controller 82 includes a refresh control circuit 1001, a multiplexer MUX, and an output circuit 1004. The refresh control circuit 1001 is provided with first and second area control circuits 1002 and 1003 for performing refresh control of the first and second areas 991 and 992 of the memory, respectively. In other words, in the background refresh function, the memory device performs a normal memory operation on one of the first and second regions 991 and 992 while performing the refresh operation on the other. For this purpose, it is required to individually perform refresh control on the first and second areas 991, 992.

  In the memory refresh standard, the period during which all memory areas are to be refreshed and how many refresh operations are performed are defined. For example, it is defined as “64 ms / 4096 cycles” in a 64-Mbit memory. In this case, in order to refresh all 64 Mbit cells in 64 ms, the refresh operation is repeated once every 15.6 μs (= 64 ms ÷ 4096), and 16 Kbit (= 64M ÷ 4096) refresh.

  On the other hand, as shown in FIG. 100, when the memory cell area 990 is composed of the first and second areas 991, 992, all of the 32 Mbit cells in both areas are refreshed 2048 times in 64 ms. It will be necessary. Therefore, in order to perform the refresh operation while switching the first and second regions at random, the control circuits 1002 and 1003 for separately controlling the refresh of the first and second regions are necessary.

  FIG. 101 is an operation flowchart of the memory controller that controls the background refresh. In the image processing system, the image processing apparatus outputs a memory operation request to the memory controller, and a memory operation event corresponding to the memory operation request occurs in the memory controller. Furthermore, a refresh process event also occurs in the memory controller. Therefore, it is necessary to arbitrate between the memory operation event and the refresh processing event. In the above example, during horizontal access, if both events do not occur in the same area (bank), the command for the other event can be issued even if processing for one event is not complete .

  For example, when a refresh event occurs, the memory controller generates a first operation code and first area information (1010), and even if the operation of the second area is not completed (NO in 1011), If the first area is different from the second area (No in 1012), the first operation code is issued (1013). If the first area to be refreshed is the same as the active second area (Yes in 1012), the process waits until the operation of the second area is completed (Yes in 1011).

  Similarly, when a memory operation event occurs, the memory controller generates a second operation code and second area information (1014), and even if the operation of the first area is not completed as described above. (No in 1015) If the second area is different from the first area (No in 1016), the second operation code is issued (1017). If the second area subject to the memory operation event is the same as the first area in operation (Yes in 1016), the process waits until the operation of the first area is completed (Yes in 1015).

  FIG. 102 is a diagram showing a relationship between background refresh and horizontal access in the present embodiment. In the memory map 12, the background refresh is executed in the banks BA2 and BA3 while the horizontal access 1020 to the banks BA0 and BA1 is being executed. Similarly, the background refresh is executed in the banks BA0 and BA1 while the horizontal access 1021 to the banks BA2 and BA3 is being executed. The same applies to the horizontal accesses 1022 and 1023. As described above, when horizontal access is started continuously, a bank in which no access is generated for a certain period is determined in advance, so that a refresh operation can be performed on the bank without the access. By controlling in this way, refresh operation commands for all banks are issued during horizontal access, and horizontal access is not interrupted. Therefore, when accessing two-dimensionally arranged data such as image data by raster scanning from the upper left to the lower right, a dead cycle due to the refresh operation is eliminated and high-speed raster scanning can be performed.

  FIG. 103 is a diagram showing the relationship between background refresh, horizontal access, and rectangular access in the present embodiment. This is an example in which a rectangular access 1024 occurs between the horizontal accesses 1020 and 1021 described above. An image processing system including an image memory, a memory controller, and an image processing apparatus requests both horizontal access and rectangular access to the image memory. In rectangular access, an arbitrary address in the memory is accessed every time image data is compressed or decompressed, so it is difficult to predict which bank will be accessed. On the other hand, in the horizontal access, only a specific bank is accessed for a certain period, and the remaining banks are not accessed.

  Therefore, in the horizontal access 1020, the refresh bank information SA (61 in the figure) indicating the bank to be refreshed is input together with the background refresh command BREN (60 in the figure). In this example, since the horizontal access 1020 occurs for the banks BA0 and BA1, the refresh target banks are BA2 and BA3. In response to the background refresh command BREN, the control circuit in the memory device commands a refresh operation to the refresh target banks BA2 and BA3. In this horizontal access 1020, the bank address BA = 0 and the row address RA = 0 are input together with the active command ACT, the page areas of BA0 and RA0 are activated, the bank address BA = 0, the column address CA =, together with the read command RD. 0 is input and data is read. Similarly, bank address BA = 1 and row address RA = 0 are input together with active command ACT, the page area of BA1 and RA0 is activated, and bank address BA = 1 and column address CA = 0 are input along with read command RD. And data is read out. In horizontal access, these operations are repeated for a fixed time. Meanwhile, the refresh operation is repeated in the banks BA2 and BA3.

  In the horizontal access 1021, the same operation as described above is performed. That is, BA0,1 is input as the refresh bank information SA (66 in the figure) together with the background refresh command BREN (65 in the figure), and the refresh operation is performed in the banks BA0,1. In parallel with this refresh operation, an active command and a read command are repeatedly input, and a horizontal access operation to the banks BA2 and BA3 is performed. During the rectangular access 1024, the background refresh operation is not performed.

  The background refresh command BREN corresponds to the first code. An active command ACT, a read command RD, or a write command WT (not shown) corresponds to the second code described above.

  FIG. 104 is a diagram for explaining the number of background refreshes and the number of blocks in the present embodiment. The background refresh is executed for a bank in which no access occurs when only a specific bank is accessed in a certain period in advance, such as during horizontal access. In this embodiment, in addition to the refresh bank information SA indicating the refresh target bank, a refresh burst length RBL indicating the number of refreshes executed in response to one background refresh command BREN, and one refresh operation. The number of blocks simultaneously refreshed, that is, the refresh block number RBC indicating the number of word lines, is supplied from the memory controller to the memory device.

  That is, in horizontal access, access to some banks is repeated for a certain period according to the size of the access target image. However, the horizontal access period is variable and the occurrence of horizontal access is also random. Therefore, it is required to perform the refresh operation for a desired number of addresses in the refresh target bank during the horizontal access period. For example, when a refresh operation is required for the address N during the horizontal access period T, assuming that the cycle time τ required for one refresh operation is T ÷ τ ≧ N, one block (1 The refresh operation may be executed N times for a single word line. However, if T ÷ τ ≧ N is not satisfied, it is necessary to effectively reduce N by simultaneously performing a refresh operation for a plurality of blocks (a plurality of word lines) in one refresh operation. The number of blocks that are simultaneously refreshed is the refresh block number RBC.

  Further, when the access target data size is larger than the predetermined size, the horizontal access period extends to a certain extent. In such a case, if the refresh operation is repeated a plurality of times for one background refresh command BREN, the number of commands issued can be reduced. In this case, the number of refreshes that can be executed in the horizontal access period T is T ÷ τ, which is the refresh burst length RBL. By specifying this refresh burst length RBL when horizontal access is started, the memory device has completed the refresh cycle at the end of the horizontal access period T. A normal memory operation cycle can be entered.

  Returning to FIG. 104, three combinations of the refresh burst length RBL and the refresh block number RBC are shown for the example in which the bank Bank0 is composed of 4 blocks Block-0 to 3. Each block Block has a word line WL, a bit line BL, and a sense amplifier group S / A connected to the bit line BL, and four blocks Block-0 to 0-3 each have a sense amplifier group S / A. And can be refreshed at the same time. Note that the refresh operation includes an active operation and a precharge operation. The normal operation includes an active operation, a read or write operation, and a precharge operation.

  FIG. 104A shows an example in which RBL = 2 and RBC = 1. In response to the background refresh command BREN, the refresh operation is continuously performed on the word lines WL0 and WL1 of the block Block-0, and in response to the next command BREN, the word lines WL0 and WL1 of the block Block-1 The refresh operation is performed continuously. In this case, since RBC = 1, the refresh operation is performed only in one block, and the current consumption associated with the refresh operation can be reduced.

  FIG. 104B shows an example in which RBL = 1 and RBC = 4. In response to the background refresh command BREN, the refresh operation is simultaneously performed on the word line WL0 of the four blocks Block-0 to 3. Although only one refresh cycle is executed, since refresh is performed simultaneously in four blocks, refresh for four addresses is completed. However, instantaneous current consumption is large.

  Finally, FIG. 104C shows an example in which RBL = 2 and RBC = 2. In response to the background refresh command BREN, the refresh operation is continuously performed on the word lines WL0 and WL1 of the two blocks Block-0 and 1. As a result, the number of row addresses to be refreshed is 4, but the refresh operation is simultaneously performed in two memory blocks, so that the instantaneous current consumption can be suppressed as compared with FIG.

  As described above, in the background refresh of the present embodiment, the refresh bank information SA indicating the refresh target bank, the refresh burst length RBL, and the refresh block number RBC are input together with the command BREN or the register set command EMRS. Thus, it is possible to flexibly cope with the occurrence and period of random horizontal access.

  By the way, the memory controller can cause the memory device to execute a plurality of background refresh operations by setting the refresh burst length RBL. However, once the refresh operation starts, the refresh operation for the refresh burst length RBL times cannot be changed. Inconvenient. Therefore, in the present embodiment, as will be described later, the refresh burst length RBL can be further increased by adding, reset to a new burst length RBL, or the refresh operation can be stopped. The addition function of the burst length RBL makes it possible to issue a background refresh command in advance in order to flexibly cope with random horizontal access. The burst length reset function can be used when a new horizontal access occurs. The refresh operation stop command is effective when the refresh burst length RBL once set is too long.

  Further, in the present embodiment, it is possible to use a refresh all command for executing a refresh operation for all remaining addresses. As a result, the refresh operation can be forcibly performed in a memory area in which valid data is not stored, and the refresh counter can be reset. This will also be described in detail later.

  FIG. 105 is an operation timing chart of background refresh in this embodiment. FIG. 105A shows an example in which a refresh operation is performed on the banks BA0, 1 during the horizontal access 1020 to the banks BA2, 3, and the refresh burst is simultaneously sent to the memory device simultaneously with the background refresh command BREN (60 in the figure). A length RBL and a refresh block number RBC are issued (1052 in the figure). Thereafter, the active command ACT and the read command RD corresponding to the horizontal access are repeated.

  On the other hand, in FIG. 105B, before the horizontal access 1020 is started, the refresh burst length RBL and the refresh block number RBC are issued together with the extended mode register set command EMRS (051 in the figure) by the register access 1050. (1053 in the figure). As a result, the memory device sets RBL and RBC in the internal mode register. Thereafter, in the horizontal access 1020, the refresh bank information SA is supplied simultaneously with the background refresh command BREN (1054 in the figure), and in response to this, the memory device performs a refresh operation corresponding to the registered RBL and RBC. . Thereafter, an active command ACT and a read command RD corresponding to horizontal access are repeatedly issued.

  As described above, the refresh burst length RBL and the refresh block number RBC may be set every time together with the command BREN, or may be set in the mode register in advance. If it is set in the mode register, it is not necessary to set it with the command BREN every time.

  FIG. 106 is a diagram for explaining the refresh burst length in the present embodiment. FIG. 106A is a timing chart when one refresh is performed in response to the auto-refresh command AREF. On the other hand, FIG. 106B corresponds to this embodiment, and is a timing chart when refreshing a plurality of times (RBL) is performed for one background refresh command BREN. In either case, refresh is performed on the banks BA0 and BA1 during horizontal access to the banks BA2 and BA3.

  In FIG. 106A, the refresh bank information (0, 1) is supplied to the bank address terminal BA together with the auto refresh command AREF, the refresh control signal refz becomes H level inside the memory device, and the refresh operation REF is performed. . After the inter-command time tRRD, the active command ACT is issued to BA2 and BA3, the corresponding read command RD is issued to BA2 and BA3, and the precharge command PRE is issued to BA2 and BA3. Is done. Thereafter, the auto-refresh command AREF is issued again at the timing of the clock number 10, and the refresh is executed for the banks BA0 and BA1. Thus, since the refresh operation REF is performed only once for one auto-refresh command AREF, it is necessary to issue the auto-refresh command AREF many times.

  In contrast, in FIG. 106B, in response to the background refresh RBEN, the refresh operation REF is repeated a number of times corresponding to the preset refresh burst length RBL. That is, the control circuit in the memory activates the refresh control signal refz and executes the refresh operation. When the refresh operation ends, the control circuit further activates the refresh control signal refz and executes the refresh operation in response to the refresh interval signal refintvalx. To do. In this way, the refresh operation is repeated the number of times of the refresh burst length RBL. Therefore, it is not necessary to issue the refresh command many times. Specifically, no refresh command is issued at clock number 10. Thereby, since the second refresh operation is completed earlier by 1060 in the figure, the refresh operation cycle is substantially shortened. Therefore, by setting the refresh burst length RBL and automatically executing a plurality of refreshes, the efficiency of command issuance by the memory controller can be increased.

  FIG. 107 is a diagram for explaining the refresh burst length in the present embodiment. FIG. 107A is a timing chart when the refresh burst length RBL is specified and the background refresh is performed, and FIG. 107B is a timing chart when the background refresh is performed without specifying the RBL. However, both are examples in which the refresh operation is repeated a plurality of times in response to the command BREN.

  In the case of FIG. 107A, the memory device repeats the refresh operation REF internally for a preset refresh burst length RBL in response to the background refresh command BREN (1070 in the figure). Therefore, the internal refresh operation is completed at clock number 20 and the precharge operation for the banks BA0 and BA1 is completed. Therefore, the memory controller can perform normal access by issuing an active command ACT (1071 in the figure) for the bank BA0 at the clock number 21.

  On the other hand, in the case of FIG. 107B, since the number of refresh times is not designated, the memory device internally repeats the refresh operation REF in response to the command BREN (1072 in the figure). The memory controller issues a precharge command PRE (1073 in the figure) to the bank BA0 at clock number 21 in order to stop the repeated refresh operation. However, since the new internal refresh operation REF starts at clock number 20, the refresh operation cannot be stopped in response to the precharge command PRE at clock number 21. Therefore, the memory controller cannot issue the active command ACT (1074 in the figure) until the already started refresh operation is completed, and eventually the time tREFC (about several tens of ns) required for the refresh operation elapses from the precharge command PRE. Only after that, the active command ACT can be issued. In other words, if the number of times of refresh is not specified in advance, the memory controller needs to stop the refresh operation with a precharge command, and the precharge command for stopping the refresh operation cannot immediately stop the refresh operation. The issue of the active command to be issued next is delayed.

  The invention described in US Patent Publication No. US2005 / 0265104A1 of Patent Document 6 described above corresponds to FIG. 107 (B) described above. On the other hand, this embodiment mode corresponds to FIG.

  The above is the outline of the background refresh function. The configuration of the memory device for realizing this function will be described below.

[Memory device having background refresh function]
FIG. 108 is an overall configuration diagram of a memory device having a background refresh function. In the figure, an input terminal group 93 includes a clock CLK, command signals / CS, / RAS, / CAS, / WE, a 2-bit bank address BA <1: 0>, and a 14-bit address A <13: 0>. Terminals are shown, and each is input to the input buffer 94 and latched in the latch circuit 720 in synchronization with the clock CLK. The command decoder 1080 is provided in the command control unit 95 shown in FIG. 9, decodes the command signals / CS, / RAS, / CAS, / WE, and performs internal control corresponding to the commands EMRS, ACT, BREN, PRE. As a signal, a mode register set pulse signal mrspz, an active pulse signal actpz, a refresh pulse signal refpz, and a precharge pulse signal prepz are output. Bank address BA <1: 0> is latched to become internal bank address baz <1: 0>, and based on this, normal bank decoder 1081 generates bank selection signals bnkz <0: 3>. The refresh bank decoder 1082 also uses the refresh bank selection signal ref_bnkz <based on the bank address baz <1: 0>, the signal input from the address terminal, and the set value modez * set in the mode register 96. 0: 3> is generated. The mode register 96 sets a set value input from the bank address baz <1: 0> and the address az <13: 0> in response to the mode register set pulse signal mrspz.

  The memory device 86 has four banks 92 in addition to the control circuit described above. Each bank includes a core 1086 including a memory cell array, a decoder, and a sense amplifier, a core control circuit 1085 that controls the core, a refresh address counter 1083 that generates a refresh address (row address) REF_RA of each bank, and an external supply. The address latch circuit 1084 latches either the address az <13: 0> or the refresh address REF_RA. In the drawing, only the detailed configuration of the bank Bank0 is shown, but the other banks Bank1, 2, 3 have the same configuration.

  The core control circuit 1085 in each bank activates the internal core if the bank selection signal bnkz <0: 3> is selected in response to the active pulse signal actpz generated in response to the active command ACT. Turn into. In this case, the address latch circuit 1084 latches the address az <13: 0> supplied from the outside, and supplies it to the decoder in the core 1086. The core control circuit 1085 activates the internal core if the refresh bank selection signal ref_bnkz <0: 3> is selected in response to the refresh pulse signal refpz generated in response to the background refresh command BREN. To refresh. In this case, the address latch circuit 1084 latches the refresh address REF_RA of the refresh address counter 1083 and supplies it to the decoder in the core.

[Example of bank configuration of memory device]
FIG. 109 is a bank configuration diagram of a memory device having a background refresh function. FIG. 109 shows the configuration of the four banks of FIG. All four banks Bank0-3 have a refresh address counter 1083, an address latch circuit 1084, a core 1086, and a core control circuit 1085. Then, the bank selection signals bnkz <0: 3> and the refresh bank selection signal ref_bnkz <0: 3> are input to the four banks Bank0-3, respectively, and when they are selected, the core control circuit 1085 The core is activated in response to the active pulse signal actpz, and the core is activated in response to the refresh pulse signal refpz. In this example, since each bank has a refresh address counter 1083, refresh control can be performed independently for each bank. Therefore, refresh control can be performed on one, two, or three of the remaining banks while the other banks are operating normally. As described with reference to FIG. 100, the refresh control is independently performed in each bank.

  FIG. 110 is another bank configuration diagram of the memory device having the background refresh function. In this example, each bank Bank0-3 includes a core 1086, an address latch circuit 1084, and a core control circuit 1085. A refresh address counter 1100 is provided in common to the two banks Bank0, 1, and supplies the refresh address REF_RA to both banks Bank0, 1. A refresh address counter 1101 is provided in common to the two banks Banks 2 and 3 and supplies the refresh address REF_RA to both banks Banks 2 and 3. In this example, refresh control can be performed independently for every two banks. That is, while the banks Bank0 and Bank1 are operating normally, the banks Bank2 and Bank3 can perform a refresh operation in parallel, and vice versa. Of course, the four banks can be simultaneously refreshed.

  FIG. 111 is another bank configuration diagram of the memory device. In this example, a refresh address counter is not provided in the bank, but a pointer 1112 indicating a word line to be refreshed is provided between the address decoder 1111 and the word driver 1113. In the normal memory operation, an address latch circuit 1110 provided in common to each bank is activated in response to an active pulse signal actpz, and latches an external address az <13: 0> to address in each bank. The decoder 1111 is activated and decodes an address when the bank selection signal bnkz <0: 3> is selected. The word driver 1113 selected by the decoder drives the word line and activates the memory cell region 1114. Then, the amplifier control circuit 1115 activates the sense amplifier 1116 at a predetermined timing.

  On the other hand, during the background refresh, when the refresh bank selection signal ref_bnkz <0: 3> is in the selected state, the pointer 1112 is activated by the refresh pulse signal refpz, and the word driver 1113 corresponding to the selected pointer is the word line. And a refresh operation is performed by the memory cell region 1114 and the sense amplifier 1116. When the refresh operation ends, the pointer 1112 changes the next pointer to the selected state. In this way, each time the refresh operation is completed, the pointer group 1112 can move the selected position to the subsequent position, and the word lines in the memory cell area can be driven in order.

  In the example of FIG. 111, since the refresh pointer group 1112 is provided in all four banks, the four banks can perform refresh control independently.

  FIG. 112 is a diagram for explaining the background refresh operation in the present embodiment. FIG. 112A corresponds to the conventional example, and when an auto-refresh command AREF is received, the memory device performs a refresh operation in all internal banks. This figure shows an example in which the number of refreshes is 1. During the refresh cycle, tREFC cannot execute the normal memory operation, and receives the active command ACT from clock number 9 and resumes the normal memory operation.

  In contrast, FIG. 112B corresponds to the present embodiment, and in response to the background refresh command BREN, the memory device starts a refresh operation for the banks BA0 and BA1 designated by the bank address BA. To do. In parallel, the memory device receives an active command ACT and a read command RD for the banks BA2 and BA3 and performs a read operation. The precharge command PRE is received after the read command RD and the banks BA2 and BA3 are precharged.

  In the example of FIG. 112B, the refresh bank information “0, 1” is input from the bank address terminal BA and the refresh burst length “8” is input from the address terminal Add simultaneously with the background refresh command BREN. . However, as illustrated, the refresh bank information “0, 1” may be input from a specially provided terminal SA, and the refresh burst length “8” and the number of refresh blocks “1” may be input from terminals RBL, RBC. .

  As shown in FIG. 112, according to the background refresh function of the present embodiment, the refresh operation is performed in parallel with the normal memory operation, so that the normal memory operation is not interrupted by the refresh operation.

[Refresh bank decoder, core control circuit, address latch circuit]
Next, specific examples of the refresh bank decoder, core control circuit, and address latch circuit shown in FIGS. As a premise, the relationship between the bank address BA <1: 0> and the selected bank is shown below.
Bank 0 is selected when BA <1> = 0 and BA <0> = 0
Bank selected by BA <1> = 0, BA <0> = 1 is Bank1
Bank selected by BA <1> = 1, BA <0> = 0 is Bank2
Bank selected by BA <1> = 1, BA <0> = 1 is Bank3
FIG. 113 is a diagram showing circuits of the first and second refresh bank decoders. The refresh bank decoder 1082 (1) of the first example of FIG. 113A is applied when the memory device performs a refresh operation every two banks, and the bank address terminal BA <1 when the background refresh command BREN is input. The logic of> controls whether the banks Bank 0 and 1 or the banks Bank 2 and 3 are selected. Therefore, the logic of the bank address terminal BA <1> is valid (V: Valid), and the logic of the bank address terminal BA <0> is invalid (Don't care). Specifically, if the bank address terminal BA <1> = H, the refresh bank selection signal ref_bnkz <2,3> = H and the banks Bank2 and 3 are selected, and if the bank address terminal BA <1> = L, the refresh bank The selection signal ref_bnkz <0,1> = H and the banks Bank0, 1 are selected.

  The refresh bank decoder 1082 (2) of the second example of FIG. 113 (B) is applied when the memory device performs the refresh operation every two banks, and the bank address terminal BA <0 when the background refresh command BREN is input. > Controls whether the banks Bank 0 and 2 or the banks Bank 1 and 3 are selected. Therefore, the logic of the bank address terminal BA <1> is invalid (Don't care). The specific operation is the same as in the first example.

  The background refresh performed during horizontal access is preferably the first example when the combination of banks constituting one horizontal line is Bank 0, 1 (or Bank 2, 3). On the other hand, when the combination of banks constituting one horizontal line is Bank 0, 2 (or Bank 1, 3), the second example is preferable. The combination of horizontal banks depends on the memory mapping of the memory system that uses the memory. Therefore, depending on the memory mapping, the memory device needs to have one of the refresh bank decoders of the first and second examples.

  FIG. 114 shows a circuit of the third refresh bank decoder. The third refresh bank decoder 1082 (3) is an example in which the first and second examples are combined, and the decode signal on the bank address baz <0> side is determined according to the set value modez set in the mode register. , Baz <1> side has four selectors SEL for selecting one of the decoded signals. As shown in the logical value table in the figure, if modez = 1, the bank address baz <1> is valid (V: Valid), the decode signal on the side of baz <1> is selected, and the refresh bank selection signal ref_bnkz < It is selected by a combination of 0,1> and ref_bnkz <2,3>. On the other hand, if modez = 0, the bank address baz <0> becomes valid (V: Valid), the decode signal on the side of baz <0> is selected, and the refresh bank selection signals ref_bnkz <0,2>, ref_bnkz <1, It is selected by the combination of 3>. Therefore, if the set value modez is set in the mode register according to the memory mapping, any memory mapping can be handled.

FIG. 115 shows a circuit of the fourth refresh bank decoder. The fourth refresh bank decoder 1082 (4) switches the bank selection mode according to the 2-bit set value modez <1: 0> set in the mode register. The four types of bank selection modes are as follows, as shown in the table in the figure.
(1) When modez <1: 0> = 1,1, one bank specified by the bank address terminals BA <1> and BA <0> is selected. That is, only one bank is selected from the four banks.
(2) When modez <1: 0> = 1,0, two banks of the bank Bank0,1 or Bank2,3 selected by the bank address terminal BA <1> are selected.
(3) In the case of modez <1: 0> = 0,1, two banks of either bank Bank0, 2 or Bank1, 3 selected by the bank address terminal BA <0> are selected.
(4) When modez <1: 0> = 0,0, all refresh bank selection signals ref_bnkz <0: 3> are selected. Therefore, when the refresh command BREN is input, refresh is executed in four banks.

  In the refresh bank decoder 1082 (4), when modez <0> = 1, two NAND gates to which the bank address baz <0> is input are activated, and the predecode signal ba0x, z becomes 1 or 0, It is selected by a combination of refresh bank selection signals ref_bnkz <0,2>, <1,3>. Conversely, when modez <1> = 1, two NAND gates to which the bank address baz <1> is input are activated, the predecode signal ba1x, z becomes 1 or 0, and the refresh bank selection signal ref_bnkz < It is selected by a combination of 0,1>, <2,3>.

  In this example, the mode register setting value should be set to modez <1: 0> = 1,0 in a system where the combination of banks that make up one horizontal line is Bank0,1 (Bank2,3). In a system where the combination of banks constituting one horizontal line is Bank 0, 2 (Bank 1, 3), the mode register setting value may be set to modez <1: 0> = 0,1. Also, modez <1: 0> = 1,1 is set for systems that want to perform refresh in 1 bank units, and modez <1: 0> = 0,0 is set for systems that perform refresh simultaneously for all banks as before. Good.

  FIG. 116 shows a circuit of the fifth refresh bank decoder. The fifth refresh bank decoder 1082 (5) selects one of the bank selection modes (1 bank, 2 banks, 2 banks, 4 banks) according to the 2-bit address terminal A <1: 0> supplied simultaneously with the command BREN. ) Can be switched. That is, in this example, a setting value input from the 2-bit address terminal A <1: 0> is used instead of the mode register setting value modez <1: 0> in the fourth example of FIG. Switching of the bank selection mode is the same as in FIG. According to the fifth example, the refresh bank selection combination can be changed every time the command BREN is issued. Therefore, even in the rectangular mode, it is possible to refresh in the background by changing the combination of selection of the banks to be refreshed.

  FIG. 117 is a diagram showing a circuit of a sixth refresh bank decoder. The sixth refresh bank decoder 1082 (6) can designate a combination of two banks to be refreshed simultaneously by the bank address terminals BA <1> and BA <0> when the refresh command BREN is input. 114 is the same as the third example in FIG. 114 in that the combination of two banks can be switched. In the fifth example, the bank address input at the same time as the command is used instead of the mode register setting value in the fifth example. This can be done by the logic of the terminals BA <1> and BA <0>.

  The refresh bank decoder 1082 (6) receives the bank selection signal bnkz <3: 0> generated from the bank address BA <1: 0> by the normal bank decoder, and generates the refresh bank selection signal ref_bnkz <0: 3>. .

First, as in the memory map 1170, in a system where the combination of banks constituting one horizontal line is Bank 0, 1 (or Bank 2, 3),
If BA <1> = 0, BA <0> = 0, bank selection signal bnkz <0> is selected (bankz <0> = High, others are Low), and banks Bank0 and Bank1 are selected,
If BA <1> = 1 and BA <0> = 1, the bank selection signal bnkz <3> is selected (bankz <3> = High, others are Low), and the banks Bank2 and Bank3 are selected.

On the other hand, as in the memory map 1171, in a system where the combination of banks constituting one horizontal line is Bank 0, 2 (or Bank 1, 3),
If BA <1> = 0 and BA <0> = 1, the bank selection signal bnkz <1> is selected, and banks Bank1 and Bank3 are selected.
If BA <1> = 1 and BA <0> = 0, the bank selection signal bnkz <2> is selected to select banks Bank0 and Bank2.

FIG. 118 is a diagram showing a circuit of a seventh refresh bank decoder. The seventh refresh bank decoder 1082 (7) selects one refresh target bank according to the 4-bit address terminal A <3: 0> input simultaneously with the command BREN. For example, bank Bank0 has address terminal A <0>, bank Bank1 has address terminal A <1>, bank Bank2 has address terminal A <2>, bank Bank3 has address A <3> terminal Make it correspond. When background refresh command is input (1) If A <3> = 0, A <2> = 0, A <1> = 1, A <0> = 1, select Bank0 and Bank1 (2) A <3> = 1, A <2> = 1, A <1> = 0, A <0> = 0, select Bank2 and Bank3 (3) A <3> = 0, A <2> = 1 , A <1> = 0, A <0> = 1, select Bank0 and Bank2 (4) A <3> = 1, A <2> = 0, A <1> = 1, A <0> If = 0, select Bank1 and Bank3 (5) If A <3> = 1, A <2> = 1, A <1> = 1, A <0> = 1, all Bank0,1,2 , 3 is selected.
(6) If any of A <3: 0> is 1, the corresponding one bank is selected.
In this case, the bank address terminal BA <1: 0> and the remaining address terminals A <13: 4> are ignored.

  FIG. 119 is a configuration diagram of the core control circuit. The core control circuit is provided in each bank as shown in FIG. The illustrated core control circuit is an example in which a refresh operation is performed only once in response to a refresh command. A control circuit for controlling the refresh operation for the number of times of the refresh burst length RBL of this embodiment will be described later.

  First, the core control circuit 1085 is responsive to the active pulse signal actpz, the refresh pulse signal refpz, and the precharge pulse signal pretz, and a timing control circuit 1190 that generates various timing signals, and in response to the refresh pulse signal refpz. A refresh control circuit 1191 for controlling refresh. The RS flip-flop FF1 composed of two NAND gates latches the active state, and the RS flip-flop FF3 latches the refresh state. A set input 1192 and a reset input 1193 are input to the RS flip-flop FF1. A set input 1194 and a reset input 1195 are input to the RS flip-flop FF3.

  In the figure, an active state signal rasz indicates an active state at the H level and a precharge state at the L level. The equalize signal eqlonz equalizes the bit line pair of the memory cell array at the H level and cancels equalization at the L level. The word line activation signal wlonz activates the word line at the H level, and deactivates the word line at the L level. The sense amplifier activation signal saonz activates the sense amplifier at the H level and deactivates at the L level. The active pulse signal actpz is set to H level by the command decoder in response to the active command ACT. The refresh pulse signal refpz becomes H level when a refresh command is input. The precharge pulse signal prepz becomes H level when the precharge command PRE is input. The bank selection signal bnkz <#> is an output signal of a normal bank decoder, and designates a bank on which an active or precharge operation is performed when Bnkz <#> becomes H level. # Is the bank number. The refresh bank selection signal ref_bnkz <#> is an output signal of the refresh bank decoder, and designates a bank on which the refresh operation is executed when ref_bnkz <#> becomes H level.

  FIG. 120 is a timing chart showing the operation of the core control circuit. In response to the auto-refresh command AREF at clock number 0, a command decoder (not shown) generates a refresh pulse signal refpz, thereby setting both the RS flip-flops FF1 and FF3 in the bank specified by ref_bnkz. As a result, the active state signal rasz becomes H level, the equalize signal eqlonz becomes L level, and the word line activation signal wlonz becomes H level after the delay time of the delay circuit DELAY-2. In response to this, the word line selected by the row address is driven. Next, after the delay time of the delay circuit DELAY-3, the sense amplifier activation signal saonz becomes H level, the sense amplifier is activated, and rewriting is performed.

  On the other hand, the refresh active state signal ref_rasz is also at the H level due to the set state of the RS flip-flop FF3. Then, after the delay time of the delay circuit DELAY-4 from the rising edge of the sense amplifier activation signal saonz, the AND gate 1196 causes the refresh precharge pulse ref_prepz to become H level, and both RS flip-flops FF3 and FF1 are reset. By resetting the RS flip-flop FF1, the active state signal rasz becomes L level, the word line activation signal wlonz also becomes L level, and the word line becomes L level. Then, after the delay time DELAY-1, the ecoize signal eqlonz becomes H level, the bit line pairs of the memory cells are equalized, and the precharge of the memory cell array is completed. As a result, the one-cycle precharge operation is completed.

  In normal operation, the RS flip-flop FF1 is set in response to the H level of the active pulse signal actpz corresponding to the active command ACT received at the clock number 9, and the equalize signal eqlonz goes to the L level, and the signal rasz, wlonz and saonz sequentially become H level, and the memory cell array is activated. Then, in response to the H level of the precharge pulse prepz corresponding to the precharge command PRE, the RS flip-flop FF1 is reset, the signals rasz, wlonz, saonz sequentially become L level, and the equalize signal eplonz becomes H level. , The memory cell array is precharged. The above is one cycle of normal operation. During normal operation, the refresh control circuit 1191 does not operate.

  As described above, the refresh operation includes the active operation and the precharge operation, and the normal operation includes the active operation, the read / write operation, and the precharge operation. In FIG. 120, the read command or the write command is omitted. In a refresh burst operation to be described later, the one-cycle precharge operation is repeated the number of times corresponding to the refresh burst length.

  FIG. 121 is a diagram showing the configuration and operation of the address latch circuit. The address latch circuit 1084 is provided in each bank as shown in FIG. 108, and outputs a row address RA <13: 0> to the memory core. Therefore, 13 illustrated address latch circuits 1084 are provided in parallel. When the bank selection signal bnkz <#> is at the H level in response to the active pulse signal actpz, the address latch circuit is turned on and the address signal az <13: 0> from the outside is latched by the latch circuit 1200. Latch. On the other hand, if the refresh bank selection signal ref_bnkz <#> is H level in response to the refresh pulse signal refpz, the address latch circuit is turned on and the refresh address counter 1083 refresh address REF_RA <13: 0>. Is latched by the latch circuit 1200.

  In addition, as shown in the timing chart of FIG. 121, a refresh row address strobe pulse signal Ref_ra_strbpz is generated in response to the refresh pulse signal refpz, and the refresh address counter 1083 increments the address in response thereto. The incremented refresh address REF_RA <13: 0> is latched by the latch circuit 1200 in response to the next refresh pulse signal refpz.

[Refresh burst control]
Next, a characteristic refresh burst control in the background refresh operation of the present embodiment will be described. The refresh burst control means that the memory device repeats the refresh operation for the number of refresh burst lengths in response to one background refresh command. As a result, as shown in FIG. 106, the number of command issuances can be reduced, and access efficiency can be improved.

  FIG. 122 is a timing chart showing the refresh burst operation. In this example, in the memory map 12 at the upper right in the figure, the second row is horizontally accessed while the first row is refreshed. The refresh bank information SA = 0,1 and the refresh burst length RBL = 4 are supplied from the memory controller to the memory device together with the background refresh command BREN at the clock number 0. Although the refresh block number RBC is also supplied, it is omitted in this example. As shown in FIG. 105, the refresh bank information SA and the refresh burst length RBL are set in the mode register by the mode register set command or supplied together with the refresh command BREN. The supplied external terminals are, for example, bank address terminals, address terminals, special terminals, and the like. Specific examples will be described later.

  When the background refresh command BREN is received at the clock number 0, the memory device repeatedly executes the refresh operation four times for the banks Bank0 and Bank1. Further, the memory controller issues an active command ACT to the banks Bank 2 and 3 with clock numbers 2 and 4, issues a read command RD with clock numbers 5 and 7, and issues a precharge command PRE with clock numbers 8 and 9. . Similarly, an active command ACT for the banks Bank 2 and 3 is issued at clock numbers 11 and 13, followed by a read command RD and a precharge command PRE. In response to these, the memory device performs an active operation in banks Bank2 and Bank3. The active operation in the banks Bank 2 and 3 is executed in parallel with the refresh operation in the banks Bank 0 and 1.

  By specifying the refresh burst length RBL, four refresh operations are completed at the clock number 16, and the active command ACT for the banks Bank0, Bank1 can be issued immediately after the clock 19.

  FIG. 123 is a configuration diagram of a core control circuit that controls the refresh burst operation. This core control circuit becomes clearer by referring to FIG. 119 and FIG. 120 together. In addition to the timing control circuit 1190 and the refresh control circuit 1191 of FIG. 119, the core control circuit 1085 includes a refresh burst length register 1231 in which the refresh burst length RBL is set, a refresh burst length counter 1230 for counting the number of refresh operations, A refresh burst end detection circuit 1232 for comparing the outputs and detecting the end of the refresh burst operation is provided. The core control circuit 1085 in FIG. 123 receives the refresh burst length RBL (4 bits: 1 to 16 times) from the address terminal A <7: 4> simultaneously with the background refresh command BREN (FIG. 105 (A )).

  In the refresh burst length register 1231, as shown in the table 1231T in the figure, the refresh burst length RBL = 1 shown in the table 1231T corresponding to the 4-bit information input from the address terminal az <7: 4>. ~ 16 are set. This setting is performed when the refresh pulse signal refpz generated in response to the background refresh command BREN = H and the refresh bank selection signal ref_bnkz <#> = H.

  The refresh burst length counter 1230 is reset when the refresh pulse signal refpz = H and the refresh bank selection signal ref_bnkz <#> = H. The refresh control circuit 1191 outputs an internal refresh pulse signal int_refpz (= H) for instructing the next refresh operation every time one cycle of refresh operation is completed, and in response to this, the refresh burst length counter 1230 counts the count value. Is incremented. When the count value of the counter 1230 matches the burst length RBL set in the refresh burst length register 1231, the refresh burst end detection circuit 1232 outputs the refresh burst end signal rb_endz (= H). In response to this, the refresh control circuit 1191 resets the RS flip-flop circuit that latches the refresh state, and does not output the internal refresh pulse signal int_refpz and the refresh precharge pulse signal ref_prepz thereafter.

  FIG. 124 is another configuration diagram of the core control circuit that controls the refresh burst operation. The core control circuit 1085 is an example (corresponding to FIG. 105B) in which the refresh burst length RBL input to the address terminals az <7: 4> together with the mode register set command EMRS is set in the mode register 96. In the mode register 96, 4-bit data input to the address terminals az <7: 4> in response to the mode register set pulse mrspz is set as the refresh burst length RBL (table 1231T in FIG. 123), and the bank address terminal The bank information to be refreshed input to baz <1: 0> is also set. Further, the refresh block number RBC may be set.

  The refresh burst end detection circuit 1232 receives the signal modez <7: 4> indicating the refresh burst length from the mode register 96 and compares it with the count value of the refresh burst length counter 1230. Other configurations are the same as those in FIG.

  FIG. 125 is a detailed circuit diagram of the timing control circuit 1190 and the refresh control circuit 1191 in the core control circuit. The configuration indicated by arrows 1250 to 1254 in the figure is added to the configuration of FIG. That is, the RS flip-flop FF2 that latches the refresh state is set in response to the refresh pulse signal refpz generated by the refresh command BREN, and the refresh state signal ref_statez indicated by the arrow 1250 is set to H. The refresh state signal ref_statez is maintained at H during the refresh burst operation.

  In order to control the repetition of the refresh operation, the refresh control circuit 1191 has an internal refresh pulse signal int_refpz (arrows 1251, 1252) after the delay time DELAY-5 after the equalize signal eqlonz becomes H level at the end of the refresh cycle. ) To H level (DELAY-0 pulse width). This internal refresh pulse signal int_refpz sets the RS flip-flop FF1 (arrow 1253) and instructs the start of the next refresh cycle. The internal refresh pulse signal int_refpz increments the refresh counter as described above.

  In order to stop the refresh operation, the refresh control circuit 1191 sets the refresh burst end signal rb_endz (arrow 1254) to the H level when the burst length refresh cycle is completed, and when the refresh operation cycle is completed. When the refresh precharge pulse signal ref_prepz becomes H level, the RS flip-flop FF2 is reset by the reset input 1195, and the refresh state signal ref_statez is reset to L. As a result, the output of the AND gate 1197 is fixed at the L level, and the internal refresh pulse signal int_refpz instructing the start of the next refresh cycle is not output any more.

  FIG. 126 is another detailed circuit diagram of the timing control circuit 1190 and the refresh control circuit 1191 in the core control circuit. The refresh control circuit 1191 of this core control circuit is provided with an oscillator 1260 that is activated by the H level of the refresh state signal ref_statez, instead of the AND gate 1197 and the delay circuit DELAY-5 shown in FIG. The oscillator 1260 oscillates at the same frequency as the refresh cycle, and continues to output the internal refresh pulse signal int_refpz instructing the start of the next refresh cycle while the refresh state signal ref_statez is at the H level. When the refresh burst end signal rb_endz becomes H level and the refresh precharge pulse signal ref_prepz becomes H level at the end of one cycle of the refresh operation, the RS flip-flop FF2 is reset and the refresh state signal ref_statez is reset to L. Then, the oscillator 1260 stops. The rest is the same as FIG.

  125 and 126 will be described in detail with reference to FIG. 129 after FIGS. 127 and 128 are described.

  127 is a block diagram of the refresh burst length counter 1230, the refresh burst length register 1231 and the refresh burst end detection circuit 1232. This is a specific example of FIG. 123, and is a specific example excluding the register of FIG. The counter in the refresh burst length counter 1230 is reset to “0” in response to the refresh pulse signal refpz, and is incremented in response to the internal refresh pulse signal int_refpz instructing the start of the refresh cycle. The counter value rblcz <3: 0> is output to the refresh burst end detection circuit 1232.

  The refresh burst length register latches the signal at the address terminal az <7: 4> in response to the refresh pulse signal refpz, and sends rblrz <3: 0> indicating the latched refresh burst length to the refresh burst end detection circuit 1232 Output.

  The refresh burst end detection circuit 1232 compares the counter value rblcz <3: 0> with the refresh burst length rblrz <3: 0>, and outputs a refresh burst end signal rb_endz when the two match completely. Subsequent refresh operations are stopped by this refresh burst end signal rb_endz.

  FIG. 128 is a block diagram of the address latch circuit. In addition to the configuration of FIG. 121, in response to the internal refresh pulse signal int_refpz indicated by an arrow 1280, the address latch circuit 1084 changes the refresh address REF_RA <13: 0> of the output of the refresh address counter 1083 to the switch 1202. Via the latch circuit 1200. That is, in the refresh burst operation, the internal refresh pulse signal int_refpz (= H) is repeatedly output in order to repeat the refresh cycle. Accordingly, in response to this, the address latch circuit 1084 needs to latch a new refresh address from the refresh address counter 1083 and increment the counter.

  FIG. 129 is a timing chart of the refresh burst operation. The refresh burst operation by the core control circuit shown in FIGS. 125 to 128 will be described with reference to FIGS. First, a refresh burst operation starts in response to the background refresh command BREN. Also in this example, the refresh target banks Bank0, 1 and the refresh burst length RBL = 4 are designated.

  In response to the refresh command BREN, the refresh pulse signal refpz is output, and in response to this, the values of the address terminals A <7> to A <4> are taken into the refresh burst length register 1231 of the refresh target banks Bank0,1. In the figure, rblrz <3: 0> = 0011b is an example of the burst length RBL = 4. At the same time, the counter value of the refresh burst length counter 1230 of the banks Bank0,1 is reset to rblcz <3: 0> = 0000b. The refresh state signal ref_statez is set to the H level by the RS flip-flop FF2 in the refresh controller circuit 1191.

  At this time, the RS flip-flop FF1 in the timing control circuit 1190 is also set, the active state signal rasz = High, and the refresh cycle operation starts. At the same time, the timing control circuit 1190 sets the equalize signal eqlonz = Low, the word line activation signal wlonz = High, and sets the sense amplifier activation signal saonz to the H level as shown in FIG. 120 (not shown). As a result, the banks Bank0 and Bank1 become active, and the cell data is rewritten.

  After a delay time DELAY-4 from the sense amplifier activation signal saonz, the AND gate 1196 outputs the refresh precharge signal ref_prepz, the RS flip-flop FF1 is reset, the active state signal becomes rasz = Low, and the equalize signal becomes eqlonz = High. Thus, the precharge operation starts. At this time, since the value of the refresh burst length register 1231 and the value of the refresh burst length counter 1230 are different (rblrz <3: 0> ≠ rblcz <3: 0>), the refresh end signal rb_endz remains low.

  The refresh control circuit 1191 outputs an internal refresh pulse signal int_refpz via the AND gate 1197 after the delay time DELAY-5 from the equalize signal eqlonz = High, sets the RS flip-flop FF1, and performs the next refresh operation. Start. At this time, the value of the refresh burst length counter is counted up to 0001b. The address latch circuit 1984 (FIG. 128) latches the count value of the refresh address counter 1083. Thereafter, the same refresh operation is repeated.

  When the third internal refresh pulse signal int_refpz is output and the fourth refresh operation is started, the value of the refresh burst length counter is incremented to rblcz <3: 0> = 0011b. At this time, the refresh burst length register value rblrz <3: 0> = and the refresh burst length counter value rblcz <3: 0> are the same (rblrz <3: 0> = rblcz <3: 0> = 0011b) The refresh burst end detection circuit 1232 sets the refresh burst end signal rb_endz = High. At the end of the fourth refresh operation, the precharge signal ref_prepz is output and the active state signal rasz = Low. At this time, since the refresh end signal rb_endz = High, the RS flip-flop FF2 is reset by the reset input 1195. As a result, the refresh state signal ref_statez changes to Low. With this ref_statez = Low, when the equalize signal eqlonz = High is brought along with the precharge operation, the internal refresh signal int_refpz for starting the next refresh operation is not output, and four refresh burst operations are completed.

  In the example of FIG. 126 as well, the internal refresh signal int_refpz is output by the oscillator 1260. However, when the fourth refresh operation is started and the refresh state signal ref_statez is reset to L, the oscillator 1260 is stopped, and then the internal refresh signal is reset. The refresh signal int_refpz is not output. As a result, the refresh operation is completed after four times.

[Refresh burst stop control]
The refresh burst function repeats a refresh cycle for a specified burst length when a single background refresh command is input. Therefore, the number of command inputs can be reduced to increase memory access efficiency. However, if the burst length is increased, memory access flexibility is lost if access to the bank is not permitted until the background refresh operation once started is completed. Therefore, the memory device of the present embodiment has a refresh burst stop function.

  FIG. 130 is a diagram showing an outline of the refresh burst stop operation. The memory device inputs a background refresh command BREN at clock number 0, and starts a refresh operation with burst length RBL = 4 times at banks BNK0,1. However, if the memory device inputs the stop command STOP during the third refresh cycle, it does not enter the next refresh cycle after completing the refresh cycle being executed. Since the refresh cycle being executed cannot be stopped, the stop operation by the stop command STOP means that a new refresh cycle is not entered.

  The stop command STOP is specified by, for example, a refresh command (for example, / CS = L, / RAS = L, / CAS = L, / WE = H) and an address terminal signal at the time of command input. That is, the command signal is the same as the refresh command, and is distinguished by the address terminal signal. Alternatively, a precharge command (for example, / CS = L, / RAS = L, / CAS = H, / WE = L) is used as the stop command STOP.

  FIG. 131 is a block diagram of a core control circuit having a refresh burst stop function. The refresh control circuit 1191 of the core control circuit of FIGS. 123 and 124 includes a refresh state control circuit 1191B and a refresh state control circuit 1191. The command decoder 1080 outputs a refresh stop pulse signal ref_stoppz in response to the stop command in addition to the refresh pulse signal refpz in response to the background refresh command.

  The refresh state control circuit 1191B sets the refresh state signal ref_statez to H level in response to the refresh pulse signal refpz, and resets the refresh state signal ref_statez to L level in response to the refresh stop pulse signal ref_stoppz. This refresh state signal ref_statez controls the refresh control circuit 1191 to start and stop refreshing. The refresh control circuit 1191 also ends the refresh operation as described above even when the refresh cycle of the burst length is completed by the refresh burst end signal rb_endz indicating the end of the refresh cycle of the burst length.

  FIG. 132 is a circuit diagram of the refresh state control circuit. FIG. 132A shows an example in which a stop command is given by a background refresh command BREN and an address terminal signal. FIG. 132B shows an example in which a precharge command is given as a stop command. The RS flip-flop FF2 incorporated in these corresponds to the RS flip-flop FF2 in FIGS. 125 and 126, and controls the refresh state signal ref_statez indicating the refresh state or the refresh stop state.

  In any refresh state control circuit 1191B, the RS flip-flop FF2 is set with the refresh pulse signal refpz = H to set the refresh state signal ref_statez = H, the refresh burst end signal rb_endz <#> = H, and the refresh precharge pulse signal. In response to ref_prepz = H, the NAND gate 1321 resets the refresh state signal ref_statez = L. Up to this point, the normal refresh burst operation is performed.

  In FIG. 132 (A), in response to the refresh stop pulse signal ref_stoppz = H generated by the stop command, the RS flip-flop FF2 is reset via the inverter 1322, and the refresh state signal ref_statez = L. . In this case, since only the RS flip-flop FF2 in the refresh target bank is in the set state (refresh state, ref_statez = H), the refresh is performed in response to the common refresh stop pulse signal ref_stoppz = H in the memory device. Only the RS flip-flop FF2 in the target bank is reset.

  On the other hand, in FIG. 132 (B), only the bank selected by the refresh bank selection signal ref_bnkz <#> = H in response to the precharge pulse signal prepz = H generated in response to the precharge command is RS flip-flop. FF2 is reset. During the normal operation cycle, the refresh bank selection signal ref_bnkz <#> = L, so the RS flip-flop FF2 is not reset by the precharge command.

  FIG. 133 is a circuit diagram of the timing control circuit 1190 and the refresh control circuit 1191 of the core control circuit. 125 is different from the circuit diagram of FIG. 125 in that in addition to the RS flip-flop FF2 of the refresh state control circuit 1191B of FIG. 132, an RS flip-flop FF3 for managing the active state and the precharge state during the refresh operation is provided. The RS flip-flop FF3 generates a refresh active state signal ref_rasz. Then, the AND gate 1332 outputs a refresh precharge pulse signal ref_prepz instructing precharge during the refresh cycle based on the refresh active state signal ref_rasz = H regardless of the state of the refresh state signal ref_statez. The refresh active state signal ref_rasz operates in the same manner as the active state signal rasz during refresh.

  125 differs from FIG. 125 in that the arbitration circuit 1334 sets the refresh state signal ref_statez = L by the timing after the delay time DELAY-5 from the equalization signal eqlonz = H instructing the start of precharge and the stop command or the precharge command. When the refresh state signal ref_statez = H, an internal refresh pulse signal int_refpz = H is output to instruct the start of a new refresh cycle. When the refresh state signal ref_statez = L, a new refresh cycle starts. The internal refresh pulse signal int_refpz = H is not output.

  FIG. 134 is another circuit diagram of the timing control circuit 1190 and the refresh control circuit 1191 of the core control circuit. Here, instead of the AND gate 1333 in FIG. 133, an oscillator 1260 is provided, which corresponds to the example in FIG. Similarly to FIG. 126, the oscillator 1260 is enabled when the refresh state signal ref_statez = H, and outputs an internal refresh pulse signal int_refpz = H instructing the start of the next refresh cycle. The oscillator is disabled when the refresh state signal ref_statez = L. The arbitration circuit 1334 monitors the timing of the output of the oscillator and the refresh state signal ref_statez, passes the oscillator output during the refresh state signal ref_statez = H, and prohibits the passage of the oscillator output when the refresh state signal ref_statez = L. To do.

  FIG. 135 is a timing chart showing the operation of FIG. The operations of the timing control circuit 1190 and the refresh control circuit 1191 in FIGS. 133 and 134 are as follows. In response to the refresh pulse signal refpz = H by the background refresh command BREN, the RS flip-flops FF1 and FF3 are set, and both the active state signal rasz and the refresh active state signal ref_rasz become H level. In response to this, the word line and the sense amplifier are driven to perform an active operation.

  When the active operation is completed, the refresh precharge pulse signal ref_prepz = H is output after the delay time DELAY-4 in response to the sense amplifier activation signal saonz = H, the RS flip-flops FF1, FF3 are reset, Both the active state signal rasz and the refresh active state signal ref_rasz become L level. As a result, the precharge operation starts. After the delay time DELAY-5 from the equalization signal eqlonz = H for starting the precharge operation, an internal refresh pulse signal int_refpz = H for instructing the start of the next refresh cycle is output, and the next refresh cycle starts.

  Then, the stop command STOP is input during the active operation of the third refresh cycle. In response to this, the refresh stop pulse signal Ref_stoppz = H is output from the command decoder, and the refresh state control circuit 1191B outputs the refresh state signal ref_statez = L. The AND gate 1332 sets the refresh active state signal ref_rasz = H at the timing after the delay time DELAY-4 from the sense amplifier activation signal saonz = H, which is the timing indicating the end of the active operation of the third refresh cycle. Based on this, a refresh precharge pulse signal ref_prepz = H for instructing the start of precharge is output. Thereby, the precharge operation of the third refresh cycle is surely executed.

  In response to the refresh precharge pulse signal ref_prepz = H, the RS flip-flops FF1 and FF3 are reset, and the equalize signal eqlonz = H and the precharge operation starts. Then, at the timing after the delay time DELAY-5, the arbitration circuit 1334 does not output the internal refresh pulse signal int_refpz = H instructing the start of the next refresh cycle based on the refresh state signal ref_statez = L.

  As described above, according to the above core control circuit, when the stop command STOP input at an arbitrary timing is generated using the refresh state signal ref_statez and the refresh active state signal ref_rasz, the precharge of the refresh cycle in operation is performed. This ensures that the operation can be completed, and prohibits entering a new refresh cycle after the stop command STOP.

  FIG. 136 is a circuit diagram of a command decoder for realizing the refresh stop function. The node 1361 of the command decoder 1080 becomes H level when / CS = L, / RAS = L, / CAS = L, / WE = H. When the address terminal A <8> 1360 is at the L level and az <8> = L, the refresh pulse signal refpz = H is set by the AND gate 1363 and the refresh operation is started. On the other hand, when the address terminal A <8> 1360 is at the H level and az <8> = H, the AND gate 1362 causes the refresh stop pulse signal ref_stoppz = H to stop the refresh operation.

[Countdown refresh burst control]
Next, an embodiment in which refresh burst control is performed using a down counter will be described. In the above example, the refresh burst counter is counted up every refresh cycle. However, in the following embodiment, when the refresh burst counter is counted down every refresh cycle and all the count values of the refresh burst counter become zero, , The refresh burst operation is terminated. Therefore, the stop control can be performed by resetting all the refresh burst counters to 0 in response to the stop command during the background refresh operation.

  In addition, by using this down counter, before the refresh burst operation is completed, a new background refresh command is input, and the refresh burst counter is overwritten to the burst length specified by the new command. It is possible to perform control such as adding the burst length specified by a simple command to the current refresh burst counter.

  Further, in the following embodiment, the refresh address counter is incremented or decremented every refresh cycle, but the refresh address counter is initialized from the existing count value by a refresh all command that refreshes all the remaining refresh addresses at once. Control for returning to a value will also be described.

  FIG. 137 is a block diagram of a core control circuit 1085 that performs countdown type refresh burst control. In this example, the refresh start and stop are controlled by the background refresh command BREN and the address terminal A <5>.

  Similar to the circuit diagram of FIG. 131, the core control circuit 1085 includes a timing control circuit 1190 for generating control signals for active operation and precharge operation for the core, and a refresh control circuit 1191 for performing refresh control in the background refresh operation. Have. Further, the core control circuit sets a refresh burst length register 1231 for setting the refresh burst length RBL input from the address terminal A <3: 0> in response to the refresh pulse signal refpz, and the refresh burst length RBL as a refresh pulse signal. A refresh burst length counter 1230 is input in response to refpz, counts down with a down signal downz, and resets all count values to 0 in response to an address terminal A <5> = H corresponding to a stop command.

  A refresh burst operation is started by a refresh pulse signal refpz corresponding to the background refresh command, a down signal downz is output every refresh cycle, the refresh burst length counter 1230 counts down, and an internal refresh instructing the next refresh cycle A pulse signal int_refpz is output. The refresh control circuit 1191 repeats the above refresh cycle operation while the count values rblcz <3: 0> of the refresh burst length counter are not all 0 (L level). When the count values rblcz <3: 0> are all 0 (L level), the refresh control circuit 1191 does not output the internal refresh pulse signal int_refpz that instructs a new refresh cycle. When the count value rblcz <3: 0> is all 0 (L level) by the stop command by the address terminal A <5> = H, the refresh control circuit 1191 similarly does not output the internal refresh pulse signal int_refpz.

  The core control circuit 1085 in FIG. 137 has a refresh address comparison circuit 1370. In response to the refresh all command REFALL, the refresh address comparison circuit 1370 sets the refresh all signal rblcallz = H, monitors the refresh address ref_az <13: 0> of the refresh address counter 1083, and refresh address ref_az <13: 0> = When all H are detected, the refresh all signal reblcallz = L. In response to the refresh all command REFALL, the refresh pulse signal int_refpz is output, the refresh operation starts, and the refresh all signal rblcallz = H until all the refresh addresses ref_az <13: 0> of the refresh address counter 1083 become H. During the period, the refresh control circuit 1191 continues to output the internal refresh pulse signal int_refpz. When the refresh address ref_az <13: 0> = all H and the refresh all signal rblcallz = L, the refresh control circuit 1191 stops outputting the internal refresh pulse signal int_refpz and no further refresh cycle occurs. The refresh address counter 1083 counts down the refresh address ref_az <13: 0> in response to the sense amplifier activation signal saonz. Instead of the sense amplifier activation signal saonz, the internal refresh pulse signal int_refpz may be used to count down.

  FIG. 138 is a truth table showing the correspondence between the refresh burst length set in the refresh burst length register 1231 and the address terminals A <3: 0>. The value of the address terminal A <3: 0> is set in the register 1231 as the refresh burst length as it is.

  FIG. 139 is a configuration diagram of the core control circuit 1085 that performs countdown type refresh burst control. In this circuit, the refresh burst length counter 1230 is reset to ALL = 0 in response to the stop command REFSTOP. The rest is the same as the circuit diagram of FIG.

  FIG. 140 is a circuit diagram of the timing control circuit 1190 and the refresh control circuit 1191 in the core control circuit 1085. As described above, the timing control circuit 1190 is set in response to the active pulse signal actpz during normal operation, the refresh pulse signal refpz during background refresh operation, and the internal refresh pulse signal int_refpz during refresh burst operation. RS flip-flop FF1. When the flip-flop FF1 is set, an active state signal rasz <#> or the like is output, and the core performs active operation.

  Then, the refresh control circuit 1191 sets the refresh interval signal refitvalx = H after the delay time DELAY-6 after the active state signal rasz <#> becomes L level, and generates an internal refresh pulse signal int_refpz for instructing the next refresh cycle. Output. Further, the refresh control circuit 1191 outputs a down signal downz = H having a pulse width of the delay time DELAY-7 in response to the word line drive signal wlonz <#> = H, and the count value of the refresh burst length counter 1230 is output. Count down.

  The output of the NAND gate 1400 becomes the L level when the refresh burst length count value rblcz <3: 0> = all L and the refresh all signal rblcallz = L, and the internal refresh pulse signal int_refpz is output via the AND gate 1401. Is prohibited. Since the refresh all signal rblcallz = L in the normal state, the output of the internal refresh pulse signal int_refpz is prohibited when the refresh burst length count value rblcz <3: 0> = all L during the refresh burst operation. During the refresh all signal rblcallz = H corresponding to the refresh all command, the internal refresh pulse signal int_refpz is output regardless of the refresh burst length count value rblcz <3: 0>.

  Note that an address terminal A <10> in FIG. 140 is a signal for instructing an all-bank precharge operation of the SDRAM, and resets the RS flip-flop FF1 to control the precharge operation. The specific operation of the above circuit will be described in detail later.

  141 and 142 are circuit diagrams of the refresh burst length register 1231 and the refresh burst length counter 1230. FIG. FIG. 141 is an example in which a stop command is input at the background refresh command BREN and the address terminal A <5>, and FIG. 142 is an example in which the stop command is input by a dedicated command REFSTOP. The rest is the same.

  The refresh burst length register 1231 fetches the refresh burst length RBL from the address terminal A <3: 0> into the latch circuits 1410 and 1412 in response to the refresh pulse signal refpz. Since the normal down signal downz and the self-refresh mode signal srefz are both at the L level, the gates 1411 and 1413 output the latched value as it is as the refresh burst length register value rblrz <3: 0>. Further, the refresh burst length register 1231 sets the register value rblrz <3: 0> = 0001 in response to the self-refresh signal srefz = H commanding the conventional refresh operation of the SDRAM.

  The refresh burst length counter 1230 has a down counter 1414 that takes in the register value rblrz <3: 0> in response to the refresh pulse signal refpz = H and counts down in response to the down signal downz = H. Further, the down counter 1414 responds to the refresh pulse signal refpz = H corresponding to the stop command and the address terminal A <5> = H (in response to the refresh stop command REFSTOP in the example of FIG. 142), and rblcz <3 : 0> = all reset to low.

  FIG. 143 is a circuit diagram of the refresh address counter 1083 and the refresh address comparison circuit 1370. The refresh address counter 1083 is a 14-bit counter that counts down the refresh address ref_az <13: 0> in response to the refresh bank selection signal ref_bnkz <#> = H and the sense amplifier activation signal saonz <#> = H. To do.

  The refresh address comparison circuit 1370 has an RS flip-flop FF4 that is set in response to the refresh all command REFALL, and a NAND gate group 1432 that detects all the refresh addresses ref_az <13: 0> = H. In the normal state, the RS flip-flop FF4 is reset, the node 1430 is at the H level, and the refresh all signal rblcallz = L. In response to the refresh all command REFALL, the RS flip-flop FF4 is set, the node 1430 becomes L level, and the refresh all signal rblcallz = H. While rblcallz = H, the refresh operation is repeated by the refresh control circuit 1191, and the refresh address counter 1083 is counted down every time the sense amplifier activation signal saonz = H. When all the refresh addresses ref_az <13: 0> change from L to H, the NAND group 1432 detects it, sets the node 1431 to the H level, and sets the refresh all signal rblcallz = L. In response to this, the refresh control circuit 1191 stops the refresh operation, and the RS flip-flop FF4 is reset. Thus, the refresh all operation for refreshing all the remaining addresses in the refresh address counter 1083 is completed.

  FIG. 144 is a timing chart when the countdown type core control circuit has RBL = 3. In response to the background refresh command BREN, a refresh pulse signal refpz = H is generated, and in response, the register 1231 and the counter 1230 in FIGS. 141 and 142 are reset, and the refresh burst length register value rblrz <3: 0> , Refresh burst length counter value rblcz <3: 0> are both set to 0011b. With rblcz <3: 0> = 0011b, the output of the NAND 1400 of the refresh control circuit 1191 in FIG. 140 changes from L to H, and the internal refresh pulse signal int_refpz = H is output. Further, the RS flip-flop FF1 of the timing control circuit 1190 in FIG. 140 is set, the active state signal rasz becomes H level, the refresh control circuit 1191 sets the refresh interval signal refitvalx = L via the AND gate 1402, The internal refresh pulse signal int_refpz = L.

  Then, the core is activated, and the refresh control circuit 1191 outputs the down signal downz = H via the AND gate 1430 in response to the sense amplifier activation signal saonz = H. In response to this, the refresh burst length counter 1230 of FIGS. 141 and 142 counts down the count value rblcz <3: 0>. The refresh control circuit 1191 sets the refresh interval signal refitvalx = H after the delay time DELAY-6 after the active state signal rasz becomes L level, and outputs a new internal refresh pulse signal int_refpz.

  When the above refresh cycle is repeated three times, the refresh burst length counter count value rblcz <3: 0> = 0000b, the output of the NAND gate 1400 of the refresh control circuit 1191 becomes L level, and the AND gate 1401 Therefore, the subsequent internal refresh pulse signal int_refpz is not output. This completes the refresh operation with a burst length of 3.

  FIG. 145 is a timing chart of the refresh stop operation of the countdown core control circuit. In this example, the refresh operation is stopped by the stop command during the refresh operation with the refresh burst length RBL = 3. When the refresh start command is input by the background refresh command BREN and the address terminal A <5> = L, the refresh operation starts. The starting operation is the same as in FIG. When a refresh stop command is input at clock number 7 using the background refresh command BREN and the address terminal A <5> = H, the refresh burst length counter 1230 (FIG. 141) is reset and its count value rblcz <3. : 0> becomes 0000b. In response to this, the output of the NAND gate 1400 of the refresh control circuit 1191 becomes L level, and the internal refresh pulse signal int_refpz thereafter is not output. Note that the precharge of the refresh cycle is controlled by the timing control circuit 1190 in the same manner as the normal operation.

  FIG. 146 is a timing chart of the refresh stop operation of the countdown type core control circuit. Unlike FIG. 145, stop control is performed by a refresh stop command REFSTOP. The rest is the same as FIG.

  FIG. 147 is a timing chart showing the refresh all operation of the countdown type core control circuit. In response to the refresh all command REFALL, REFALL = H is set, the RS flip-flop FF4 of the refresh address comparison circuit 1370 (FIG. 143) is set, the node 1430 becomes L level, and the refresh all signal rblcallz = H. As a result, the output of the NAND gate 1400 of the refresh control circuit 1191 (FIG. 140) becomes H level, the internal refresh pulse signal int_refpz = H is output, and the refresh cycle starts.

  Every refresh cycle, the refresh address ref_az <13: 0> of the refresh address counter 1083 (FIG. 140) is counted down, ref_az <13: 0> = all L (count value 0000h), and ref_az <13: 0> = all When it becomes H (count value 3FFFh), the NAND gate group (FIG. 143) detects it, the refresh all signal REFALL = L, the NAND gate 1400 of the refresh control circuit 1191 (FIG. 140) becomes L level, and then The output of the internal refresh pulse signal int_refpz is stopped. As a result, the refresh operation is completed for all the remaining refresh addresses, and the count values of the refresh address counter 1083 are all reset to 1.

  FIG. 148 is a timing chart showing the refresh command resetting operation of the countdown type core control circuit. In this figure, in the first background refresh command BREN, the refresh burst length RBL = 14 (A <3: 0> = 1110b) is set and the refresh operation starts, and the refresh burst length counter is counted down for each refresh operation. . Before the refresh burst length counter value rblcz <3: 0> = 0000b, the refresh burst length RBL = 2 (A <3: 0> = 0010b) is further input by the second command BREN, and the counter at that time The new refresh burst length RBL = 2 (A <3: 0> = 0010b) is added to the value rblcz <3: 0> = 1011b, and the counter value rblcz <3: 0> = 11101b (13 remaining times) is obtained. .

  As described above, in the refresh burst control, the memory controller has a function of adding a refresh burst length by a new background refresh command, so that the memory controller issues a background refresh command in advance for a future background refresh operation. can do.

  FIG. 149 is a timing chart showing the refresh command resetting operation of the countdown type core control circuit. In this example, the refresh burst length RBL = 2 (A <3: 0> = 0010b) is input by the second command BREN, and the new refresh burst length is used instead of the counter value rblcz <3: 0> = 1011b at that time. RBL = 2 (A <3: 0> = 0010b) is overwritten, and the counter value rblcz <3: 0> = 0010b (remaining twice).

  As described above, the refresh burst control has a function of overwriting the refresh burst length with a new background refresh command, so that the memory controller cancels the background refresh operation once started and starts a new background refresh operation. Can be started. By adding or overwriting the burst length RBL with a new background refresh command as shown in FIGS. 148 and 149, the contents can be freely changed after the refresh burst operation starts, and the memory controller Control flexibility can be increased.

[Active and refresh interlocking control]
Next, control for linking active and refresh will be described. In the embodiments described above, the normal memory operation active command ACT and the background refresh operation command BREN are separate commands, and the memory controller issues these commands separately to the normal memory device. The memory operation and the background refresh operation are executed.

  In contrast, in the following embodiment, the memory device responds to the input of the active command for normal memory operation by setting the mode register or the like to execute the background refresh operation in conjunction with the active command in advance. Thus, in addition to the normal active operation in the selected bank, the refresh operation in the refresh target bank is performed. By having such a function, the memory controller does not need to issue a background refresh command.

  FIG. 150 is a timing chart showing active and refresh interlocking control. At clock number 2, the bank address BA = 2 is input together with the active command ACT, and in response to this, the memory device executes an active operation in the bank BANK2 and a refresh operation in the bank BANK1. At clock number 4, as shown in the table in the figure, bank address BA = 3 is input together with active command ACT, and in response to this, the memory device executes an active operation in bank BANK3 and in bank BANK0. Perform a refresh operation.

  That is, as shown in the table in the figure, the memory device performs a refresh operation in a specific bank corresponding to the value of the bank address BA <1: 0> input together with the active command ACT. That is, if bank BANK0 is selected with the active command, refresh operation is performed with bank BANK3, if bank BANK1 is selected with the active command, refresh operation is performed with bank BANK2, and if bank BANK2 is selected with the active command, refresh operation is performed with bank BANK1. If the bank BANK3 is selected by the active command, the refresh operation is performed with the bank BANK0. With this combination, any of the memory mappings 1170 and 1171 shown in FIG. 117 can perform background refresh to a bank that is not subject to horizontal access by an active command accompanying horizontal access.

  In the present embodiment, one background refresh operation is executed in response to the active command ACT. Therefore, the refresh burst length RBL = 1 is fixed.

  FIG. 151 is a circuit diagram of a refresh bank decoder in active and refresh interlock control. When the mode value modez = H, the AND gate group 1510 in the refresh bank decoder 1082 responds to each of the bank selection signals bnkz <#> = H output from the normal bank decoder, and the refresh bank selection signal ref_bnkz <#>. = H is output. The relationship between the normally active operation selected bank and the refresh selected bank is as shown in the table of FIG. On the other hand, when the mode value modez = L, the AND gate group 1510 prohibits the refresh operation linked with the refresh bank selection signal ref_bnkz <3: 0> = L all.

  The mode value modez = H / L is set in the internal register in advance by the mode register set command EMRS. Alternatively, it is input from a predetermined external terminal. Therefore, according to the above example, the mode value modez = H is set in the case of horizontal access, the background refresh operation is performed in conjunction with the active command ACT, and the mode value modez = L in the case of rectangular access. It is desirable to set to prohibit the background refresh operation.

  FIG. 152 is a circuit diagram of a core control circuit in active / refresh interlock control. The core control circuit 1085 is provided for each bank. Therefore, the control for each bank is distinguished by the bank selection signal bnkz <#> and the refresh bank selection signal ref_bnkz <#>. First, in the selected bank (bnkz <#> = H), the RS flip-flop FF1 of the timing control circuit 1190 is set in response to the active pulse signal actpz = H via the NAND gate 1520, and the active state signal rasz is set. Set to H level to activate the core.

  On the other hand, in the refresh selection bank (ref_bnkz <#> = H), the RS flip-flop FF1 is set in response to the active pulse signal actpz = H via the NAND gate 1521, and the active state signal rasz is set to H level. Activate the core. At the same time, the RS flip-flop FF3 in the refresh control circuit 1191 is also set through the NAND gate 1522 in response to the active pulse signal actpz = H, and sets the refresh active state signal ref_rasz to the H level. The refresh operation starts when the active state signal rasz is H level, and in response to the sense amplifier activation signal saonz = H, the RS flip-flop FF1 is reset by the refresh precharge pulse signal ref_prepz = H, and the precharge operation is started. Done. At the same time, the RS flip-flop FF3 is reset.

  FIG. 153 is a circuit diagram of an address latch circuit in active / refresh interlock control. This circuit is also provided in each bank. In the address latch circuit 1084, in the selected bank (bnkz <#> = H), the latch circuit 1200 latches the external address az <13: 0> in response to the active pulse signal actpz = H. On the other hand, in the refresh selection bank (ref_bnkz <#> = H), the latch circuit 1200 latches the refresh address ref_az <13: 0> of the refresh address counter 1083 in response to the active pulse signal actpz = H. Even in response to the normal refresh pulse signal refpz = H, the latch circuit 1200 latches the refresh address ref_az <13: 0>. The rest is the same as FIG.

  As described above, in response to the normal active command, the normal active operation and the background refresh operation are executed in parallel with a preset bank combination.

[Control by the number of refresh blocks]
Next, the control by the refresh block number RBC in the present embodiment will be described. In the background refresh operation of this embodiment, in addition to the refresh burst length RBL that defines the number of refresh cycles, the number of blocks (number of word lines) RBC that are simultaneously activated in one refresh cycle can be set. .

  By increasing the number of refresh blocks RBC, it is possible to execute refresh for many refresh addresses at the same time. Therefore, when the period in which the background refresh can be performed is short, it is desirable to set the refresh block number RBC large. On the other hand, at the same time as the number of refresh blocks RBC is increased, a refresh operation is performed on many word lines, increasing instantaneous power consumption. Therefore, if the period during which the background refresh is possible is long, it is desirable to set the refresh block number RBC as small as possible. Therefore, the memory controller sets the refresh block number RBC to an optimum value in accordance with the background refreshable period and the power consumption conditions.

  FIG. 154 is a configuration diagram of the bank circuit. As described with reference to FIG. 108, each bank 92 includes a refresh address counter 1083, an address latch circuit 1084, a memory cell array 1086M and a row decoder 1086D constituting a core circuit. The memory cell array 1086M has four sets of blocks RBLK0-3 each including a memory cell array MCA0-3 and sense amplifier column pairs SA00,01 to SA30,31. Since the four sets of blocks RBLK0-3 all have a sense amplifier array SA, they can be simultaneously activated to perform a refresh operation. Then, one or both of the upper 2 bits of the count value REF_A <13: 0> of the refresh address counter 1083 are degenerated (both inverted and non-inverted addresses are H level) by the mode setting value modez <1: 0>. As a result of this degeneration, the row address RA <13: 0> input to the row decoder 1086D activates the four blocks RBLK0-3 simultaneously, activates two blocks simultaneously, or activates one block. It becomes an address that enables operation.

  FIG. 155 is a diagram illustrating control of memory blocks in the core according to the number of refresh blocks. When the number of refresh blocks RBC = 1 (modez <1: 0> = 00), in response to the background refresh command BREN, the word line WL of the memory block RBLK0 to be refreshed in the core is driven to perform the refresh operation. Is called. When the number of refresh blocks RBC = 2 (modez <1: 0> = 01), the word lines WL of the two memory blocks RBLK0 and 2 to be refreshed in the core are driven in response to the background refresh command BREN. A refresh operation is performed. When the number of refresh blocks RBC = 4 (modez <1: 0> = 11), in response to the background refresh command BREN, the four memory blocks RBLK0,1,2,3 to be refreshed in the core The word line WL is driven and a refresh operation is performed.

  FIG. 156 is a circuit diagram of the address latch circuit. As shown in the truth table in the figure, the number of word lines activated simultaneously by signals modez <0> to <1> for setting the number of refresh blocks RBC set in the mode register is 1, 2, or 4. .

  The address latch circuit 1084 has a latch group 1564 that latches the non-inverted signal and inverted signal of the upper 2 bits of the 14-bit row address, and a latch group 1565 that latches the lower 12 bits of the address. Then, in response to the active pulse signal actpz, the latch group 1564 latches the non-inverted signals of the external addresses az <13> and <12> and the inverted signals by the inverters 1566 and 1567. Similarly, the latch group 1564 latches the non-inverted signals of the refresh addresses REF_A <13> and <12> and the inverted signals by the inverters 1568 and 1569 in response to the refresh pulse signal refpz. However, in response to the mode register setting signals modez <0>, <1>, the NAND gates 1560 to 1563 reduce both the non-inverted signal and the inverted signal of the refresh address REF_A <13>, <12> to the H level. The Thereby, the word lines of a plurality of memory blocks can be driven simultaneously.

  FIG. 157 is a circuit diagram of a predecoder circuit in the row decoder. A part of the predecoder circuit is shown. This predecoder circuit selects the four memory blocks by combining the non-inverted signal raz <12>, <13> of the upper 2 bits row address and the inverted signals rax <12>, <13> A signal rblkz <3: 0> is generated. The operation of this predecoder circuit is shown in the table in the figure.

  The operations of FIGS. 156 and 157 are as follows.

First, when RBC = 1, modez <0> = modez <1> = 0,
raz <13> is in phase with REF_A <13>, rax <13> is the opposite phase of REF_A <13>
raz <12> is in phase with REF_A <12> and rax <12> is out of phase with REF_A <12>. Then, the predecoder circuit 1086D selects one of the four blocks RBLK and activates one word line WL.

Next, when RBC = 2, modez <0> = 1, modez <1> = 0,
raz <13> is High, rax <13> is also High, raz <12> is in phase with REF_A <12>, and rax <12> is in reverse phase with REF_A <12>. Then, the predecoder circuit 1086D selects two of the four blocks RBLK and activates the two word lines WL.

Finally, if RBC = 4, modez <0> = 1, modez <1> = 1,
raz <13> is High, rax <13> is also High, raz <13> is High, rax <13> is also High
It becomes. Then, four of the four RBLKs are selected by the predecoder circuit 1086D and the four word lines WL are activated.

  This is the end of the description of the memory device having the background refresh function. Next, a memory controller that controls the memory device to perform a background refresh operation will be described.

[Memory controller that controls background refresh]
In order for the memory device to execute the background refresh function, the memory controller needs to provide the memory device with the background refresh command BREN, the refresh bank information SA, and the refresh burst length RBL. Further, it is desirable that the memory controller also provides the refresh block number RBC to the memory device. Therefore, a memory controller that controls background refresh will be described below.

  FIG. 158 is a configuration diagram of a memory system having a background refresh function. The image processing device 81 outputs a horizontal access or rectangular access request to the two-dimensionally arranged image data to the memory controller 82, and the memory controller 82 controls access to the memory device 86. The image processing device 81 outputs an access type signal ATYP, an image address ADR, an image size signal SIZE, and a read / write signal RWX together with an access request signal REQ to the memory controller 82, and the memory controller 82 receives an acknowledge signal ACK. Send back. Also, write data or read data is transferred by the data bus DATA while the strobe signal STB is asserted.

  Based on the access request from the image processing device 81 and various information, the memory controller 82 stores the background refresh command, the refresh bank information SA, the refresh burst length RBL, and the refresh block number RBC in the memory device 86 in the case of horizontal access. In addition, the active command CMD, the bank address BA, the row address RA, the read or write command CMD, the bank address BA, and the column address CA corresponding to horizontal access are output to the memory device 86. A similar signal corresponding to the rectangular access is output to the memory device 86. The memory controller 82 outputs the write data DQ to the memory device 86 in the write access, and inputs the read data DQ from the memory device 86 in the read access.

  FIG. 159 is a diagram illustrating an example of memory mapping. In the figure, the relationship between the memory mapping 12 and various information received by the memory controller 82 from the image processing device 81 is shown. This memory mapping 12 corresponds to frame image data composed of 2048 pixels in total, 64 pixels in the X direction and 32 pixels in the Y direction. A block of 8 × 8 pixels is associated with a page area specified by the bank address BA and the row address RA. Each pixel has, for example, 1-byte image data. In the page area, odd rows are associated with bank addresses BA0 and BA1, and even rows are associated with bank addresses BA2 and BA3.

In such a memory map 12, the upper left pixel corresponds to the image address ADR = 0x000, POSX, POSY = 0,0, and the rightmost pixel in the first row is the image address ADR = 0x03F, POSX, POSY = 0. , 63, the pixel at the left end of the 32nd row corresponds to the image address ADR = 0x7C0, POSX, POSY = 31,0. In this case, the image address ADR can be represented by position information POSX and POSY of the upper left pixel of the access area. In other words, for the 12-bit image address ADR [11: 0]
POSY [5: 0] = ADR [11: 6], POSX [5: 0] = ADR [5: 0]
become. Therefore, the memory controller 82 can obtain the position information POSX and POSY of the upper left pixel of the access area from the image address ADR received from the image processing device 81. In the example of FIG. 159, since the vertical direction is 32 pixels, the position information POSY [5: 0] in the vertical direction may be 5 bits.

Next, the horizontal size SIZEX and the vertical size SIZEY of the access area are supplied by an image size signal SIZE and an access type signal ATYP, respectively. In other words,
SIZEX = SIZE, SIZEY = ATYP
It is. For horizontal access, SIZEY = ATYP = 0_0000b is supplied, and for rectangular access, SIZEY = ATYP is an arbitrary value other than 0. Therefore, the memory controller 82 can distinguish between horizontal access and rectangular access depending on whether the access type signal ATYP is 0 or not.

  FIG. 160 is a diagram showing the top pixel address and size information in horizontal access and rectangular access. In the case of horizontal access (A), the head pixel address ADR and the size are SIZEX = SIZE and SIZEY = ATYP = 0 as shown in the figure. In the case of rectangular access (B), the head pixel address ADR and the size are SIZEX = SIZE and SIZEY = ATYP as shown in the figure.

  Furthermore, the memory controller 82 can also obtain the bank address BA and row address RA of the first pixel in the access area based on the memory map 12 from the position information POSX and POSY of the upper left pixel in the access area. The memory controller 82 can also discriminate whether or not to access a plurality of banks from the position information POSX and POSY of the upper left pixel of the access area and the size information SIZE and ATYP.

  Further, the memory controller 82 can obtain the number of pixels to access the memory device from the size information SIZE, ATYP, and further, clock cycles necessary for transferring at least data of the number of pixels to and from the image processing device. It can be determined that the next memory access request does not occur during the number of periods. Then, the memory controller 82 can obtain the refresh burst length RBL in the background refresh from such a period, or can obtain the refresh block number RBC.

  FIG. 161 is a configuration diagram of the memory controller. The memory controller 82 includes a horizontal access determination unit 1610, a refresh burst length RBL calculation unit 1611, an active bank number generation unit 1612, a background refresh bank number generation unit 1613, a memory interface 1614, a control unit 1615 therein. These constitute one sequencer SEQ of the plurality of sequencers SEQ shown in FIG. Therefore, a plurality of sequencers SEQ shown in FIG. 161 are provided corresponding to a plurality of access sources.

  First, the horizontal access determination unit 1610 determines whether or not the access type signal ATYP indicating the vertical size SIZEY is “0” by the first comparator CMP1. The first comparator CPM1 outputs “1” if ATYP = 0. Further, the horizontal access determination unit 1610 determines whether the size signal SIZE indicating the size SIZEX in the horizontal direction exceeds the clock number MEMREF of one refresh cycle by the second comparator CMP2. The second comparator CMP2 outputs “1” if SIZE ≧ MEMREF. Therefore, if the outputs of both comparators are “1”, the AND gate outputs a background refresh enable signal “1”, and requests the controller 1615 to issue a background refresh command. The clock number MEMREF is set in a register in the memory controller, for example.

  Next, the refresh burst length RBL calculation unit 1611 calculates the refresh burst length RBL in the background refresh. Specifically, the number of possible refresh cycles can be obtained by dividing the horizontal size SIZE by the number of clocks MEMREF. This division is performed by the bit shift circuit SFT. The refresh burst length RBL is output to the memory device as 0 to 15 or 1 to 16 by the address terminal A [7: 4], for example, as shown in FIGS.

  The active bank number generation unit 1612 includes an adder ADD, a third comparator CMP3, a decoder DEC0, a selector SEL0, and a decoder DEC1. The decoder DEC1 converts an input signal into an output signal with reference to the table. The active bank number generation unit 1612 obtains a bank address corresponding to the access area based on the size signal SIZE and the image address ADR supplied from the image processing apparatus. This bank address BA [1: 0] indicates the bank number to be output together with the active command.

  FIG. 163 is a chart for explaining the decoder DEC0 and the selector SEL0 of the active bank number generation unit. In the active bank number generation unit 1612, the adder ADD adds the lower 3 bits ADR [2: 0] of the image address ADR and the size signal SIZE which is the horizontal size. The lower 3 bits ADR [2: 0] of the image address ADR are the lower 3 bits of the position information POSX = ADR [5: 0] in the horizontal direction of the first pixel, and are 8 × 8 of the memory map 12 shown in FIG. This is information indicating the pixel position in the page area of the pixel. The comparator CMP3 determines whether or not the value obtained by adding the horizontal size SIZE to the lower 3 bits ADR [2: 0] of the image address ADR exceeds “8”. In this case, only one bank is accessed and only one bank needs to be activated. If this is exceeded, a plurality of page areas are accessed by horizontal access, so two banks need to be activated. Then, an output indicating whether one bank or two banks of the comparator CMP3 is active and the fourth bit of the position information of the first pixel in the access area are ADR [9] = POSY [3], ADR [3] = POSX [ 3], the decoder DEC0 outputs selection control signals 0 to 7 for the selector SEL0.

In the memory map of FIG. 159, since each page area is composed of 8 × 8 pixels, ADR [9] = POSY [3], ADR [3] = 4th bit of the position information POSX, POSY of the top pixel The relationship between POSX [3] and bank address BA [1: 0] is as follows.
ADR [9] = POSY [3], ADR [3] = POSX [3] = 0,0 BA [1: 0] = 0,0 (Bank BA0)
ADR [9] = POSY [3], ADR [3] = POSX [3] = 0,1 BA [1: 0] = 0,1 (Bank BA1)
ADR [9] = POSY [3], ADR [3] = POSX [3] = 1,0 BA [1: 0] = 1,0 (Bank BA2)
ADR [9] = POSY [3], ADR [3] = POSX [3] = 1,1 BA [1: 0] = 1,1 (Bank BA3)
Further, in the memory map different from that in FIG. 159, the relationship with the bank address is different.

  FIG. 163 shows the decoder DEC0 corresponding to the combination of the output SIZE + ADR [2: 0] of the adder ADD and ADR [9] = POSY [3], ADR [3] = POSX [3]. Output signals (SEL0 selection control signals 0 to 7) are shown. Further, FIG. 163 also shows input terminals ACTBA0 to ACTBA0 to SEL0 that are selected in response to the output signal of the decoder DEC0 (SEL0 selection control signals 0 to 7).

  In other words, the decoder DEC0 has four combinations of ADR [9] = POSY [3] and ADR [3] = POSX [3] for SIZE + ADR [2: 0] not exceeding 8 and exceeding Output "0" to "7". As described above, the four combinations of ADR [9] = POSY [3] and ADR [3] = POSX [3] are associated with the bank address where the first pixel of the access area is located. When SIZE + ADR [2: 0] does not exceed 8, only one bank needs to be active. When SIZE + ADR [2: 0] exceeds 8, it is necessary to activate two banks.

  161 is selected by a selector SEL0 that selects a value set in ACTBA0 to 7 of the register 543 and a selector SEL0 according to a selection signal composed of outputs 0 to 7 of the decoder DEC0. The decoder DEC1 converts the set values of ACTBA0 to ACTBA7 of the register 543 into the active bank number ACT_BA [1: 0] with reference to the table Table.

  FIG. 164 is a chart for explaining the meanings of values 000b to 111b that can be set in ACTBA of the register 543. “B” means binary notation. The set values 000b to 011b correspond to the case where the active bank that is actively operated corresponding to the access area is BA0 to 3, and the set values 100b, 101b, 110b, and 111b are the active banks BA0 & 1, BA0 & 2, BA2 & 3, BA1 & 3, respectively. This corresponds to the case. In contrast to the banks activated by these normal memory operations, the background refresh target bank depends on the memory map Map 1 and 2, and whether the background refresh is executed in two banks or one bank. As shown in FIG. That is, it is as follows.

  If the active bank is BA0 (set value 000b), the refresh bank is BA2 & 3 (Map1) or BA1 & 3 (Map2) in 2-bank refresh, and BA2 (Map1) or BA1 (Map2) in 1-bank refresh.

  In the case of the active bank BA1 (set value 001b), the refresh bank is BA2 & 3 (Map1) or BA0 & 2 (Map2) in the two-bank refresh, and BA3 (Map1) or BA0 (Map2) in the one-bank refresh.

  In the case of the active bank BA2 (set value 010b), the refresh bank is BA0 & 1 (Map1) or BA1 & 3 (Map2) in 2-bank refresh, and BA0 (Map1) or BA3 (Map2) in 1-bank refresh.

  For the active bank BA3 (set value 011b), the refresh bank is BA0 & 1 (Map1) or BA0 & 2 (Map2) in 2-bank refresh, and BA1 (Map1) or BA2 (Map2) in 1-bank refresh.

  If the active bank is BA0 & 1 (set value 100b), the refresh bank is BA2 & 3 (Map1) in the 2-bank refresh, and BA2or3 (Map1) in the 1-bank refresh. Memory map Map2 is out of scope.

  In the case of the active bank BA0 & 2 (set value 101b), the refresh bank is BA1 & 3 (Map2) in 2-bank refresh, and BA1or3 (Map2) in 1-bank refresh. Memory map Map1 is out of scope.

  In the case of the active bank BA2 & 3 (set value 110b), the refresh bank is BA0 & 1 (Map1) in 2-bank refresh, and BA0or1 (Map1) in 1-bank refresh. Memory map Map2 is out of scope.

  In the case of the active bank BA1 & 3 (set value 111b), the refresh bank is BA0 & 2 (Map2) in the 2-bank refresh, and BA0or2 (Map2) in the 1-bank refresh. Memory map Map1 is out of scope.

  By defining the setting value in the register 543 in this way, eight cases corresponding to the outputs 0 to 7 of the decoder DEC0 depending on the memory mapping adopted by the system and whether it is 2-bank refresh or 1-bank refresh. The active bank number ACT_BA [1: 0] and the background refresh bank numbers BR_BA [1: 0] and BR_A [3: 0] corresponding to can be arbitrarily set.

  FIG. 165 is a diagram showing a conversion table of the decoder DEC1. An active bank is associated with outputs (inputs of DEC1) 0 to 7 of the selector SEL0. This correspondence is also shown in FIG. Therefore, the operation of the decoder DEC1 corresponding to the example of the register setting value will be described.

  FIG. 166 is a chart showing a conversion operation of the decoder DEC1 corresponding to the first example of the register setting value. The register setting value of the first example corresponds to the memory map Map1, and “01234466” is set to the eight input terminals of the selector SEL0. Accordingly, the decoder DEC1 refers to the table of FIG. 165 and corresponds to the output value “01234466” of the selector SEL0 selected corresponding to the selection signal of the selector SEL0 (the output signal of the decoder DEC0), as shown in FIG. Output (DEC1 Output). For the selector output value “0123”, one bank is selected, and for the selector output value “4466”, two banks are selected.

  FIG. 167 is a chart showing the conversion operation of the decoder DEC1 corresponding to the second example of the register set value. The register setting value of the second example corresponds to the memory map Map2, and “01235577” is set to the eight input terminals of the selector SEL0. Accordingly, the decoder DEC1 generates the output (DEC1 Output) shown in FIG. 167 with reference to the table in FIG. 165, corresponding to the output value “01235577” of the selector SEL0. Also in this case, one bank is selected for the selector output value “0213”, and two banks are selected for the selector output value “6677”.

  Next, the background refresh bank number generation unit 1613 in FIG. 161 backs the selector SEL1 for selecting the set value set in BRBA0 to 3 of the register 543 with the lower 2 bits of the output of the selector SEL0, and the selector output. And a decoder DEC2 for converting the bank numbers to BR_BA [1: 0] and BR_A [3: 0]. This background refresh target bank number BR_BA [1: 0] corresponds to the case where two banks are refreshed, and corresponds to, for example, the bank address BA [1: 0] in FIG. Further, the background refresh target bank number BR_A [3: 0] corresponds to the case where one bank is refreshed, and corresponds to, for example, the address terminal A [3: 0] in FIG.

  FIG. 168 is a chart showing the operation of the selector SEL1. Using the lower 2 bits of the selector SEL0 as a selection signal, the value of BRBA0-3 set in the register 543 is selected.

  FIG. 169 is a chart showing a conversion table of the decoder DEC2. The decoder input (DEC2 Input) is a value 0 to 7 that can be set in the register 543 corresponding to BRBA0 to BRBA3, and the value “0, 1, 2, 3” corresponds to 1 bank refresh, and each bank 0 Corresponds to refreshing ~ 3. The values “4” and “6” correspond to the 2-bank refresh in the case of the map Map1, and correspond to refreshing the banks 0 & 1, 2 & 3, respectively. The values “5” and “7” correspond to the 2-bank refresh in the case of the map Map2 and correspond to refreshing the banks 0 & 2, 1 & 3, respectively. In this case as well, an arbitrary value can be set in the register 543 in accordance with the memory maps Map1 and Map2 and in accordance with the 1-bank refresh or 2-bank refresh.

  FIG. 170 shows the operation of the decoder DEC2 in the case of the first register set value. This example is applied to 2-bank refresh in the memory map Map1, and BRBA0 to 3 are "6644" in the first register setting value. These set values are selected by the selector SEL1 in accordance with the lower 2 bits of the output of the selector SEL0, and the decoder DEC2 refers to the conversion table (FIG. 169) and determines the background refresh bank number BA [1: 0] is output. That is, if the input of the decoder DEC2 is “6”, the bank Bank2 & 3 is refreshed, and if it is “4”, the bank Bank0 & 1 is refreshed.

  FIG. 171 is a diagram illustrating the operation of the decoder DEC2 in the case of the second register set value. This example is applied to the two-bank refresh in the memory map Map2, and BRBA0 to 3 are "7755" in the second register setting value. These set values are selected by the selector SEL1 in accordance with the lower 2 bits of the output of the selector SEL0, and the decoder DEC2 refers to the conversion table (FIG. 169) and determines the background refresh bank number BA [1: 0] is output. That is, if the input of the decoder DEC2 is “7”, the bank Bank1 & 3 is refreshed, and if it is “5”, the bank Bank0 & 2 is refreshed.

  FIG. 172 is a diagram illustrating the operation of the decoder DEC2 in the case of the third register set value. This example is applied to one bank refresh in the memory map Map1, and BRBA0 to 3 are "2301" in the third register set value. These set values are selected by the selector SEL1 in accordance with the lower two bits of the output of the selector SEL0, and the decoder DEC2 refers to the conversion table (FIG. 169) and refers to the background refresh bank number A [3: 0] is output. That is, the banks Bank2, 3, 0, 1 are refreshed corresponding to the input of the decoder DEC2 corresponding to “2, 3, 0, 1”.

  FIG. 173 is a diagram illustrating the operation of the decoder DEC2 in the case of the fourth register set value. This example is applied to one-bank refresh in the memory map Map2, and BRBA0 to 3 are "1302" in the fourth register setting value. These set values are selected by the selector SEL1 in accordance with the lower two bits of the output of the selector SEL0, and the decoder DEC2 refers to the conversion table (FIG. 169) and refers to the background refresh bank number A [3: 0] is output. That is, the banks Bank1,0, 3, and 2 are refreshed corresponding to the input of the decoder DEC2 corresponding to "1, 3, 0, 2".

  As described above, there are at most four combinations of banks to be refreshed with respect to the active banks by the normal access operation. Therefore, the input of selector SEL1 is limited to four. However, the refresh bank corresponding to the active bank is selected by selecting one of the four inputs of selector SEL1 with the lower two bits of the output value of selector SEL0. Can be generated.

  Returning to FIG. 161, the background refresh mode signal BRMD is input to the control unit 1615. This mode signal BRMD is a signal indicating whether 4 bank refresh, 2 or 1 bank refresh, and is set in the register 543. When the mode signal BRMD is 4-bank refresh, the background refresh operation is prohibited.

  In response to the background refresh enable signal BR_EN, the control unit 1615 supplies selection signals S2, S3, S4 corresponding to the command to the selectors 2, 3, 4 when outputting BREN, ACT, etc. to the command CMD. To do. When the background refresh enable signal BR_EN is at the H level, the control unit 1615 causes the selector SEL2 to select the refresh burst length RBL_A [7: 4] and the selector SEL3 to select the background refresh bank number BR_BA when the command BREN is output. [1: 0] is selected, and the selector SEL4 is caused to select the background refresh address BR_A [3: 0]. As a result, the refresh burst length RBL is output from the address terminal A [7: 4], and the background refresh bank number BR_BA [1: 0] is output from the bank address terminal BA [1: 0]. Then, the controller 1615 causes the selector SEL2 to select other A [7: 4], the selector SEL3 to select the active bank number ACT_BA [1: 0], and the selector 4 to select other when the command ACT is output. Let A [3: 0] be selected. As a result, the normal address A [7: 4] is sent from the address terminal A [7: 4], and the selected bank address BA [1: 0] to be activated is sent from the bank address terminal BA [1: 0]. Is output.

  FIG. 162 is an operation timing chart of the memory controller. In this example, the image processing apparatus 81 outputs the image address ADR = 0x0000, the size signal SIZE = 32, the access type signal ATYP = 000b, and the read / write signal RWX = H while asserting the access request signal REQ from the clock number 3. Then, the 32-byte read data DATA is input in 32 clock cycles while asserting the strobe signal STB from the clock number 22.

  On the other hand, the memory controller 82 starts from the image address ADR = 0x0000, the size signal SIZE = 32, and the access type signal ATYP = 000b, and the image data start pixel position POSX, POSY = 0,0, active bank ACT_BA = BA0, BA1, row It is determined that the access is horizontal such as addresses RA0, A1 and column address CA0, and that background refresh is performed for banks BR_BA = BA2, BA3 with a refresh burst length RBL = 4. Then, the memory controller 82 outputs the background refresh command BREN, the refresh banks BA2, 3 and the refresh burst length RBL = 4 at the clock number 6 to the memory device, and further, the active command ACT and the bank address BA0 at the clock number 8. The row address RA0 is output, the active command ACT, the bank address BA1, and the row address RA1 are output at the clock number 10, and subsequently, the read command RD, the bank address BA0, and the column address CA0 are output, and the read command RD, Bank address BA1 and column address CA0 are output, and precharge command PER, bank address BA0, precharge command PER, and bank address BA1 are output. The burst length BL of each read command is 8. Therefore, the memory controller outputs two more sets of the above commands ACT, RD, and PRE. As a result, 32-byte data d0 to d31 are received from the data terminal DQ of the memory device. Then, the memory controller outputs the data d0 to d31 to the image processing apparatus in 32 clock cycles from the clock number 22.

The memory controller 82 outputs an appropriate refresh block number RBC to the memory together with the register set command EMRS, and sets it in the register in the memory. In this case, the memory controller 82 determines the refresh burst length RBL from the number of clock cycles necessary for data transfer obtained from the size signal SIZE in consideration of the refresh block number RBC. Further, the memory controller 82 can output the refresh burst length RBL to the memory together with the register set command EMRS and set it to the register in the memory.
<Parameter input method>
In the foregoing, various access and refresh functions have been described for memory devices that store two-dimensional arrangement data such as image data. In this case, parameters necessary for realizing various functions are input from the memory controller to the memory device. The method for inputting this parameter will be described below.

  FIG. 174 is a diagram showing the start byte signal SB in the byte boundary. As already described, in the byte boundary, the start byte signal SB indicating the first byte in the memory unit area composed of 4 bytes is input to the memory device. In FIG. 173, when an area 1740 that crosses two adjacent page areas selected by the banks 0 and 1 and the row address RA5 is an access target, a start byte signal SB = 2 is supplied to the memory device. As a result, within the page area of bank 0 and row address RA5, out of 4 byte data B0 to B3 selected by column address CA7, 2 byte data B2 and B3 and page area of bank 1 and row address RA5 Of the 4 byte data B0 to B3 selected by the column address CA4, the 2 byte data B0 and B1 are associated with the input / output terminals, and the 4 byte data is input / output. This association of 4-byte data corresponds to the case where the memory map 12 is in the up mode. In the down mode, the association of 4-byte data is different.

  In the memory device, in order to calculate the column address CA4 of the adjacent page area from the column address CA7 of the access area 1740, step number data CST = 4 of the column address in the page area is set in the register in advance.

  FIG. 175 is a diagram illustrating a relationship between the second information BMR of the byte combination data and the first information SB (start byte). In the upper half of FIG. 175, the second information BMR corresponds to the up mode, and in the lower half, the second information BMR corresponds to the down mode. Each of them indicates a combination of 4 bytes associated with an input / output terminal corresponding to the start byte SB = 0-3. The up mode is as shown in FIG. In the down mode, the 4-byte array in the 4-byte area is the reverse of the up mode. Accordingly, the combination of the start byte SB and the 4 bytes associated with the input / output terminals has an inverse relationship with the up mode. This second information BMR is also input to the memory device and set as necessary.

  FIG. 176 shows a row address step RS. In the multi-bank access, the memory device obtains the remaining bank address and row address based on the bank address and row address in the upper left page area of the rectangular access area 1760. Therefore, step information RS of the row address is necessary as information of the memory mapping 12. Therefore, the memory device inputs the step information RS of the row address and sets it in the register as necessary. In the case of the rectangular access area 1740, the bank address BA3 and the row address RA1 are given together with the active command. In the case of 4-bank access (multi-bank information SA ′ = 4), the row addresses RA2, RA5, RA6 is required.

  FIG. 177 is a diagram showing the memory mapping information AR. In the figure, two types of memory mapping are shown. For example, AR = 0 for type A and AR = 1 for type B are input to the memory device and set in the register. In multi-bank access, an access target bank is calculated based on the memory mapping information AR. Also in the background refresh, a refresh target bank is obtained based on the memory mapping information AR. In type A, odd-numbered rows are composed of banks 0 and 1, even-numbered rows are composed of banks 2 and 3, and in type B, odd-numbered rows are composed of banks 0 and 2 and even-numbered rows are composed of banks 1 and 3. The row address RA is the same. The example of FIG. 176 is a case of type A.

  FIG. 178 is a diagram showing the refresh burst length RBL and the refresh block number RBC in the background refresh. In the background refresh, the refresh operation is repeated the number of times of the refresh burst length RBL in response to the command, and each refresh operation is performed in parallel on the blocks having the refresh block number RBC. FIG. 178 (A) shows an example of RBC = 2 and RBL = 6, and refresh is performed with a total of 12 word lines in 6 refreshes. FIG. 178B is an example of RBC = 3 and RBL = 4. In this case as well, refresh is performed with a total of 12 word lines in four refreshes. FIG. 178C is an example of RBC = 4 and RBL = 3. In this case as well, refresh is performed with a total of 12 word lines in three refreshes.

  As described above, each memory device needs to input necessary parameters in order to realize various accesses. There are two methods for inputting this parameter, such as a method using a dedicated input terminal and a method using an address input terminal that is not used. The parameter input method differs depending on whether the memory device has a single data rate or a double data rate. The parameter input method also differs depending on whether the address is a multiple input (multiplex system) or a non-multiple input (non-multiplex system). These will be described below.

  FIG. 179 is a diagram showing the configuration of a dedicated input terminal, its input buffer, and mode register in the memory device. The parameter signal input to the dedicated input terminal SP is input to the dedicated input buffer 1790, the signal 1792 latched there is set in the mode register 1791, and the set signal 1793 is supplied to an internal circuit (not shown). However, when the function corresponding to the parameter signal (byte boundary function, multi-bank access function, background refresh function) is disabled, the corresponding parameter needs to be set to the default value.

  Therefore, in accordance with the enable signal 1794 indicating whether the function is enabled or disabled, the input parameter is set in the mode register 1791 if enabled, and a default value is set in the mode register 1791 as a parameter if disabled. The input buffer 1790 takes in the signal from the dedicated input terminal SP when the enable signal 1794 is enabled, and the output signal 1792 is clamped at the H level when disabled. Therefore, when disabled, it is not necessary to connect the dedicated input terminal SP and the input buffer 1790 with a bonding wire.

  FIG. 180 is a diagram showing a configuration of a dedicated input terminal, its input buffer, and a mode register in the memory device. Here, an example in which the start byte SB, the multi-bank information SA ′, and the refresh bank information SA are input from the dedicated terminal SP as an example among various parameters is shown.

  A 2-bit start byte SB is input from the dedicated terminal SP0, taken into the input buffer 1790-0, and set in the mode register 1791-0. Setting to the mode register 1791-0 is performed in response to the mode register set pulse MRSPZ. However, when the enable signal 1800 is disabled, the mode register 1791-0 is set to a default value (SB = 0, start byte = 0), and the output of the input buffer 1790-0 is clamped. This enable signal 1800 is supplied from a mode register MRS, a bonding option, a fuse circuit, etc. (not shown).

  Similarly, 2-bit multi-bank information SA 'is input from the dedicated terminal SP1, is taken into the input buffer 1790-1, and is set in the mode register 1791-1. Setting to the mode register 1791-1 is performed in response to the mode register set pulse MRSPZ. When the enable signal 1801 is disabled, the value of the mode register is set to a default value (SA ′ = 0, only one bank is selected), and the output of the input buffer is clamped as described above.

  Similarly, the 2-bit refresh bank information SA is also input from the dedicated terminal SP2 and set in the mode register 179102. When the enable signal 1802 is disabled, the value of the mode register is set to the default value (SA = 3, all banks are selected) as described above, and the output of the input buffer is clamped. Each of these 2-bit information SB, SA ', SA is inputted in parallel from two dedicated terminals. Alternatively, it may be input serially from one dedicated terminal.

  FIG. 181 is a diagram illustrating an example of a mode register. In this example, the aforementioned parameters are input from the address terminal and set in the mode register. In the figure, mode register areas 1810, 1811 and 1812 are shown. The input values and set values of the address terminals A0 to A6 are shown corresponding to the combination of the bank addresses BA0 and BA1, and the rising edge RiseEdge and falling edge FallEdge of the synchronous clock.

  First, when the bank address BA0 = 0, BA1 = 0 is input together with the mode register set command MRS, the burst length input from the address terminals A0-A2 and the address terminal are input to the mode register 1810 at the rising edge RiseEdge of the clock. The read latency input from A3-A5 is set, and the write recovery value input from address terminals A0-A2 is set at the falling edge FallEdge.

  Next, when the bank address BA0 = 1, BA1 = 0 is inputted together with the mode register set command MRS, values (illustrated) inputted from the address terminals A0-A5 at the rising edge RiseEdge of the clock are inputted to the mode register 1811. Byte shift function flag BS input from address terminals A0 to A4, second information BMR of byte combination information, multibank function flag MB, background refresh function flag BR, memory mapping at falling edge FallEdge respectively set Information AR is set. Although only the information indicating whether these are enabled or disabled is illustrated, the byte shift information SB, the multi-bank information SA ′, the refresh bank information SA, the refresh block number RBC, and the like are designated as described above. It is also possible to set information in the mode register.

  Further, when the bank address BA1 = 0, BA1 = 1 is input together with the mode register set command MRS, the row address step information RS input from the address terminals A0-A5 is input to the mode register 1812 at the rising edge RiseEdge of the clock. The row address step information RS input from the address terminals A0 to A5 is also set at the falling edge FallEdge.

  Note that the mode register area when the bank address BA0 = 1, BA1 = 1 is used for setting during the test. Table 1813 shows a normal mode register MRS and an extended mode register EMRS for combinations of bank addresses BA0 and BA1. Further, Tables 1814 to 1819 show values of address terminals A0 to A6 in the mode register area 1811 and respective set values.

  FIG. 182 is a diagram illustrating an example of the enable signal generation circuit. FIG. 182 (A) shows enable signal generation circuits 1820 and 1821 set by the bonding option. The enable signal generation circuit 1820 includes a bonding option terminal 1825, a power supply terminal Vdd, and a ground terminal Vss. By connecting the bonding option terminal 1825 and the power supply terminal Vdd with a bonding wire, the enable signal 1794 becomes Vdd. Enable special access features. On the other hand, the enable signal generation circuit 1821 connects the bonding option terminal 1825 and the ground terminal Vss with a bonding wire, so that the enable signal 1794 becomes Vss and disables the access function.

  FIG. 182 (B) shows enable signal utterance circuits 1822 and 1823 set by the fuse FS. The enable signal utterance circuit 1822 includes a power supply Vdd, a ground power supply Vss, a resistor R1, and a fuse FS. By blowing the fuse FS, the enable signal 1794 becomes Vdd and is enabled. The enable signal utterance circuit 1823 is disabled because the enable signal 1794 becomes Vss by not blowing the fuse FS.

  FIG. 183 is a diagram illustrating an input method in a single data rate (SDR). In this example, parameters are input from dedicated terminals (Special Pin 0, 1). In the figure, (A) is synchronized with the rising edge of the clock CLK (solid line), together with the background refresh command BREN, the bank address BA0 and BA1 are input from the bank address terminal, and the refresh bank information SA0 and SA1 are input from the dedicated terminal, respectively. Is done. In FIG. 6B, in synchronization with the rising edge of the clock CLK, the bank address BA0 and BA1 are input from the bank address terminal and the multi-bank information SA′0 and SA′1 are input from the dedicated terminal, together with the active command ACT. The (C) in the figure, in synchronization with the rising edge of the clock CLK, the bank address BA0, BA1 is input from the bank address terminal, and the start byte information SB0, SB1 is input from the dedicated terminal together with the read or write command RD / WR. The Although not shown, parameters such as RBL, RBC, AR, RST, and CS are input from a dedicated terminal together with the extended mode register set command EMRS in synchronization with the rising edge of the clock CLK.

  FIG. 184 is a diagram illustrating an input method at a double data rate (DDR). This example is also an example in which parameters are input from a special terminal (Special Pin). The relationship between each command and parameter is the same as in FIG. In FIG. 184, since it is a double data rate, bank addresses BA0, 1 and parameters SA0, SA1, SA′0, SA′1, SB0, SB1 are input in synchronization with the rising edge and falling edge of the clock. .

  Next, a method for inputting parameters from an unused address terminal without using a dedicated terminal will be described.

  FIG. 185 is a diagram illustrating an input method in the ADQ multiplex input method. In the ADQ multiplex input method, an address input terminal and a data input / output terminal are constituted by a common terminal, an address is input together with a command, and data is subsequently input / output. If the number of data terminals is larger than the number of address terminals, parameters can be input from the common terminal together with the address when a command is input.

  FIG. 185 (A) shows an input circuit configuration, in which a common terminal ADQ (A / DQ0 to A / DQ20, 21 bits) and a data terminal DQ (DQ21 to DQ31, 11 bits) are provided, and the common terminal ADQ is an address. The data terminal DQ is used only by the data. Therefore, parameters can be input using this data terminal DQ. The common terminal ADQ is connected to the address buffer 1850 and the input / output buffer 1852-0, and is connected to the address latch circuit 1851 and the memory cell 1853-0, respectively. The data terminal DQ is connected to the dedicated buffer 1854 and the input / output buffer 1852-1, and is connected to the mode selector 1855 and the memory cell 1853-1, respectively.

  FIG. 185B shows a timing chart and is an example of SDR. First, together with the write command WR, a 21-bit address ADD is input from the common terminal ADQ, and a parameter SP is input from the data terminal DQ. The address ADD is input to the address buffer 1850 and the parameter SP is input to the dedicated buffer 1854. After 3 clocks from the command WR, 32-bit data is input from the common terminal ADQ and the data terminal DQ. If the command is a read command RD, data is output. The parameters SP input together with the command are, for example, multibank information SA ', refresh bank information SA, start byte SB, and the like.

  In the ADQ multiplex, the active command and the write command are not input in a time division manner as in the SDRAM, but the row and column addresses are input at a time together with the command, and then the data is input / output. Therefore, when an address is input together with a command, a parameter can be input from an unused data terminal DQ.

  FIG. 186 is a diagram illustrating an input method in the address multiplex input method. The address multiplex input method is an input method such as SDRAM, where the address terminal Add is shared by the row address and the column address, and the row address and the column address are input from the common address terminal Add in the RAS cycle and CAS cycle, respectively. However, if the number of row addresses is larger than the number of column addresses due to the configuration of the memory cell array, parameters can be input from address terminals that are not used during the CAS cycle. For example, the start byte SB is input in the CAS cycle.

  FIG. 186 (A) shows an input circuit configuration, and address terminals Add (Add0 to 7 and 8 bits) are connected to address buffers 1850-0 and 1850-1, which are respectively connected to a row address latch circuit 1851-0 and a column. It is connected to the address latch circuit 1851-1. The address terminal Add (Add8 to 13, 6 bits) is connected to an address buffer 1850-2 and a start byte buffer 1860, which are connected to a row address latch circuit 1851-2 and a start byte selector circuit 1861, respectively. The

  FIG. 186B shows a timing chart and is an example of SDR. First, a 14-bit row address RA is input from the address terminals Add [7: 0] and Add [13: 8] together with the active command ACT in the RAS cycle, and 8 bits together with the read or write command RD / WR in the CAS cycle. Column address CA is input from address terminal Add [7: 0], and start byte SB [1: 0] is input from one of address terminals Add [13: 8].

  FIG. 187 is a diagram illustrating an input method in the address multiplex method at the double data rate (DDR). In the RAS cycle in which the active command ACT is input, a 14-bit row address RA is input from the address terminals Add [7: 0] and Add [13: 8] in synchronization with the rising edge of the clock, and the falling edge of the clock The parameter SP is input from the address terminals Add [7: 0] and Add [13: 8] in synchronization with the above. The parameter SP is, for example, row address step information RS, memory map information AR, multibank information SA ′, and the like.

  Further, in the CAS cycle in which the read or write command RD / WR is input, the 8-bit column address CA is input from the address terminal Add [7: 0] in synchronization with the rising edge of the clock, and at the falling edge of the clock. In synchronization, the parameter SP is input from any one of the address terminals Add [7: 0]. The parameter SP is, for example, a start byte SB, column address step information CST, access rectangle size information (W, H), byte combination second information BMR (UP, DOWN, ALL, EVEN, ODD).

  In the case of the DDR and address multiplex system, since the input timing is four times in total, parameters can be input using an unused address terminal.

  FIG. 188 is a diagram illustrating an input method in the address multiplex method at the double data rate (DDR). In this example, the number of address terminals is reduced to 8-bit Add [5: 0] and Add [7: 6]. In the DDR and address multiplex systems, there are four input timings, so there are still unused address terminals even if the address terminals are reduced in this way. Therefore, parameters can be input from the unused address terminals.

  First, in the RAS cycle in which the active command ACT is input, the 8-bit row address RA is input from the address terminals Add [5: 0] and Add [7: 6] in synchronization with the rising edge of the clock, and the rising edge of the clock. In synchronization with the falling edge, a 6-bit row address RA is input from the address terminal Add [5: 0], and the parameter SP is input from the address terminal Add [7: 6]. The parameter SP is, for example, multibank information SA ′, row address step information RS, memory map information AR, and the like.

  In addition, in a CAS cycle in which a read or write command RD / WR is input, an 8-bit column address CA is input from address terminals Add [5: 0] and Add [7: 6] in synchronization with the rising edge of the clock. The parameter SP is input from one of the address terminals Add [5: 0] and Add [7: 6] in synchronization with the falling edge of the clock. The parameter SP is, for example, a start byte SB, column address step information CST, access rectangle size information (W, H), byte combination second information BMR (UP, DOWN, ALL, EVEN, ODD).

  As described above, parameters necessary for realizing special functions such as byte boundary access, multi-bank access, and background refresh can be input from a dedicated terminal or from an unused address terminal. An optimum parameter input method corresponding to the input method of the memory device is selected.

  The above embodiment is summarized as follows.

(Appendix 1)
A plurality of banks each having a memory core including a memory cell array and selected by a bank address;
A memory device comprising: a control circuit for causing a memory core in a refresh target bank to continuously perform a refresh operation corresponding to the refresh burst length information in response to a background refresh command and refresh burst length information.

(Appendix 2)
In a memory device that operates in response to a command from a memory controller,
A plurality of banks each having a memory core including a memory cell array and selected by a bank address;
In response to a background refresh command, the memory core in the refresh target bank set by the memory controller continuously executes the refresh operation for the number of refresh burst lengths set by the memory controller, and the refresh target While the memory core in the bank is executing the refresh operation, in response to the normal operation command, the normal operation command is sent to the memory core in the bank other than the refresh target bank and selected by the bank address. And a control circuit that executes a normal memory operation corresponding to the memory device.

(Appendix 3)
In Appendix 2,
Further, each of the plurality of banks or each of the plurality of sets of the plurality of banks has a refresh address counter that counts refresh target addresses in the corresponding banks,
The control circuit is
A background refresh control unit that outputs a refresh control signal to the set refresh target bank in response to the background refresh command;
A refresh burst length register in which the refresh burst length is set;
Provided in each of the plurality of banks and in response to the background refresh control signal, the memory core performs a refresh operation for the address of the refresh address counter by the number of refresh burst lengths set in the refresh burst length register. A memory device comprising: a core controller to be executed.

(Appendix 4)
In Appendix 2,
A refresh block number indicating the number of memory blocks activated simultaneously in one refresh cycle is supplied,
In response to the background refresh command, the control circuit causes the refresh target bank to perform a refresh operation for simultaneously activating the memory blocks having the number of refresh blocks for the set number of refresh burst lengths. A memory device.

(Appendix 5)
In Appendix 3,
The refresh burst length is input simultaneously with the background refresh command, the refresh burst length register is provided corresponding to the bank, and the input refresh burst length is set in the refresh burst length register in the refresh target bank. A memory device.

(Appendix 6)
In Appendix 4,
In addition, it has a refresh block number register,
Enter the number of refresh blocks simultaneously with the background refresh command,
The memory device, wherein the inputted number of refresh blocks is set in the refresh block number register.

(Appendix 7)
In Appendix 3,
The refresh burst length register is provided in a mode register;
Enter the refresh burst length simultaneously with the mode register setting command,
A memory device in which the inputted refresh burst length is set in a refresh burst length register in the mode register.

(Appendix 8)
In Appendix 4,
A refresh block number register is provided in the mode register,
Enter the number of refresh blocks at the same time as the mode register setting command.
A memory device in which the number of input refresh blocks is set in a refresh block number register in the mode register.

(Appendix 9)
In Appendix 3,
The core controller responds to a newly input background refresh command during the refresh burst length times, and the refresh target is the number of times the refresh burst length is added to the remaining number of refresh operations. A memory device characterized by causing a memory core in a bank to continuously execute the refresh operation.

(Appendix 10)
In Appendix 3,
The core controller responds to a newly input background refresh command during the refresh burst length times refresh operation, regardless of the remaining number of refresh operations, the refresh burst length times, A memory device characterized by causing a memory core in a target bank to continuously execute the refresh operation.

(Appendix 11)
In Appendix 3,
In response to a refresh all command, the core controller causes a memory core in the refresh target bank to repeatedly perform a refresh operation from an address in the refresh address counter to a remaining address.

(Appendix 12)
In Appendix 3,
The memory device, wherein the core controller stops the refresh operation in the memory core in the refresh target bank in response to a background refresh stop command during the refresh operation of the refresh burst length.

(Appendix 13)
In Appendix 12,
In response to the background refresh stop command, the core controller does not start the next refresh operation after the memory core in the refresh target bank ends the refresh operation being executed. apparatus.

(Appendix 14)
In Appendix 3,
Based on the setting of the active refresh interlock flag in the mode register, the background refresh control unit responds to the normal memory operation command to the background refresh in a bank other than the access target bank corresponding to the input bank address. A memory device that supplies a control signal.

(Appendix 15)
In Appendix 3,
The core controller has a refresh burst length counter that counts up for each refresh operation,
The core controller resets the refresh burst length counter in response to the background refresh command, and until the counter value of the refresh burst length counter reaches the refresh burst length set in the refresh burst length register. A memory device characterized by causing a memory core in a refresh target bank to execute the refresh operation.

(Appendix 16)
In Appendix 3,
The core controller has a refresh burst length counter that counts down for each refresh operation,
In response to the background refresh command, the core controller sets the refresh burst length in the refresh burst length counter, and the memory in the refresh target bank until the counter value of the refresh burst length counter reaches zero. A memory device, characterized by causing a core to perform the refresh operation.

(Appendix 17)
In a memory device that operates in response to a command from a memory controller,
A plurality of banks each having a memory core including a memory cell array and selected by a bank address;
A control circuit for controlling the operation of the memory cell array in the bank,
Based on memory mapping in which a memory logical space has a plurality of page areas selected by the bank address and row address, the plurality of page areas are arranged in a matrix, and adjacent page areas are associated with different bank addresses The plurality of banks store two-dimensional array data,
In a horizontal access period in which the two-dimensional array data is accessed in the horizontal direction, the control circuit responds to a normal operation command corresponding to the horizontal access to a memory core in the bank selected by the bank address. A memory device for executing a normal memory operation corresponding to the normal operation command and causing a memory core in a refresh target bank other than the horizontal access target bank to execute a refresh operation in response to a background refresh command; .

(Appendix 18)
In Appendix 17,
In the rectangular access period for accessing the two-dimensional array data to an arbitrary rectangular area, the control circuit responds to the normal operation command to the bank selected by the bank address and the selected bank. A memory device characterized by causing a memory core in an adjacent bank to execute the normal memory operation and prohibiting a refresh operation during the normal memory operation.

(Appendix 19)
A memory controller;
A memory device that operates in response to a command from the memory controller;
The memory device includes:
A plurality of banks each having a memory core including a memory cell array and selected by a bank address;
In response to a background refresh command, the memory core in the refresh target bank set by the memory controller continuously executes the refresh operation for the number of refresh burst lengths set by the memory controller, and the refresh target While the memory core in the bank is executing the refresh operation, in response to the normal operation command, the normal operation command is sent to the memory core in the bank other than the refresh target bank and selected by the bank address. And a control circuit for executing a normal memory operation corresponding to the memory system.

(Appendix 20)
In a memory controller for controlling a memory device having a plurality of banks each having a memory core including a memory cell array and selected by a bank address, and a control circuit for controlling the operation of the memory cores in the plurality of banks,
In response to an access request from the host device, a normal operation command corresponding to the access request is supplied to the memory device together with a bank address, and the normal operation is performed on the memory core in the normal access target bank selected by the bank address. Has a sequencer to execute
In response to the access request, the sequencer supplies refresh memory information specifying a bank other than the bank to be accessed normally and a refresh burst length specifying the number of refresh operations to the memory device together with a background refresh command. Then, during the normal operation, the memory controller in the refresh target bank corresponding to the refresh bank information continuously performs the refresh operation for the number of times of the refresh burst length.

(Appendix 21)
In Appendix 20,
In response to the access request, the sequencer determines whether or not the background refresh command can be issued based on information indicating the access target data area. If the background refresh command can be issued, the sequencer determines the access target data area. A memory controller, wherein the refresh bank information and the refresh burst length are obtained based on the indicated information.

(Appendix 22)
In Appendix 21,
And a register in which memory map information for associating the two-dimensional arrangement data with the memory space and bank number information for executing the refresh operation in response to the background refresh command are set.
The memory controller, wherein the sequencer obtains the refresh bank information and a refresh burst length based on setting information of the register in addition to information indicating the access target data area.

(Appendix 23)
A memory controller;
A memory device that operates in response to a command from the memory controller;
The memory device includes:
Each having a memory core including a memory cell array and having a plurality of banks selected by bank addresses;
Based on memory mapping in which a memory logical space has a plurality of page areas selected by the bank address and row address, the plurality of page areas are arranged in a matrix, and adjacent page areas are associated with different bank addresses The plurality of banks store two-dimensional array data,
Further, during a horizontal access period in which the two-dimensional array data is accessed in the horizontal direction, in response to a normal operation command, a normal memory corresponding to the normal operation command is sent to the memory core in the bank selected by the bank address. A memory system comprising: a control circuit for executing an operation and causing a memory core in a refresh target bank other than the horizontal access target bank to execute a refresh operation in response to a background refresh command.

(Appendix 24)
In Appendix 23,
In the rectangular access period for accessing the two-dimensional array data to an arbitrary rectangular area, the control circuit responds to the normal operation command to the bank selected by the bank address and the selected bank. A memory system characterized by causing a memory core in an adjacent bank to execute the normal memory operation and prohibiting a refresh operation during the normal memory operation.

(Appendix 25)
In a memory controller for controlling a memory device having a plurality of banks each having a memory core including a memory cell array and selected by a bank address, and a control circuit for controlling the operation of the memory cores in the plurality of banks,
Based on memory mapping in which a memory logical space has a plurality of page areas selected by the bank address and row address, the plurality of page areas are arranged in a matrix, and adjacent page areas are associated with different bank addresses The plurality of banks store two-dimensional array data,
In response to an access request from the host device, it is determined that the access request is a horizontal access for accessing the two-dimensional array data in the horizontal direction, and a normal operation command corresponding to the horizontal access is sent to the memory together with a bank address. A sequencer that supplies the device and causes the memory core in the horizontal access target bank selected by the bank address to perform normal operation;
In response to the access request, the sequencer supplies refresh memory information specifying a bank other than the horizontal access target bank to the memory device together with a background refresh command, so that the refresh bank A memory controller that causes a memory core in a refresh target bank corresponding to information to perform a refresh operation.

(Appendix 26)
In Appendix 25,
When the access request is a rectangular access for accessing the two-dimensional array data to an arbitrary rectangular area, a normal operation command corresponding to the rectangular access is supplied to the memory device together with a bank address, A memory controller characterized by causing a memory core in an access target bank selected by a bank address to perform a normal operation and not issuing the background refresh command during the normal memory operation.

10: Display device 12: Memory mapping 14, 14E: Memory unit area 15: Image memory 22: Rectangular area
SA: refresh bank information SB, BMR: byte combination information SB: first information (start byte information) BMR: second information (UP, DOWN, AL)
SA ′: Multi-bank information RS: Row address step number data CST, CAWrap: Column address step number data RS: Row address step number data 81: Access source block 82: Memory controller 86: Memory device RBL: Refresh burst length RBC: Refresh Number of blocks AR: Memory mapping information

Claims (6)

In a memory device that operates in response to a command from a memory controller,
A plurality of banks each having a memory core including a memory cell array and selected by a bank address;
A control circuit for controlling the operation of the memory cell array in the bank,
The memory logical space has a plurality of page areas selected by the bank address and the row address, the plurality of page areas are arranged in a matrix, and adjacent page areas are associated with different bank addresses, and the first bank Based on the memory mapping in which the first page region group assigned to the address is arranged in the first row and the second page region group assigned to the second bank address is arranged in the second row, The plurality of banks store two-dimensional array data;
The control circuit responds to a normal operation command corresponding to the horizontal access during a horizontal access period in which one of the first and second rows is accessed in the horizontal direction for the two-dimensional array data. The memory core in the bank selected by the bank address is caused to execute a normal memory operation corresponding to the normal operation command, and the bank address assigned to the other row of the first and second rows is set to the refresh target bank. In response to a background refresh command notified as a bank address, the memory core in the refresh target bank is caused to perform a refresh operation ,
Further, the control circuit responds to the normal operation command during the rectangular access period for accessing the two-dimensional array data to an arbitrary rectangular area and the selected bank and the selected bank. to the memory core in the banks adjacent to the bank, the normal to perform memory operations, the memory device characterized that you prohibit the refresh operation in the normal during memory operation. In a memory device that operates in response to a command from a memory controller,
A plurality of banks each having a memory core including a memory cell array and selected by a bank address;
A control circuit for controlling the operation of the memory cell array in the bank,
Based on memory mapping in which a memory logical space has a plurality of page areas selected by the bank address and row address, the plurality of page areas are arranged in a matrix, and adjacent page areas are associated with different bank addresses The plurality of banks store two-dimensional array data,
In a horizontal access period in which the two-dimensional array data is accessed in the horizontal direction, the control circuit responds to a normal operation command corresponding to the horizontal access to a memory core in the bank selected by the bank address. Causing a normal memory operation corresponding to the normal operation command to be executed, and in response to a background refresh command, causing a memory core in a refresh target bank other than the horizontal access target bank to execute a refresh operation;
In the rectangular access period for accessing the two-dimensional array data to an arbitrary rectangular area, the control circuit responds to the normal operation command to the bank selected by the bank address and the selected bank. A memory device characterized by causing a memory core in an adjacent bank to execute the normal memory operation and prohibiting a refresh operation during the normal memory operation. A memory controller;
A memory device that operates in response to a command from the memory controller;
The memory device includes:
Each having a memory core including a memory cell array and having a plurality of banks selected by bank addresses;
The memory logical space has a plurality of page areas selected by the bank address and the row address, the plurality of page areas are arranged in a matrix, and adjacent page areas are associated with different bank addresses, and the first bank Based on the memory mapping in which the first page region group assigned to the address is arranged in the first row and the second page region group assigned to the second bank address is arranged in the second row, The plurality of banks store two-dimensional array data;
Furthermore, the two-dimensional array data is stored in the bank selected by the bank address in response to a normal operation command during a horizontal access period in which one of the first and second rows is accessed in the horizontal direction. A background refresh command for causing a memory core to perform a normal memory operation corresponding to the normal operation command and notifying a bank address assigned to the other of the first and second rows as a bank address of a refresh target bank In response to the normal operation command in a rectangular access period in which the memory core in the refresh target bank executes a refresh operation, and the two-dimensional array data is accessed to an arbitrary rectangular area. To the bank selected by the bank address and the selected bank. Memory system, characterized in that the memory core in the bank that is in contact, the normal to perform memory operations, a control circuit you prohibit the refresh operation in the normal during memory operation. A memory controller;
A memory device that operates in response to a command from the memory controller;
The memory device includes:
Each having a memory core including a memory cell array and having a plurality of banks selected by bank addresses;
Based on memory mapping in which a memory logical space has a plurality of page areas selected by the bank address and row address, the plurality of page areas are arranged in a matrix, and adjacent page areas are associated with different bank addresses The plurality of banks store two-dimensional array data,
Further, during a horizontal access period in which the two-dimensional array data is accessed in the horizontal direction, in response to a normal operation command, a normal memory corresponding to the normal operation command is sent to the memory core in the bank selected by the bank address. A control circuit for executing an operation and causing a memory core in a refresh target bank other than the horizontal access target bank to perform a refresh operation in response to a background refresh command;
In the rectangular access period for accessing the two-dimensional array data to an arbitrary rectangular area, the control circuit responds to the normal operation command to the bank selected by the bank address and the selected bank. A memory system characterized by causing a memory core in an adjacent bank to execute the normal memory operation and prohibiting a refresh operation during the normal memory operation. In a memory controller for controlling a memory device having a plurality of banks each having a memory core including a memory cell array and selected by a bank address, and a control circuit for controlling the operation of the memory cores in the plurality of banks,
The memory logical space has a plurality of page areas selected by the bank address and the row address, the plurality of page areas are arranged in a matrix, and adjacent page areas are associated with different bank addresses, and the first bank Based on the memory mapping in which the first page region group assigned to the address is arranged in the first row and the second page region group assigned to the second bank address is arranged in the second row, The plurality of banks store two-dimensional array data;
In response to an access request from a host device, it is determined that the access request is a horizontal access in which one of the first and second rows is accessed in the horizontal direction from the two-dimensional array data, and the horizontal A sequencer for supplying a normal operation command corresponding to access to the memory device together with a bank address, and causing a memory core in a horizontal access target bank selected by the bank address to perform a normal operation;
In response to the access request, the sequencer supplies a bank address assigned to the other one of the first and second rows as a bank address of a refresh target bank to the memory device together with a background refresh command. During the normal operation, the memory core in the refresh target bank is caused to perform a refresh operation ,
Further, when the access request is a rectangular access for accessing the two-dimensional array data to an arbitrary rectangular area, the sequencer supplies a normal operation command corresponding to the rectangular access to the memory device together with a bank address. Thus, the memory core in the access target bank selected by the bank address performs a normal operation, and the background refresh command is not issued during the normal memory operation . In a memory controller for controlling a memory device having a plurality of banks each having a memory core including a memory cell array and selected by a bank address, and a control circuit for controlling the operation of the memory cores in the plurality of banks,
Based on memory mapping in which a memory logical space has a plurality of page areas selected by the bank address and row address, the plurality of page areas are arranged in a matrix, and adjacent page areas are associated with different bank addresses The plurality of banks store two-dimensional array data,
In response to an access request from the host device, it is determined that the access request is a horizontal access for accessing the two-dimensional array data in the horizontal direction, and a normal operation command corresponding to the horizontal access is sent to the memory together with a bank address. A sequencer that supplies the device and causes the memory core in the horizontal access target bank selected by the bank address to perform normal operation;
In response to the access request, the sequencer supplies refresh memory information specifying a bank other than the horizontal access target bank to the memory device together with a background refresh command, so that the refresh bank Causing the memory core in the refresh target bank corresponding to the information to perform a refresh operation,
The sequencer, the case of the rectangular access that the access request to access said two-dimensional array data to any rectangular area supplies a normal operation command corresponding to the rectangular access to the memory device along with the bank address, A memory controller characterized by causing a memory core in an access target bank selected by the bank address to perform a normal operation and not issuing the background refresh command during the normal memory operation.