JP5454291B2 - Nonvolatile memory device and nonvolatile memory - Google Patents

Description

  The present invention relates to a non-volatile memory such as a flash memory, and a non-volatile storage device such as a memory card or a memory module including a non-volatile memory and a controller.

  In recent years, a memory card as a non-volatile storage device equipped with a NAND type flash memory which is a rewritable non-volatile memory has expanded its market as a storage medium for digital cameras and mobile phones.

  Further, since the storage capacity of the nonvolatile storage device is increased as the semiconductor device is miniaturized at the same time, the price of the gigabyte band is lower than that of the HDD. Along with this, the application has been expanded to in-vehicle applications such as PND (Portable Navigation Device).

  However, the expansion of applications for in-vehicle applications means the expansion of use in more severe voltage environments. In other words, use is made at a voltage outside the voltage range of the NAND flash memory specification.

  Generally, a memory card is composed of a NAND type flash memory and a controller. In order to solve the problems that occur in the voltage range specified in the specification, measures are taken from each of the flash memory and the controller.

  Moreover, flash memory is a general-purpose component and can be procured in the market. Therefore, the combination of flash memory and controller is infinite. Therefore, in order to protect the data in the flash memory, a voltage detection circuit is mounted in the flash memory. A voltage detection circuit in the flash memory determines whether the voltage can operate the flash memory. Depending on the determination result of the voltage detection circuit, the flash memory stops internal operations and protects data from destruction.

  Furthermore, in order to protect the data in the flash memory, the controller applies a voltage to the flash memory for a certain period when the voltage supplied to the controller decreases (see, for example, Patent Document 1).

JP 10-133961 A

  As described above, measures are taken against power supply fluctuations in the flash memory and the controller, but no measures are taken as a whole memory card system. For this reason, when viewed as a memory card system, a problem may occur.

  In addition, regarding the data protection of the flash memory by the voltage detection circuit of the flash memory itself, the controller is in a state where normal operation is not guaranteed by the determination result of the voltage drop in the voltage detection circuit during writing / erasing of the data of the flash memory. There is no mechanism to recognize this. Therefore, the controller side determines that the processing of the flash memory is normal, resulting in a malfunction.

  The parameters required for flash memory processing are changing due to the miniaturization of the flash memory process. Specifically, there are an increase in time required for the erasing process and an increase in current consumption required for the erasing process. Therefore, when the voltage is guaranteed in the controller, the absolute time for which the voltage is to be guaranteed becomes longer and the amount of current to be supplied is also increased. Therefore, it has become difficult to guarantee the voltage on the controller side.

  An object of the present invention is to avoid occurrence of a malfunction by a controller correctly recognizing an operation state caused by a voltage fluctuation in a flash memory.

In order to achieve this object, a nonvolatile memory of the present invention is a nonvolatile memory including a memory cell array, a read / write control unit, an external interface unit, a power supply voltage detection unit, and a status holding unit, The status held in the status holding unit indicates that the first state indicating that data cannot be written to and erased from the nonvolatile memory, and that data can be written to and erased from the nonvolatile memory. Any of the second states shown can be read from the outside of the non-volatile memory through the external interface unit, and the voltage applied to the non-volatile memory in the power supply voltage detection unit is lower than a predetermined voltage value. when it is detected that the lower, held in the status holding unit of the first state as a status Even after the voltage applied to the non-volatile memory is higher than the predetermined voltage value, holding a first state as a status to the status memory.

  According to the present invention, the controller reads out the state of the nonvolatile memory with respect to the decrease in the voltage applied to the nonvolatile memory from the nonvolatile memory, so that the nonvolatile memory and the controller perform processing based on the same recognition. Therefore, it is possible to realize a highly reliable nonvolatile memory device that can avoid the occurrence of.

The figure which showed the structure of the non-volatile memory of Embodiment 1. The figure which showed the structure of the non-volatile memory device of Embodiment 1. The figure which showed the structure of the controller of the non-volatile memory device of Embodiment 1. The figure which showed the state transition of the non-volatile memory of Embodiment 1 Flowchart of write processing of nonvolatile storage device of embodiment 1 The figure which shows the applied voltage to the non-volatile memory device of Embodiment 1, and the timing chart of an internal state

(Embodiment 1)
The nonvolatile memory device according to Embodiment 1 will be described with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a nonvolatile memory. The flash memory 101 is a nonvolatile memory that stores data in a nonvolatile manner. The external interface unit 102 is an interface that exchanges data read / write data and control signals with respect to the flash memory 101 with a controller outside the flash memory 101. The flash memory cell array 103 includes a plurality of memory cells that store data in a nonvolatile manner in the flash memory 101. The buffer memory 104 is located between the external interface unit 102 and the flash memory cell array 103. The buffer memory 104 is used when writing data to the flash memory cell array 103 from a controller outside the flash memory 101 to the flash memory cell array 103, or reading data written to the flash memory cell array 103 and outputting the data to the outside of the flash memory 101. Save data temporarily. The read / write control unit 105 understands the command input from the controller outside the flash memory 101 via the external interface unit 102 and controls the flash memory cell array 103 to read, write, and erase data with respect to the memory cell. The power supply voltage detection unit 106 is a circuit that detects the level of the voltage applied to the flash memory 101 with respect to a predetermined level. The predetermined level is a lower limit level of a voltage range in which the flash memory 101 can operate normally. The reset unit 107 resets the operation in the flash memory 101 when the power supply voltage drops below a predetermined level based on the detection result of the power supply voltage detection unit 106. By doing so, erroneous writing is avoided. The power status holding unit 108 holds information indicating whether or not the power supply voltage applied to the flash memory 101 by the power supply voltage detection unit 106 has dropped below a predetermined level. The power status holding unit 108 can be referred to from the outside of the flash memory 101 via the external interface unit 102.

  Although not shown in detail, an actual flash memory requires another configuration including a booster circuit, but is not shown here because it is not directly related to the present invention.

  FIG. 2 is a diagram showing the configuration of the nonvolatile memory device of this embodiment. The flash memory 101 has the internal configuration shown in FIG. The memory card 201 includes a flash memory 101 and a controller 202. The controller 202 is connected to a host device outside the memory card 201, a memory card interface 203, a ground line 204, a flash memory power line 205, and a controller power line 206. The controller 202 is connected to the flash memory 101 and the flash memory interface 207. The flash memory interface 207 includes a chip enable signal CE, a command enable signal CLE, an address enable signal ALE, a write enable signal WE, a read enable signal RE, a data bus IO1 to 8, a ready busy signal R / B, and a write protect signal WP. The power and ground of the flash memory 101 are connected to the outside of the memory card 201 as a flash memory power line 205 and a ground line 204, respectively. From the outside of the memory card 201, 1.8V from the controller power supply line 206 and 3.3V from the flash memory power supply line 205 are applied. A controller power supply line 205 connected to the controller 202 is used as a power supply for the flash memory interface 207 with the flash memory 101.

  FIG. 3 is a diagram showing the configuration of the controller 202. The controller 202 includes a control unit 301, a flash memory control unit 302, a host interface unit 303, a buffer memory 304, and a controller voltage detection unit 305.

  Although not shown in detail, the actual controller requires another configuration including an ECC circuit, but is not shown individually because there is no direct relationship with the present embodiment.

  The control unit 301 controls the entire controller 202. The flash memory control unit 302 has a flash memory interface 207 and controls the flash memory 101. The flash memory control unit 302 transfers data to be read from the flash memory 101 and data to be written to the flash memory 101 from the buffer memory 304. The host interface unit 303 has a memory card interface 203 and controls communication with a host device outside the memory card 201. The host interface unit 303 transfers data to be written to the memory card 201 from the host device and data to be read to the memory card 201 from the buffer memory 304. The controller voltage detection unit 305 determines whether or not the voltage level of the controller power supply line 206 applied to the controller 202 satisfies a specified level. For example, the detection level of the controller voltage detection unit is set to 1.6 V with respect to the supply voltage 1.8 V from the controller power supply line 206.

  FIG. 4 is a diagram showing transition of the internal status of the flash memory 101. The status inside the flash memory 101 is a status held in the power status holding unit 108. When a voltage is applied to the memory card 201, the status becomes “PowerOn” status. In this state, the controller 202 can recognize that the status is “PowerOn” by issuing a status read command to the flash memory 101. In the “Power On” status, the external interface unit 102 of the flash memory 101 does not operate ignoring the write / erase command from the controller 202.

  When the controller 202 issues a state transition command to the flash memory 101, the flash memory 101 transits from the “Power On” status to the “Normal” status. The external interface unit 102 of the flash memory 101 operates without ignoring the write / erase command from the controller 202 on the condition that the status is “Normal” and writing is not prohibited by the write protect signal WP. To do.

  When the voltage applied from the flash memory power supply line 205 decreases to a predetermined voltage or lower in the “Normal” status, the reset unit 107 detects the voltage decrease and resets the operation in the flash memory 101. By this reset, the status in the flash memory 101 changes to “PowerOn”.

  In the “Power On” status, the controller 202 cannot write / erase data to / from the flash memory 101.

  Thereafter, the status does not change even if the voltage applied from the flash memory power supply line 205 rises and becomes higher than the specified voltage.

  Here, the change from the “Normal” status to the “PowerOn” status is the detection of the voltage drop by the reset unit 107. However, the voltage drop may be detected by the reset unit 107 during execution of the write / erase command by the read / write control unit 105 of the flash memory 101. Since the object of the present invention is to correctly recognize the operating state due to voltage fluctuations, it is not always necessary to change the status with respect to a voltage drop during a period in which the operating state does not change.

  Here, in the “PowerOn” status, the write / erase command is ignored. This is a redundant mechanism for protecting data written in the flash memory 101, and is not necessarily an essential function for correctly recognizing an operation state due to voltage fluctuation, which is an object of the present invention. Absent.

  FIG. 5 is a flowchart of data erasing / writing to the flash memory 101 by the controller 202.

  The flash memory cell array 103 is composed of a plurality of physical blocks, and the physical block is composed of a plurality of physical pages. The flash memory 101 uses a data erasing unit as a physical block unit and a data writing unit as a physical page unit.

  Before performing the writing process, the controller 202 sets the status of the flash memory 101 to “Normal”.

  First, in process 501, the controller 202 issues a data erase command to the flash memory 101 by designating a physical block to which data is written.

  In the determination process 502, the controller 202 acquires the status from the flash memory 101 and determines whether the status of the flash memory 101 is “Normal” and whether the erasure process in the process 501 is successful. When the status is “PowerOn”, there is a possibility that the supply voltage of the flash memory power supply line 205 is lower than the specified voltage during the period when the flash memory 101 is erasing data, and the erasing process is not successful. is there. Furthermore, since it may not be possible to correctly determine whether or not the erasure process has succeeded due to a decrease in the supply voltage of the flash memory power supply line 205, the process proceeds to a power-on process.

  When the status is “Normal”, it is understood that the supply voltage of the flash memory power supply line 205 does not decrease during the period when the flash memory 101 is erasing data. At this time, if the deletion process in the process 501 has failed, the process proceeds to the process 506, and if successful, the process proceeds to the process 503.

  In process 503, the controller 202 designates a physical page and issues a data write command to the flash memory 101 in units of physical pages.

  In the determination process 504, the controller 202 acquires the status from the flash memory 101 and determines whether the status of the flash memory 101 is “Normal” and whether the writing process in the process 503 is successful. When the status is “PowerOn”, there is a possibility that the supply voltage of the flash memory power supply line 205 is lower than the specified voltage during the period in which the flash memory 101 is writing data, and the writing process is not successful. is there. Furthermore, since it may not be possible to correctly determine whether or not the writing process is successful due to a decrease in the supply voltage of the flash memory power supply line 205, the process proceeds to a power-on process.

  When the status is “Normal”, it can be seen that the supply voltage of the flash memory power supply line 205 does not decrease during the period in which the flash memory 101 is writing data. At this time, if the writing process in process 501 fails, the process proceeds to process 506, and if successful, the process proceeds to process 503.

  In process 505, the controller 202 determines whether or not unwritten data remains. When there is unwritten data, the controller 202 makes a transition to process 503, and when all data has been written, the process ends. .

  In process 506, the physical block that has failed in the erase or write process is registered to be managed as a defective block, and the process ends in error.

  FIG. 6 is a diagram showing a change in operation inside the memory card 201 with respect to fluctuations in power supply from the outside of the memory card 201. In FIG. 6, the uppermost row shows the power supply voltage applied to the memory card 201 from the controller power supply line 206. The second stage shows the power supply voltage applied to the memory card 201 from the flash memory power supply line 205.

  The “reset period” below is a period in which the reset unit 107 in the flash memory 101 resets the flash memory 101. The “status” below it indicates the status held in the power status holding unit 108 in the flash memory 101. The “state transition command” below it indicates the issuance of a state transition command from the controller 202 to the flash memory 101.

  From time t601, the external host device starts applying a voltage to the memory card 201.

  At time t602, the voltage supplied from the controller power supply line 206 reaches a specified voltage, and the controller 202 starts to operate. When the controller 202 starts to operate, it repeatedly performs a status transition command and status confirmation on the flash memory 101. At the stage of time t602, since the flash memory power supply line 205 is below the detection level of the power supply voltage detection unit 106, the flash memory 101 is in a reset state, and the status of the flash memory 101 is “PowerOn”. Therefore, even if the controller 202 issues a status transition command to the flash memory 101, the status of the flash memory 101 remains in the “PowerOn” state, and the status that the controller 202 reads from the flash memory 101 is naturally “PowerOn”. is there.

  At time t603, since the flash memory power supply line 205 exceeds the detection level of the power supply voltage detection unit 106, the flash memory 101 is not in the reset state, and the status of the flash memory 101 is “Normal” in response to the status transition command from the controller 202. Transition to the state. The controller 202 can also read the status “Normal” from the flash memory 101 and confirm that the flash memory 101 is ready for writing or erasing.

  Thereafter, the controller 202 operates by receiving data write / read commands from / to the memory card 201 from the external host device and erasing / writing / reading data to / from the flash memory 101.

  At time t604, the flash memory power supply line 205 falls below the detection level of the power supply voltage detection unit 106. The flash memory 101 is in a reset state, and the status of the flash memory 101 transitions to “PowerOn”. When erasing or writing to the flash memory 101, the controller 202 confirms that the status of the flash memory 101 has transitioned to “PowerOn” in the determination processing 502 and the determination 504 processing in the flowchart of FIG. Recognize that the previous erase or write may not have been successful.

  The controller repeatedly performs a status transition command and status confirmation on the flash memory 101 in the same manner as when the power is turned on.

  At time t605, the flash memory power supply line 205 exceeds the detection level of the power supply voltage detection unit 106, receives the status transition command from the controller 202, and the status of the flash memory transitions to “Normal”.

  INDUSTRIAL APPLICABILITY The present invention is useful for a nonvolatile memory device with high user convenience that can effectively improve data reliability of the nonvolatile memory device.

DESCRIPTION OF SYMBOLS 101 Flash memory 102 External interface part 103 Flash memory cell array 104 Buffer memory 105 Reading / writing control part 106 Power supply voltage detection part 107 Reset part 108 Power status holding part 201 Memory card 202 Controller 203 Memory card interface 204 Ground line 205 Flash memory power supply line 206 Controller Power line 207 Flash memory interface 301 Control unit 302 Flash memory control unit 303 Host interface unit 304 Buffer memory 305 Controller voltage detection unit

Claims (6)

A non-volatile memory comprising a memory cell array, a read / write control unit, an external interface unit, a power supply voltage detection unit, and a status holding unit,
The status held in the status holding unit indicates that the first state indicating that data cannot be written to and erased from the nonvolatile memory, and that data can be written to and erased from the nonvolatile memory. Any of the second states shown can be read from outside the nonvolatile memory through the external interface unit,
In the power supply voltage detection unit, when it is detected that the voltage applied to the nonvolatile memory is lower than a predetermined voltage value , the first state is held in the status holding unit as a status,
A non-volatile memory that holds the first state as a status in the status holding unit even after a voltage applied to the non-volatile memory becomes higher than a predetermined voltage value. The change in status due to the detection of the voltage value in the power supply voltage detection unit,
The nonvolatile memory is performed only during a period during which data is written and erased.
The non-volatile memory according to claim 1. When the voltage applied to the nonvolatile memory is higher than a predetermined voltage value,
The status of the status holding unit can be changed from the status of the first state as the status of the second state from the outside of the nonvolatile memory,
The nonvolatile memory according to claim 2. The change from the first state to the second state can be performed without lowering the voltage applied to the nonvolatile memory,
The non-volatile memory according to claim 3. The nonvolatile memory further includes a reset unit,
At the timing of changing from the second state to the first state,
The reset unit resets the entire nonvolatile memory,
The non-volatile memory according to claim 3 . A nonvolatile memory device comprising the nonvolatile memory according to any one of claims 1 to 5 and a controller that controls the nonvolatile memory,
The controller is
A command for transitioning to the second state is input to the nonvolatile memory, and the status is read from the nonvolatile memory to confirm that it is in the second state. A non-volatile memory device that performs erasing and writing.

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