JP5445346B2 - LSI power supply cutoff area expansion method and program thereof - Google Patents

Description

  The present invention relates to an LSI power supply cutoff area expansion method and a program thereof.

  In semiconductor integrated circuits (LSIs), increase in power consumption due to leakage current has been regarded as a problem as miniaturization and circuit scale increase in recent years. As a solution to this problem, a power gating method that cuts off the power of a circuit block that is not operating is used. The circuit block whose power is shut off is selected in units of functional blocks, for example, and the power is shut off for the circuit block in the non-operating state.

  The power supply control unit built in the LSI cuts off the power gate in the power cut-off area in accordance with the power cut-off condition, and suppresses power consumption. In order to enable such LSI design, in the LSI design stage, in addition to RTL and netlists, which are hardware description files in HDL (Hardware Description Language), power shutdown areas and power shutdown conditions are defined. A power specification file is generated.

JP 2008-186229 A JP 2009-53989 A JP 2003-281210 A

  Since the power shut-off area is defined in units of functional blocks, there may be areas before and after the power shut-off area, together with the power shut-off area, that do not interfere with the operation of the LSI even if the power is shut off. Since such a region is outside the power shut-off region, power is supplied even when the power is shut off, resulting in leakage power consumption.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for extending a power cut-off area in an LSI and a program therefor.

A first aspect of the power cut-off area extending method is that a computer describes a hardware description file describing a plurality of circuit elements of an integrated circuit and net information for connecting the circuit elements stored in a recording medium, and the internal circuit Inputting a power specification file defining a power domain in which power supply of each of the power supplies is controlled and a power shut-off domain in which the power is shut down under a predetermined condition;
An input port of a latch circuit or an integrated circuit where the computer back traces the net information and the circuit element from the input terminal (A) of the power shutoff domain to the hardware description file and reaches the back trace. Is extracted as the first node (B), and the net information and the circuit element are forward-traced from the output terminal (A ′) of the first isolation cell connected to the output terminal of the power cutoff domain. A first extraction step of extracting, as a second node (B ′), an output port of the latch circuit or integrated circuit that the forward trace reaches,
The computer forward traces the hardware description file from the first node (B), extracts a latch circuit or output port to which the forward trace arrives as a third node (C), and , A second extraction step of back-tracing from the second node (B ′) and extracting a latch circuit or input port reached by the back-trace as a fourth node (C ′);
The computer, with respect to the hardware description file, the first node (of the first combination circuit between the input terminal (A) and the first node (B) of the power-off domain). A third combination circuit excluding the second combination circuit (D) between B) and the third node (C) is extracted, and the first combination circuit connected to the output terminal of the power shut-off domain is further extracted. Among the fourth combinational circuits between the output terminal (A ′) of the isolation cell and the second node (B ′), the second node (B ′) and the fourth node (C ′) A third extraction step of extracting a sixth combinational circuit excluding the fifth combinational circuit (D ′) between
The computer adds the third and sixth combinational circuits to the power cut-off domain for the hardware description file and the power supply specification file, and is connected to the input side of the sixth combinational circuit. And an expansion step of deleting one isolation cell and generating a new second isolation cell on the output side of the sixth combinational circuit.

  According to the first aspect, it is possible to automatically expand the power shut-off area, and to generate a power-saving LSI hardware description file and a power specification file.

It is a figure which shows the power supply cutoff by the power gating method regarding this Embodiment. It is a block diagram of LSI explaining the expansion | extension of the power interruption area | region in this Embodiment. FIG. 3 is a configuration diagram of an LSI in which a power cut-off region in the present embodiment is extended. It is a block diagram of the semiconductor design apparatus in this Embodiment. It is a flowchart figure of the power cutoff area expansion program of this Embodiment. FIG. 6 is a more detailed flowchart of the power cut-off area expansion processing step S1 in FIG. 5. It is a figure explaining extraction process S11 of the path | pass and circuit in connection with a power-supply-cutoff area | region. It is a figure explaining extraction process S12 of a path and a circuit which cannot interrupt a power supply It is a figure explaining extraction process S12 of a path and a circuit which cannot interrupt a power supply It is a figure explaining extraction process S13 of an extended power supply cutoff part. It is a figure explaining isolation cell deletion and reinsertion process S2. It is a figure explaining isolation cell deletion and reinsertion process S2. FIG. 6 is an original circuit diagram before an extension process of a power cutoff region. It is a figure which shows the example of the net list | wrist of the integrated circuit of FIG. It is a figure which shows the example of the power supply specification file of the integrated circuit of FIG. It is a figure which shows the index after performing the power supply interruption area | region expansion process to the integrated circuit of FIG. It is a figure which shows the net list to which the index of FIG. 16 was added. FIG. 14 is a diagram illustrating isolation cell deletion / reinsertion processing into the integrated circuit of FIG. 13. It is a figure which shows the integrated circuit after the power-supply-cutting area | region expansion process was performed to the integrated circuit of FIG. FIG. 20 is a diagram showing a net list of the integrated circuit after the expansion process of FIG. 19. FIG. 20 is a diagram showing a power supply specification file of the integrated circuit after the extension process of FIG. 19.

  FIG. 1 is a diagram showing power shutdown by the power gating method according to the present embodiment. FIG. 1 shows some of the circuits built in the LSI. In the figure, the LSI includes a power supply domain PD2 in which the supply of the power supply VDD is controlled, a latch circuit FF1 including a flip-flop that supplies an input signal to the power supply domain PD2, and a latch circuit FF2 that latches an output signal of the power supply domain PD2. Have The power domain PD2 has a plurality of combinational circuits and a sequential circuit inside, and is connected to the power supply VDD via a P-channel power switch transistor Ppw.

  The LSI further includes a CPU and a power supply control unit PMU. In response to the control from the CPU, the power supply control unit PMU supplies a power cutoff signal PS1 to the gate of the power switch transistor Ppw, and the power cutoff signal PS1. When the transistor Ppw becomes L level, the transistor Ppw becomes conductive and the power supply domain PD2 enters a power supply state. When the transistor Ppw becomes H level, the transistor Ppw becomes nonconductive and the power supply domain PD2 enters a power supply cutoff state.

  The power switch transistor that performs power shutdown may be an N-channel power switch transistor Npw provided between the power domain PD2 and the ground Vss, instead of the transistor Ppw. In that case, when the power shut-off signal PS1 from the power control unit PMU becomes H level, the transistor Npw becomes conductive and the power domain PD2 enters the power supply state, and when it becomes L level, the transistor Npw becomes non-conductive and the power domain PD2 becomes The power is cut off.

  FIG. 2 is a block diagram of an LSI for explaining the extension of the power cutoff region in the present embodiment. The LSI of FIG. 2 has power supply domains PD1 and PD2. The power domain PD1 includes a plurality of combinational circuits CMB and a plurality of sequential circuits, for example, flip-flops FF1 to FF7. Then, the power control unit PMU controls the on / off of the power switch transistor of the power domain PD2 by the power shut-off signal PS1.

  In the LSI shown in FIG. 2, the input signal from the combinational circuit CMB1 in the power supply domain PD1 is supplied to the input terminal IN1 of the power supply domain PD2, and the output terminal OUT1 of the power supply domain PD2 supplies the output signal to another combinational circuit CMB2. To do. Flip-flops FF1 to FF4 are connected to the combination circuit CMB1 on the input side, and flip-flops FF5 to FF7 are connected to the combination circuit CMB2 on the output side.

  On the other hand, when the power supply domain PD2 is turned off, if the output terminal OUT1 enters a high impedance state, a through-leakage current is generated in the subsequent CMOS circuit. In order to avoid this, an isolation cell ISO1 is provided at the output terminal OUT1. This isolation cell ISO1 is an output fixed isolation cell that fixes the logical value, which is its output voltage, to H level or L level in response to an isolation enable signal ISOEN generated by the power control unit PMU when the power is shut off. is there. As will be described later, the isolation cell includes an output fixed isolation cell that fixes an output to a logic value of H or L according to the isolation enable signal, and a logic of the output terminal of the power shutoff domain according to the isolation enable signal. There are latch-type isolation cells that latch values.

  In FIG. 2, the combinational circuit CMB1 on the input side should have a circuit that wastes power by merely supplying a signal to the power domain PD2 when the power domain PD2 is powered off. is there. Similarly, the output combinational circuit CMB2 is also a circuit in which the operation is stopped and the leakage power is consumed wastefully because the output of the isolation cell ISO1 is fixed when the power supply domain PD2 is cut off. There should be.

  FIG. 3 is a configuration diagram of an LSI in which the power cut-off region is expanded in the present embodiment. The power cutoff region expansion method in the present embodiment automatically analyzes the circuits in the LSI, extracts the circuits CMB1-1 and CMB2-1 that operate wastefully when the power source domain PD2 is shut down, and supplies the power cutoff region. And the step S2 of moving the isolation cell connected to the output terminal of the power domain PD2 when the circuit CMB2-1 is combined with the power cutoff region PD2.

  As shown in FIG. 3, first, the combinational circuit CMB1 of FIG. 2 is automatically analyzed, and the combinational circuit CMB1-1 that operates wastefully when the power supply domain PD2 is powered off, and the circuit CMB1- that performs necessary operations. The combinational circuit CMB1-1 that performs a useless operation is combined with the power domain PD2 that is powered off to extend the power cutoff region. Since the output of the combinational circuit CMB1-2 is output to the flip-flop FF4, the operation is not wasteful and is a necessary operation. Therefore, the combinational circuit CMB1-2 is not extracted as an extension region.

  Similarly, the combinational circuit CMB2 in FIG. 2 is automatically analyzed, and the combinational circuit CMB2-1 that operates wastefully when the power domain PD2 is powered off is distinguished from the circuit CMB2-2 that performs the necessary operation. Then, the combinational circuit CMB2-1 that performs useless operation is combined with the power domain PD2 that is powered off to extend the power cutoff area. Since the output of the flip-flop FF5 is input to the input of the combinational circuit CMB2-2, the operation is not wasteful and is a necessary operation. Therefore, the combinational circuit CMB2-2 is not extracted as an extension region.

  Accordingly, the isolation cell ISO1 in FIG. 2 is deleted, and new isolation cells ISO1-2 and ISO1-2 are generated on the output side of the combinational circuit CMB2-1 expanded in FIG. That is, it can be said that the isolation cell ISO1 in FIG. 2 has been moved as the isolation cells ISO1-2 and ISO1-2 in FIG.

  FIG. 4 is a configuration diagram of the semiconductor design apparatus according to the present embodiment. In the semiconductor design device of FIG. 4, a CPU, a memory RAM, an input interface, a communication interface, a graphic processing unit 10, and a hard disk device HDD which is a large-capacity recording medium are connected via a bus. A monitor device is connected to the graphic processing unit 10.

  The recording medium HDD stores the power cut-off area expansion program of the present embodiment, and the CPU executes the program to execute the power cut-off area expansion method of the present embodiment. The recording medium HDD further includes a hardware description file HDL describing a plurality of circuit elements of the LSI and net information for connecting the circuit elements, a plurality of power supply domains in which supply of power in the LSI is controlled, and a predetermined number. A power specification file that defines a power shut-off domain in which power is shut off under conditions, isolation cell insertion information, and the like, and a library containing cell libraries and isolation cell information are stored. These files specify the LSI circuit configuration on which the power shut-off area expansion processing is performed. Then, the power-off area extension program executes the above-described power-off area extension processing for these files, and changes to a file that specifies a new LSI with the extended power-off area.

  Although not shown, the semiconductor design apparatus stores an ordinary LSI design tool as a program in the recording medium HDD, or accesses an LSI design tool stored on the network via a communication interface to perform an LSI design process. Execute. LSI design tools include, for example, a logic synthesis tool that converts RTL level HDL into a netlist, a logic verify tool that checks the logic operation of an LSI described in the netlist, an automatic layout tool, and a timing verification tool. It is.

  FIG. 5 is a flowchart of the power cut-off area expansion program according to this embodiment. The power cut-off area expansion program performs a data input process S0 for inputting the data of the hardware description file 12, the library 14, and the power supply specification file 16 described with reference to FIG. Then, the power shutdown area expansion program next executes a power shutdown area expansion process S1. In this process S1, the LSI circuit configuration specified by the hardware description file 12, the library 14, and the power specification file 16 is automatically analyzed, and when the power domain PD2 described with reference to FIG. The combinational circuits CMB1-1 and CMB2-1 that are operating at the same time are extracted and combined to expand the power cutoff region of the power domain PD2.

  Next, the power shutdown area expansion program executes a power shutdown area extension process S1 and an isolation cell deletion / reinsertion process S2 for deleting and reinserting the necessary isolation cells in accordance with the extension process. Then, the program reflects the change in the integrated circuit configuration by the above processes S1 and S2 in the hardware description file 12X and the power supply specification file 16X, and outputs the data (S3).

  The configuration of the LSI shown in FIG. 3 is specified by the changed hardware description file 12X and power supply specification file 16X. In other words, in the net description and RTL hardware description file 12X, the net information for connecting each circuit element is changed by deleting and reinserting the isolation cell, and the isolation cell is newly defined and its net information is also defined. The In addition, in the power specification file 16X, the combinational circuits CMB1-1 and CMB2-1 expanded as the power cutoff region are added to the power cutoff domain that is newly controlled for power cutoff, and the information of the isolation cell is also changed. The hardware description file 12X and the power supply specification file 16X will be specifically described later.

  FIG. 6 is a more detailed flowchart of the power shut-off area expansion processing step S1 in FIG. As shown here, the power cut-off area expansion process S1 is performed by the power cut-off area being cut off by the back trace from the input terminal of the power supply domain defined in the power cut-off area and the forward trace from the output terminal. Sometimes a path or a circuit related to the input terminal and the output terminal is extracted (S11). Further, out of the extracted paths and circuits, paths and circuits that cannot be powered off together with the power shutdown area are extracted (S12). Then, from the path and circuit extracted in step S11, the path and circuit obtained by removing the path and circuit extracted in step S12 are extracted as an extended power shut-off region (S13).

  Hereinafter, the power cutoff region expansion processing S1 and the isolation cell deletion / reinsertion processing S2 in the present embodiment will be specifically described. The hardware description file 12 is an RTL or a net list. By referring to the library for this file, circuit elements and net information for connecting them can be obtained, and the circuit configuration of the integrated circuit can be specified. it can. The power specification file 16 includes information on a power domain and a power shut-off area where power is controlled, isolation cell insertion information, and the like. Therefore, when a computer, which is a semiconductor design device, inputs these data, which instance, macro pin, and port in the integrated circuit belong to which power domain, and where the isolation cell is inserted. Information can be obtained. Isolation cell information is included in power supply specification files and libraries.

  FIG. 7 is a diagram for explaining the path / circuit extraction step S11 related to the power cutoff region. In FIG. 7, the power domain PD2 is defined as the power shut-off area. In this extraction step S11, an index A is attached to the input terminal of the power shut-off area PD2, nets of the nets and circuit elements are back-traced from the input terminal A, and an index B is attached to the flip-flop or the port when it is reached (S11). -1).

  Similarly, an index A ′ is attached to the output terminal of the isolation cell connected to the output terminal of the power cutoff region. In this case, the isolation cell is limited to the output fixed isolation cell of the AND and OR gates in the upper right in the figure, and the latch type isolation cell that latches the logical value of the output terminal of the power cutoff region PD2 is excluded. This is because the latch-type isolation cell needs to continue to store the latched logic value without being cut off even when the power supply in the power cut-off region PD2 is cut off. Then, the net and the cell are forward traced from the output terminal A ', and when the flip-flop or port is reached, the index B' is attached thereto.

  The combination circuit CMB1-1 and CMB1-2 between the indexes A and B and the combination circuit CMB2-1 and CMB2-2 between the indexes A ′ and B ′ are candidates for power shutdown together with the power shutdown area PD2. It is.

  Of the three types of isolation cells shown in the upper right of FIG. 7, the isolation cell of the AND gate receives the output of the power cutoff domain PD2 and the isolation enable signal ISOEN, and the isolation enable signal ISOEN is at the L level. Sometimes the output is fixed at L level. Also in the isolation cell of the OR gate, the output of the power cutoff domain PD2 and the isolation enable signal ISOEN are input, and when the isolation enable signal ISOEN is at the L level, the output is fixed at the H level. Which isolation cell is inserted is determined based on the specifications of the LSI when the power shutdown domain PD2 is powered off.

  Further, the latch type isolation cell shown in the upper right of FIG. 7 also receives the output of the power cutoff domain PD2 and the isolation enable signal ISOEN, and the output terminal of the power cutoff domain PD2 at the timing when the enable signal ISOEN becomes H level. Latch the logical value of.

  8 and 9 are diagrams for explaining the path / circuit extraction step S12 in which the power cannot be shut off. In the combinational circuit extracted in the extraction step S11 of FIG. 7, a circuit whose output is supplied to other than the power cutoff region PD2 and a circuit whose input is supplied from a circuit other than the power cutoff region PD2 are together with the power cutoff region PD2. Should not be powered off.

  Therefore, in the path / circuit extraction step S12 where the power cannot be shut off, forward tracing is performed from the index B, and when a flip-flop or port other than the power shut-off area PD2 is reached, an index C is added thereto (S12-1). Further, back tracing is performed from the index B ', and when the flip-flop or port other than the isolation cell is reached, the index C' is added thereto. In this case, even when the latch type isolation cell is reached, the index C 'is also targeted.

  That is, in FIG. 8, the output of the combinational circuit CMB1-2 is supplied to the latch circuit C and the output port C, and the output signal of the latch circuit C ′ and the signal of the input port C ′ are supplied to the input of the combinational circuit CMB2-2. Turned out to be.

  In FIG. 9, index C is a flip-flop or output port that needs to input an output signal from the combinational circuit CMB1-2, and index C ′ is a flip-flop or input port that supplies a signal to the combinational circuit CMB2-2. . Accordingly, the combinational circuits CMB1-2 and CMB2-2 on the path B-C from the index B to C and on the path B'-C 'from the index B' to C 'cannot be powered off, Indexes D and D ′ are attached (S12-3).

  FIG. 10 is a diagram for explaining the extraction step S13 of the extended power cutoff unit. Of the combinational circuits on the path between AB and A′-B ′ extracted in step S11, the circuit excluding combinational circuits D and D ′ on the path between BC and B′-C ′ Since the power can be shut off together with the power shut-off area PD2, only the circuit of that portion is extracted. Therefore, the combinational circuits CMB1-1 and CMB2-1 in FIG. 10 are extracted. If the path between B-A and B'-A 'is only a net (connection wiring), it is excluded from the extracted circuit because no power is supplied.

  FIG. 11 is a diagram for explaining the isolation cell deletion / reinsertion step S2. The left side of FIG. 11 is a circuit example before moving the isolation cell, and the right side is a circuit example after moving. The isolation cell is provided on the output terminal side of the power domain PD2, which is a power cutoff region. In FIG. 11, it is assumed that the combinational circuits CMB2-1 (1) and CMB2-1 (2) are extracted as extended areas where the power is shut off.

  In the example of the circuit before movement on the left side of FIG. 11, the isolation cell ISO− between the combinational circuits CMB2-1 (1) and CMB2-1 (2) combined as the power cutoff region PD2 and the power cutoff region PD2. 1 is changed to the isolation cell ISO-2 on the output side of the combination circuit CMB2-1 (1) and CMB2-1 (2) in the extended region in the circuit example after the movement on the right side (S2-1). In this case, the type of the isolation cell ISO-2 to be newly inserted is the combination circuit CMB2-1 (in the extended region based on the fixed output logical values 1 and 0 of the isolation cell ISO-1 in the circuit before the movement on the left side. 1) and CMB 2-1 (2) are selected in correspondence with the logical values 1 and 0 generated. That is, when the power is shut off, the output logic value generated by the circuits CMB2-1 (1) and 2-1 (2) based on the fixed output logic value of the isolation cell ISO-1 before the movement is newly set. Either an output L type output fixed isolation cell or an output H type output fixed isolation cell is selected so that a simple isolation cell ISO-2 is generated.

  In the example of FIG. 11, all the output logic values of the combinational circuit CMB2-1 (1) are “0”, so that all the newly inserted isolation cells ISO-2 are of the output L type. Further, since the output logic values of the combinational circuit CMB20-1 (2) are all “1”, the isolation cell ISO-2 inserted therein becomes the output H type.

  Further, the output of one inverter in the combined circuit CMB2-1 (2) to be combined is input to the same power cut-off region PD2. Therefore, the isolation cell is not necessary for the output of the inverter and is deleted (S2-2).

  FIG. 12 is a diagram for explaining the isolation cell deletion / reinsertion step S2. FIG. 12 shows an LSI circuit obtained as a result of step S2. A combinational circuit CMB1-2 is added to the input side of the original power cutoff region PD2, and a combinational circuit CMB2-1 is added to the output side as a power cutoff region. That is, the power shut-off area PD2 is expanded. Further, a new isolation cell is inserted into the output terminal of the output side combinational circuit CMB2-1.

  As described above, according to the method for extending the power cut-off area and the program thereof according to the present embodiment, the LSI circuit configuration specified based on the hardware description file such as the net list, the library, and the power supply specification file, and the power domain Based on the information of the power shut-off area and the isolation cell, it is possible to extract areas where power can be shut off simultaneously on the input side and output side of the power shut-off area, and move the isolation cell accordingly. As a result, it is possible to automatically generate a hardware description file and a power specification file in which the power shut-off area is expanded. As a result, the power consumption of the generated LSI can be further suppressed.

  Next, the method for extending the power cut-off area will be described with specific examples. FIG. 13 is an original circuit diagram before the expansion process of the power shut-off area, and shows an example of the circuit. Using this circuit diagram as an example, a description example of a netlist and a power specification file is shown, and how this circuit diagram is analyzed and how it is changed when the above power cut-off area expansion method is applied. explain.

  The integrated circuit LSI of FIG. 13 has power domains PD1 and PD2, and the power domain PD2 is also a power cutoff region. In the figure, each cell or module has its instance (unique name) appended. For example, although the instance name of the flip-flop FFA1 is uFFA1 (u is an abbreviation of μ), “FFA1” is simply added for simplicity. The same applies to other cells and modules. Also, IN1, OUT1, etc. are added to the ports, IN_A, etc. are added to the input terminals of the module MOD2, and OUT_A, etc. are added to the output terminals. Further, in the figure, names of nets (wirings) connecting each cell, for example, n1 to n42 are also appended.

  FIG. 14 is a diagram showing an example of the net list of the integrated circuit of FIG. In this net list, “module Top (IN1, IN2, OUT1, OUT2)” defines the input terminal and output terminal of the integrated circuit LSI. In FIG. 20, the input terminal input, the output terminal output, and the net wire are defined. Each instance IN1, IN2, OUT1, OUT2, n1 to n42 is defined.

  Furthermore, in the net list, a cell of the circuit on the input side of the power domain PD2 on the left side of the integrated circuit of FIG. 13 is defined at 21 in the figure. For example, as the inverter INVA on the third row, the instance name uINVA1 and the net n1 connected to the input of the inverter “.A (n1)” and the output port OUT1 connected to the output “.Y ( OUT1) ”. The definition of the inverter INVA is defined in the library 14. For example, the library 14 defines that the inverter INVA has an input .A and an output .Y, and has a logic function for inverting and outputting the input. .

  In addition, in the figure, it is defined that the power domain PD2 is the module MOD2, the instance name uMOD2, and the input terminal .IN_A and the like are connected to the net n6 and the like. Reference numeral 23 in the figure defines cells connected to the output terminal of the power domain PD2 on the right side of the integrated circuit LSI in FIG. Of these lines, in the first line, as the isolation cell ISOLA, the instance name uISOLA1 and the net n15 connected to its input ".A (n15)" and the net ISOEN connected to the enable terminal ".EN (ISO17)" is specified, and net "n17" is connected to the output ".Y (n17)". The other cells are the same, and are clear when compared with FIG.

  Referring to the net list in FIG. 14 which is a kind of hardware description file of the integrated circuit and the definition of the cells and isolation cells in the library 14, the integrated circuit cells and macros in FIG. The configuration is specified.

  FIG. 15 is a diagram showing an example of the power supply specification file of the integrated circuit of FIG. In the power specification file, a power domain PD1 is defined at 30 in the figure, and a power domain PD2 is defined at 31 in the figure. For the power domain PD2, it is specified that the instance name is uMOD2 and the power shutdown condition (shutoff_condition) is when the output signal ISO of the power control mode uPMU is output. That is, the power domain PD2 is also a power shutdown domain. In addition, in the figure, the power supply state name VDD1 specifies that the voltage is 1.2V.

  Next, in the power specification file, at power supply mode PM1, both power domains PD1 and PD2 are in the on state (power supply state), and in power supply mode PM2, only power domain PD1 is in the on state (power supply) in the power specification file 33 State). Also, in FIG. 34, the rule of the isolation cell is defined. For example, in the case of the isolation rule ISO_PD1_L, the output of the isolation cell is fixed to L with respect to the output terminal of the power domain PD2. This is a condition when the output signal ISO of the power supply control unit PMU is output, and is specified to be inserted into the outputs OUT_A, OUT_B, OUT_F, OUT_H, and OUT_I of the module uMOD2 that is the power domain PD2.

  Similarly, reference numeral 34 in the figure defines an isolation rule ISO_PD1_H as an H level fixed output isolation and an isolation rule ISO_PD1_KP as a latch type isolation that holds an output.

  By referring to the power specification file of FIG. 15, in the integrated circuit specified by the net list and library of FIG. 14, the power domains, the power shut-off conditions of each power domain, the power voltage, the power mode, The insertion position and type of the isolation cell can be specified.

  FIG. 16 is a diagram showing an index after the power cut-off area expansion process is performed on the integrated circuit of FIG. That is, FIG. 16 shows a state in which the power cut-off area expansion process S1 is executed on the integrated circuit of FIG. 13 and indexes A to D are added to each node. That is, index A at the input terminal of power domain PD2, and flip-flop arrived after back tracing and index B at the input port, index A 'at the output terminal of power domain PD2, and flip-flop arrived after forward tracing Index B 'is added to the output port. Also, index C is applied to the flip-flops and output ports that have been reached by forward tracing from index B, index D is applied to the cells between index BC, and flip-flops and input ports that have been reached by back-tracing from index B ′. Has an index C ', and an index D' is added to cells between indexes B'-C '. Furthermore, AB, BC, A'-B ', B'-C', etc. are added to the cells and nets (connection wiring) between the above indexes.

  Then, cells to which indexes AB and A′-B ′ have been added but cells to which indexes BC and B′-C ′ have not been added are extended to power-off regions CMB1-1 (1), CMB1. -1 (2), CMB2-1 (1), and CMB2-1 (2).

  FIG. 17 is a diagram showing a netlist to which the index of FIG. 16 is added. The description is the same as in FIG. 14 except that the underlined cells, terminals, and nets have indexes A to D, AB, BC, A'-B ', B'- shown in FIG. C 'is attached. However, although FIG. 17 does not display to distinguish those indexes, it can be understood in combination with FIG. 16 which index has been added.

  In the net list of FIG. 17, the index D is assigned to the cell surrounded by the alternate long and short dash line. The cells surrounded by the solid line are the newly expanded cells of the power cutoff areas CMB1-1 (1), CMB1-1 (2), CMB2-1 (1), and CMB2-1 (2). These areas can be easily extracted by analyzing the index added in the net list of FIG.

  FIG. 18 is a diagram showing isolation cell deletion / reinsertion processing to the integrated circuit of FIG. Although it is equivalent to FIG. 11, FIG. 18 shows a selection method S2-3 of the type of the newly inserted isolation cell ISO-2. That is, according to the logic value output from the combinational circuit CMB2-1 (1), CMB2-1 (2) that receives the output logic value of the isolation cell ISO-1 to be deleted in the left circuit, The type of isolation ISO-2 to be newly inserted, H level fixed output isolation cell (AND gate) or L level fixed output isolation cell (OR gate) is selected. In the figure, steps S2-1 and S2-2 are as described in FIG.

  FIG. 19 is a diagram illustrating the integrated circuit after the power cut-off region expansion process is performed on the integrated circuit of FIG. As is clear from comparison with the integrated circuit of FIG. 13, first, the combinational circuits CMB1-1 (1), CMB1-1 (2), CMB2-1 (1), and CMB2-1 (2) are used as new power-off regions. Added to the same power-off area as the power domain PD2. Then, on the output side of the power domain PD2, the isolation cells ISOLA1, ISOLA2, ISOHA1, ISOHA2, ISOLA4, ISOLA5 in FIG. 13 are deleted, and in FIG. 19, isolation cells ISOLA1, ISOLA6, ISOLA7, ISOHA4 are newly inserted. ing. In addition, new nets (connection wirings) n50 to n54 are generated, and nets n17, n18, and n25 to n27 are deleted.

  FIG. 20 is a diagram showing a net list of the integrated circuit after the expansion process of FIG. The underlined portion in the figure is a portion changed from the net list of FIG. 14 for the original integrated circuit of FIG. In the figure, the cells corresponding to the combination circuit CMB1-1 (1), CMB1-1 (2), CMB2-1 (1), and CMB2-1 (2) of the extended power shut-off area are shown. The net connected to is changed. In addition, new isolation cells ISOLA1, ISOLA6, ISOLA7, and ISOHA4 have been added.

  FIG. 21 is a diagram showing a power supply specification file of the integrated circuit after the expansion process of FIG. This power specification file includes instances uINVA3, uOR2A1, uOR2A2, uINVA4, uAND2A3, uAND2A4, uAND3A5, uINVA6, uINVA9, uINVA9, uINVA6, uINVA9, uINVA10 has been added. In other words, the cells of these instances have been added and expanded in the power domain PD2 that is powered off together.

  In addition, the power supply specification file in FIG. 21 includes the insertion positions and cell types of new isolation cells ISOLA1, ISOLA6, ISOLA7, and ISOHA4, as L-level output fixed isolation cells ISO_PD1_L, and cell output terminals uAND2A3 / Y, uAND2A5 / It is defined that it is provided in Y, uINVA6 / Y and that it is provided in the cell output terminal uINVA9 / Y as the H level output fixed isolation cell ISO_PD1_H.

  13 to 21, for a specific integrated circuit, a description example of a netlist and a power supply specification file, a description example of a netlist and a power supply specification file that are changed as a result of processing for extending a power shutdown area, and after the change. An example of an integrated circuit can be understood.

  In the above specific example, a netlist is used as an example of the hardware description file. However, in the RTL description file, the circuit configuration can be specified in the same manner, and the above power cut-off area expansion process can be performed. It is obvious to those skilled in the art.

  As described above, according to the present embodiment, an area in which power can be shut off simultaneously in an integrated circuit having a power shut-off domain can be expanded, so that an integrated circuit in which leakage power is suppressed can be designed.

LSI: Integrated circuit PD2: Power domain, Power cutoff area A: Input A ′: Output CMB1-1, CMB2-1: Combination circuit expanded as power cutoff area

Claims (5)

A hardware description file in which a computer stores a plurality of circuit elements of an integrated circuit and net information for connecting the circuit elements stored in a recording medium, and a power supply domain in which supply of each power supply in the integrated circuit is controlled And a power specification file that defines a power shutdown domain in which power is shut down under a predetermined condition,
The computer backtracks the net information and the circuit element from the input terminal of the power shutdown domain to the hardware description file, and sets the first input port of the latch circuit or integrated circuit to which the backtrace arrives . extracted as a node, further latch circuit the forward tracing by forward tracing and the net information and circuitry from the output terminal of the first isolation cells connected to the output terminal of the power shutoff domain reaches or A first extraction step of extracting an output port of the integrated circuit as a second node ;
The computer forward traces the hardware description file from the first node , extracts a latch circuit or an output port to which the forward trace arrives as a third node , and further extracts the second node A second extraction step of extracting, as a fourth node , a latch circuit or input port that is backtraced from
The computer, with respect to the hardware description file, includes a first combination circuit and a third node of the first combinational circuit between the input terminal of the power shutoff domain and the first node . extracting a third combination circuit excluding the second combinational circuit located between, further, the output terminal of the first isolation cells connected to the output terminal of the power-off domain as with the second node A third extraction step of extracting a sixth combinational circuit excluding the fifth combinational circuit between the second node and the fourth node from among the fourth combinational circuits in between;
The computer adds the third and sixth combinational circuits to the power cut-off domain for the hardware description file and the power supply specification file, and is connected to the input side of the sixth combinational circuit. An LSI power supply cutoff region expansion method comprising: an expansion step of deleting one isolation cell and generating a new second isolation cell on the output side of the sixth combinational circuit. In claim 1,
The integrated circuit includes a power control unit, and the power control unit shuts off the power supply to the power shut-off domain and an isolation enable signal that puts the isolation cell into an isolation state when the power is shut off. And
The isolation cell includes an output fixed isolation cell that fixes an output to a fixed logic value according to the isolation enable signal, and a logic value of an output terminal of the power shut-off domain according to the isolation enable signal. A latch type isolation cell,
An LSI power supply cutoff region expansion method, wherein an output terminal of the first isolation cell is an output terminal of an output fixed isolation cell excluding the latch isolation cell. In claim 2,
In the expansion step, as the newly generated second isolation cell, the output of the sixth combinational circuit is generated based on the fixed logic value of the output of the first isolation cell when the power is shut off. A method for extending a power-off area of an LSI, which selects an output fixed isolation cell that outputs the same logical value as the logical value as a fixed logical value. In any one of Claims 1 thru | or 3,
The hardware description file is a file that describes the integrated circuit at a register transfer level , or a netlist having an input / output terminal of the circuit element and net information connected thereto. . A hardware description file describing a plurality of circuit elements of an integrated circuit and net information connecting them, stored in a recording medium, a power domain in which the supply of power in each of the integrated circuits is controlled, and predetermined conditions Inputting a power specification file that defines a power shutdown domain in which power is shut down in
For the hardware description file, the net information and circuit elements are backtraced from the input terminal of the power shutdown domain, and the input port of the latch circuit or integrated circuit that the backtrace reaches is extracted as the first node. Furthermore, the net information and the circuit element are forward traced from the output terminal of the first isolation cell connected to the output terminal of the power shut-off domain, and the output of the latch circuit or integrated circuit reached by the forward trace A first extraction step of extracting a port as a second node ;
The hardware description file is forward-traced from the first node, the latch circuit or output port that the forward trace reaches is extracted as a third node , and further back-traced from the second node. A second extraction step of extracting, as a fourth node , a latch circuit or input port to which the backtrace reaches,
For the hardware description file, the first combination circuit between the first node and the third node in the first combinational circuit between the input terminal of the power cutoff domain and the first node . extracting a third combination circuit excluding the second combinational circuit, further, a is between the first isolation cell output terminal and the second node connected to an output terminal of the power shutoff domain A third extraction step of extracting a sixth combinational circuit excluding a fifth combinational circuit between the second node and the fourth node among the four combinational circuits;
For the hardware description file and the power supply specification file, the third and sixth combinational circuits are added to the power cut-off domain, and the first isolation connected to the input side of the sixth combinational circuit A computer-readable LSI power cut-off area expansion program for causing a computer to execute an expansion process of deleting a cell and generating a new second isolation cell on the output side of the sixth combinational circuit.

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