JP5445066B2 - Analysis support program, analysis support apparatus, and analysis support method - Google Patents

Description

  The present invention relates to an analysis support program, an analysis support apparatus, and an analysis support method that support correlation analysis between a delay of a target circuit and a leakage current.

  In recent years, with the miniaturization of semiconductor integrated circuits, delays caused by processes and variations in leak current (delay variations, leak current variations) are increasing. The delay is the time required for input / output of a signal between elements in a circuit or between elements. A leak current is a current that flows out at a location that should not flow in an electronic circuit.

  There are a statistical delay analysis (SSTA: Statistical Static Timing Analyzer) and a statistical leak analysis as a method for estimating the delay and leakage current of the target circuit in consideration of these variations. SSTA is a technique for optimizing timing estimation by giving a variation in delay of each element in a target circuit as a probability density distribution and statistically handling the delay of the entire circuit.

  On the other hand, it is known that the delay variation and the leakage current variation are correlated with each other because they are caused by the process. For example, the delay and the leakage current have a trade-off relationship that the leakage current increases as the delay decreases. Therefore, in order to perform accurate yield analysis of the target circuit, it is necessary to analyze the correlation between delay and leakage current.

  Conventionally, there is a Monte Carlo simulation in which a delay analysis tool (STA: Static Timing Analysis) and a leak analysis tool are repeatedly executed as a method for performing a correlation analysis between a delay and a leak current. In addition, in the correlation analysis between the delay and the leakage current, there is a technique of modeling the delay distribution into a normal distribution and performing an approximate calculation (for example, see Non-Patent Document 1 below).

Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen Director, "Accurate and Efficient Gate-Level Parametric Yield Estimation Considering Correlated Variations in Leakage Power and Performance", Proc. DAC 2005, p. 535-540

  However, according to the Monte Carlo simulation described above, in order to perform accurate correlation analysis, it is necessary to repeatedly execute the delay analysis tool and the leak analysis tool about several thousand times. For this reason, there is a problem that the processing time required for the correlation analysis is increased, which leads to a prolonged design period.

  In addition, according to the method of modeling the delay distribution as described above into a normal distribution, in a circuit including a large number of partial circuits operating in parallel, the delay distribution of the entire circuit tends to be non-normal, resulting in a decrease in analysis accuracy. There is a case. As a result, there is a problem that the circuit design is reworked as a result, the work load on the designer is increased, and the design period is prolonged.

  The present invention solves the above-described problems caused by the prior art, and provides an analysis support program, an analysis support apparatus, and an analysis support method capable of reducing the processing time required for the correlation analysis between the delay of the target circuit and the leakage current. The purpose is to provide.

  In order to solve the above-described problems and achieve the object, the disclosed analysis support program, analysis support apparatus, and analysis support method are independent for each element included in any one of a plurality of parallel paths in the target circuit. The standard deviation of the first delay distribution of each element based on the delay variation of each of the above-described paths is modeled as a series circuit, and any one of the paths based on the delay variation independent of each element is modeled. The standard deviation of the first delay distribution is calculated, the calculated standard deviation of the first delay distribution of any one of the paths, and the first delay distribution of any one of the paths obtained from the statistical delay analysis of the target circuit The standard deviation of the first delay distribution of each element is corrected using the standard deviation of the target circuit, and the delay and leakage of the target circuit are corrected using the corrected standard deviation of the first delay distribution of each element. Current phase By performing the analysis, we obtain a correlation distribution representing the correlation between delay and leak current of the target circuit, and the requirements to output the acquired correlation distribution.

  According to the analysis support program, the analysis support apparatus, and the analysis support method, there is an effect that it is possible to shorten the processing time required for the correlation analysis between the delay of the target circuit and the leakage current.

It is explanatory drawing which shows an example of the outline | summary of this analysis method. It is a circuit diagram which shows an example of an object circuit. It is a block diagram which shows an example of the hardware constitutions of an analysis assistance apparatus. It is a block diagram which shows the functional structure of an analysis assistance apparatus. It is explanatory drawing which shows an example of the memory content of a cell delay variation table. It is explanatory drawing which shows an example of the memory content of a cell leak variation table. It is explanatory drawing which shows an example of the memory content of a correlation coefficient table. It is explanatory drawing which shows an example of the memory content of the cell table in a path | pass. It is explanatory drawing which shows an example of the memory content of a SSTA result table. It is explanatory drawing which shows an example of the memory content of the variation table after correction | amendment. It is explanatory drawing which shows an example of the memory content of a leak / delay correlation table. It is explanatory drawing which shows the specific example of leak and delay correlation distribution. It is explanatory drawing which shows an example of the memory content of a leak and frequency correlation table. It is explanatory drawing which shows an example of the memory content of the leak and frequency correlation table after deletion. It is explanatory drawing which shows an example of the memory content of a frequency yield table. It is explanatory drawing which shows the specific example of leak * frequency correlation distribution and frequency yield distribution. It is a flowchart which shows an example of the analysis assistance process procedure of an analysis assistance apparatus. It is a flowchart which shows an example of the specific process sequence of a variation correction process. It is a flowchart (the 1) which shows an example of the specific process sequence of a leak and delay correlation distribution acquisition process. It is a flowchart (the 2) which shows an example of the specific process sequence of a leak and delay correlation distribution acquisition process. It is a flowchart which shows an example of the specific process sequence of a leak and frequency correlation distribution calculation process. It is a flowchart which shows an example of the specific process sequence of a frequency yield distribution calculation process.

  Exemplary embodiments of an analysis support program, an analysis support apparatus, and an analysis support method according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Outline of this analysis method)
First, an example of the outline of this analysis method according to the embodiment will be described. In this specification, the target circuit is a circuit (for example, a processor) including a plurality of paths operating in parallel. A path is a path from one cell in the target circuit to another cell. A cell is a circuit element such as a NOT gate, AND gate, wiring, buffer, INV (inverter), and FF included in the target circuit.

  That is, the path is a path from one FF (flip-flop) in the target circuit to another FF, for example. The path may be a path from the data input terminal in the target circuit to the FF, or may be a path from the FF to a certain data output terminal.

  FIG. 1 is an explanatory diagram showing an example of an outline of the present analysis method. In this analysis method, the processing time is shortened while ensuring the analysis accuracy of the correlation analysis between the delay of the target circuit and the leakage current. Here, there are variations for the delay and leakage current of the target circuit, which are independent for each cell in the target circuit, and for all cells in the target circuit.

  Specifically, the delay variation includes a first delay variation independent of each cell and a second delay variation common to all cells. Therefore, the delay variation of the cell can be expressed using these first / second delay variations. Specifically, for example, the delay variation of the cell can be expressed using the following formula (1).

However, d _C is a delay variation of the cell, α is a first delay variation parameter, and β is a second delay variation parameter. Further, m is the average of the first delay distribution of the cells based on the first delay variation, and s is the standard deviation of the first delay distribution. Ap and an are standard deviations of the second delay distribution of the cells based on the second delay variation.

d _C = m + s × α + f (β)
f (β) = ap × β (β ≧ 0), f (β) = an × β (β <0)
... (1)

  In addition, variations in leakage current include a first leakage current variation independent of each cell and a second leakage current variation common to all cells. Therefore, the cell leakage current variation can be expressed using these first / second leakage current variations. Specifically, for example, cell leakage current variation can be expressed using the following equation (2).

Here, l _C is a cell leakage current variation, α ′ is a first leakage current variation parameter, and β ′ is a second leakage current variation parameter. Further, a, b, and c are coefficients specific to each cell.

l _C = exp (a + b × α ′ + c × β ′) (2)

Here, α, α ′, β, and β ′ are random variables, for example, a standard normal distribution with an average of “0” and a standard deviation of “1”. Further, the alpha, alpha 'has a correlation of the correlation coefficient [rho _alpha. The correlation coefficient [rho _alpha is specific to each cell in the target circuit. Also, β and β ′ have a correlation coefficient ρ. This correlation coefficient ρ is common to all cells in the target circuit.

  In general, in the correlation analysis between the delay of the target circuit and the leakage current, there is a correlation between cells, so it is necessary to consider the first delay variation and the second delay variation of each cell. On the other hand, the logic circuit in the target circuit includes not only "serial" coupling between cells but also "merging" in which multiple signals are input to one cell, so the processing of correlation analysis is complicated. (1-1 in FIG. 1).

  Therefore, in this analysis method, each path in the target circuit is modeled as a series circuit in which cells in the path are connected in series ((1-2) in FIG. 1). Specifically, for example, in the present analysis method, the first delay variation of the path is configured to be the addition of the first delay variation of each cell in the path using the following formula (3).

However, the path Pi is an arbitrary path in the target circuit, d _intra is the first delay variation of the path Pi, and M is the average of the first delay distribution of the path Pi. Α _j is a first delay variation parameter of an arbitrary cell Cj in the path Pi, and s _j is a standard deviation of the first delay distribution of the cell Cj (j = 1, 2,..., N).

d _intra = M + s ₁ × α ₁ + s ₂ × α ₂ + ... + s _j × α _j + ... + s _n × α _n (3)

  For this reason, the delay variation of the path Pi can be expressed using the following equation (4). Here, di is the delay variation of the path Pi, and M ′ is the average of the first delay distribution of the path Pi. Further, f (β) is the second delay variation of the path Pi, and Ap and An are standard deviations of the second delay distribution of the path Pi based on the second delay variation.

di = M ′ + s ₁ × α ₁ + s ₂ × α ₂ +... + s _j × α _j +... + s _n × α _n + f (β)
f (β) = Ap × β (β ≧ 0), f (β) = An × β (β <0)
... (4)

  Thus, in this analysis method, the first delay variation of the path Pi is configured to be the addition of the first delay variation of each cell Cj in the path Pi. As a result, the processing contents of the correlation analysis between the delay of the target circuit and the leakage current are simplified, and the processing time required for the correlation analysis can be shortened.

However, if each path in the target circuit is simply modeled as a series circuit, the accuracy of the correlation analysis will be reduced. Therefore, in this analysis method, the first delay variation d _intra of the path Pi is reconfigured so as to match the average M and the standard deviation S of the first delay distribution of the path Pi obtained using the existing SSTA method.

Here, the average and standard deviation of the first delay variation of the whole series circuit are expressed by the following general formulas (5) and (6). The following equation (6) uses the property that the first delay variation of each cell Cj in the path Pi is independent of each other. Where M ′ is the average of the first delay distribution of the entire series circuit, and S ′ is the standard deviation of the first delay distribution of the entire series circuit. m _j is the average of the first delay distribution of the cell Cj.

M ′ = m ₁ + m ₂ +... + _{Mn n} (5)

S ′ ² = s ₁ ² + s ₂ ² +... + S _n ² (6)

  In this analysis method, first, the first delay distribution and the second delay distribution of the path Pi are calculated using the SSTA method. In this analysis method, the average M ′ of the first delay distribution of the path Pi in the above equation (3) is replaced with the path calculated by the SSTA method instead of M ′ calculated using the above equation (5). Let M be the average of the first delay distribution of Pi.

In this analysis method, the standard deviation _Sj of the first delay distribution of the cell Cj is corrected using the standard deviation S of the first delay distribution of the path Pi calculated by SSTA and the above equation (6) (see FIG. 1 (1-3)). Specifically, for example, in this analysis method, using the following equation (7), to correct the standard deviation s _j of the first delay distribution of cell C _j. Here, p _j is the standard deviation of the first delay distribution of the corrected cell Cj.

p _j = (S / S ′) × s _j (7)

  As a result, the delay variation of the path Pi is expressed using the following equation (8).

di = M + p ₁ × α ₁ + p ₂ × α ₂ +... + p _j × α _j +... + p _n × α _n + f (β)
f (β) = Ap × β (β ≧ 0), f (β) = An × β (β <0)
... (8)

As described above, in this analysis method, the path Pi is modeled as a series circuit, and the first delay variation d _intra of the path Pi is calculated as an average M and a standard deviation S of the first delay distribution of the path Pi calculated by the SSTA method. Reconfigure to match. As a result, the processing time required for the correlation analysis between the delay of the target circuit and the leakage current can be shortened, and the analysis accuracy of the correlation analysis can be ensured.

(Example of target circuit)
Next, an example of the target circuit will be described. FIG. 2 is a circuit diagram illustrating an example of the target circuit. In the drawing, a part of the target circuit is extracted and displayed. In FIG. 2, the target circuit 200 is configured to include paths Pa to Pc. In this analysis method, at least one of the paths Pa to Pb in the target circuit 200 is modeled as a series circuit, and a correlation analysis between delay and leakage current is performed.

  Here, in the target circuit 200, the path Pa is a path from FF1 → INV1 → INV2 → AND1 → INV3 → INV4 → NOR1 → FF2. The path Pb is a path from FF1 → INV1 → INV2 → AND1 → INV5 → INV6 → NOR2 → FF3. The path Pc is a path from FF1 → INV1 → INV2 → AND1 → INV5 → INV7 → NOR3 → FF4.

(Hardware configuration of analysis support device)
Next, the hardware configuration of the analysis support apparatus according to the present embodiment will be described. FIG. 3 is a block diagram illustrating an example of a hardware configuration of the analysis support apparatus. In FIG. 3, an analysis support apparatus 300 includes a CPU (Central Processing Unit) 301, a ROM (Read-Only Memory) 302, a RAM (Random Access Memory) 303, a magnetic disk drive 304, a magnetic disk 305, and an optical disk. A drive 306, an optical disk 307, a display 308, an I / F (Interface) 309, a keyboard 310, a mouse 311, a scanner 312, and a printer 313 are provided. Each component is connected by a bus 320.

  Here, the CPU 301 governs overall control of the analysis support apparatus 300. The ROM 302 stores a program such as a boot program. The RAM 303 is used as a work area for the CPU 301. The magnetic disk drive 304 controls the reading / writing of the data with respect to the magnetic disk 305 according to control of CPU301. The magnetic disk 305 stores data written under the control of the magnetic disk drive 304.

  The optical disk drive 306 controls the reading / writing of the data with respect to the optical disk 307 according to control of CPU301. The optical disk 307 stores data written under the control of the optical disk drive 306, and causes the computer to read data stored on the optical disk 307.

  The display 308 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As this display 308, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  The I / F 309 is connected to a network 314 such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and is connected to other devices via the network 314. The I / F 309 serves as an internal interface with the network 314 and controls data input / output from an external device. For example, a modem or a LAN adapter can be adopted as the I / F 309.

  The keyboard 310 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 311 performs cursor movement, range selection, window movement, size change, and the like. A trackball or a joystick may be used as long as they have the same function as a pointing device.

  The scanner 312 optically reads an image and takes in the image data into the analysis support apparatus 300. The scanner 312 may have an OCR (Optical Character Reader) function. The printer 313 prints image data and document data. As the printer 313, for example, a laser printer or an ink jet printer can be employed.

(Functional configuration of analysis support device)
Next, a functional configuration of the analysis support apparatus 300 will be described. FIG. 4 is a block diagram illustrating a functional configuration of the analysis support apparatus. In FIG. 4, the analysis support apparatus 300 includes an input unit 401, an acquisition unit 402, a calculation unit 403, a correction unit 404, a creation unit 405, and an output unit 406. Specifically, the functions (input unit 401 to output unit 406) serving as the control unit are, for example, a program stored in a storage device such as the ROM 302, RAM 303, magnetic disk 305, and optical disk 307 shown in FIG. The function is realized by executing the function or by the I / F 309.

  In the following description, unless otherwise specified, cells in the target circuit are expressed as “cells C1 to CN”, and paths in the target circuit are expressed as “paths P1 to PL”.

  The input unit 401 has a function of receiving input of circuit information related to the target circuit. The circuit information includes, for example, a net list related to the target circuit, variation data (see FIGS. 5 and 6), correlation data (see FIG. 7), in-path cell data (see FIG. 8), and the like. Specifically, for example, the input unit 401 receives an input of circuit information by a user operation using the keyboard 310 and the mouse 311 shown in FIG. The input unit 401 may acquire circuit information by receiving from an external computer device or extracting from a database or library (not shown).

  Here, the net list is electronic data indicating a cell group in the target circuit and a connection relationship between the cells. The variation data is model data relating to the first delay variation and the second delay variation of the cells C1 to CN. The variation data is stored, for example, in a cell delay variation table 500 shown in FIG. 5 and a cell leak variation table 600 shown in FIG.

  The correlation data is information representing the correlation between the delay of the target circuit and the leakage current. The correlation data is stored, for example, in a correlation coefficient table 700 shown in FIG. The in-path cell data is information for specifying a cell in the path Pi. The intra-path cell data is stored, for example, in an intra-path cell table 800 shown in FIG.

  FIG. 5 is an explanatory diagram showing an example of the contents stored in the cell delay variation table. In FIG. 5, a cell delay variation table 500 has fields of cell ID, m, s, ap, and an. By setting information in each field, delay variation data 500-1 to 500-N of each cell C1 to CN are stored as records.

  The cell ID is an identifier for identifying the cells C1 to CN in the target circuit. m is the average of the first delay distributions of the cells C1 to CN. s is the standard deviation of the first delay distribution of each cell C1 to CN. ap and an are standard deviations of the second delay distribution of the cells C1 to CN. Here, ap is a standard deviation when the second delay variation parameter β is “β ≧ 0”, and an is a standard deviation when the second delay variation parameter β is “β <0”.

The delay variation of each cell C1 to CN can be expressed by substituting the delay variation data 500-1 to 500-N corresponding to each cell C1 to CN into the above equation (1). For example, the delay variation of the cell C1 is “d _C = m (1) + s (1) × α + f (β)” (however, when “β ≧ 0”, “f (β) = ap (1) × β And “β <0”, “f (β) = an (1) × β”).

  FIG. 6 is an explanatory diagram showing an example of the contents stored in the cell leak variation table. In FIG. 6, the cell leak variation table 600 has fields of cell ID, a, b, and c. By setting information in each field, leak variation data 600-1 to 600-N of the cells C1 to CN are stored as records.

The cell ID is an identifier for identifying the cells C1 to CN in the target circuit. “a”, “b”, and “c” are coefficients specific to the cells C1 to CN regarding the leakage current variation. The leakage current variations of the cells C1 to CN can be expressed by substituting the leakage variation data 600-1 to 600-N corresponding to the cells C1 to CN into the above formula (2). For example, the leakage current variation of the cell C1 is “l _C = exp (a (1) + b (1) × α ′ + c (1) × β ′)”.

  FIG. 7 is an explanatory diagram showing an example of the contents stored in the correlation coefficient table. In FIG. 7, the correlation coefficient table 700 has fields for cell ID, first variation correlation coefficient, and second variation correlation coefficient. By setting information in each field, correlation data 700-1 to 700-N of each cell C1 to CN are stored as records.

  The cell ID is an identifier for identifying the cells C1 to CN in the target circuit. The first variation correlation coefficient is a correlation coefficient representing the correlation between the first delay variation parameter α and the first leakage current variation parameter α ′. The second variation correlation coefficient is a correlation coefficient representing the correlation between the second delay variation parameter β and the second leakage current variation parameter β ′.

  For example, the correlation coefficient representing the correlation between the first delay variation parameter α and the first leakage current variation parameter α ′ of the cell C1 is “ρ (1)”. In the case of “ρ (1) = 1”, “α = α ′”. Further, the correlation coefficient representing the correlation between the second delay variation parameter β and the second leakage current variation parameter β ′ of the cell C1 is “ρ”.

  FIG. 8 is an explanatory diagram of an example of the contents stored in the intra-pass cell table. In FIG. 8, the intra-path cell table 800 includes fields of path ID, number of cells in path, and intra-path cell ID / cell ID. By setting information in each field, in-path cell data 800-1 to 800-L of each path P1 to PL is stored as a record.

  The path ID is an identifier for identifying the paths P1 to PL in the target circuit. The number of cells in a path is the total number of cells included in each path P1 to PL. The in-path cell ID / cell ID is an identifier for identifying cells in the paths P1 to PL.

  Specifically, the in-path cell ID (path ID, cell number) is a cell number for specifying a cell in the path. The cell number is, for example, the order of cells from the beginning of the path. The cell ID is an identifier for identifying the cells C1 to CN. For example, C (1,2) / C5 represents the second cell C5 from the beginning of the path P1.

  5 to 8 are stored in a storage device such as the ROM 302, the RAM 303, the magnetic disk 305, and the optical disk 307 shown in FIG. Here, the intra-path cell data (see FIG. 8) is input to the analysis support apparatus 300, but the present invention is not limited to this. For example, the analysis support apparatus 300 may create in-path cell data based on a net list related to the target circuit.

  Returning to the description of FIG. 4, the acquisition unit 402 has a function of acquiring the first delay distribution and the second delay distribution of each path Pi in the target circuit by executing statistical delay analysis of the target circuit. Specifically, for example, the acquisition unit 402 gives the circuit information of the target circuit to the simulator and executes SSTA. Then, the acquisition unit 402 acquires the first delay distribution and the second delay distribution of each path Pi as the SSTA result.

  The simulator may be included in the analysis support apparatus 300 or may be included in an external computer apparatus. However, when an external computer device is provided, the acquisition unit 402 transmits circuit information of the target circuit to the external computer device, and acquires an analysis result from the external computer device. The acquired SSTA result is stored in, for example, the SSTA result table 900 shown in FIG.

  FIG. 9 is an explanatory diagram of an example of the contents stored in the SSTA result table. In FIG. 9, the SSTA result table 900 has fields of path ID, M, S, Ap, and An. By setting information in each field, the SSTA results 900-1 to 900-L of the paths P1 to PL are stored as records.

  The path ID is an identifier for identifying the paths P1 to PL in the target circuit. M is the average of the first delay distribution of the path Pi. S is the standard deviation of the first delay distribution of the path Pi. Ap and An are standard deviations of the second delay distribution of the path Pi. However, Ap is a standard deviation when the second delay variation parameter β is “β ≧ 0”, and An is a standard deviation when the second delay variation parameter β is “β <0”. The SSTA result table 900 is stored in a storage device such as the ROM 302, the RAM 303, the magnetic disk 305, and the optical disk 307, for example.

  Returning to the description of FIG. 4, the calculation unit 403 has a function of calculating the standard deviation S ′ (i) of the first delay distribution of the path Pi when the path Pi in the target circuit is modeled as a series circuit. Specifically, for example, the calculation unit 403 uses the standard deviation s (C (i, j)) of the first delay distribution of the cell C (i, j) in the path Pi to use the first delay of the path Pi. A standard deviation S ′ (i) of the distribution is calculated. The standard deviation s (C (i, j)) is the standard deviation of the cells C1 to CN corresponding to the intra-path cell ID “C (i, j)” (j = 1, 2,..., N ( i)).

  More specifically, for example, first, the calculation unit 403 refers to the intra-path cell table 800 and identifies the cells C (i, 1) to C (i, n (i)) included in the path Pi. . Thereafter, the calculation unit 403 refers to the cell delay variation table 500, and standard deviations s (C (i, 1)) to s (s) of the cells C (i, 1) to C (i, n (i)). C (i, n (i))) is specified.

  Then, the calculation unit 403 substitutes the standard deviations s (C (i, 1)) to s (C (i, n (i))) into the following equation (9), and obtains the square root, thereby obtaining a path. The standard deviation S ′ (i) of the first delay distribution of Pi is calculated. Note that the calculated standard deviation S ′ (i) of the first delay distribution of the path Pi is stored in a storage device such as the RAM 303, the magnetic disk 305, and the optical disk 307.

S (i) ′ ² = s (C (i, 1)) ² + s (C (i, 2)) ² +... + S (C (i, n (i))) ² (9)

  The correcting unit 404 uses the calculated standard deviation S ′ (i) of the first delay distribution of the path Pi and the acquired standard deviation S (i) of the first delay distribution of the path Pi to A function of correcting the standard deviation s (C (i, j)) of the first delay distribution of the cell C (i, j). Specifically, for example, the correction unit 404 corrects the standard deviation s (C (i, j)) of the first delay distribution of the cell C (i, j) using the following equation (10). Here, p (i, j) is the standard deviation of the first delay distribution of the corrected cell C (i, j).

    p (i, j) = (S (i) / S ′ (i)) × s (C (i, j)) (10)

  The corrected standard deviation p (i, j) of the first delay distribution of the corrected cell C (i, j) is stored in, for example, the corrected variation table 1000 shown in FIG.

  FIG. 10 is an explanatory diagram showing an example of the stored contents of the corrected variation table. In FIG. 10, the post-correction variation table 1000 has fields for path ID and standard deviation of the first delay distribution. By setting information in each field, post-correction variation data 1000-1 to 1000-L of each path P1 to PL is stored as a record.

  The path ID is an identifier for identifying the paths P1 to PL in the target circuit. The standard deviation of the first delay distribution is the standard deviation p (i, j) of the first delay distribution of the corrected cell C (i, j) in each path Pi. The corrected variation table 1000 is stored in a storage device such as the ROM 302, the RAM 303, the magnetic disk 305, and the optical disk 307, for example.

  Returning to the description of FIG. 4, the creation unit 405 generates the standard deviation p (i, j) of the first delay distribution of the corrected cell C (i, j), the first delay distribution and the first delay distribution of the acquired path Pi. It has a function of creating a function model that expresses the delay variation of the path Pi using the two delay distribution. Specifically, for example, the creation unit 405 creates a function model that expresses the delay variation of the path Pi using the following equation (11).

Here, α _j is a first delay variation parameter independent of the cell C (i, j), and β is a second delay variation parameter common to all the cells C1 to CN. M (i) is an average of the first delay distribution of the path Pi calculated by SSTA, and Ap and An are standard deviations of the second delay distribution of the path Pi calculated by SSTA.

d (i) = M (i) + p (i, 1) × α ₁ + p (i, 2) × α ₂ +... + p (i, n (i)) × α _{n (i)} + f (β)
f (β) = Ap (1) × β (β ≧ 0), f (β) = An (1) × β (β <0)
(11)

  The creation unit 405 also creates a function model that represents the leakage current variation of the path Pi based on the leakage current variation independent of each cell in the target circuit and the leakage current variation common to all cells in the target circuit. Have Specifically, for example, the creation unit 405 creates a function model that expresses the leakage current variation of the path Pi using the following equation (12).

However, α ′ _j is a first leakage current variation parameter independent of the cell C (i, j), and β ′ is a second leakage current variation parameter common to all the cells C1 to CN. Further, a (C (i, j)), b (C (i, j)), and c (C (i, j)) are coefficients specific to the cell C (i, j) regarding the leakage current variation. These coefficients are specified from the cell leak variation table 600 using the cell ID corresponding to the cell C (i, j) in the intra-path cell table 800.

l (i) = exp (a (C (i, 1)) + b (C (i, 1)) × α ′ ₁ + c (C (i, 1)) × β ′ ₁ ) + exp (a (C (i , 2)) + b (C (i, 2)) × α ′ ₂ + c (C (i, 2)) × β ′ ₂ ) +... + Exp (a (C (i, n (i))) + b (C (I, n (i))) * [alpha] ' _{n (i)} + c (C (i, n (i))) * [beta]' _{n (i)} )
(12)

  The acquisition unit 402 has a function of acquiring a correlation distribution between the delay of the target circuit and the leakage current. Specifically, for example, the acquisition unit 402 gives circuit information about the target circuit, corrected variation data 1000-1 to 1000-L, and the created function model to the simulator, and executes a Monte Carlo simulation. Then, the acquiring unit 402 acquires the delay of the target circuit and the leak / delay correlation distribution of the leak current as a simulation result from the simulator.

  The specific processing contents of the correlation analysis between the delay of the target circuit and the leakage current will be described with reference to FIGS. 19A and 19B. The simulator may be included in the analysis support apparatus 300, or may be included in an external computer apparatus. The acquired correlation distribution is stored in, for example, the leak / delay correlation table 1100 shown in FIG.

  FIG. 11 is an explanatory diagram of an example of the contents stored in the leak / delay correlation table. In FIG. 11, a leak / delay correlation table 1100 has fields of correlation ID, leak current, and delay. By setting information in each field, leak / delay correlation data 1100-1 to 1100-K are stored as records.

  The correlation ID is an identifier for identifying an analysis result by the k-th Monte Carlo simulation (k = 1, 2,..., K). K is the number of iterations of Monte Carlo simulation. The leakage current is an analysis value (unit: [mA], for example) representing the leakage current of the target circuit. The delay is an analysis value (unit: [ps], for example) representing the delay of the target circuit. The leak / delay correlation table 1100 is stored in a storage device such as the ROM 302, the RAM 303, the magnetic disk 305, and the optical disk 307, for example.

  The output unit 406 has a function of outputting the acquired correlation distribution. Specifically, for example, the output unit 406 may graph the leak / delay correlation data 1100-1 to 1100-K in the leak / delay correlation table 1100 shown in FIG. Good (see FIG. 12).

  The output format includes, for example, display on the display 308, print output to the printer 313, and transmission to an external device via the I / F 309. Alternatively, the data may be stored in a storage area such as the RAM 303, the magnetic disk 305, and the optical disk 307.

  FIG. 12 is an explanatory diagram showing a specific example of the leak / delay correlation distribution. In FIG. 12, a leak / delay correlation distribution 1200 is a graph showing the correlation between the delay of the target circuit and the leak current. Specifically, in the leak / delay correlation distribution 1200, points corresponding to the number of iterations of Monte Carlo simulation (K) are plotted. According to this leak / delay correlation distribution 1200, for example, it is possible to determine the variation in delay of the target circuit due to the variation in the leak current generated in the target circuit.

  Returning to the description of FIG. 4, the calculation unit 403 calculates a correlation distribution that represents the correlation between the leak current and the frequency of the target circuit based on the acquired correlation distribution that represents the correlation between the delay of the target circuit and the leak current. Have Specifically, for example, the calculation unit 403 calculates the frequency f (k) of the target circuit by substituting the delay d (k) of the target circuit into the following equation (13), whereby the leak / frequency correlation distribution is calculated. Is calculated.

    f (k) = 1 / d (k) (13)

  The calculated leak / frequency correlation distribution is stored in, for example, the leak / frequency correlation table 1300 shown in FIG.

  FIG. 13 is an explanatory diagram showing an example of the contents stored in the leak / frequency correlation table. In FIG. 13, a leak / frequency correlation table 1300 has fields of correlation ID, leak current, and frequency. By setting information in each field, leak / frequency correlation data 1300-1 to 1300-K are stored as records.

  The correlation ID is an identifier for identifying an analysis result by the k-th Monte Carlo simulation. The leak current is an analysis value representing the leak current of the target circuit. The frequency is a calculated value (unit: [Hz], for example) representing the frequency of the target circuit. The leak / frequency correlation table 1300 is stored in a storage device such as the ROM 302, the RAM 303, the magnetic disk 305, and the optical disk 307, for example.

  The output unit 406 has a function of outputting a correlation distribution representing the correlation between the calculated leakage current of the target circuit and the frequency. Specifically, for example, the output unit 406 may graph the leak / frequency correlation data 1300-1 to 1300-K in the leak / frequency correlation table 1300 shown in FIG. Good (see FIG. 16).

  The calculation unit 403 has a function of calculating a yield distribution related to the frequency of the target circuit based on a correlation distribution representing a correlation between the leakage current of the target circuit and the frequency. Specifically, for example, first, the calculation unit 403 refers to the leak / frequency correlation table 1300 to sort the frequencies f (1) to f (K) of the target circuit in ascending order. Thereafter, the calculation unit 403 may calculate a frequency yield distribution related to the frequency of the target circuit using the following formula (14). Y (k) is a yield at which the frequency of the target circuit is equal to or higher than f (k).

    Y (k) = (K−k + 1) / K (14)

Further, calculator 403, among the leak frequency correlation distribution, also make it a leakage current based on the frequency of the target circuit becomes less than the predetermined threshold l _0, it calculates the frequency yield distribution concerning frequency of the target circuit Good. Specifically, for example, first, the calculating unit 403, from the leak frequency correlation table 1300, delete the leak frequency correlation data leakage current l (k) is the threshold value l ₀ or more.

Note that the threshold value ₁₀ is arbitrarily set based on, for example, the required specifications of the target circuit and stored in a storage device such as the RAM 303, the magnetic disk 305, and the optical disk 307. As a result, leak / frequency correlation data relating to a chip that does not satisfy the required specifications even if manufactured without a defect can be excluded from the calculation target of the frequency yield distribution.

  FIG. 14 is an explanatory diagram of an example of the stored contents of the leak / frequency correlation table after deletion. In FIG. 14, the leak / frequency correlation table 1300 stores leak / frequency correlation data 1400-1 to 1400 -K ′. K ′ is the number of leak / frequency correlation data in the leak / frequency correlation table 1300 after deletion.

  Thereafter, the calculation unit 403 sorts the frequencies f (1) to f (K ′) of the target circuit in ascending order with reference to the leak / frequency correlation table 1300 after deletion. Then, the calculation unit 403 calculates a frequency yield distribution related to the frequency of the target circuit using the following equation (15).

    Y (k) = (K′−k + 1) / K ′ (15)

  Note that the calculated frequency yield distribution of the target circuit is stored in, for example, the frequency yield table 1500 shown in FIG. FIG. 15 is an explanatory diagram of an example of the contents stored in the frequency yield table. In FIG. 15, the frequency yield table 1500 has fields of frequency and yield. By setting information in each field, yield data 1500-1 to 1500-K ′ relating to the frequency of the target circuit is stored as a record.

  The frequency is the frequency f (k) of the target circuit (k = 1, 2,..., K ′). The yield is a yield at which the frequency of the target circuit is f (k) or more. The frequency yield table 1500 is stored in a storage device such as the ROM 302, the RAM 303, the magnetic disk 305, and the optical disk 307, for example.

  Returning to the description of FIG. 4, the output unit 406 has a function of outputting a yield distribution related to the calculated frequency of the target circuit. Specifically, for example, the output unit 406 may graph the yield data 1500-1 to 1500-K ′ in the frequency yield table 1500 shown in FIG. (See FIG. 16).

  FIG. 16 is an explanatory diagram showing a specific example of the leak / frequency correlation distribution and the frequency yield distribution. In FIG. 16, a leak / frequency correlation distribution 1610 is a graph showing the correlation between the frequency of the target circuit and the leak current. Specifically, in the leak / frequency correlation distribution 1610, points corresponding to the number of iterations of Monte Carlo simulation (K) are plotted.

  According to the leak / frequency correlation distribution 1610, for example, it is possible to determine a change in the frequency of the target circuit due to a change in the leak current generated in the target circuit.

  In FIG. 16, frequency yield distributions 1620 and 1630 are graphs representing yields relating to the frequency of the target circuit. Specifically, the frequency yield distribution 1620 is a frequency yield distribution based on the leak / frequency correlation data 1400-1 to 1400-K ′ (see FIG. 14). On the other hand, the frequency yield distribution 1630 is a frequency yield distribution based on the leak / frequency correlation data 1300-1 to 1300-K (see FIG. 13).

  According to the frequency yield distributions 1620 and 1630, for example, it is possible to determine the variation in the yield of the target circuit due to the variation in the frequency of the target circuit. Further, according to the frequency yield distribution 1620, leak / frequency correlation data regarding a chip that does not satisfy the required specifications even though it is manufactured without any problem is excluded from the calculation target, so that the frequency yield distribution of the target circuit can be more accurately determined. Can be judged.

(Analysis support processing procedure of the analysis support device)
Next, the analysis support processing procedure of the analysis support apparatus 300 will be described. FIG. 17 is a flowchart illustrating an example of an analysis support processing procedure of the analysis support apparatus. In the flowchart of FIG. 17, first, the input unit 401 determines whether or not input of circuit information related to the target circuit has been received (step S1701).

  Here, after waiting for input of circuit information (step S1701: No) and receiving the input (step S1701: Yes), each path in the target circuit is obtained by executing SSTA of the target circuit by the acquisition unit 402. The first delay distribution and the second delay distribution of Pi are acquired (step S1702).

  Thereafter, the correction unit 404 executes a variation correction process for correcting the standard deviation s (C (i, j)) of the first delay distribution of the cell C (i, j) in the path Pi (step S1703). Then, the acquisition unit 402 executes a leak / delay correlation distribution acquisition process for acquiring a leak / delay correlation distribution representing the correlation between the delay of the target circuit and the leak current (step S1704).

  Next, the calculation unit 403 executes a leak / frequency correlation distribution calculation process for calculating the leak / frequency correlation distribution of the target circuit based on the acquired leak / delay correlation distribution (step S1705). Then, the calculation unit 403 executes frequency yield distribution calculation processing for calculating the frequency yield distribution of the target circuit based on the calculated leak / frequency correlation distribution (step S1706).

  Finally, the output unit 406 outputs the calculated frequency yield distribution of the target circuit (step S1707), and the series of processes according to this flowchart ends. As a result, the processing time required for the correlation analysis between the delay of the target circuit and the leakage current can be shortened, and the analysis accuracy of the correlation analysis can be ensured.

<Dispersion correction processing procedure>
Next, a specific processing procedure of the variation correction processing in step S1703 shown in FIG. 17 will be described. FIG. 18 is a flowchart illustrating an example of a specific processing procedure of the variation correction processing.

  In the flowchart of FIG. 18, first, the calculation unit 403 sets “i” of the path Pi to “i = 1” (step S1801), and sets the standard deviation S ′ (i) of the first delay distribution of the path Pi to “ S ′ (i) = 0 ”is set (step S1802).

Thereafter, the calculation unit 403 sets “j = 1” in the cell C (i, j) in the path Pi to “j = 1” (step S1803), and “S ′ (i) = S ′ (i) + s (C (I, j)) ² ”is calculated (step S1804). Then, the calculation unit 403 increments j (step S1805), and determines whether “j” is larger than the total number of cells “n (i)” in the path Pi (step S1806).

  If “j ≦ n (i)” (step S1806: NO), the process returns to step S1804. On the other hand, if “j> n (i)” (step S1806: Yes), the calculation unit 403 calculates “S ′ (i) = sqrt (S ′ (i))” (step S1807).

  Next, the calculation unit 403 sets “j” of the cell C (i, j) to “j = 1” (step S1808), and “p (i, j) = (S (i) / S ′ (i)”. ) × s (C (i, j)) ”is calculated (step S1809). Then, the calculation unit 403 increments j (step S1810), and determines whether “j” is greater than “n (i)” (step S1811).

  If “j ≦ n (i)” (step S1811: NO), the process returns to step S1809. On the other hand, when “j> n (i)” (step S1811: Yes), the calculation unit 403 increments “i” (step S1812), and “i” is the total number of paths “L” in the target circuit. It is determined whether it is larger (step S1813).

  Here, if “i ≦ L” (step S1813: NO), the process returns to step S1802. On the other hand, if “i> L” (step S1813: Yes), the process proceeds to step S1704 shown in FIG. Thereby, the first delay variation of the path Pi modeled as a series circuit can be corrected in consideration of the independence of the cell C (i, j).

<Leak / delay correlation distribution acquisition procedure>
Next, a specific processing procedure of the leak / delay correlation distribution acquisition processing in step S1704 shown in FIG. 17 will be described. 19A and 19B are flowcharts illustrating an example of a specific processing procedure of the leak / delay correlation distribution acquisition processing. Here, a case where the leak / delay correlation distribution is calculated by a simulator provided in the analysis support apparatus 300 will be described.

  In the flowchart of FIG. 19A, first, the acquisition unit 402 sets the number K of iterations of Monte Carlo simulation (step S1901). The number of repetitions K is set in advance and stored in a storage device such as the ROM 302, the RAM 303, the magnetic disk 305, and the optical disk 307.

  The number of iterations “k” is set to “k = 1” by the simulator (step S1902). Then, standard normal random numbers β and β ′ of the correlation ρ are generated by the simulator (step S1903). Note that ρ is a second variation correlation coefficient in the correlation coefficient table 700, and β and β ′ are second delay / leakage current variation parameters.

  Then, “i” of the path Pi is set to “i = 1” by the simulator (step S1904). Next, the variable “delay (i)” regarding the delay of the path Pi is set to “delay (i) = 0” by the simulator (step S1905), and the variable “leak (i) regarding the leakage current of the path Pi is set to“ leak ”. (I) = 0 ”(step S1906).

  Thereafter, standard normal random numbers α and α ′ of the correlation ρ (j) are generated by the simulator (step S1907). Note that ρ (j) is the first variation correlation coefficient of the cells C1 to CN corresponding to the cell C (i, j) in the correlation coefficient table 700, and α and α ′ are the first delay / leakage current variation. It is a parameter.

  Next, “delay (i) = delay (i) + p (i, j) × α” is calculated by the simulator (step S1908). Note that p (i, j) is specified from the corrected variation table 1000, for example.

  In addition, by the simulator, “leak (i) = leak (i) + exp (a (C (i, j)) + b (C (i, j)) × α ′ + c (C (i, j))) × β ′ ) "Is calculated (step S1909). Note that a (C (i, j)), b (C (i, j)), and c (C (i, j)) are specified from the cell leak variation table 600, for example.

  Then, “delay (i) = delay (i) + M (i) + f (β, i)” is calculated by the simulator (step S1910). Note that f (β, i) is the second delay distribution of the path Pi (provided that f (β) = Ap (1) × β when β ≧ 0, and f (β) = An when β <0. (1) × β). Further, M (i), Ap, and An are specified from the SSTA result table 900, for example.

  Thereafter, the simulator increments “i” (step S1911), and determines whether “i” is greater than “L” (step S1912). Here, if “i ≦ L” (step S1912: No), the process returns to step S1905. On the other hand, if “i> L” (step S1912: YES), the process proceeds to step S1913 shown in FIG.

  19-2, first, “d (k) = max (delay (1), delay (2),..., Delay (L))” is calculated by the simulator (step S1913). The obtaining unit 402 stores the calculated d (k) in the leak / delay correlation table 1100 (step S1914).

  Next, “1 (k) = leak (1) + leak (2) +... + Leak (L)” is calculated by the simulator (step S1915). The obtaining unit 402 stores the calculated l (k) in the leak / delay correlation table 1100 (step S1916).

  Thereafter, the simulator increments “k” (step S1917), and determines whether “k” is greater than “K” (step S1918). If “k ≦ K” is satisfied (step S1918: NO), the process returns to step S1903 shown in FIG. On the other hand, if “k> K” (step S1918: Yes), the process proceeds to step S1705 shown in FIG.

  As a result, a leak / delay correlation distribution representing the correlation between the delay of the target circuit and the leak current can be acquired. In addition, since the correlation analysis between the delay and the leakage current is a mathematical formula-based Monte Carlo simulation, the calculation speed can be increased and the processing time required for the correlation analysis can be shortened.

<Leakage / frequency correlation distribution calculation procedure>
Next, a specific processing procedure of the leak / frequency correlation distribution calculation processing in step S1705 shown in FIG. 17 will be described. FIG. 20 is a flowchart illustrating an example of a specific processing procedure of the leak / frequency correlation distribution calculation processing.

  In the flowchart of FIG. 20, first, the calculation unit 403 sets “k” representing the correlation ID to “k = 1” (step S2001), and extracts d (k) from the leak / delay correlation table 1100 (step S2001). S2002). Thereafter, the calculation unit 403 calculates “f (k) = 1 / d (k)” (step S2003), and stores f (k) in the leak / frequency correlation table 1300 (step S2004).

  Then, the calculation unit 403 increments “k” (step S2005), and determines whether “k” is greater than “K” (step S2006). If “k ≦ K” is satisfied (step S2006: No), the process returns to step S2002. On the other hand, if “k> K” (step S2006: Yes), the process proceeds to step S1706 shown in FIG. As a result, a leak / frequency correlation distribution representing the correlation between the frequency of the target circuit and the leak current can be calculated.

<Frequency yield distribution calculation processing procedure>
Next, a specific processing procedure of the frequency yield distribution calculation process in step S1706 shown in FIG. 17 will be described. FIG. 21 is a flowchart illustrating an example of a specific processing procedure of frequency yield distribution calculation processing.

In the flowchart of FIG. 21, first, the calculating unit 403, from the leak frequency correlation table 1300, delete the leak frequency correlation data leakage current l (k) is the threshold value _{l 0} or more (step S2101).

  Thereafter, the calculation unit 403 sorts the frequencies f (1) to f (K ′) of the target circuit in ascending order with reference to the deleted leak / frequency correlation table 1300 (step S2102). Then, the calculation unit 403 sets the correlation ID “k” to “k = 1” (step S2103). “Y (k) = (K′−k + 1) / K ′” is calculated (step S2104).

  Next, the calculation unit 403 stores the calculated Y (k) in the frequency yield table 1500 (step S2105). Then, the calculation unit 403 increments “k” (step S2106), and determines whether “k” is greater than “K ′” (step S2107).

  If “k ≦ K” (step S2107: NO), the process returns to step S2104. On the other hand, if “k> K” (step S2107: YES), the process proceeds to step S1707 shown in FIG. Thereby, the yield distribution relating to the frequency of the target circuit can be calculated.

  As described above, according to the present embodiment, the path in the target circuit is modeled as a series circuit, and the first delay distribution of the modeled path Pi is the first delay distribution of the path Pi calculated by SSTA. Correction can be made using one delay distribution. As a result, the processing time required for the correlation analysis between the delay of the target circuit and the leakage current can be shortened, and the analysis accuracy can be ensured.

  Further, according to the present embodiment, a leak / frequency correlation distribution that represents the correlation between the frequency of the target circuit and the leak current is calculated based on the leak / delay correlation distribution that represents the correlation between the delay of the target circuit and the leak current. Can do. As a result, it is possible to determine a variation in delay of the target circuit due to a variation in leak current generated in the target circuit.

  Further, according to the present embodiment, it is possible to calculate a yield distribution related to the frequency of the target circuit based on the leak / frequency correlation distribution that represents the correlation between the leak current and the frequency of the target circuit. As a result, it is possible to determine a change in the frequency of the target circuit due to a change in the leakage current generated in the target circuit.

Further, according to the embodiment, in the leakage-frequency correlation distribution, based on the frequency of the target circuit leakage current of the target circuit is a threshold less than l _0, it is possible to calculate the frequency yield distribution of the circuit it can. As a result, even if the chip is manufactured without any defects, data regarding chips that do not satisfy the required specifications can be excluded, and the frequency yield distribution of the target circuit can be calculated more accurately.

  The analysis support method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. The analysis support program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The analysis support program may be distributed through a network such as the Internet.

  In addition, the analysis support apparatus 300 described in the present embodiment includes an IC for a specific application such as a standard cell or a structured specific integrated circuit (ASIC) (hereinafter simply referred to as “ASIC”) or a PLD (Programmable) such as an FPGA. It can also be realized by Logic Device). Specifically, for example, the function (input unit 401 to output unit 406) of the analysis support apparatus 300 described above is defined by HDL description, and the HDL description is logically synthesized and given to the ASIC or PLD to support analysis. The apparatus 300 can be manufactured.

300 Analysis Support Device 401 Input Unit 402 Acquisition Unit 403 Calculation Unit 404 Correction Unit 405 Creation Unit 406 Output Unit 500 Cell Delay Variation Table 600 Cell Leakage Variation Table 700 Correlation Coefficient Table 800 Cell Cell in Path 900 SSTA Result Table 1000 Variation after Correction Table 1100 Leak / delay correlation table 1300 Leak / frequency correlation table 1500 Frequency yield table

Claims (7)

On the computer,
Using any one of the plurality of parallel paths in the target circuit as a series circuit using the standard deviation of the first delay distribution of each element based on the independent delay variation in each element included in the path A calculation procedure for calculating a standard deviation of the first delay distribution of any one of the paths based on an independent delay variation in each element when modeled;
Using the standard deviation of the first delay distribution of any of the paths calculated by the calculation procedure, and the standard deviation of the first delay distribution of any of the paths obtained from the statistical delay analysis of the target circuit A correction procedure for correcting the standard deviation of the first delay distribution of each element;
By performing a correlation analysis of the delay of the target circuit and the leakage current using the standard deviation of the first delay distribution of each element after correction corrected by the correction procedure, the delay of the target circuit and the leakage current An acquisition procedure for acquiring a correlation distribution representing the correlation;
An output procedure for outputting the correlation distribution acquired by the acquisition procedure;
An analysis support program characterized by causing In the computer,
The second deviation of any one of the paths based on the standard deviation of the first delay distribution of each element after the correction and the delay variation common to all elements in the target circuit obtained from the statistical delay analysis of the target circuit. Using a standard deviation of a delay distribution, a first creation procedure for creating a function model that expresses delay variation of any of the paths;
A second creation procedure for creating a function model expressing the leakage current variation of any of the paths based on the leakage current variation independent of each element and the leakage current variation common to all the elements; Let
The acquisition procedure is as follows:
The correlation analysis is executed using the function model created by the first and second creation procedures and a correlation coefficient representing the correlation between the delay variation of each element and the leakage current variation of each element. The analysis support program according to claim 1, wherein the correlation distribution is acquired. In the computer ,
Based on the correlation distribution representing the correlation between the delay of the target circuit and the leak current acquired by the acquisition procedure, the second calculation procedure for calculating the correlation distribution representing the correlation between the leak current and the frequency of the target circuit is executed. ,
The output procedure is as follows:
The analysis support program according to claim 1 or 2, wherein a correlation distribution representing a correlation between a leakage current and a frequency of the target circuit calculated by the second calculation procedure is output. In the computer ,
Based on the correlation distribution representing the correlation between the leakage current and the frequency of the target circuit calculated by the second calculation procedure, to execute the third calculation step of calculating the yield distribution concerning frequency of the target circuit,
The output procedure is as follows:
4. The analysis support program according to claim 3, wherein a yield distribution relating to the frequency of the target circuit calculated by the third calculation procedure is output. The third calculation procedure includes:
Of the correlation distribution representing the correlation between the leak current and the frequency of the target circuit, the yield distribution related to the frequency of the target circuit is calculated based on the frequency of the target circuit at which the leak current of the target circuit is less than a predetermined threshold. 5. The analysis support program according to claim 4, wherein the analysis support program is calculated. Using any one of the plurality of parallel paths in the target circuit as a series circuit using the standard deviation of the first delay distribution of each element based on the independent delay variation in each element included in the path Calculating means for calculating a standard deviation of the first delay distribution of any one of the paths based on an independent delay variation in each element when modeled;
Using the standard deviation of the first delay distribution of any of the paths calculated by the calculating means and the standard deviation of the first delay distribution of any of the paths obtained from the statistical delay analysis of the target circuit Correcting means for correcting the standard deviation of the first delay distribution of each element;
By performing a correlation analysis between the delay of the target circuit and the leak current using the standard deviation of the first delay distribution of each element after correction corrected by the correction means, the delay of the target circuit and the leak current An acquisition means for acquiring a correlation distribution representing the correlation;
Output means for outputting the correlation distribution acquired by the acquisition means;
An analysis support apparatus comprising: Computer
Using any one of the plurality of parallel paths in the target circuit as a series circuit using the standard deviation of the first delay distribution of each element based on the independent delay variation in each element included in the path A calculation step of calculating a standard deviation of the first delay distribution of any one of the paths based on an independent delay variation in each element when modeled;
Using the standard deviation of the first delay distribution of any path calculated by the calculating step and the standard deviation of the first delay distribution of any path obtained from the statistical delay analysis of the target circuit A correction step of correcting the standard deviation of the first delay distribution of each element;
By performing a correlation analysis between the delay of the target circuit and the leakage current using the standard deviation of the first delay distribution of each element after correction corrected by the correction step, the delay of the target circuit and the leakage current An acquisition step of acquiring a correlation distribution representing the correlation;
An output step of outputting the correlation distribution acquired by the acquisition step;
The analysis support method characterized by performing this.

Images