JP5443557B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that can stably execute various powerful effects.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

  The above-mentioned performance operation is centered on the image production on the liquid crystal display device. In conjunction with this image production, a lamp production that blinks various lamps, an audio production that outputs a sound that excites the player, Movable effects such as moving animals are executed. In addition, there is a demand for further enriching the production variations as much as possible so that the content of the production can be further advanced and appealed to the player, and the long-time game will not get bored.

  The present invention meets the above-described requirements, and an object of the present invention is to provide a gaming machine capable of enriching presentation operations.

In order to achieve the above-described object, the present invention is a gaming machine that executes a lottery process caused by a predetermined switch signal and executes an image effect corresponding to the lottery result. A main control unit that outputs a control command for specifying a result; and an image control unit that executes an image effect corresponding to a lottery result specified by the control command using a display device, the image The control unit acquires various control commands from the upstream control unit based on the first memory that stores its own control program in a non-volatile manner and the control program stored in the first memory. A computer circuit that comprehensively controls a series of image effects based on a predetermined control command, a second memory that stores CG data that is basic data for image effects in a nonvolatile manner, and a computer. Image processing that incorporates an internal storage unit that can be accessed from the data circuit, reads out necessary data from the second memory based on instructions written in the internal storage unit, generates a predetermined image signal, and outputs it to the display device And the second memory includes a memory element that receives the same selection signal by connecting each N-byte output terminal to the upper and lower N bytes of the 2N-byte data bus of the image processing circuit. One set or a plurality of sets are provided, and each time the memory device receives the same base point address information via the 2N-byte data bus, the data after the addresses, each N bytes total 2N bytes, is configured to sequentially output, the image processing circuit, for CG data read in 2N bytes, each memory element A separate operation, the addition operation of 1 byte is executable configured.

  The output operation in units of 2N bytes is preferably continued in response to the clock signal as long as the selection signal is at the active level.

  According to the gaming machine of the present invention described above, every time a 1-bit clock signal is received in common after receiving the same base address information, the CG data after the base address is in units of 2 N bytes in total for each N bytes. Since the data are output in order, a large number of data can be quickly acquired, and the production operation can be further enriched.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram illustrating a circuit configuration of an effect control unit. It is a block diagram which illustrates the internal structure of a digital amplifier. It is a block diagram which illustrates the internal structure of a motor / lamp drive board | substrate. It is a block diagram which illustrates the circuit structure of an image control part. 4 is a diagram schematically illustrating memory configurations of an effect control unit and an image control unit. It is drawing explaining the memory element which comprises CGROM. 9 is a diagram for explaining the address configuration of the memory element and the checksum calculation procedure. It is a block diagram which illustrates the internal structure of VDP. 2 is a diagram illustrating an internal configuration and operation of a power supply sequence circuit. It is drawing explaining the connection relation of VDP and a display apparatus. It is a flowchart explaining operation | movement of an effect control part. It is a flowchart explaining a part of FIG. 14 in detail. It is a flowchart explaining operation | movement of an image control part. It is a flowchart explaining a part of FIG. 16 in detail. It is drawing explaining the modification of a memory structure. It is drawing which illustrates the operation | movement content corresponding to a test command.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, at the upper left and right positions and the lower side of the glass door 6, all three speakers are arranged. The two speakers arranged in the upper part are each configured to output sound of the left and right channels R and L, and the lower speaker is configured to output heavy bass.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A movable effect body (not shown) is housed in a concealed state below the central opening HO, and at the time of a movable notice effect, the movable effect body rises into an exposed state so that a predetermined reliability can be obtained. The notice effect is realized. Here, the notice effect is an effect that informs indefinitely that a big hit state advantageous to the player will occur, and the reliability of the notice effect means the probability that the big hit state will result.

  A display device DS composed of a large liquid crystal color display (LCD) is disposed in the central opening HO. The display device DS is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DS has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, there is a case where a reach effect that expects a big hit state is invited, and in the special symbol display portions Da to Dc and the surroundings, an appropriate notice effect is executed.

  In the game area in which the game ball falls and moves, the first symbol start port 15a, the second symbol start port 15b, the first big winning port 16a, the second big winning port 16b, the normal winning port 17 and the gate 18 are arranged. It is installed. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  On the upper part of the first symbol starting port 15a, there is arranged an effect stage 14 configured to be able to win a prize in the first symbol starting port 15 after the game ball entering from the introduction port IN moves in a seesaw shape or a roulette shape. Yes. And when a game ball wins the 1st symbol starting port 15, it is comprised so that the fluctuation | variation operation | movement of the special symbol display parts Da-Dc will be started.

  The second symbol start port 15b is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws. When the stop symbol after fluctuation of the normal symbol display unit 19 displays a winning symbol, a predetermined symbol is displayed. The opening / closing claw is opened only for a time or until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The first big prize opening 16a is configured with a slide board that advances and retreats in the front-rear direction, and the second big prize opening 16b is configured with an opening / closing plate that is pivotally supported at the lower end and opens forward. . The operation of the first grand prize opening 16a and the second big prize opening 16b is not particularly limited. In this embodiment, the first big prize opening 16a corresponds to the first symbol start opening 15a, and the second big prize opening 16b is comprised corresponding to the 1st symbol starting port 15b.

  That is, when a game ball is won at the first symbol start opening 15a, the changing operation of the special symbol display portions Da to Dc is started. After that, when the predetermined big hit symbol is aligned with the special symbol display portions Da to Dc, the first big hit A special game is started, and the slide board of the first big winning opening 16a is opened forward to facilitate the winning of a game ball.

  On the other hand, when a predetermined big hit symbol is aligned with the special symbol display portions Da to Dc as a result of the fluctuating motion started by winning the game ball in the second symbol start opening 15b, a special game corresponding to the second big hit is started, The open / close plate of the two major winning openings 16b is opened to facilitate the winning of game balls. The game value of the special game (hit state) varies according to the jackpot symbols to be arranged, etc., which game value is given based on the lottery result according to the winning timing of the game ball in advance It is determined.

  In a typical big hit state, the opening / closing plate closes when a predetermined time elapses after the opening / closing plate of the big winning opening 16 is opened or when a predetermined number (for example, 10) of game balls wins. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations, and FIG. 4 shows a part of it in detail. As shown in FIG. 3, the pachinko machine GM receives 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Main control board 21 that centrally handles the sound, an effect control board 22 that executes a lamp effect and a sound effect based on a control command CMD received from the main control board 21, and a control command CMD ′ received from the effect control board 22 Based on the image control board 23 for driving the display device DS, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls, A launch control board 25 that launches a game ball in response to an operation is mainly configured.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. The control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27 and the image interface board 28, and is output from the main control board 21. Is transmitted to the payout control board 24 via the main board relay board 32. Although the control commands CMD, CMD ′, and CMD ″ are all 16 bits long, the main control board 21 and the payout control board 24 are used. The control commands related to are transmitted in parallel every two 8 bit lengths. On the other hand, the control command CMD 'transmitted from the effect control board 22 to the image control board 23 is 16 bits in length and transmitted in parallel. Therefore, even when the notification effects including the movable notification effect are diversified and a large number of control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  By the way, in the present embodiment, the production interface board 27 and the production control board 22 are directly connected to each other by a male connector and a female connector without passing through a wiring cable, and two circuit boards are laminated. . Similarly, with respect to the image interface board 28 and the image control board 23, two circuit boards are laminated by directly connecting a male connector and a female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Therefore, in this specification, the control board 21 to 24, the circuits mounted on the interface boards 27 to 28, and the operations realized by the circuits are generically named. May be referred to as a section 22 ′, an image control section 23 ′, and a payout control section 24. That is, in this embodiment, the effect control board 22 and the effect interface board 27 constitute an effect control part 22 ′, and the image control board 23 and the image interface board 28 constitute an image control part 23 ′. . Note that all or part of the effect control unit 22 ′, the image control unit 23 ′, and the payout control unit 24 are sub-control units.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 35. Each is fixed in place on the front frame 3. On the other hand, a main control board 21, an effect control board 22, and an image control board 23 are fixed to the back of the game board 5 together with the display device DS and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power relay board 33 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The effect interface board 27 outputs the received system reset signal SYS to the effect control unit 22 'and the image control unit 23' as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been applied to the power supply board 20, and one of the effect control unit 22 ′ and the image control unit 23 ′ is generated by the power supply reset signal. The chip microcomputer is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The production control unit 22 ′ and the image control unit 23 ′ execute the production operation in a dependent manner based on the control command from the main control unit 21. The system reset signal SYS output from is used.

  By the way, the reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and unless a regular clear pulse is received from the CPUs of the control units 21 and 24, Each CPU is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. The initialization switch SW operated by the attendant is turned on. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As described above, the effect control board 22 and the effect interface board 27 are integrated by connector connection, and the effect control unit 22 ′ is connected to each level from the power supply board 20 via the power relay board 33. A DC voltage (5V, 12V, 32V) and a system reset signal SYS are received (see FIGS. 3 and 4).

  The effect control unit 22 'receives the control command CMD and the strobe signal STB from the main control unit 21 via the command relay board 26 (see FIGS. 3 and 4). However, in an operation test executed at the product development stage or the like, various test control commands are supplied from the inspection device to the effect control unit 22 'together with a strobe signal.

  The effect control unit 22 ′ drives a lamp group composed of a large number of LED lamps and electric lamps by outputting a lamp driving signal to the lamp driving substrate 29. Further, by outputting a lamp drive signal and a motor drive signal to the motor / lamp drive board 30, the lamp group is driven and the effect motor groups M1 to Mn configured by a plurality of stepping motors are driven. Note that the lamp drive signal and the motor drive signal are both serial signals, and no matter how much the number of lamps or production motors is increased in order to enrich the production contents, the number of wiring cables will not increase, and the equipment configuration will be Simplified.

  The lamp group realizes the lamp effect almost constantly, while the effect motor group suddenly starts operation and realizes the movable notice effect by the movable effector.

  In addition, the effect control unit 22 ′ sends a control command CMD ′ and a strobe signal STB ′ to the image control unit 23 ′, a system reset signal SYS received from the power supply board 20, and two types of DC voltages (12V, 5V). ) Is output (see FIGS. 3 and 4).

  Then, the image controller 23 'drives the display device DS based on the control command CMD' to execute various image effects. As shown in FIG. 4, the display device DS emits light by the LED backlight, and five pairs of LVDS (Low voltage differential signaling) signals from the image interface board 28 and the backlight power supply voltage (12 V). ) And driven. The backlight of the display device DS is configured such that the luminance by PWM control can be controlled.

  Next, the configurations of the effect control unit 22 'and the image control unit 23' described above will be described in more detail with reference to FIG. As shown in FIG. 4, the production interface board 27 receives three types of DC voltages (5V, 12V, and 32V) from the power supply board 20 via the power supply relay board 33. Here, the DC voltage 5V is distributed to the rendering interface board 27, the lamp driving board 29, the motor / lamp driving board 30, the image interface board 28, and the image control board 23 as the power supply voltage of the digital logic circuit. The digital circuit is operating.

  However, the direct current voltage 5V is not distributed on the effect control board 22, and the direct current voltage 3.3V stepped down from 12V by the DC / DC converter and the direct current stepped down from 3.3V by the DC / DC converter. Only the voltage 1.8V is distributed from the production interface board 27 to the production control board 22.

  In this way, the production control board 22 of the present embodiment is driven by the power supply voltage of 3.3V or lower because all the circuits are driven. Therefore, even if the production interface board 27 is arranged and laminated immediately above the production control board 22, there is no problem in heat dissipation.

  The direct current voltage 12V received from the power supply board 20 by the effect interface board 27 is used as the power supply voltage of the digital amplifier 46 as it is, and is distributed to the motor / lamp drive board 30 and the lamp drive board 29 for each lamp. Group power supply voltage. On the other hand, the direct current voltage 32V received from the power supply board 20 is stepped down to the direct current voltage 13V in the DC / DC converter of the production interface board and distributed to the motor / lamp drive board 30.

  As shown in FIG. 4, the effect control unit 22 ′ controls a one-chip microcomputer (MC) 40 that executes processing such as voice effect, lamp effect, notice effect by effect movable body, and data transfer, and the control of the one-chip microcomputer 40. A flash memory 41 for storing the program PGMe and various effects data EN, a voice synthesis circuit 42 for reproducing and outputting a voice signal based on an instruction from the one-chip microcomputer 40, and a voice signal to be reproduced And an audio memory 43 for storing compressed audio data as original data.

  The voice synthesis circuit 42 and the voice memory 43 are connected by a 26-bit voice address bus and a 16-bit voice data bus. Therefore, 1G-bit compressed audio data can be stored in the audio memory 43. Then, the compressed voice data (16 bits) designated by the voice address bus (26 bits) is output to the voice data bus, and is decompressed by the voice synthesis circuit 42 to reproduce the voice data.

  Incidentally, in the case of the present embodiment, the effect data EN stored in the flash memory 41 includes scenario data for managing the progress of the effect of the lamp effect and the sound effect, the lamp drive data for determining the blinking mode of the LED, the motor Motor driving data for determining the rotation mode of the motor. The lamp driving data and the motor driving data are sequentially output bit by bit to become a lamp driving serial signal and a motor driving serial signal.

As shown in FIGS. 4 and 8, the one-chip microcomputer (MC) 40 and the flash memory 41 are connected by a 23-bit CPU address bus and a 16-bit CPU data bus. The flash memory 41 of the embodiment has a memory capacity of 8M (= 2 ²³ ) × 16 bits, but the control program stored in the flash memory 41 includes the entire control program PGMe including the effect data EN, Built-in program that performs checksum operation. In this checksum calculation, data in the flash memory 41 is added in units of 1 byte, and the result of the addition is stored in a 2-byte length. Therefore, the checksum value is 2 bytes long.

  By the way, the one-chip microcomputer 40, the flash memory 41, and the voice memory 43 operate at the power supply voltage 3.3V, and the voice synthesis circuit 42 operates at the power supply voltage 3.3V and the power supply voltage 1.8V. Therefore, significant power saving is realized. Here, 1.8V is the power supply voltage of the computer core part of the speech synthesis circuit, and 3.3V is the power supply voltage of the I / O part.

  The one-chip microcomputer 40 includes a plurality of parallel input / output ports PIO. The control command CMD and the strobe signal STB from the main control unit 21 are input to the first input port PO1, and the control command CMD ′ and the strobe signal STB ′ are output from the second input port PO2. Has been.

  Specifically, the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 are supplied to the first input port PO1 at the power supply voltage 3.3V in the buffer 44 of the effect interface board 27. Is converted into a logic level corresponding to, and supplied twice in units of 8 bits. The interrupt signal STB is supplied to the interrupt terminal of the one-chip microcomputer, and the effect control unit 22 'is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 ′ includes (1) an abnormality notification and other notification control commands, and (2) control for specifying an outline of various effect operations resulting from winning at the symbol start opening. A command (variation pattern command) and a control command (symbol designation command) for designating a symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the change pattern command is acquired, the effect control unit 22 ′ performs an effect lottery subsequently to further specify the effect outline specified by the acquired change pattern command. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking LEDs and a sound effect preparation operation by a speaker are performed, and an effect operation by a lamp or speaker is performed on the image control unit 23 ′. A control command CMD ′ relating to the synchronized image effect is output.

  In order to realize such an image effect synchronized with the effect operation, the effect control unit 22 ′ controls the 16-bit length together with the strobe signal (interrupt signal) STB ′ for the image control unit 23 ′ through the second input port PO2. The command CMD ′ is output toward the effect interface board 27. In addition, when receiving the symbol designating command, the notification control command related to the display device DS, and other control commands, the effect control unit 22 ′ collects the control commands in units of 8 bits into a 16-bit length. In this state, it is output toward the effect interface board 27 together with the interrupt signal STB ′.

  Corresponding to the configuration of the production control board 22 described above, the production interface board 27 is provided with an output buffer 45, and a 16-bit control command CMD ′ and a 1-bit interrupt signal STB ′ are sent to the image interface. It is output to the substrate 28. These data CMD ′ and STB ′ are transmitted to the image control board 23 via the image interface board 28.

  The effect interface board 27 is provided with a digital amplifier 46 that receives the audio signal output from the audio synthesis circuit 42. As described above, the speech synthesis circuit 42 operates with power supply voltages of 3.3 V and 1.8 V, and the digital amplifier 46 performs class D amplification operation with a power supply voltage of 12 V, reducing power consumption. It is possible to produce a loud sound while suppressing it.

  The left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. Therefore, the voice synthesis circuit 42 needs to generate a three-channel voice signal, and if this is transmitted in parallel, the wiring between the voice synthesis circuit 42 and the digital amplifier 46 becomes complicated.

  Therefore, in this embodiment, the voice synthesis circuit 42 and the digital amplifier 46 are connected by four signal lines in order to prevent deterioration of sound quality and avoid complicated wiring. In this case, the transfer clock signal SCLK, the channel control signal LRCLK, and the 2-bit length serial signals SDATA1 and SDATA2 are suppressed to a total of 4 bit signal lines. Note that the amplitude level of any signal is 3.3V.

  Here, SDATA1 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers arranged at the upper part of the gaming machine, and SDATA2 is a monaural signal of the heavy bass speaker arranged at the lower part of the gaming machine. This is a serial signal for the PCM data to be specified. The voice synthesis circuit 42 transmits the left channel audio signal L while maintaining the channel control signal LRCLK at the L level, and maintains the channel control signal LRCLK at H level while maintaining the channel control signal LRCLK at the L level. Is transmitted. Since there is one heavy bass speaker in this embodiment, a monaural audio signal is transmitted, but it is of course possible to transmit it as a stereo audio signal.

  In any case, in this embodiment, four types of audio signals can be transmitted with four cables, and therefore, signal transmission without audio deterioration due to noise can be performed with the minimum number of cables. That is, since it is serial transmission, the number of cables is overwhelmingly smaller than parallel transmission. When analog transmission is employed, the number of cables is the same, but noise is superimposed on an analog signal having an amplitude of 3.3 V, and the sound quality is greatly deteriorated. On the other hand, when the amplitude level is increased, the power supply wiring becomes complicated and the power consumption increases.

  Such serial signals SDATA1 and SDATA2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. In the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after D / A conversion, D-class amplification is performed and supplied to each speaker.

  Although the internal configuration of the digital amplifier 46 is appropriate, FIG. 5 shows an internal configuration diagram when YDA171 (YAMAHA) is used as the digital amplifier. Although it is not limited to such an internal configuration, in any case, in this embodiment, since the voice synthesis circuit 42 and the digital amplifier 46 are connected by a serial line, the bit length of the PCM data (voice data) is increased. Even if the sound quality is improved, it is not necessary to change the wiring cable and the like, and the circuit configuration can be simplified.

  In addition, the effect interface board 27 is provided with buffer circuits 47 and 48 for outputting serial data output from the one-chip microcomputer 40. Here, the output buffer 47 transfers the lamp driving signal (serial signal) transmitted from the one-chip microcomputer 40 to a shift register circuit disposed on the lamp driving substrate 29. A shift register circuit (not shown) on the lamp driving substrate 29 converts the lamp driving signal into a parallel signal and drives the LED lamp group.

  The other buffer circuit 48 functions as an input / output buffer and transfers the serial signal transmitted from the one-chip microcomputer 40 to the motor / lamp drive board 30 as it is, while the origin of the group of effect motors M1 to Mn. An origin sensor signal (serial signal) indicating the position is transferred to the one-chip microcomputer 40.

  In the case of the present embodiment, the serial signal transmitted from the one-chip microcomputer 40 to the buffer circuit 48 includes a lamp driving signal (serial signal) for lighting the lamp group and a motor driving signal (serial) for rotating the effect motor. Signal) is continuous. The motor / lamp drive board 30 divides the series of serial signals into 16-bit lengths and converts each 16-bit length into a parallel signal to execute a lamp effect and a movable notice effect. Specifically, a series of lamp effects is executed as the effect operation determined by lottery in response to the control command CMD, and when a motor drive signal is received, the effect motors M1 to Mn are rotated to appropriately A movable notice effect is being executed.

  FIG. 6A is a block diagram specifically showing the circuit configuration of the motor / lamp drive board 30. As shown in the figure, the motor / lamp drive board 30 includes a PS converter 50 that serially converts the origin sensor signals of the effect motors M1 to Mn, and an input buffer 51 that receives a control signal for the PS converter 50 from the one-chip microcomputer 40. A step-down unit 52 that steps down the DC voltage 13V to 12V, an input buffer 53 that receives a lamp drive signal and a motor drive signal from the one-chip microcomputer 40, and drive control units 54 and 55 that drive and control a lamp group and a production motor group The sink driver 56 receives the drive current of each effect motor. The PS conversion unit 50, the input buffers 51 and 53, the drive control unit 54, and the sink driver 56 operate using a DC voltage of 5V as a power supply voltage.

  The origin sensor signal is an output of an origin sensor that detects whether or not the production motors M1 to Mn are located at the origin, and each origin sensor uses a DC voltage of 12V or 5V as a power supply voltage. These 1-bit and n-bit origin sensor signals are acquired by the PS converter 51 in synchronization with the hold signal LOAD output from the one-chip microcomputer 40, and the PS converter 51 receives the transfer received from the one-chip microcomputer 40. In synchronization with the clock CK, the origin sensor signal is converted into a serial signal and transmitted to the one-chip microcomputer 40.

  As described above, in this embodiment, the one-chip microcomputer 40 can appropriately grasp whether or not each effect motor M1 to Mn is located at the origin. In addition, the possibility of misjudgment is greatly reduced by using a DC voltage (12V, 5V) of a different system from the power supply line (13V) where electromagnetic noise may be superimposed as the power supply voltage of each origin sensor. I am letting.

  Next, in the step-down unit 52, the input side 13V is used as a driving power source for each lamp, the output side 12V is used as a driving power source for the effect motors M1 to Mn, and the power lines are separated from each other. Further, as described above, the input buffer 53 and the drive control units 54 and 55 use the DC voltage 5V generated in a completely different system from the DC voltage 13V as the power supply voltage.

  Therefore, even if the large production motor groups M1 to Mn suddenly start operation, there is a very low possibility that the lamp drive signal of each lamp is affected by power supply noise or the like. Similarly, even if the lamps are flashed violently with high luminance, the possibility that the motor drive signals of the effect motors M1 to Mn are affected by power supply noise or the like is extremely low.

  By the way, the drive control unit 54 for the production motor and the drive control unit 55 for the lamp have the same configuration. From the one-chip microcomputer 40, the operation control signal EN, the serial signal DATA, and the transfer clock signal CK Are operating in common. The serial signal DATA includes a lamp driving signal and a motor driving signal.

  The drive control units 54 and 55 have, for example, 5-bit length address terminals (A0 to A4), and are configured so that addresses can be appropriately assigned. In this embodiment, the address terminals (A0 to A4) having a 5-bit length are fixedly assigned in advance to the H level or the L level as a hardware configuration.

  The drive control units 54 and 55 are configured to have a large number of internal control registers R1 to Rm, and by setting (writing) control data Di (8-bit length) in each of the control registers R1 to Rm, Each output of the 16-bit output terminal is appropriately controlled.

  The register numbers of the control registers R1 to Rm are 8 bits long. In this embodiment, the address terminals (A0 to A4) having a 5-bit length are set in advance to the H / L level, and the addresses ADRi of the elements 54 and 55 are fixed values.

  The operation content realized by setting the control data Di in each control register R1 to Rm includes not only the ON / OFF state of each output terminal but also the fade operation (fade in / out) until reaching the ON / OFF state. ) And the duty ratio (0 to 99.6%) in the PWM control of the output terminal in the ON state. Therefore, the one-chip microcomputer 40 does not need to bother to change the lamp drive signal (serial data) for PWM control at the time of brightness control or fade in / out presentation, and simply changes the control data of the corresponding register Ri. As a result, the control burden is greatly reduced.

  Of course, by controlling the lamp drive signal with PWM, it is possible to perform fade-in / out effects different from fixed fade operations. In short, according to this embodiment, various lamp effects are possible. It becomes. When such various lamp effects are executed, there is a concern that considerable high-frequency noise is superimposed on the output signal of the drive control unit 55, but it is difficult to affect the effect motors M1 to Mn as described above. It is.

  FIG. 6B is a time chart showing a communication protocol between the one-chip microcomputer 40 and the plurality of drive control units 54, 55... As shown in the figure, the one-chip microcomputer 40 first sets the operation control signal EN to the ON state (H level), and (1) the address number ADRi () of the drive control units 54 to 55 to which the control data Di is to be written. (8 bits long), (2) the number of control registers R1 to Rm to write control data Di in the drive control unit (8 bits long), (3) control data Di (8 bits) to be written to the control register Ri Is output as a serial signal in synchronization with the transfer clock signal CK.

  If the first register number Ri is designated for a series of control registers R1 to Rm, the subsequent control data (set values) D1, D2, R3... Are represented by Ri, Ri + 1, Ri + 2. The control data is recognized by the drive control units 54 and 55 and automatically acquired. Therefore, it is not always necessary to set a set value in all the control registers Ri. For example, in the case of a write process to a series of M control registers Ri to Ri + M−1, M pieces of control data and two pieces of address data Therefore, a total output process of 8 × (M + 2) bits is sufficient.

  When the output of all data is completed, the one-chip microcomputer 40 may return the operation control signal EN from the ON state to the OFF state, and the drive control unit identified by the address number ADRi corresponds to this operation. The operation corresponding to the control data D1... Acquired in the series of control registers Ri.

  Since the production motors M1 to Mn execute the movable advance notice production, the production motors M1 to Mn normally stand by at the origin position in the concealed state. Therefore, the drive control unit 54 retains the control data in the OFF state, and normally it is not necessary to receive control data transfer from the one-chip microcomputer (MC) 40. However, since the control drive unit of this embodiment specifies the address number ADRi and receives the control data Di, there is no influence on the drive control unit 54 that is not designated by the address number even if the serial signal is repeatedly transferred. Don't give.

  Therefore, according to the configuration of the present invention, the drive control unit 55... 55 for controlling the lamp that continuously repeats the dynamic lamp effect and the drive control unit 54 for the movable notice effect that rarely starts the notice operation. Can have the same configuration. In addition, the one-chip microcomputer 40 can handle the motor drive signal and the lamp drive signal in the same row except for determining whether or not to add the motor drive signal to the lamp drive signal. The burden can be reduced.

  Further, by setting all or a part of the drive control units 55, 55 for lamp control to the same address value, it is possible to collect the lighting data (control data) transfer processing related to a large number of lamps, and to produce the effect control. The control burden on the unit 22 is reduced. For example, when the right and left lamp groups of the gaming machine are always caused to emit light in the same manner, a drive control unit 55R for driving the right lamp group and a drive control unit 55L for driving the left lamp group are provided. Only by setting the same address value, the lighting data transfer process can be completed at once.

  FIG. 7 is a circuit block diagram illustrating in detail the image control unit 23 ′ (the image interface board 28 and the image control board 23) including the surrounding boards. FIG. 8 is a block diagram illustrating a connection relationship between the memory (ROM / RAM) and the microprocessor (one-chip microcomputer) MC, in particular, for the effect control board 22 and the image control board 23. As described above, the image control unit 23 'operates by receiving the control command CMD', the strobe signal STB ', and the system reset signal SYS from the effect control unit 22'. In addition, two types of DC voltages 5V and 12V are received via the production control unit.

  As shown in FIG. 7, the image control unit 23 ′ receives a control command via the effect interface board 27 and executes an image control operation, and a control program for the one-chip microcomputer 60. A flash memory 61 for storing the image, a VDP (Video Display Processor) 62 for driving the display device DS based on an instruction from the one-chip microcomputer 60, a graphic ROM (CGROM) 63 for storing image compression data for image production, An SDRAM (Synchronous Dynamic Random Access Memory) 64 functioning as a work area (Video RAM) of the VDP 62 and a watchdog timer WDT for forcibly resetting the one-chip microcomputer 60 are included.

  The VDP 62 incorporates an SDRAM interface circuit (SDRAM_I / F), a CGROM interface circuit (ROM_I / F), and a one-chip microcomputer interface circuit (CPU_I / F). FIG. 11). The VDP 62 and the SDRAM 64 are connected via an SDRAM interface circuit (SDRAM_I / F), a 3-bit + 13-bit SDRAM first address bus, a 32-bit SDRAM first data bus, The second address bus for SDRAM of 3 bits + 13 bits and the second data bus for SDRAM of 32 bits are connected.

  Here, among the first and second 16-bit address information, the 3 bits are bank switching signals, and the remaining 13 bits are ROW data (13 bits) and COLUMN recognized by time division. Data (10 bits). Corresponding to this, each memory (SDRAM) is divided into 8 banks, but 3 bits supplied from the VDP 62 to the SDRAM 64 function as a bank switching signal.

  Also, by combining ROW data (13 bits) and COLUMN data (10 bits), the selected address becomes 8192 * 1024 = 8M, and there are 8 banks, so a total of 64M × 16 bits = 1G bits in one memory Become long.

  In the case of the present embodiment, the SDRAM 64 functions as a work area for decompressing moving image compressed data or the like. However, by using a total of 4 DDR2 (double data rate 2) type SDRAMs having a memory capacity of 1 Gbit, a total of 4G The memory capacity is a sufficient amount of bits.

  The data input / output terminal of each memory is 16 bits long, but for a pair of SDRAM 64, the data input / output terminal of one memory is connected to the upper 16 bits of the SDRAM data bus, and the data input / output of the other memory is connected. By connecting the terminal to the lower 16 bits of the SDRAM data bus, high-speed data access in units of 32 bits is possible. Since this is true for the first data bus and the second data bus, when the first and second data buses are combined, data access in 64-bit units is possible. In the present embodiment, in particular, since a DDR2 type SDRAM is used, even high-quality moving image data can be smoothly reproduced without any trouble, and an advanced image effect can be achieved.

  Next, the CGROM 63 will be described. The CGROM 63 is a memory that stores, in a compressed state, image data for generating a high-quality still image, an effect moving image that changes at high speed, and the like. Therefore, there is little possibility that an arbitrary address is randomly accessed like the SDRAM 64, and it is considered that there are many sequential accesses that sequentially access consecutive addresses.

  Therefore, in this embodiment, paying attention to this operation content, all data is read by the ROM data bus without using the ROM address bus prepared in the interface circuit (ROM_I / F) for CGROM. The structure which implement | achieves operation | movement is taken. According to the configuration of the present embodiment, not only the wiring on the substrate can be suppressed and the component space can be secured, but also the manufacturing cost can be suppressed.

  FIG. 9A illustrates an internal configuration of a memory (8 Gbit ROM) suitable for the configuration of the present embodiment. As shown in the figure, this memory has a 32-bit data input / output terminals IO0 to IO31, a chip enable terminal CE, a read clock terminal RE, an operation state output terminal R / B, And a reset terminal RES. Note that the storage capacity of one element is 256M × 32 bits = 8 Gbit length.

  As shown in FIGS. 7 to 8, the CGROM 63 of this embodiment is configured by arranging the above-mentioned 8 Gbit length memories (CG1 to CG4), and the VDP 62 and the CGROM 63 are interface circuits for CGROM ( It is connected via a ROM_I / F) via a 64-bit ROM data bus. As described above, in this embodiment, the ROM address bus is not used.

  Of the four CGROMs, the lower 32 bits of the 64-bit ROM data bus are connected to the memory CG1 and the memory CG3, and the upper 32 bits of the 64-bit ROM data bus are connected to the memory CG2 and the memory CG4. It is connected. A common chip enable signal CE0 and read clock signal RE0 are supplied to the memory CG1 and the memory CG2 (see FIG. 8).

  Therefore, the memory CG1 and the memory CG2 perform a memory read operation at the same timing, and the 32-bit data output from each of the memories CG1 and CG2 is connected via the ROM data bus. Thus, a memory read operation in units of 64 bits is realized. Similarly, a common chip enable signal CE1 and a read clock signal RE1 are supplied to the memory CG3 and the memory CG4, thereby realizing a memory read operation in units of 64 bits.

  FIG. 10A illustrates the internal configuration of the memory CG1 and the memory CG2, and shows the state after address 0X0000 — 0000 for convenience. Note that 0X means hexadecimal notation. For example, the usable final address 0X0FAF_FFFF of this memory corresponds to decimal numbers 263, 192, and 575.

  The VDP 62 of this embodiment manages the data of the CGROM 63 in units of 1 byte, and addresses are assigned in units of 1 byte. Further, the same chip enable signal CE0 and the read clock signal RE0 are commonly supplied to the memory CG1 and the memory CG2, and the same address information is always supplied to the memory CG1 and the memory CG2. It is configured.

  For this reason, the 32 bits of the memory CG1 and the 32 bits of the memory CG2 can be consecutively numbered, and 0, 1, 2, 3, 4, 5, 6, 7 · shown in FIG. ... 4095 means 0 address, 1 address, 2 addresses,... 4095, numbered in units of 1 byte.

  FIG. 9B is a time chart showing the operation contents of each memory (CG1, CG2), and illustrates a memory read operation in which the VDP 62 reads image data from the memory CG1 and the memory CG2 in units of 64 bits. Show.

  First, the VDP 62 asserts the chip enable signal CE0 to L level, and then outputs the read clock signal RE0. The VDP 62 also outputs the same address to the lower 32 bits and upper 32 bits of the ROM data bus. Information AD0 to AD2 is output. Here, the address information AD0 to AD2 is 21-bit data for specifying a base address (start address) of a series of sequential accesses. In these memories CG1 to CG4, since the lower 9 bits (bit8 to bit0) of the base address need to be all 0, the base address becomes a value of 0X200 skip (see FIG. 10A).

  As shown in FIG. 9B, the address information AD0 to AD2 is output in the order of AD0.fwdarw.AD1.fwdarw.AD2 in three steps following the start key data S (= 0XBFBF_BFBF). The output address information AD0 to AD2 is acquired in the memories CG1 and CG2 in synchronization with the rising edge of the read clock signal RE0.

  In this embodiment, the upper 32 bits of the ROM data bus are connected to the memory CG2, and the lower 32 bits of the ROM data bus are connected to the memory CG1 (see FIG. 7). Address information AD0 to AD2 is output in duplicate on the upper 32 bits and lower 32 bits of the ROM data bus. Therefore, for example, when the base point address 0X0000_0000 is accessed, the addresses 0 to 3 of the memory CG1 and the addresses 4 to 7 of the memory CG2 shown in FIG. 10A are accessed together.

  In any case, the address information AD0 is 5 bits of Bit24 to Bit28 out of the 32-bit length address, and the same 5-bit data is also output to Bit8 to Bit12 and Bit16 to Bit20 in duplicate. Therefore, even if bit corruption occurs during data transmission, correct bit data can be acquired in the memory by majority logic or the like.

  On the other hand, the address information AD1 is 8 bits from Bit16 to Bit23 out of the 32-bit length address, and the same 8-bit data is also output to Bit8 to Bit15 and Bit24 to Bit31. Further, the address information AD2 is 8 bits from Bit 8 to Bit 15 in the 32-bit length address, and the same 5-bit data is also output to Bit 16 to Bit 23 and Bit 24 to Bit 31 in duplicate.

  Thus, after outputting the address information AD0 to AD2 in three steps, the VDP 62 outputs the end key data E (= 0X0000 — 0000), whereby the transmission of the address information AD0 to AD2 is completed. Thereafter, when the decoding operation is completed in the memories CG1 and CG2 having received the same address information, the operation state output terminals R / B of the memories CG1 and CG2 are asserted at L level, and then the data in the memories CG1 and CG2 are respectively Are output to the ROM data bus in units of 32 bits. In FIG. 9B, HiZ means a high-impedance state in the three-state output, and-means that the value of the data bus at that timing has no influence on the VDP 62 and the memories CG1 and CG2. Means.

  Since the falling edge of the read clock RE0 output from the VDP 62 is a data output instruction to the memories CG1 and CG2, the VDP 62 acquires data on the ROM data bus after a predetermined timing has elapsed from the falling edge of the read clock RE0. As a result, a memory read operation is executed. Such a memory read operation can be executed continuously as long as the read clock RE0 is continued. According to the configuration of this embodiment, sequential access that accesses consecutive addresses in the order of addresses can be executed quickly. it can.

  When the necessary sequential access is completed, the VDP 62 may return the chip enable signal CE0 to the H level, and as a result, the subsequent ROM data bus is in the HiZ state.

  Note that if new address information (AD0 to AD2) is output following the start KEY data S (= 0XBFBF_BFBF), the memory read of another address can be started, but the base address is 0X0000_0000. The value is a value that is a multiple of 0X200. As shown in FIG. 10A, since the interval between the base address and the next base address is 0X200 = 512, 512 * 64 corresponding to the output of 512 read clocks RE0. Bit data is obtained.

  As described above, according to the configuration of the present embodiment, new data is transferred to the memory CG1 and the memory CG2 by data transmission of the start KEY data S → address information AD0 → address information AD1 → address information AD2 → start KEY data E. After designating the same base point address, 64 bits of data (32 bits of CG1 + 32 bits of CG2) (data for 8 addresses) can be read out together with one read clock, and the read clock is output after that Since 64-bit data can be acquired each time, a quick memory read operation is realized. This relationship is the same for the memory CG3 and the memory CG4.

  By the way, the CGROM configured in this way stores CG data that realizes various types of sprites related to still images and moving images with the data structure shown in FIG. A sprite means a group of images such as a character design and a background image, for example. CG data that realizes such a sprite is divided into pattern attributes and pattern data.

  Here, the pattern data is a bitmap that determines the pattern of the sprite. For example, for a sprite having N × M pixels, each pixel is expressed by, for example, RGB three primary colors (RGB color space) with a 24-bit gradation. In this case, the length is N × M × 3 × 24 bits.

  On the other hand, the pattern attribute is variable length data indicating an attribute value unique to the pattern data, and is composed of a 4-byte length essential attribute area and a variable length extended attribute area (see FIG. 9C). . In addition to the 3-byte data that specifies the vertical and horizontal sizes of the sprite, the essential attribute area includes pattern data information (number of bits per pixel, color space type, etc.), alpha data Includes several bits that specify the storage format, whether or not a checksum value is stored in the extended attribute area, or whether or not an alpha table or palette table exists in the pattern data area It is.

  In this embodiment, by storing predetermined bit data in the essential attribute area, the check attribute value is stored in the extended attribute area. Correspondingly, the 1-byte area of the extended attribute area is stored in the 1-byte area. In addition, a checksum value is stored that, when added to the 8-bit total value of the sprite data, results in an addition of zero.

  When reading the sprite data (CG data), the VDP 62 accompanies the checksum operation, and the addition result obtained by adding the checksum value to the total value at the time of reading all the data does not become zero. In this case, a ROM error interrupt is generated. In response to the ROM error interrupt, the one-chip microcomputer 60 executes predetermined error processing, which will be described later.

  Returning to FIG. 7 and continuing the description, the one-chip microcomputer 60 and the VDP 62 of the image control unit 23 'are connected by a 21-bit CPU address bus and a 32-bit CPU data bus. When evaluated from the one-chip microcomputer 60, the VDP 62 is an I / O device that can be arbitrarily accessed from the one-chip microcomputer 60, and a large number of registers R1 to Rn built in the VDP 62 are targets of READ / WRITE. That is, by writing the information output to the CPU data bus to the predetermined register Ri specified by the address information of the CPU address bus, the VDP 62 can be instructed to execute a predetermined operation, and the predetermined register Rj By reading this information, it is possible to grasp the operation state and operation result of the VDP 62.

  The register Ri built in the VDP includes, for example, (1) a register Rx that defines an operation start address, (2) a register Ry that defines an operation end address, and (3) an operation content when executing a checksum operation. A register Rz to be defined and (4) two result storage registers RsL and RsH are included. Therefore, in this embodiment, by utilizing these registers Rx, Ry, Rz, RsL, and RsH, the VDP 62 is allowed to execute a checksum calculation in an arbitrary area of the CGROM 63, and the one-chip microcomputer 60 stores the calculation result in the register. It is obtained from RsL and RsH.

  This checksum calculation is started when the one-chip microcomputer 60 receives an inspection control command from the upstream one-chip microcomputer 40, from the calculation start address specified in the register Rx to the calculation end address specified in the register Ry. The addition operation defined by the register Rz is executed for the data of.

  More specifically, for the address data in 1-byte units of the CGROM 63, an addition operation in 8-bit units is executed for every 4 bytes, that is, for each memory element, and the calculation results are stored in the two registers RsL and RsH, respectively. Stored in 16-bit length. The arrows in FIG. 10 (b) and FIG. 10 (c) indicate the procedure of this checksum calculation. For a given memory element CGi, 8 bytes for 4 bytes for each byte from the execution start address. When the bit addition operation is completed, the 8-bit addition operation is continued for the continuous addresses of the same memory element CGi. When the addition operation up to the operation end address is completed, the 16-bit operation result is stored in the register RsL and the register RsH. Is done.

  In the illustrated example, the checksum operation is collectively performed on the memories CG1 and CG2, the addition result of the memory CG1 is stored in the register RsL, and the addition result of the memory CG2 is stored in the register RsH. This is the same for the memories CG3 and CG4. For the memories CG3 and CG4, the checksum operation is collectively performed, the addition result of the memory CG3 is stored in the register RsL, and the addition result of the memory CG4 is stored in the register RsH. Is saved.

  In this embodiment, although 64-bit data can be acquired by one access to the CGROM 63, an 8-bit addition operation is executed every 4 bytes, and the result is obtained in 2-byte length. Since the data is stored, the garbled data can be detected for each memory element CGi. That is, unlike the present embodiment, if 64-bit data is continuously added, even if bit corruption can be detected, the memory element in which bit corruption has occurred cannot be specified.

The SDRAM 64 and the CGROM 63 have been described above. Next, the flash memory 61 of the image control unit 23 ′ will be described. The one-chip microcomputer 60 and the flash memory 61 are connected by a 23-bit CPU address bus and a 16-bit CPU data bus. The flash memory 61 has a memory capacity of 8M (= 2 ²³ ) × 16 bits, but the control program includes a program that executes the same checksum operation as the VDP 62 executes for the entire control program including constant data. Built in. That is, the entire flash memory 61 is also subjected to an addition operation in units of 1 byte, and the operation result is stored in a 16-bit length.

  Returning to FIG. 7 and continuing the description, the output of the watchdog timer WDT shown in FIG. 7 is supplied to the OR circuit together with the system reset signal SYS, and when any of the input signals to the OR circuit becomes an active level, The one-chip microcomputer 60 and the VDP 62 are reset synchronously. Therefore, when the control operation is initialized due to the program runaway of the one-chip microcomputer 60, the operation of the VDP 62 is initialized correspondingly, and the contradictory and unnatural image effect is executed. It will not be done.

  In this embodiment, the power supply voltage of each element is minimized in order to suppress the power consumption as much as possible. The power supply voltage of each element is (1) the one-chip microcomputer 60 is 3.3V and 1.25V. (2) Flash memory 61 is 1.25V, (3) VDP62 is 3.3V, 1.8V and 1.1V, (4) CGROM 63 is 3.3V, and (5) SDRAM 64 is 1.8V. .

  As described above, in this embodiment, a large number of DC voltages are required to save power, and the supply timings of circuit elements having a plurality of power supply voltages need to be optimized. On the other hand, only two types of direct current voltages are distributed for the purpose of suppressing the number of wiring cables between the effect control unit 22 'and the image control unit 23'.

  Therefore, by arranging a plurality of DC / DC converters having control terminals and providing a power sequencer 65, a large number of DC voltages are supplied to each element at an optimal timing. FIG. 12 shows an internal configuration (a) of LM3881 (national semiconductor) as an example of the power sequencer 65 and an operation time chart (b) executed even when the power sequencer 65 is used.

  In the case of the power sequencer 65 in FIG. 12A, when the INV terminal is at the L level, the operation starts in response to the operation start command EN at the H level, and the clock defined by the capacitance connected to the TADJ terminal. The first control signal PCNT1 rises after nine cycles of the signal Clock, the second control signal PCNT2 rises after eight cycles of the clock signal, and the third control signal PCNT3 rises after another eight cycles of the clock signal.

  On the other hand, when the operation start command EN transitions to the L level, the third control signal PCNT3 falls after 9 cycles of the clock signal, the second control signal PCNT2 falls after 8 cycles of the clock signal, and further 8 cycles after the clock signal. The third control signal PCNT3 falls.

  In the present embodiment, as shown in FIG. 7, the operation start command EN is an AND logic output of two types of DC voltages supplied from the effect control unit 22 '(effect interface board 27). The first control signal PCNT1 is supplied to the operation enable terminal EN of the DC / DC converter V1 for generating 1.1V, and the second control signal PCNT2 is an operation enable for the DC / DC converter V2 for generating 3.3V. It is supplied to the terminal EN.

  The third control signal PCNT3 is converted into an AND logic output with 3.3V and supplied to the operation enable terminal EN of the DC / DC converter V3 for generating 1.8V. Each DC / DC converter described above starts the voltage conversion operation on condition that the operation enable terminal EN becomes H level.

  Therefore, as shown in FIG. 12B, the DC / DC converter V1 first functions based on 5V distributed from the effect control unit 22 'to generate the DC voltage 1.1V. This DC voltage 1.1V is a power supply voltage for the digital circuit and the built-in VRAM built in the VDP 62, and the normal operation start sequence of the VDP 62 after the power is turned on by starting the operation before other built-in circuits. Is secured.

  After the above operation, since the second control signal PCNT2 becomes H level, the DC / DC converter V2 that receives 12V distributed from the effect control unit 22 'functions to generate the DC voltage 3.3V. The DC voltage 3.3V is supplied to the DC / DC converter V4 for 1.25V. Since this converter V4 does not have an operation enable terminal, the DC voltage 1.V is started immediately. 25V is generated.

  The two types of DC voltages 3.3V and 1.25V generated by being controlled by the second control signal PCNT2 are supplied to the one-chip microcomputer 60, the flash memory 61, and the CGROM 63 at almost the same timing. Each of the circuit elements is ready for operation start without delay after power-on. At this timing, the system reset signal SYS is at the L level, and after this level has been maintained for a while, the power supply circuit of the power supply board is operating so as to change to the H level. The power will be reset.

  Finally, when the third control signal PCNT3 changes to H level, the AND logic output of the third control signal PCNT3 and 3.3V is supplied to the DC / DC converter V3 to generate a DC voltage of 1.8V. This DC voltage 1.8 V is supplied to the VDP 62, SDRAM 64, and SDRAM power supply circuit 68 at almost the same timing, so that the SDRAM 64 and the SDRAM interface circuit in the VDP 62 can be operated in synchronization. Become. Therefore, when the system reset signal SYS changes to the H level, the VDP 62 can smoothly start the initial setting operation.

  FIG. 11 is a block diagram showing an internal configuration of the VDP 62 and a connection relationship between the SDRAM 64, the CGROM 63, and the one-chip microcomputer. The VDP 62 reads CG data from the CGROM 63 based on an instruction from the one-chip microcomputer 60, and generates and outputs a series of image data groups for varying effects executed by the display device DS. The variation effect image data group is finally generated by the display controller 78 and output to the LVDS_I / F unit 75.

  Here, each of the image data group for change effect and the image data group for notice effect is configured by combining moving image data that continuously changes and still image data that does not move continuously. In addition, the RGB pixels constituting the image data group for variation effect are each 8 bits long (256 gradations), and realize high-quality image effects on the display device DS.

  As shown in the figure, the one-chip microcomputer 60 and the VDP 62 are connected via a CPU_I / F unit, and the command memory 70 stores a large number of command lists for specifying a series of image effects in advance. The command list is classified into a variable effect and a notice effect, and various types of lists are prepared to increase the variety of effects.

  The one-chip microcomputer 60 accesses the system control register 71 when necessary, and sets a start address of a predetermined command list that specifies a series of image effects to be executed. Then, the command parser (syntax analyzer) 72 analyzes the command list specified by the system control register 71 and passes the internal code corresponding to the analysis result to the internal modules such as the moving picture decoder 73 and the still picture decoder 74. . Then, each internal module starts its operation, secures necessary image data in the VRAM (Video RAM) area based on the CG data of the CGROM 63, and sends the frame image data to the LVDS_IF unit (LVDS transmission) every predetermined time. Part) 75. The LVDS_IF unit 75 is a part that converts frame image data into an LVDS signal and outputs it.

  By the way, in this embodiment, in order to facilitate a series of drawing operations by the VDP 62 at high speed, the CGROM 63 includes moving image compression data for specifying a series of moving images that change at high speed, still compression data for specifying a still image, Is memorized separately. The still compressed data read from the CGROM 63 via the ROM_I / F unit and the CG memory controller is expanded by the still image decoder 74 and temporarily stored in the built-in VRAM 77. On the other hand, the moving image compressed data read from the CGROM 63 is configured to be decompressed by the moving image decoder 73 and temporarily stored in the SDRAM 64.

  That is, in this embodiment, since the external SDRAM 64 is used as the VRAM, there is no limit on the memory capacity as in the case of using the built-in RAM. It is also possible to continuously decode the moving image compressed data and secure it in advance of the SDRAM, so that image processing can be realized at high speed. In addition, the RAM 64 of this embodiment is composed of a DDR2 SDRAM (Double-Data-Rate 2 SDRAM), and realizes data transfer at a higher speed than the SDRAM, and generates two non-common image data at high speed. be able to.

  The image data secured in the VRAM areas 64 and 77 in this way is read by the display controller 78 and output from the LVDS / IF unit 75 after gamma correction or the like.

  FIG. 13 shows the relevant part (LVDS transmitter 75) of FIG. 7 and FIG. 11 in more detail with respect to the connection relationship between the VDP 62 having the above-described internal configuration and the display device DS. As shown in the figure, the display device DS of the present embodiment is configured to include an LVDS reception unit (LVDS_I / F) 81 corresponding to the LVDS transmission unit (LVDS_I / F) 75 of the VDP 62.

  As shown in FIG. 13A, the LVDS_I / F unit (LVDS transmission unit) 75 is a part that converts parallel data including 24 bits of RGB data into an LVDS (low voltage differential signaling) signal. LVDS means a low-voltage differential transmission system for high-speed transmission of RGB data and the like with low noise and low power. In this embodiment, several mA is applied to a pair of signal transmission lines (one twisted pair line). While a low level signal current is supplied from the transmission side, this signal current is received by a terminating resistor of about 100Ω provided on the reception side. Therefore, although the voltage amplitude is a low level of about several hundred mV, reliable signal transmission is realized by changing the current direction corresponding to the logic level (H / L).

  In this embodiment, as shown in FIG. 13A, a total of 28-bit parallel data (TA0 to TA0) including all 24-bit RGB signals (each 8 bits long) and horizontal / vertical synchronization signals. TA6, TB0 to TB6, TC0 to TC6, TD0 to TD6) are converted into four pairs of differential signals in the LVDS transmission unit 75. Then, a differential signal of a pair of transfer clocks is added to this and transmitted to the display device DS through five twisted pair lines.

  7 and 13A, these four pairs of differential signals are evaluated from the standpoint of the display device DS, and (RXIN0 +, RXIN0−), (RXIN1 +, RXIN1-), (RXIN2 +, RXIN2−) are evaluated. ), (RXIN3 +, RXIN3 +), (RXCLK +, RXCLK−).

  As shown in FIG. 13B, during a period of the transfer clock RXCLK, the twisted pair lines (RXIN0 +, RXIN0−) serially transfer G0 → R5 → R4 → R3 → R2 → R1 → R0 to obtain a twisted pair line. In (RXIN1 +, RXIN1-), B1 → B0 → G5 → G4 → G3 → G2 → G1 are serially transferred, and in the twisted pair lines (RXIN2 +, RXIN2-), DE → (VS) → (HS) → B5 → B4 → B3 → B2 is serially transferred, and NA → B7 → B6 → G7 → G6 → R7 → R6 is serially transferred on the twisted pair line (RXIN3 +, RXIN3-).

  Here, R0 to R7 are 8-bit length data indicating the luminance of the red pixel, G0 to G7 are 8-bit length data indicating the luminance of the green pixel, and B0 to B7 are 8-bit length data indicating the luminance of the blue pixel. It is. In addition, (VS) and (HS) indicate vertical synchronization timing and horizontal synchronization timing, and DE means DATA ENABLE. Note that NA is unused.

  The display device DS that receives the four pairs of differential signals is provided with an LVDS receiver 81 corresponding to the LVDS transmitter 75 of the VDP 62. A series of serial data is converted into parallel data, and four sets of parallel data RA0 to RA6, RB0 to RB6, RC0 to RC6, and RD0 to RD6 are obtained. As apparent from the serial data string shown in FIG. 13B, the parallel data RA0 to RA6 are specifically 7 bits of R0 to R5 and G0, and other parallel data are also shown in FIG. 13B. This corresponds to the serial data shown.

  The display device DS realizes screen display based on the RGB gradation data extracted from these. In this way, in this embodiment, the pixel data is 8 bits for each RGB (256 gradations), and a full color image effect can be realized.

  Moreover, since the LVDS signal is used for signal transmission between the VDP 62 and the display device DS, the voltage amplitude is low enough (several hundred mV), and the rise time and fall time of the digital signal are correspondingly short, so high-speed communication is possible. It can be realized, and an image effect transitioning to a high speed can be realized smoothly. Moreover, since it is not affected by common mode noise, an unnatural pixel does not occur.

  Further, since the number of cables is small, space saving and cost reduction are realized, and signal transmission can be performed with a low level voltage, so that power saving can be achieved. Therefore, by utilizing these advantages, it is possible to enrich game effects by arranging more movable effects bodies.

  Since the twisted pair lines (RXIN3 +, RXIN3-) are configured to serially transfer NA → B7 → B6 → G7 → G6 → R7 → R6, the twisted pair lines (RXIN3 +, RXIN3-) are not used, or In addition, by serially transferring NULL data through the twisted pair lines (RXIN3 +, RXIN3-), it is easy to suppress 64 gradations of 6 bits for each of RGB.

  Incidentally, as shown in FIG. 7, in addition to the above-described LVDS signal, two types of DC voltages (12V, 3.3V) and a PWM control signal VBR are transmitted to the display device DS from the image interface board 28. ing.

  Here, the direct-current voltage 3.3V is a power supply voltage of the electronic circuit of the display device DS including the LVDS receiver 81, and the power is reduced by the low power supply voltage. On the other hand, the DC voltage 12V is a power supply voltage of the liquid crystal backlight unit BL composed of LED lamps. In this embodiment, the backlight unit BL is configured by a plurality of LED lamps connected in series, and the cold cathode tube is not used. Therefore, the circuit configuration can be simplified, the power can be reduced, and the performance can be improved. .

  On the other hand, in order to use a cold cathode tube, an inverter circuit that converts a high voltage of about 32 V DC to an AC voltage of about 1000 V at a frequency of about 30 kHz to 45 kHz is necessary, a large installation space, and high power consumption. Although it has become a noise source on the top (about several watts), all of these problems are solved in this embodiment.

  That is, since the backlight unit BL of this embodiment is a DC drive of 12V, it does not become a noise source, an inverter circuit is unnecessary, and power consumption is reduced to half or less.

  Further, the display device DS of this embodiment has a built-in drive circuit that receives a DC voltage of 12 V and supplies a drive current of about 40 to 65 mA to a plurality of LED lamps. This drive circuit is configured so that the dimming of the LED lamp can be controlled by the PWM control signal VBR. For example, for a gaming machine in which a player is not seated, the backlight can be turned off. But power saving is realized.

  Note that the PWM control signal VBR of the embodiment has a voltage amplitude of 3.3 V and is configured so that the duty ratio can be arbitrarily set in the range of 0 to 100%. And the brightness | luminance of a backlight can be changed to a desired level by changing a duty ratio suitably in the state which sent regulation current (40-65mA) to LED of an energized state.

  The hardware configuration of the gaming machine according to the present embodiment has been described above. Next, the control operation realized by the one-chip microcomputer MC of the effect control unit 22 and the image control unit 23 'will be described.

  FIG. 14 is a flowchart for explaining the operation of the effect control unit 22 that executes the effect operation based on the control command CMD received from the main control unit 21. Note that an inspection control command CMD (test command TST) may be received from the inspection apparatus EX at the development stage or during defect inspection (see FIGS. 3 and 8).

  As shown in the figure, the effect control unit 22 includes a main process (a) that is started when the CPU is reset, a reception interrupt process (b) that is activated by a strobe signal STB, and a first timer interrupt that is activated every 10 mS. It includes a process (c) and a second timer interrupt process (d) started every 2 mS.

  As shown in FIG. 14C, in the first timer interrupt process, the interrupt flag is set to the ON state and the process ends (ST32). Further, as shown in FIG. 14 (d), in the second timer interrupt process, a lamp effect process (ST33) for driving the electric lamp and an effect motor process (ST34) for driving the effect movable body as necessary. It is executed every 2 ms.

  As shown in FIG. 14A, in the main process (CPU reset process), the initial setting in the one-chip microcomputer 40 is executed (ST10), and then the backup determination process is executed (ST11). The backup determination process is a process for determining the validity of the data stored in the backup process (ST28). Data stored in the backup process (ST28) is not particularly limited. For example, (1) a sum value of a checksum calculation for predetermined data in the RAM area, (2) specific data discretely stored in the RAM area, (3) Backup data in which predetermined data in the RAM area is stored in another area can be exemplified.

  In the determination of such backup data, if the validity cannot be confirmed, the entire area of the RAM is initialized, and the production control unit 22 is shifted to the process of step ST13 to cold start (ST12).

  By the way, unlike the main control unit 21 and the payout control unit 24, the production control unit 22 is not provided with a backup power source, and therefore it may not be possible to detect legitimate data in the backup determination process (ST11). However, the CPU is reset not only at the time of power reset corresponding to power-on, but also at the time of abnormal reset when the CPU reset signal becomes an active level due to noise or a watchdog timer.

  Therefore, in this embodiment, a backup determination process (ST11 to ST12) is provided in order to continue the game operation up to that point and to hot start the operation of the effect control unit 22 as much as possible when the CPU is reset abnormally. Yes.

  However, since not all data is determined in the backup determination process (ST28), the operation of the effect control unit 22 should be returned to the initial state when the CPU is repeatedly abnormally reset. Accordingly, the abnormality counter is incremented (+1) to count the number of abnormal resets (ST14), and if the value of the abnormality counter exceeds a predetermined value (for example, 2), the RAM clear process in step ST13 is performed to cold start. (ST15).

  As described above, even when the CPU is abnormally reset, if the backup determination (ST11) makes a correct determination and the number of abnormal resets is equal to or less than a predetermined value, the effect control unit 22 is hot-started and the game up to that point Operation continues.

  Next, the effect control unit 22 initializes the operation position of the accessory that moves appropriately and executes the notice effect regardless of whether it is hot-started or cold-started (ST16). Then, necessary initial settings are executed for the audio reproduction output circuit (audio reproduction IC) 42 (ST17). Thereafter, the CPU of the one-chip microcomputer 40 is set to the interrupt permitting state (ST18), and the random number value is updated (ST19), and a timer interrupt at an interval of 10 mS is waited (ST20). Note that the updated random value is used in the effect lottery process in order to randomize the effect operation.

  As shown in FIG. 14C, an interrupt flag is set every time a timer interrupt occurs at an interval of 10 mS (ST32). Therefore, in the process of step ST20 of the main process, it is repeatedly checked that the interrupt flag is turned on. . When the interrupt flag is turned ON, the timer update process is executed after resetting the interrupt flag to OFF (ST21).

  Subsequently, command analysis processing is executed for the control command (reception command) received in the reception interrupt processing (FIG. 14B) (ST22). The received command includes a variation pattern command, a stop command that defines the stop timing of the symbol variation operation, and the like.

  If the newly received control command is a variation pattern command, the effect lottery is executed, and the effect command specified by the lottery result is transmitted to the image control unit 23 ′ and specified by the effect command. The flag setting process necessary to start the production operation is executed. If a stop command is received, it is transferred to the image control unit 23 and a flag setting process necessary for stopping the presentation is executed.

  In addition, a test command TST for inspecting whether or not the storage contents of the nonvolatile memories mounted on the control boards 22 and 23 are normal may be received from the inspection apparatus EX. This will be described later with reference to FIG.

  When the command analysis process (ST22) is completed, an error process (ST23) and an input process (ST24) for the chance button 11 are executed as necessary. Further, an effect scenario for the lamp effect (ST33), the effect motor process (ST34) and the sound effect (ST26) is created or updated (ST25). Next, an audio effect based on the created or updated effect scenario is executed (ST26).

  Subsequently, after clearing the watchdog timer WDT (ST27) and the backup process (ST28), the process proceeds to step ST18. Examples of the backup processing include not only checksum calculation but also processing for storing specific data discretely, processing for storing all data in the work area, and the like.

  FIG. 15 is a flowchart for explaining the operation when the test command TST is received in the command analysis process (ST22). In this embodiment, the timing at which the test command TST can be received is limited after the CPU reset and before receiving the normal control command CMD. When the normal control command CMD is received, the test command TST received after that is received. Is configured to ignore.

  In order to realize such an operation, an operation mode flag FLG is prepared, and when the CPU is reset, FLG = 0 is set to an initial state in which the test command TST can be received. Thereafter, the normal control command CMD is set. Is received, the operation mode flag FLG = 2 and subsequent acceptance of the test command TST is prohibited. Note that the operation mode flag FLG = 1 indicates that the first byte of the 2-byte checksum value calculated by the effect control unit 22 has been transmitted to the image control unit 23 ′. It means that the eyes should be transmitted.

  Based on the above, the process of FIG. 15 will be described. First, it is determined whether or not the operation mode flag FLG is 1 (ST40). This process is executed regardless of whether a new control command is received. If the operation mode flag FLG = 1 and the upper 1 byte of the checksum value has been transmitted to the image control unit 23 ′, the process proceeds to step ST54, and the lower 1 byte of the checksum value. Is transmitted.

  On the other hand, when the operation mode flag FLG ≠ 1, it is determined whether a new control command has been received regardless of whether it is the normal command CMD or the test command TST (ST41), and there is an unprocessed control command. If so, it is next determined whether or not this is a test command TST (ST42).

  In this embodiment, various test commands are prepared. For example, (1) LEDs are all turned on, (2) LEDs are turned off completely, (3) LEDs are turned on in a predetermined lighting pattern. , (4) command for instructing an operation such as causing a predetermined effect motor to execute a predetermined operation, (5) checking the ROM of the effect control unit 22, and (6) checking the ROM of the image control unit 23 ′. It is included.

  The test command for instructing the ROM check of the effect control unit 22 includes the control program PGMe and the effect data EN of the flash memory 41 of the effect control unit 22, the control program PGMg of the flash memory 61 of the image control unit 23 ′, For CGROM 63 (CG1 to CG4), a test command TSTa for instructing to display each checksum value on the display device DS is included.

  Further, in place of the test command TSTa, a test command TSTb for instructing to display the checksum value of the control program PGMe on the display device DS or an instruction to display the checksum value of the effect data EN on the display device DS is instructed. The test command TSTc may be received from the inspection apparatus EX.

  Therefore, if it is determined in step ST42 that the normal control command CMD has been received, the operation mode flag FLG is set to FLG = 2 (ST58), and processing corresponding to the control command CMD is executed.

  Since the operation mode flag FLG = 2 is set in the process of step ST58, reception of the test command TST is ignored thereafter. Specifically, prior to the processing of the test command, the value of the operation mode flag FLG is determined (ST43). If FLG = 2, the subroutine processing is finished as it is.

  On the other hand, if FLG ≠ 2, it is subsequently determined whether or not a predetermined test command TSTa has been received (ST44). If the test command TSTa has been received, the received command TSTa is sent to the image control unit 23. (ST45), the operation mode flag FLG is set to FLG = 1 (ST46), and the process proceeds to step ST49.

  The transferred test command TSTa is a command for instructing the ROM check of the image control unit 23 ′ for the image control unit 23 ′. Upon receiving this test command TSTa, the image control unit 23 ′, in addition to all the checksum values (five types) calculated by the image control unit 23 ′, subsequently checksum values transmitted from the effect control unit 22 (Two types) are displayed on the display device DS.

  On the other hand, if it is determined in step ST44 that the test command TSTa has not been received, the effect control unit 22 then determines whether or not a test command TSTb has been received (ST47). If the test command TSTb is received, the test command TSTb is transferred to the image control unit 23 '(ST48).

  Since the test command TSTb is an instruction related to the checksum value of the control program PGMe, the image control unit 23 ′ receiving the test command TSTb then displays the checksum value of the control program PGMe transmitted from the effect control unit 22 on the display device DS. Will be displayed.

  On the other hand, the effect control unit 22 calculates a checksum value by executing a checksum calculation of the control program PGMe following the process of step ST48 (ST49). As described above, the checksum operation is a 1-byte addition operation, and the addition result (checksum value) is 2 bytes long.

  Therefore, the effect control unit 22 transmits the upper 1 byte and the lower 1 byte of the checksum value to the image control unit 23 'in time sequence (ST50 to ST51). Specifically, first, DC ** is transmitted to the image control unit 23 'in a 4-digit hexadecimal number, and then DD ** is transmitted to the image control unit 23'. Here, ** is the upper 1 byte or the lower 1 byte of the checksum value.

  By the way, when it is determined in the process of step ST47 that the test command TSTb has not been received, it is determined whether or not the test command TSTc has been received (ST52). If the test command TSTc is received, the test command TSTc is transferred to the image control unit 23 '(ST53).

  Since the test command TSTc is an instruction related to the checksum value of the effect data EN, the image control unit 23 ′ receiving the test command TSTc then displays the checksum value of the effect data EN transmitted from the effect control unit 22 on the display device DS. Will be displayed.

  On the other hand, the effect control unit 22 performs a checksum operation on the effect data EN following the process of step ST53, and calculates a checksum value having a 2-byte length (ST54). Then, the upper 1 byte and the lower 1 byte of the checksum value are transmitted to the image control unit 23 'in time sequence (ST55 to ST56).

  Specifically, first, DE ** is transmitted to the image control unit 23 'in a 4-digit hexadecimal number, and then DF ** is transmitted to the image control unit 23'. In this case as well, ** means the upper 1 byte or the lower 1 byte of the checksum value. Then, the operation mode flag FLG is set to FLG = 0, and the subroutine processing is finished (ST57).

  On the other hand, if a test command other than those described above has been received, processing corresponding to the instruction is executed after the determination in step ST52. The processing content is appropriately determined. For example, various operation tests of LEDs with respect to lamp effects, various operation tests of motors and solenoids with respect to movable accessory effects, and voice operation tests with respect to sound effects may be exemplified. it can. Note that the number of test commands and the operation content when receiving each test command are determined as appropriate, and for example, the operation shown in FIG. 19 is conceivable.

  As described above, the production control unit 22 has been described in detail. Next, the operation of the image control unit 23 'will be described. The image control unit 23 ′ includes a main process (FIG. 16A) started by resetting the CPU, a reception interrupt process (not shown) activated by a strobe signal STB ′, and a ROM error interrupt (FIG. 16C). )) And a V blank interrupt.

  As shown in FIG. 16A, in the main process that is started after the CPU is reset, an initialization process is first executed (ST61). The CPU reset includes not only a power reset but also an abnormal reset in which the CPU reset signal becomes an active level due to noise or a watchdog timer WDT.

  The specific contents of the initialization process are as shown in FIG. 16B. First, it is determined whether or not the CPU reset is caused by power-on (ST70). Next, the value of the abnormality counter is determined (ST71), and if the value of the abnormality counter is 3 or more, the cold start process shown in steps ST72 to ST77 is executed.

  Specifically, first, each part of the one-chip microcomputer 60 is initialized (ST72), and the CPU work area of the built-in RAM is cleared to zero (ST73). Since a flag value and a counter value for managing a series of image effects (design variation operations) are secured in the work area of the CPU, the image effects are completely initialized by clearing them to zero.

  Next, all the VDP work areas that store the flag values and counter values that define the operation of the VDP 62 are cleared to zero, and the internal registers of the VDP 62, VRAM (Video RAM), and others are also initialized. (ST74 to ST77). As a result, the display device DS has exactly the same initial display contents as when the power is turned on.

  On the other hand, if it is determined in step ST71 that the value of the abnormality counter is less than 3, hot start processing shown in steps ST78 to ST82 is executed instead of the cold start processing described above.

  In the hot start process, first, the abnormality counter is incremented (+1) (ST78), and each part of the one-chip microcomputer 50 is initialized (ST79). However, the CPU work area is not cleared to zero and the data before the CPU reset is maintained as it is.

  The same applies to the VDP 62, and the internal registers are initialized without clearing the VDP work area to zero (ST80). However, since the VRAM is initialized (ST81), for the display device DISP, the screen before the CPU reset disappears for a moment. However, since the image production so far is re-executed back to an appropriate timing by the hot start (ST82), no particular problem occurs.

  When the initialization process (ST61) is completed, the watchdog timer is cleared (ST62), various timers for managing the progress of the image effect are updated (ST63), and transmitted from the effect control unit 22. Command analysis processing is executed for the control command CMD ′ (ST64). The control command CMD ′ (including the effect command) and the test commands TSTa to TSTc transmitted from the effect control unit 22 are acquired by reception interrupt processing (not shown) and stored in the reception buffer.

  Therefore, after analyzing the type of the newly received control command CMD '(ST64), the command-specific processing corresponding to the control command type is executed (ST65). The command-by-command processing (ST65) is executed when a change stop process executed when a stop command is received, a change start process executed when an effect command corresponding to a change pattern command (effect command) is received, or when a notice command is received. A notice process, a jackpot start process for starting the effect of the jackpot state, and the like are included.

  When a test command is received from the effect control unit 22, the process of FIG. 17 is executed. Hereinafter, a description will be given with reference to FIG. After determining whether or not any control command is newly received (ST90), it is determined whether or not a test command TSTa is received (ST91).

  When the test command TSTa has been transferred, the calculation start address, the calculation end address, and the calculation method are written in a predetermined register of the VDP 62 to check the CGROM 63 (CG1 to CG4) with respect to the VDP 62. The sum calculation is instructed, and the checksum value calculated in the corresponding register is displayed on the display device DS (ST92).

  As described with reference to FIG. 10, when an instruction from the one-chip microcomputer 60 is written in a predetermined setting register, the VDP 62 performs an addition operation in units of 8 bits on the data stored in the CGROM 63, and the result of the addition is 2 bytes. The length is stored in predetermined registers RsL and RsH. Specifically, first, 16 bits × 2 addition results are obtained for the memories CG1 and CG2 and displayed on the display device DS. Next, 16 bits × 2 addition results are obtained for the memories CG3 and CG4. Obtained and displayed on the display device DS.

  Next, with respect to the flash memory 61 (control ROM) of the image control unit 23 ', the one-chip microcomputer 60 itself performs the same addition operation as described above, and displays the addition result on the display device DS (ST93). As a result, as illustrated in the lower column of FIG. 17, in the lower five lines of the display screen, the checksum values of the flash memory (PG) 61, CG1, CG2, CG3, and CG4 are hexadecimal numbers 4 respectively. Displayed in digits. Therefore, a defective ROM can be reliably identified during development and maintenance.

  Further, following the NO determination in step ST91, it is determined whether or not the test command TSTb has been transferred (ST94). If the test command TSTb has been received, the flash memory 41 of the effect control unit 22 is In order to display the checksum value of the program part (EN-ROM), a screen of the display device DS is prepared (ST95). It should be noted that the checksum value (2 bytes long) to be displayed is thereafter transmitted from the effect control unit 22 on a byte-by-byte basis in the form of DC ** or DD **.

  When the command DC ** or the command DD ** is received from the effect control unit 22, the checksum value is sequentially displayed on the display screen DS for each byte (ST98 to ST99). Note that the command DC ** and the command DD ** are transmitted even after the test command TSTa, and the same processing is executed. In the uppermost column of FIG. 17, a checksum value (−−−−) of 4 hexadecimal digits (1 byte) is displayed as EN-ROM 0X −−−.

  On the other hand, if the determination in step ST94 is NO, it is determined whether or not the test command TSTc is transferred (ST96). If the test command TSTc is received, the flash memory of the effect control unit 22 is determined. For 41, a screen of the display device DS is prepared to display the checksum value of the effect data portion (ED-ROM) (ST97). The checksum value to be displayed (2 bytes long) is then transmitted from the effect control unit 22 in the form of DE ** or DF **.

  When the command DE ** or the command DF ** is received from the effect control unit 22, the checksum value is sequentially displayed on the display screen DS for each byte (ST100 to ST101). Note that the command DE ** and the command DF ** are transmitted even after the test command TSTa, so the same processing is executed. Below the uppermost column in FIG. 17, a checksum value (−−−−) of hexadecimal 4 digits (1 byte) is displayed as ED-ROM 0X.

  As described above, since the present embodiment is configured to include the three test commands TSTa to TSTc, (1) program (EN) check of the flash memory 41 of the effect control unit 22 and (2 ) Effect data (ED) check of flash memory 41 of effect control unit 22, (3) Program and data of flash memory 41 of effect control unit 22, program (PG) and CGROM (CG1 to CG4) of image control unit 23 ′ ) Check can be performed.

  The malfunction of the rendering operation includes (a) a lamp rendering abnormality or a sound rendering abnormality caused by the flash memory 41 of the rendering control unit 22, (b) an image rendering abnormality caused by the control program of the image control unit 23 ′, ( c) Although there are a wide variety of image rendering abnormalities that appear to have problems with CG data, according to the configuration of the present embodiment, the cause of the malfunction can be quickly identified by properly using the test commands TSTa to TSTc. Can do. Of course, the type of the test command is not limited to TSTa to TSTc, and as shown in FIG. 19, a configuration may be adopted in which abnormalities in stored contents are individually checked for each ROM element.

  The case where the test command is received has been described above. However, when the normal control command CMD is received, the image effects of the above-described change start process, notice process, change stop process, and jackpot start process are performed. Start.

  Next, returning to FIG. 16, the operation after the completion of the command processing will be described. When the command-by-command processing (ST65) ends, an effect scenario for the image effect (symbol changing operation) is created or updated (ST66), and a V blank interrupt is waited (ST67). The V blank interrupt means an interrupt supplied from the VDP 62 to the one-chip microcomputer 60 in synchronization with the vertical synchronization signal of the display device DS.

  Then, if there is a V blank interrupt, based on the effect scenario updated in the process of step ST66, the image effect is advanced by writing necessary operation parameters in the register of the VDP 62 (ST68). Return to processing. In the image effect progress process (ST68), the error counter is cleared to zero at the start of a single effect.

  Finally, the ROM error interrupt will be described with reference to FIG. As described above, this ROM error interrupt is activated when a checksum error occurs at the timing when the VDP 62 finishes reading the sprite data from the CGROM 63.

  When the ROM error interrupt is activated, the corresponding error counter ERi is incremented by 1, and the value of the updated error counter ERi is determined (SS10 to SS11). Here, the error counter ERi is configured to include 14 bits specifying the sprite i in which the data abnormality is recognized, and the least significant 2 bits functioning as the error counter ERi.

  Therefore, when a ROM error interrupt occurs for a specific sprite i for the first time, the error counter ERi for that sprite is generated in the process of step SS10 and stored in the work area. Since the image control unit 23 'comprehensively controls the progress of the image effect, it is possible to specify the sprite at the timing when the ROM error occurs.

  If the lower two bits of the updated error counter ERi do not exceed the allowable value (= 1), the stack area used in the interrupt processing is released and then jumped to the start address of the control program (SS12 ). As a result, after that, the hot start process (ST78 to ST82) shown in FIG. 16B is executed, and the image effect is reexecuted retroactively.

  The reason why such a process is executed is that although a CGROM read error has occurred, the CGROM itself is not destroyed, and there is a possibility of bit corruption due to noise or the like. Thus, for each sprite, the first ROM error interrupt will be allowed.

  On the other hand, if it is determined in step SS11 that the lower 2 bits of the updated error counter ERi are 2 and exceed the allowable value (= 1), it is determined that the CGROM 63 itself has been destroyed and displayed. An error notification screen is displayed on the device DS to completely stop the image effect. This is because, since it is considered that the CGROM 63 itself is destroyed, there is a possibility that the player may feel uncomfortable due to an abnormal screen if the gaming machine is continuously operated.

  Although the error counter ERi is updated by specifying an abnormal sprite here, it is not necessarily limited, and it is also preferable to simply count the number of reading errors of the CGROM. In this case, if the number of abnormal interruptions reaches an abnormal value, an error notification screen may be displayed on the display device DS to completely stop the image effect. This is because if any sprite is notified that an abnormal bit exists, the subsequent maintenance becomes possible.

  The gaming machine in such a state is, for example, a maker repair target. In that case, the abnormal CGROM (CG1 to CG4) is specifically identified by using the inspection apparatus EX. And can quickly complete repairs.

  In the above embodiment, the CGROM 63 is configured by using the same configuration and four memory elements of the same grade (CG1 to CG4), but is not necessarily limited. That is, even when a specific bit of the CGROM 63 is destroyed, there are cases where the destruction is fatal or not. Therefore, it is preferable to adopt a circuit configuration based on this point.

  Specifically, in the CG data, the destruction of the pattern attribute (header part) is fatal, but the pattern data (main body part) is not so much, especially when the pattern data is not compressed, The destruction of one bit is not likely to be a problem in practice. Therefore, it is preferable that the header part and the main body part are separated on the memory element, the header part is stored in a highly reliable memory element, and the main body part is stored in a normal memory element.

  FIG. 18 is a block diagram showing such a configuration. In this embodiment, the VDP 62 and the CGROM 63 (CG1 to CG4) are a 23-bit ROM address bus and a 32-bit ROM data bus. Connected with. CE0 to CE3 are chip enable signals for selecting the memory elements CG1 to CG4. Therefore, CG1 to CG4 can be accessed independently.

  In addition, since the ROM address bus is used, no problem occurs even if random access is executed. Therefore, in this embodiment, the header portion of all sprite information is arranged in the memory CG1, while the main body portion data of all sprites are arranged at other appropriate positions CG2 to CG4. In the header portion, in addition to the attribute information and checksum data, the head address information of the main body data of the sprite is stored. As described above, since the memory CG1 is expensive but highly reliable, it is unlikely that the header information is destroyed, and the possibility that an unnatural image effect will appear is greatly reduced.

  In this embodiment, the header information of all the sprites stored in the CGROM 63 is also preferably stored in the resident area of the SDRAM 64 after the memory CG1 is first accessed. With such a configuration, every time a sprite to be displayed is changed, there is no waste of accessing the memory CG1, and necessary CG data can be acquired quickly.

  However, in this configuration, the header information stored in the resident area is reread from the memory CG1 at an appropriate timing (at least when a ROM error occurs). Therefore, no problem occurs even if the header information of the SDRAM 64 is garbled. Further, when the header information is made resident in the SDRAM 64, the number of random accesses to the memory CG1 can be greatly suppressed. Therefore, the VDP 62 and the memories CG1 to CG4 can be connected without using the ROM address bus. Can do. That is, instead of the circuit configuration of FIG. 18 using the ROM address bus, the circuit configuration of FIG. 8 not using the ROM address bus can be adopted.

  According to the embodiment of the present invention described above, since the data in the memory (ROM) can be checked at any timing such as product development or failure repair, the memory for storing audio data, image data, etc. can be normally used. It is possible to simplify the operation test of whether or not it is operating. Further, it is possible to quickly identify a problematic electronic component at the time of failure repair.

  In addition, the specific description content demonstrated in the Example does not specifically limit this invention, and can be changed suitably. Needless to say, the application of the present invention is not necessarily limited to a ball game machine.

GM gaming machine 22 effect control unit 23 ′ image control unit DS display device 60 computer circuit 61 first memory 63 second memory 62 image processing circuit

Claims (2)

A gaming machine that executes a lottery process caused by a predetermined switch signal and executes an image effect corresponding to the lottery result,
A main control unit that executes a lottery process and outputs a control command for specifying a lottery result; and an image control unit that executes an image effect corresponding to the lottery result specified by the control command using a display device. Configured,
The image control unit
A first memory for storing its own control program in a nonvolatile manner;
A computer that acquires various control commands from an upstream control unit based on a control program stored in the first memory, and comprehensively controls a series of image effects based on the acquired predetermined control commands Circuit,
A second memory for storing CG data, which is basic data for image production, in a nonvolatile manner;
Image processing that has an internal storage unit accessible from a computer circuit, reads out necessary data from the second memory based on an instruction written in the internal storage unit, generates a predetermined image signal, and outputs it to a display device A circuit, and
The second memory is configured by providing one or more memory elements, each having an N-byte output terminal connected to the upper and lower N bytes of the 2N-byte data bus of the image processing circuit, and receiving the same selection signal.
The memory device receives the same base point address information via the 2N-byte data bus and then receives the 1-bit clock signal in common, and stores the data after the base point for each N bytes. It is configured to output sequentially in units of 2N bytes,
The gaming machine according to claim 1, wherein the image processing circuit is an independent operation for each memory element with respect to CG data read in units of 2N bytes, and is configured to be capable of performing an addition operation in units of 1 byte .   2. The gaming machine according to claim 1, wherein the output operation in units of 2N bytes is continued corresponding to the clock signal as long as the selection signal is at an active level.

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