JP5436996B2 - 正の整数の正則なリコーディングの方法、装置及びコンピュータプログラム - Google Patents

正の整数の正則なリコーディングの方法、装置及びコンピュータプログラム Download PDF

Info

Publication number
JP5436996B2
JP5436996B2 JP2009211965A JP2009211965A JP5436996B2 JP 5436996 B2 JP5436996 B2 JP 5436996B2 JP 2009211965 A JP2009211965 A JP 2009211965A JP 2009211965 A JP2009211965 A JP 2009211965A JP 5436996 B2 JP5436996 B2 JP 5436996B2
Authority
JP
Japan
Prior art keywords
integer
regular
recoding
exponent
representation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009211965A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010072644A5 (https=
JP2010072644A (ja
Inventor
ジョイエ マルク
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Licensing SAS
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Publication of JP2010072644A publication Critical patent/JP2010072644A/ja
Publication of JP2010072644A5 publication Critical patent/JP2010072644A5/ja
Application granted granted Critical
Publication of JP5436996B2 publication Critical patent/JP5436996B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G06F7/725—Finite field arithmetic over elliptic curves
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/723—Modular exponentiation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • G06F2207/7261—Uniform execution, e.g. avoiding jumps, or using formulae with the same power profile

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Storage Device Security (AREA)
  • Medicinal Preparation (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Devices For Checking Fares Or Tickets At Control Points (AREA)
JP2009211965A 2008-09-22 2009-09-14 正の整数の正則なリコーディングの方法、装置及びコンピュータプログラム Expired - Fee Related JP5436996B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP08305581.4 2008-09-22
EP08305581 2008-09-22
EP08291125A EP2169535A1 (en) 2008-09-22 2008-11-28 Method, apparatus and computer program support for regular recoding of a positive integer
EP08291125.6 2008-11-28

Publications (3)

Publication Number Publication Date
JP2010072644A JP2010072644A (ja) 2010-04-02
JP2010072644A5 JP2010072644A5 (https=) 2012-09-20
JP5436996B2 true JP5436996B2 (ja) 2014-03-05

Family

ID=40578138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009211965A Expired - Fee Related JP5436996B2 (ja) 2008-09-22 2009-09-14 正の整数の正則なリコーディングの方法、装置及びコンピュータプログラム

Country Status (5)

Country Link
US (1) US20100074436A1 (https=)
EP (2) EP2169535A1 (https=)
JP (1) JP5436996B2 (https=)
CN (1) CN101685387B (https=)
AT (1) ATE544113T1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112883386B (zh) * 2021-01-15 2024-02-13 湖南遥昇通信技术有限公司 一种数字指纹处理及签名处理方法、设备及存储介质

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE325478T1 (de) * 1998-01-02 2006-06-15 Cryptography Res Inc Leckresistentes kryptographisches verfahren und vorrichtung
FR2811168B1 (fr) * 2000-06-30 2002-11-15 Gemplus Card Int Procede de conversion de la representation binaire d'un nombre dans une representation binaire signee
FR2815146B1 (fr) * 2000-10-11 2004-05-28 Gemplus Card Int Representation arithmetique minimale d'un nombre n en base relative r pour decomposer des operations de calcul notamment en cryptographie
FR2822260A1 (fr) * 2001-03-14 2002-09-20 Bull Sa Procedes et dispositifs pour accelerer le temps de calcul d'un produit de montgomery d'un multiplication et d'une exponentiation modulaire
FR2842672B1 (fr) * 2002-07-22 2005-01-28 Inst Nat Rech Inf Automat Dispositif et procede de decodage robuste de codes arithmetiques
FR2847402B1 (fr) * 2002-11-15 2005-02-18 Gemplus Card Int Procede de division entiere securise contre les attaques a canaux caches
FR2856537B1 (fr) * 2003-06-18 2005-11-04 Gemplus Card Int Procede de contre-mesure par masquage de l'accumulateur dans un composant electronique mettant en oeuvre un algorithme de cryptographie a cle publique
FR2856538B1 (fr) * 2003-06-18 2005-08-12 Gemplus Card Int Procede de contre-mesure dans un composant electronique mettant en oeuvre un algorithme cryptographique du type a cle publique
GB2403308B (en) * 2003-06-26 2006-06-21 Sharp Kk Side channel attack prevention in data processing apparatus
FR2880148A1 (fr) * 2004-12-23 2006-06-30 Gemplus Sa Procede d'exponentiation securisee et compacte pour la cryptographie
US7602907B2 (en) * 2005-07-01 2009-10-13 Microsoft Corporation Elliptic curve point multiplication
CN100518058C (zh) * 2005-10-12 2009-07-22 浙江大学 一种用于公钥密码运算加速的方法及其体系结构
JP2007187908A (ja) * 2006-01-13 2007-07-26 Hitachi Ltd サイドチャネル攻撃に耐性を有するモジュラーべき乗算計算装置及びモジュラーべき乗算計算方法
KR100867989B1 (ko) * 2006-12-06 2008-11-10 한국전자통신연구원 단순전력분석에 안전한 Ｌｅｆｔ－ｔｏ－Ｒｉｇｈｔ방향으로 리코딩과 스칼라 곱셈을 동시에 수행하는 스칼라곱셈 방법
WO2009105754A1 (en) * 2008-02-21 2009-08-27 Telcordia Technologies, Inc. Efficient, fault-tolerant multicast networks via network coding
EP2257909B1 (en) * 2008-03-20 2015-05-13 Université de Genève Secure item identification and authentication system and method based on unclonable features

Also Published As

Publication number Publication date
CN101685387B (zh) 2015-04-29
CN101685387A (zh) 2010-03-31
ATE544113T1 (de) 2012-02-15
EP2169535A1 (en) 2010-03-31
US20100074436A1 (en) 2010-03-25
JP2010072644A (ja) 2010-04-02
EP2169536B1 (en) 2012-02-01
EP2169536A1 (en) 2010-03-31

Similar Documents

Publication Publication Date Title
CN101213513B (zh) 保护数据处理装置免受密码攻击或分析的设备和方法
JP5182364B2 (ja) サイドチャネル攻撃に対する耐タンパ性を有する暗号処理方法
JP5977996B2 (ja) サイドチャンネル攻撃に対する抵抗力のあるモジュラー累乗法及び装置
US8700921B2 (en) Fault-resistant exponentiation algorithm
JP4351987B2 (ja) モンゴメリ変換装置、演算装置、ｉｃカード、暗号装置、復号装置及びプログラム
US8014520B2 (en) Exponentiation ladder for cryptography
US8626811B2 (en) Method and apparatus for providing flexible bit-length moduli on a block Montgomery machine
JP5436996B2 (ja) 正の整数の正則なリコーディングの方法、装置及びコンピュータプログラム
Hedabou et al. A comb method to render ECC resistant against Side Channel Attacks
US20100287384A1 (en) Arrangement for and method of protecting a data processing device against an attack or analysis
KR20140089230A (ko) 중복 형태 리코딩을 이용한 곱셈 방법 및 모듈러 곱셈기
JP4599859B2 (ja) 暗号処理演算方法、および暗号処理装置、並びにコンピュータ・プログラム
EP2085878A1 (en) An apparatus and a method for calculating a multiple of a point on an elliptic curve
Yen et al. Improvement on Ha-Moon randomized exponentiation algorithm
Reddy Elliptic Curve Cryptosystems and Side-channel Attacks.
EP2385461A1 (en) Method and apparatus for providing flexible bit-length moduli on a block Montgomery machine
Plantard et al. Enhanced digital signature using RNS digit exponent representation
Kumar et al. Reduced Precomputed Scalar Multiplication Cost for ECC
Eghdamian et al. NEW MODIFIED LEFT-TO-RIGHT RADIX-R REPRESENTATION FOR INTEGERS.
HK1176423B (en) Modular exponentiation method and device resistant against side-channel attacks
JP2004151234A (ja) べき乗演算装置
Cryptosystems A New Variant Nevine Maurice Ebied’s Key Randomization
KR20120127235A (ko) 부-채널 공격에 내성이 있는 모듈러 지수화 방법 및 디바이스
HK1164476A (en) Method and apparatus for providing flexible bit-length moduli on a block montgomery machine

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120806

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120806

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130910

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131107

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20131203

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131211

R150 Certificate of patent or registration of utility model

Ref document number: 5436996

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees